diff options
-rw-r--r-- | drivers/ata/sata_mv.c | 42 |
1 files changed, 19 insertions, 23 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 5b9f937d0f87..16c15ed3536e 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -2242,6 +2242,16 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) | |||
2242 | return; | 2242 | return; |
2243 | } | 2243 | } |
2244 | 2244 | ||
2245 | static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) | ||
2246 | { | ||
2247 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); | ||
2248 | |||
2249 | ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ | ||
2250 | if (want_gen2i) | ||
2251 | ifctl |= (1 << 7); /* enable gen2i speed */ | ||
2252 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); | ||
2253 | } | ||
2254 | |||
2245 | /* | 2255 | /* |
2246 | * Caller must ensure that EDMA is not active, | 2256 | * Caller must ensure that EDMA is not active, |
2247 | * by first doing mv_stop_edma() where needed. | 2257 | * by first doing mv_stop_edma() where needed. |
@@ -2253,18 +2263,17 @@ static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, | |||
2253 | 2263 | ||
2254 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); | 2264 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
2255 | 2265 | ||
2256 | if (IS_GEN_II(hpriv)) { | 2266 | if (!IS_GEN_I(hpriv)) { |
2257 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); | 2267 | /* Enable 3.0gb/s link speed */ |
2258 | ifctl |= (1 << 7); /* enable gen2i speed */ | 2268 | mv_setup_ifctl(port_mmio, 1); |
2259 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ | ||
2260 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); | ||
2261 | } | 2269 | } |
2262 | 2270 | /* | |
2263 | udelay(25); /* allow reset propagation */ | 2271 | * Strobing ATA_RST here causes a hard reset of the SATA transport, |
2264 | 2272 | * link, and physical layers. It resets all SATA interface registers | |
2265 | /* Spec never mentions clearing the bit. Marvell's driver does | 2273 | * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. |
2266 | * clear the bit, however. | ||
2267 | */ | 2274 | */ |
2275 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); | ||
2276 | udelay(25); /* allow reset propagation */ | ||
2268 | writelfl(0, port_mmio + EDMA_CMD_OFS); | 2277 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
2269 | 2278 | ||
2270 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | 2279 | hpriv->ops->phy_errata(hpriv, mmio, port_no); |
@@ -2711,19 +2720,6 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) | |||
2711 | hpriv->ops->enable_leds(hpriv, mmio); | 2720 | hpriv->ops->enable_leds(hpriv, mmio); |
2712 | 2721 | ||
2713 | for (port = 0; port < host->n_ports; port++) { | 2722 | for (port = 0; port < host->n_ports; port++) { |
2714 | if (IS_GEN_II(hpriv)) { | ||
2715 | void __iomem *port_mmio = mv_port_base(mmio, port); | ||
2716 | |||
2717 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); | ||
2718 | ifctl |= (1 << 7); /* enable gen2i speed */ | ||
2719 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ | ||
2720 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); | ||
2721 | } | ||
2722 | |||
2723 | hpriv->ops->phy_errata(hpriv, mmio, port); | ||
2724 | } | ||
2725 | |||
2726 | for (port = 0; port < host->n_ports; port++) { | ||
2727 | struct ata_port *ap = host->ports[port]; | 2723 | struct ata_port *ap = host->ports[port]; |
2728 | void __iomem *port_mmio = mv_port_base(mmio, port); | 2724 | void __iomem *port_mmio = mv_port_base(mmio, port); |
2729 | 2725 | ||