aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/fb/viafb.txt48
-rw-r--r--drivers/video/via/Makefile2
-rw-r--r--drivers/video/via/accel.c53
-rw-r--r--drivers/video/via/accel.h3
-rw-r--r--drivers/video/via/chip.h3
-rw-r--r--drivers/video/via/dvi.c189
-rw-r--r--drivers/video/via/dvi.h4
-rw-r--r--drivers/video/via/global.h1
-rw-r--r--drivers/video/via/hw.c648
-rw-r--r--drivers/video/via/hw.h53
-rw-r--r--drivers/video/via/ioctl.c2
-rw-r--r--drivers/video/via/lcd.c90
-rw-r--r--drivers/video/via/lcd.h6
-rw-r--r--drivers/video/via/lcdtbl.h591
-rw-r--r--drivers/video/via/tbl1636.c71
-rw-r--r--drivers/video/via/tbl1636.h34
-rw-r--r--drivers/video/via/via-core.c16
-rw-r--r--drivers/video/via/via_i2c.c31
-rw-r--r--drivers/video/via/viafbdev.c294
-rw-r--r--drivers/video/via/viafbdev.h7
-rw-r--r--drivers/video/via/vt1636.c121
21 files changed, 1022 insertions, 1245 deletions
diff --git a/Documentation/fb/viafb.txt b/Documentation/fb/viafb.txt
index f3e046a6a987..1a2e8aa3fbb1 100644
--- a/Documentation/fb/viafb.txt
+++ b/Documentation/fb/viafb.txt
@@ -197,6 +197,54 @@ Notes:
197 example, 197 example,
198 # fbset -depth 16 198 # fbset -depth 16
199 199
200
201[Configure viafb via /proc]
202---------------------------
203 The following files exist in /proc/viafb
204
205 supported_output_devices
206
207 This read-only file contains a full ',' seperated list containing all
208 output devices that could be available on your platform. It is likely
209 that not all of those have a connector on your hardware but it should
210 provide a good starting point to figure out which of those names match
211 a real connector.
212 Example:
213 # cat /proc/viafb/supported_output_devices
214
215 iga1/output_devices
216 iga2/output_devices
217
218 These two files are readable and writable. iga1 and iga2 are the two
219 independent units that produce the screen image. Those images can be
220 forwarded to one or more output devices. Reading those files is a way
221 to query which output devices are currently used by an iga.
222 Example:
223 # cat /proc/viafb/iga1/output_devices
224 If there are no output devices printed the output of this iga is lost.
225 This can happen for example if only one (the other) iga is used.
226 Writing to these files allows adjusting the output devices during
227 runtime. One can add new devices, remove existing ones or switch
228 between igas. Essentially you can write a ',' seperated list of device
229 names (or a single one) in the same format as the output to those
230 files. You can add a '+' or '-' as a prefix allowing simple addition
231 and removal of devices. So a prefix '+' adds the devices from your list
232 to the already existing ones, '-' removes the listed devices from the
233 existing ones and if no prefix is given it replaces all existing ones
234 with the listed ones. If you remove devices they are expected to turn
235 off. If you add devices that are already part of the other iga they are
236 removed there and added to the new one.
237 Examples:
238 Add CRT as output device to iga1
239 # echo +CRT > /proc/viafb/iga1/output_devices
240
241 Remove (turn off) DVP1 and LVDS1 as output devices of iga2
242 # echo -DVP1,LVDS1 > /proc/viafb/iga2/output_devices
243
244 Replace all iga1 output devices by CRT
245 # echo CRT > /proc/viafb/iga1/output_devices
246
247
200[Bootup with viafb]: 248[Bootup with viafb]:
201-------------------- 249--------------------
202 Add the following line to your grub.conf: 250 Add the following line to your grub.conf:
diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile
index d496adb0f832..96f01ee2a412 100644
--- a/drivers/video/via/Makefile
+++ b/drivers/video/via/Makefile
@@ -5,5 +5,5 @@
5obj-$(CONFIG_FB_VIA) += viafb.o 5obj-$(CONFIG_FB_VIA) += viafb.o
6 6
7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \ 7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \
8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o \ 8 via_utility.o vt1636.o global.o tblDPASetting.o viamode.o \
9 via-core.o via-gpio.o via_modesetting.o 9 via-core.o via-gpio.o via_modesetting.o
diff --git a/drivers/video/via/accel.c b/drivers/video/via/accel.c
index e44893ea590d..3c969cdef0af 100644
--- a/drivers/video/via/accel.c
+++ b/drivers/video/via/accel.c
@@ -283,11 +283,12 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
283 writel(tmp, engine + 0x1C); 283 writel(tmp, engine + 0x1C);
284 } 284 }
285 285
286 if (op != VIA_BITBLT_COLOR) 286 if (op == VIA_BITBLT_FILL) {
287 writel(fg_color, engine + 0x58);
288 } else if (op == VIA_BITBLT_MONO) {
287 writel(fg_color, engine + 0x4C); 289 writel(fg_color, engine + 0x4C);
288
289 if (op == VIA_BITBLT_MONO)
290 writel(bg_color, engine + 0x50); 290 writel(bg_color, engine + 0x50);
291 }
291 292
292 if (op == VIA_BITBLT_FILL) 293 if (op == VIA_BITBLT_FILL)
293 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001; 294 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
@@ -314,13 +315,11 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
314 return 0; 315 return 0;
315} 316}
316 317
317int viafb_init_engine(struct fb_info *info) 318int viafb_setup_engine(struct fb_info *info)
318{ 319{
319 struct viafb_par *viapar = info->par; 320 struct viafb_par *viapar = info->par;
320 void __iomem *engine; 321 void __iomem *engine;
321 int highest_reg, i; 322 u32 chip_name = viapar->shared->chip_info.gfx_chip_name;
322 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
323 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
324 323
325 engine = viapar->shared->vdev->engine_mmio; 324 engine = viapar->shared->vdev->engine_mmio;
326 if (!engine) { 325 if (!engine) {
@@ -329,18 +328,6 @@ int viafb_init_engine(struct fb_info *info)
329 return -ENOMEM; 328 return -ENOMEM;
330 } 329 }
331 330
332 /* Initialize registers to reset the 2D engine */
333 switch (viapar->shared->chip_info.twod_engine) {
334 case VIA_2D_ENG_M1:
335 highest_reg = 0x5c;
336 break;
337 default:
338 highest_reg = 0x40;
339 break;
340 }
341 for (i = 0; i <= highest_reg; i += 4)
342 writel(0x0, engine + i);
343
344 switch (chip_name) { 331 switch (chip_name) {
345 case UNICHROME_CLE266: 332 case UNICHROME_CLE266:
346 case UNICHROME_K400: 333 case UNICHROME_K400:
@@ -356,6 +343,7 @@ int viafb_init_engine(struct fb_info *info)
356 break; 343 break;
357 case UNICHROME_VX800: 344 case UNICHROME_VX800:
358 case UNICHROME_VX855: 345 case UNICHROME_VX855:
346 case UNICHROME_VX900:
359 viapar->shared->hw_bitblt = hw_bitblt_2; 347 viapar->shared->hw_bitblt = hw_bitblt_2;
360 break; 348 break;
361 default: 349 default:
@@ -386,12 +374,36 @@ int viafb_init_engine(struct fb_info *info)
386 viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free; 374 viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
387#endif 375#endif
388 376
377 viafb_reset_engine(viapar);
378 return 0;
379}
380
381void viafb_reset_engine(struct viafb_par *viapar)
382{
383 void __iomem *engine = viapar->shared->vdev->engine_mmio;
384 int highest_reg, i;
385 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
386 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
387
388 /* Initialize registers to reset the 2D engine */
389 switch (viapar->shared->chip_info.twod_engine) {
390 case VIA_2D_ENG_M1:
391 highest_reg = 0x5c;
392 break;
393 default:
394 highest_reg = 0x40;
395 break;
396 }
397 for (i = 0; i <= highest_reg; i += 4)
398 writel(0x0, engine + i);
399
389 /* Init AGP and VQ regs */ 400 /* Init AGP and VQ regs */
390 switch (chip_name) { 401 switch (chip_name) {
391 case UNICHROME_K8M890: 402 case UNICHROME_K8M890:
392 case UNICHROME_P4M900: 403 case UNICHROME_P4M900:
393 case UNICHROME_VX800: 404 case UNICHROME_VX800:
394 case UNICHROME_VX855: 405 case UNICHROME_VX855:
406 case UNICHROME_VX900:
395 writel(0x00100000, engine + VIA_REG_CR_TRANSET); 407 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
396 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); 408 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
397 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); 409 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
@@ -428,6 +440,7 @@ int viafb_init_engine(struct fb_info *info)
428 case UNICHROME_P4M900: 440 case UNICHROME_P4M900:
429 case UNICHROME_VX800: 441 case UNICHROME_VX800:
430 case UNICHROME_VX855: 442 case UNICHROME_VX855:
443 case UNICHROME_VX900:
431 vq_start_low |= 0x20000000; 444 vq_start_low |= 0x20000000;
432 vq_end_low |= 0x20000000; 445 vq_end_low |= 0x20000000;
433 vq_high |= 0x20000000; 446 vq_high |= 0x20000000;
@@ -473,7 +486,7 @@ int viafb_init_engine(struct fb_info *info)
473 writel(0x0, engine + VIA_REG_CURSOR_ORG); 486 writel(0x0, engine + VIA_REG_CURSOR_ORG);
474 writel(0x0, engine + VIA_REG_CURSOR_BG); 487 writel(0x0, engine + VIA_REG_CURSOR_BG);
475 writel(0x0, engine + VIA_REG_CURSOR_FG); 488 writel(0x0, engine + VIA_REG_CURSOR_FG);
476 return 0; 489 return;
477} 490}
478 491
479void viafb_show_hw_cursor(struct fb_info *info, int Status) 492void viafb_show_hw_cursor(struct fb_info *info, int Status)
diff --git a/drivers/video/via/accel.h b/drivers/video/via/accel.h
index 2c122d292365..79d5e10cc835 100644
--- a/drivers/video/via/accel.h
+++ b/drivers/video/via/accel.h
@@ -203,7 +203,8 @@
203#define VIA_BITBLT_MONO 2 203#define VIA_BITBLT_MONO 2
204#define VIA_BITBLT_FILL 3 204#define VIA_BITBLT_FILL 3
205 205
206int viafb_init_engine(struct fb_info *info); 206int viafb_setup_engine(struct fb_info *info);
207void viafb_reset_engine(struct viafb_par *viapar);
207void viafb_show_hw_cursor(struct fb_info *info, int Status); 208void viafb_show_hw_cursor(struct fb_info *info, int Status);
208void viafb_wait_engine_idle(struct fb_info *info); 209void viafb_wait_engine_idle(struct fb_info *info);
209 210
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
index ef1f3de2e052..48f1342897bd 100644
--- a/drivers/video/via/chip.h
+++ b/drivers/video/via/chip.h
@@ -71,6 +71,9 @@
71#define UNICHROME_VX855 12 71#define UNICHROME_VX855 12
72#define UNICHROME_VX855_DID 0x5122 72#define UNICHROME_VX855_DID 0x5122
73 73
74#define UNICHROME_VX900 13
75#define UNICHROME_VX900_DID 0x7122
76
74/**************************************************/ 77/**************************************************/
75/* Definition TMDS Trasmitter Information */ 78/* Definition TMDS Trasmitter Information */
76/**************************************************/ 79/**************************************************/
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 39b040bb3817..84e21b39dd0b 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -25,10 +25,12 @@
25static void tmds_register_write(int index, u8 data); 25static void tmds_register_write(int index, u8 data);
26static int tmds_register_read(int index); 26static int tmds_register_read(int index);
27static int tmds_register_read_bytes(int index, u8 *buff, int buff_len); 27static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
28static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information 28static void __devinit dvi_get_panel_size_from_DDCv1(
29 *tmds_chip, struct tmds_setting_information *tmds_setting); 29 struct tmds_chip_information *tmds_chip,
30static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information 30 struct tmds_setting_information *tmds_setting);
31 *tmds_chip, struct tmds_setting_information *tmds_setting); 31static void __devinit dvi_get_panel_size_from_DDCv2(
32 struct tmds_chip_information *tmds_chip,
33 struct tmds_setting_information *tmds_setting);
32static int viafb_dvi_query_EDID(void); 34static int viafb_dvi_query_EDID(void);
33 35
34static int check_tmds_chip(int device_id_subaddr, int device_id) 36static int check_tmds_chip(int device_id_subaddr, int device_id)
@@ -39,7 +41,7 @@ static int check_tmds_chip(int device_id_subaddr, int device_id)
39 return FAIL; 41 return FAIL;
40} 42}
41 43
42void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, 44void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
43 struct tmds_setting_information *tmds_setting) 45 struct tmds_setting_information *tmds_setting)
44{ 46{
45 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n"); 47 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
@@ -60,7 +62,7 @@ void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
60 return; 62 return;
61} 63}
62 64
63int viafb_tmds_trasmitter_identify(void) 65int __devinit viafb_tmds_trasmitter_identify(void)
64{ 66{
65 unsigned char sr2a = 0, sr1e = 0, sr3e = 0; 67 unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
66 68
@@ -208,8 +210,6 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
208 } 210 }
209 } 211 }
210 viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga); 212 viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga);
211 viafb_set_output_path(DEVICE_DVI, set_iga,
212 viaparinfo->chip_info->tmds_chip_info.output_interface);
213} 213}
214 214
215/* Sense DVI Connector */ 215/* Sense DVI Connector */
@@ -313,8 +313,9 @@ static int viafb_dvi_query_EDID(void)
313} 313}
314 314
315/* Get Panel Size Using EDID1 Table */ 315/* Get Panel Size Using EDID1 Table */
316static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information 316static void __devinit dvi_get_panel_size_from_DDCv1(
317 *tmds_chip, struct tmds_setting_information *tmds_setting) 317 struct tmds_chip_information *tmds_chip,
318 struct tmds_setting_information *tmds_setting)
318{ 319{
319 int i, max_h = 0, tmp, restore; 320 int i, max_h = 0, tmp, restore;
320 unsigned char rData; 321 unsigned char rData;
@@ -418,8 +419,9 @@ static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information
418} 419}
419 420
420/* Get Panel Size Using EDID2 Table */ 421/* Get Panel Size Using EDID2 Table */
421static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information 422static void __devinit dvi_get_panel_size_from_DDCv2(
422 *tmds_chip, struct tmds_setting_information *tmds_setting) 423 struct tmds_chip_information *tmds_chip,
424 struct tmds_setting_information *tmds_setting)
423{ 425{
424 int restore; 426 int restore;
425 unsigned char R_Buffer[2]; 427 unsigned char R_Buffer[2];
@@ -468,64 +470,107 @@ static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information
468void viafb_dvi_disable(void) 470void viafb_dvi_disable(void)
469{ 471{
470 if (viaparinfo->chip_info-> 472 if (viaparinfo->chip_info->
471 tmds_chip_info.output_interface == INTERFACE_DVP0)
472 viafb_write_reg(SR1E, VIASR,
473 viafb_read_reg(VIASR, SR1E) & (~0xC0));
474
475 if (viaparinfo->chip_info->
476 tmds_chip_info.output_interface == INTERFACE_DVP1)
477 viafb_write_reg(SR1E, VIASR,
478 viafb_read_reg(VIASR, SR1E) & (~0x30));
479
480 if (viaparinfo->chip_info->
481 tmds_chip_info.output_interface == INTERFACE_DFP_HIGH)
482 viafb_write_reg(SR2A, VIASR,
483 viafb_read_reg(VIASR, SR2A) & (~0x0C));
484
485 if (viaparinfo->chip_info->
486 tmds_chip_info.output_interface == INTERFACE_DFP_LOW)
487 viafb_write_reg(SR2A, VIASR,
488 viafb_read_reg(VIASR, SR2A) & (~0x03));
489
490 if (viaparinfo->chip_info->
491 tmds_chip_info.output_interface == INTERFACE_TMDS) 473 tmds_chip_info.output_interface == INTERFACE_TMDS)
492 /* Turn off TMDS power. */ 474 /* Turn off TMDS power. */
493 viafb_write_reg(CRD2, VIACR, 475 viafb_write_reg(CRD2, VIACR,
494 viafb_read_reg(VIACR, CRD2) | 0x08); 476 viafb_read_reg(VIACR, CRD2) | 0x08);
495} 477}
496 478
479static void dvi_patch_skew_dvp0(void)
480{
481 /* Reset data driving first: */
482 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
483 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
484
485 switch (viaparinfo->chip_info->gfx_chip_name) {
486 case UNICHROME_P4M890:
487 {
488 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
489 (viaparinfo->tmds_setting_info->v_active ==
490 1200))
491 viafb_write_reg_mask(CR96, VIACR, 0x03,
492 BIT0 + BIT1 + BIT2);
493 else
494 viafb_write_reg_mask(CR96, VIACR, 0x07,
495 BIT0 + BIT1 + BIT2);
496 break;
497 }
498
499 case UNICHROME_P4M900:
500 {
501 viafb_write_reg_mask(CR96, VIACR, 0x07,
502 BIT0 + BIT1 + BIT2 + BIT3);
503 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
504 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
505 break;
506 }
507
508 default:
509 {
510 break;
511 }
512 }
513}
514
515static void dvi_patch_skew_dvp_low(void)
516{
517 switch (viaparinfo->chip_info->gfx_chip_name) {
518 case UNICHROME_K8M890:
519 {
520 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
521 break;
522 }
523
524 case UNICHROME_P4M900:
525 {
526 viafb_write_reg_mask(CR99, VIACR, 0x08,
527 BIT0 + BIT1 + BIT2 + BIT3);
528 break;
529 }
530
531 case UNICHROME_P4M890:
532 {
533 viafb_write_reg_mask(CR99, VIACR, 0x0F,
534 BIT0 + BIT1 + BIT2 + BIT3);
535 break;
536 }
537
538 default:
539 {
540 break;
541 }
542 }
543}
544
497/* If Enable DVI, turn off pad */ 545/* If Enable DVI, turn off pad */
498void viafb_dvi_enable(void) 546void viafb_dvi_enable(void)
499{ 547{
500 u8 data; 548 u8 data;
501 549
502 if (viaparinfo->chip_info-> 550 switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
503 tmds_chip_info.output_interface == INTERFACE_DVP0) { 551 case INTERFACE_DVP0:
504 viafb_write_reg(SR1E, VIASR, 552 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
505 viafb_read_reg(VIASR, SR1E) | 0xC0); 553 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
554 dvi_patch_skew_dvp0();
506 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 555 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
507 tmds_register_write(0x88, 0x3b); 556 tmds_register_write(0x88, 0x3b);
508 else 557 else
509 /*clear CR91[5] to direct on display period 558 /*clear CR91[5] to direct on display period
510 in the secondary diplay path */ 559 in the secondary diplay path */
511 viafb_write_reg(CR91, VIACR, 560 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
512 viafb_read_reg(VIACR, CR91) & 0xDF); 561 break;
513 }
514 562
515 if (viaparinfo->chip_info-> 563 case INTERFACE_DVP1:
516 tmds_chip_info.output_interface == INTERFACE_DVP1) { 564 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
517 viafb_write_reg(SR1E, VIASR, 565 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
518 viafb_read_reg(VIASR, SR1E) | 0x30);
519 566
520 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */ 567 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
521 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { 568 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
522 tmds_register_write(0x88, 0x3b); 569 tmds_register_write(0x88, 0x3b);
523 } else { 570 else
524 /*clear CR91[5] to direct on display period 571 /*clear CR91[5] to direct on display period
525 in the secondary diplay path */ 572 in the secondary diplay path */
526 viafb_write_reg(CR91, VIACR, 573 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
527 viafb_read_reg(VIACR, CR91) & 0xDF);
528 }
529 574
530 /*fix DVI cannot enable on EPIA-M board */ 575 /*fix DVI cannot enable on EPIA-M board */
531 if (viafb_platform_epia_dvi == 1) { 576 if (viafb_platform_epia_dvi == 1) {
@@ -537,36 +582,40 @@ void viafb_dvi_enable(void)
537 else 582 else
538 data = 0x37; 583 data = 0x37;
539 viafb_i2c_writebyte(viaparinfo->chip_info-> 584 viafb_i2c_writebyte(viaparinfo->chip_info->
540 tmds_chip_info.i2c_port, 585 tmds_chip_info.i2c_port,
541 viaparinfo->chip_info-> 586 viaparinfo->chip_info->
542 tmds_chip_info.tmds_chip_slave_addr, 587 tmds_chip_info.tmds_chip_slave_addr,
543 0x08, data); 588 0x08, data);
544 } 589 }
545 } 590 }
546 } 591 break;
547 592
548 if (viaparinfo->chip_info-> 593 case INTERFACE_DFP_HIGH:
549 tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) { 594 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
550 viafb_write_reg(SR2A, VIASR, 595 via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
551 viafb_read_reg(VIASR, SR2A) | 0x0C);
552 viafb_write_reg(CR91, VIACR,
553 viafb_read_reg(VIACR, CR91) & 0xDF);
554 }
555 596
556 if (viaparinfo->chip_info-> 597 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
557 tmds_chip_info.output_interface == INTERFACE_DFP_LOW) { 598 break;
558 viafb_write_reg(SR2A, VIASR, 599
559 viafb_read_reg(VIASR, SR2A) | 0x03); 600 case INTERFACE_DFP_LOW:
560 viafb_write_reg(CR91, VIACR, 601 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
561 viafb_read_reg(VIACR, CR91) & 0xDF); 602 break;
562 } 603
563 if (viaparinfo->chip_info-> 604 dvi_patch_skew_dvp_low();
564 tmds_chip_info.output_interface == INTERFACE_TMDS) { 605 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
606 break;
607
608 case INTERFACE_TMDS:
565 /* Turn on Display period in the panel path. */ 609 /* Turn on Display period in the panel path. */
566 viafb_write_reg_mask(CR91, VIACR, 0, BIT7); 610 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
567 611
568 /* Turn on TMDS power. */ 612 /* Turn on TMDS power. */
569 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); 613 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
614 break;
570 } 615 }
571}
572 616
617 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
618 /* Disable LCD Scaling */
619 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
620 }
621}
diff --git a/drivers/video/via/dvi.h b/drivers/video/via/dvi.h
index 0dffcfd395f3..2c525c0c1adb 100644
--- a/drivers/video/via/dvi.h
+++ b/drivers/video/via/dvi.h
@@ -56,8 +56,8 @@
56int viafb_dvi_sense(void); 56int viafb_dvi_sense(void);
57void viafb_dvi_disable(void); 57void viafb_dvi_disable(void);
58void viafb_dvi_enable(void); 58void viafb_dvi_enable(void);
59int viafb_tmds_trasmitter_identify(void); 59int __devinit viafb_tmds_trasmitter_identify(void);
60void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip, 60void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
61 struct tmds_setting_information *tmds_setting); 61 struct tmds_setting_information *tmds_setting);
62void viafb_dvi_set_mode(struct VideoModeTable *videoMode, int mode_bpp, 62void viafb_dvi_set_mode(struct VideoModeTable *videoMode, int mode_bpp,
63 int set_iga); 63 int set_iga);
diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h
index 28221a062dda..38ef5ac66953 100644
--- a/drivers/video/via/global.h
+++ b/drivers/video/via/global.h
@@ -48,7 +48,6 @@
48#include "via_utility.h" 48#include "via_utility.h"
49#include "vt1636.h" 49#include "vt1636.h"
50#include "tblDPASetting.h" 50#include "tblDPASetting.h"
51#include "tbl1636.h"
52 51
53/* External struct*/ 52/* External struct*/
54 53
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 7dcb4d5bb9c3..36d73f940d8b 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -718,16 +718,20 @@ static struct rgbLUT palLUT_table[] = {
718 0x00} 718 0x00}
719}; 719};
720 720
721static void set_crt_output_path(int set_iga); 721static struct via_device_mapping device_mapping[] = {
722static void dvi_patch_skew_dvp0(void); 722 {VIA_LDVP0, "LDVP0"},
723static void dvi_patch_skew_dvp1(void); 723 {VIA_LDVP1, "LDVP1"},
724static void dvi_patch_skew_dvp_low(void); 724 {VIA_DVP0, "DVP0"},
725static void set_dvi_output_path(int set_iga, int output_interface); 725 {VIA_CRT, "CRT"},
726static void set_lcd_output_path(int set_iga, int output_interface); 726 {VIA_DVP1, "DVP1"},
727 {VIA_LVDS1, "LVDS1"},
728 {VIA_LVDS2, "LVDS2"}
729};
730
727static void load_fix_bit_crtc_reg(void); 731static void load_fix_bit_crtc_reg(void);
728static void init_gfx_chip_info(int chip_type); 732static void __devinit init_gfx_chip_info(int chip_type);
729static void init_tmds_chip_info(void); 733static void __devinit init_tmds_chip_info(void);
730static void init_lvds_chip_info(void); 734static void __devinit init_lvds_chip_info(void);
731static void device_screen_off(void); 735static void device_screen_off(void);
732static void device_screen_on(void); 736static void device_screen_on(void);
733static void set_display_channel(void); 737static void set_display_channel(void);
@@ -755,6 +759,66 @@ void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
755 outb(b, LUT_DATA); 759 outb(b, LUT_DATA);
756} 760}
757 761
762static u32 get_dvi_devices(int output_interface)
763{
764 switch (output_interface) {
765 case INTERFACE_DVP0:
766 return VIA_DVP0 | VIA_LDVP0;
767
768 case INTERFACE_DVP1:
769 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
770 return VIA_LDVP1;
771 else
772 return VIA_DVP1;
773
774 case INTERFACE_DFP_HIGH:
775 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
776 return 0;
777 else
778 return VIA_LVDS2 | VIA_DVP0;
779
780 case INTERFACE_DFP_LOW:
781 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
782 return 0;
783 else
784 return VIA_DVP1 | VIA_LVDS1;
785
786 case INTERFACE_TMDS:
787 return VIA_LVDS1;
788 }
789
790 return 0;
791}
792
793static u32 get_lcd_devices(int output_interface)
794{
795 switch (output_interface) {
796 case INTERFACE_DVP0:
797 return VIA_DVP0;
798
799 case INTERFACE_DVP1:
800 return VIA_DVP1;
801
802 case INTERFACE_DFP_HIGH:
803 return VIA_LVDS2 | VIA_DVP0;
804
805 case INTERFACE_DFP_LOW:
806 return VIA_LVDS1 | VIA_DVP1;
807
808 case INTERFACE_DFP:
809 return VIA_LVDS1 | VIA_LVDS2;
810
811 case INTERFACE_LVDS0:
812 case INTERFACE_LVDS0LVDS1:
813 return VIA_LVDS1;
814
815 case INTERFACE_LVDS1:
816 return VIA_LVDS2;
817 }
818
819 return 0;
820}
821
758/*Set IGA path for each device*/ 822/*Set IGA path for each device*/
759void viafb_set_iga_path(void) 823void viafb_set_iga_path(void)
760{ 824{
@@ -821,6 +885,48 @@ void viafb_set_iga_path(void)
821 viaparinfo->tmds_setting_info->iga_path = IGA1; 885 viaparinfo->tmds_setting_info->iga_path = IGA1;
822 } 886 }
823 } 887 }
888
889 viaparinfo->shared->iga1_devices = 0;
890 viaparinfo->shared->iga2_devices = 0;
891 if (viafb_CRT_ON) {
892 if (viaparinfo->crt_setting_info->iga_path == IGA1)
893 viaparinfo->shared->iga1_devices |= VIA_CRT;
894 else
895 viaparinfo->shared->iga2_devices |= VIA_CRT;
896 }
897
898 if (viafb_DVI_ON) {
899 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
900 viaparinfo->shared->iga1_devices |= get_dvi_devices(
901 viaparinfo->chip_info->
902 tmds_chip_info.output_interface);
903 else
904 viaparinfo->shared->iga2_devices |= get_dvi_devices(
905 viaparinfo->chip_info->
906 tmds_chip_info.output_interface);
907 }
908
909 if (viafb_LCD_ON) {
910 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
911 viaparinfo->shared->iga1_devices |= get_lcd_devices(
912 viaparinfo->chip_info->
913 lvds_chip_info.output_interface);
914 else
915 viaparinfo->shared->iga2_devices |= get_lcd_devices(
916 viaparinfo->chip_info->
917 lvds_chip_info.output_interface);
918 }
919
920 if (viafb_LCD2_ON) {
921 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
922 viaparinfo->shared->iga1_devices |= get_lcd_devices(
923 viaparinfo->chip_info->
924 lvds_chip_info2.output_interface);
925 else
926 viaparinfo->shared->iga2_devices |= get_lcd_devices(
927 viaparinfo->chip_info->
928 lvds_chip_info2.output_interface);
929 }
824} 930}
825 931
826static void set_color_register(u8 index, u8 red, u8 green, u8 blue) 932static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
@@ -844,295 +950,266 @@ void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
844 set_color_register(index, red, green, blue); 950 set_color_register(index, red, green, blue);
845} 951}
846 952
847void viafb_set_output_path(int device, int set_iga, int output_interface) 953static void set_source_common(u8 index, u8 offset, u8 iga)
848{ 954{
849 switch (device) { 955 u8 value, mask = 1 << offset;
850 case DEVICE_CRT: 956
851 set_crt_output_path(set_iga); 957 switch (iga) {
852 break; 958 case IGA1:
853 case DEVICE_DVI: 959 value = 0x00;
854 set_dvi_output_path(set_iga, output_interface);
855 break; 960 break;
856 case DEVICE_LCD: 961 case IGA2:
857 set_lcd_output_path(set_iga, output_interface); 962 value = mask;
858 break; 963 break;
964 default:
965 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
966 return;
859 } 967 }
968
969 via_write_reg_mask(VIACR, index, value, mask);
860} 970}
861 971
862static void set_crt_output_path(int set_iga) 972static void set_crt_source(u8 iga)
863{ 973{
864 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); 974 u8 value;
865 975
866 switch (set_iga) { 976 switch (iga) {
867 case IGA1: 977 case IGA1:
868 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); 978 value = 0x00;
869 break; 979 break;
870 case IGA2: 980 case IGA2:
871 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); 981 value = 0x40;
872 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
873 break; 982 break;
983 default:
984 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
985 return;
874 } 986 }
987
988 via_write_reg_mask(VIASR, 0x16, value, 0x40);
875} 989}
876 990
877static void dvi_patch_skew_dvp0(void) 991static inline void set_ldvp0_source(u8 iga)
878{ 992{
879 /* Reset data driving first: */ 993 set_source_common(0x6C, 7, iga);
880 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); 994}
881 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
882
883 switch (viaparinfo->chip_info->gfx_chip_name) {
884 case UNICHROME_P4M890:
885 {
886 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
887 (viaparinfo->tmds_setting_info->v_active ==
888 1200))
889 viafb_write_reg_mask(CR96, VIACR, 0x03,
890 BIT0 + BIT1 + BIT2);
891 else
892 viafb_write_reg_mask(CR96, VIACR, 0x07,
893 BIT0 + BIT1 + BIT2);
894 break;
895 }
896 995
897 case UNICHROME_P4M900: 996static inline void set_ldvp1_source(u8 iga)
898 { 997{
899 viafb_write_reg_mask(CR96, VIACR, 0x07, 998 set_source_common(0x93, 7, iga);
900 BIT0 + BIT1 + BIT2 + BIT3); 999}
901 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
902 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
903 break;
904 }
905 1000
906 default: 1001static inline void set_dvp0_source(u8 iga)
907 { 1002{
908 break; 1003 set_source_common(0x96, 4, iga);
909 }
910 }
911} 1004}
912 1005
913static void dvi_patch_skew_dvp1(void) 1006static inline void set_dvp1_source(u8 iga)
914{ 1007{
915 switch (viaparinfo->chip_info->gfx_chip_name) { 1008 set_source_common(0x9B, 4, iga);
916 case UNICHROME_CX700: 1009}
917 {
918 break;
919 }
920 1010
921 default: 1011static inline void set_lvds1_source(u8 iga)
922 { 1012{
923 break; 1013 set_source_common(0x99, 4, iga);
924 }
925 }
926} 1014}
927 1015
928static void dvi_patch_skew_dvp_low(void) 1016static inline void set_lvds2_source(u8 iga)
929{ 1017{
930 switch (viaparinfo->chip_info->gfx_chip_name) { 1018 set_source_common(0x97, 4, iga);
931 case UNICHROME_K8M890: 1019}
932 {
933 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
934 break;
935 }
936 1020
937 case UNICHROME_P4M900: 1021void via_set_source(u32 devices, u8 iga)
938 { 1022{
939 viafb_write_reg_mask(CR99, VIACR, 0x08, 1023 if (devices & VIA_LDVP0)
940 BIT0 + BIT1 + BIT2 + BIT3); 1024 set_ldvp0_source(iga);
941 break; 1025 if (devices & VIA_LDVP1)
942 } 1026 set_ldvp1_source(iga);
1027 if (devices & VIA_DVP0)
1028 set_dvp0_source(iga);
1029 if (devices & VIA_CRT)
1030 set_crt_source(iga);
1031 if (devices & VIA_DVP1)
1032 set_dvp1_source(iga);
1033 if (devices & VIA_LVDS1)
1034 set_lvds1_source(iga);
1035 if (devices & VIA_LVDS2)
1036 set_lvds2_source(iga);
1037}
943 1038
944 case UNICHROME_P4M890: 1039static void set_crt_state(u8 state)
945 { 1040{
946 viafb_write_reg_mask(CR99, VIACR, 0x0F, 1041 u8 value;
947 BIT0 + BIT1 + BIT2 + BIT3);
948 break;
949 }
950 1042
1043 switch (state) {
1044 case VIA_STATE_ON:
1045 value = 0x00;
1046 break;
1047 case VIA_STATE_STANDBY:
1048 value = 0x10;
1049 break;
1050 case VIA_STATE_SUSPEND:
1051 value = 0x20;
1052 break;
1053 case VIA_STATE_OFF:
1054 value = 0x30;
1055 break;
951 default: 1056 default:
952 { 1057 return;
953 break;
954 }
955 } 1058 }
1059
1060 via_write_reg_mask(VIACR, 0x36, value, 0x30);
956} 1061}
957 1062
958static void set_dvi_output_path(int set_iga, int output_interface) 1063static void set_dvp0_state(u8 state)
959{ 1064{
960 switch (output_interface) { 1065 u8 value;
961 case INTERFACE_DVP0:
962 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
963
964 if (set_iga == IGA1) {
965 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
966 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
967 BIT5 + BIT7);
968 } else {
969 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
970 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
971 BIT5 + BIT7);
972 }
973
974 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
975 1066
976 dvi_patch_skew_dvp0(); 1067 switch (state) {
1068 case VIA_STATE_ON:
1069 value = 0xC0;
977 break; 1070 break;
1071 case VIA_STATE_OFF:
1072 value = 0x00;
1073 break;
1074 default:
1075 return;
1076 }
978 1077
979 case INTERFACE_DVP1: 1078 via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
980 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { 1079}
981 if (set_iga == IGA1) 1080
982 viafb_write_reg_mask(CR93, VIACR, 0x21, 1081static void set_dvp1_state(u8 state)
983 BIT0 + BIT5 + BIT7); 1082{
984 else 1083 u8 value;
985 viafb_write_reg_mask(CR93, VIACR, 0xA1,
986 BIT0 + BIT5 + BIT7);
987 } else {
988 if (set_iga == IGA1)
989 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
990 else
991 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
992 }
993 1084
994 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); 1085 switch (state) {
995 dvi_patch_skew_dvp1(); 1086 case VIA_STATE_ON:
1087 value = 0x30;
996 break; 1088 break;
997 case INTERFACE_DFP_HIGH: 1089 case VIA_STATE_OFF:
998 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) { 1090 value = 0x00;
999 if (set_iga == IGA1) {
1000 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1001 viafb_write_reg_mask(CR97, VIACR, 0x03,
1002 BIT0 + BIT1 + BIT4);
1003 } else {
1004 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1005 viafb_write_reg_mask(CR97, VIACR, 0x13,
1006 BIT0 + BIT1 + BIT4);
1007 }
1008 }
1009 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
1010 break; 1091 break;
1092 default:
1093 return;
1094 }
1011 1095
1012 case INTERFACE_DFP_LOW: 1096 via_write_reg_mask(VIASR, 0x1E, value, 0x30);
1013 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 1097}
1014 break;
1015 1098
1016 if (set_iga == IGA1) { 1099static void set_lvds1_state(u8 state)
1017 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); 1100{
1018 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); 1101 u8 value;
1019 } else {
1020 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1021 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1022 }
1023 1102
1024 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); 1103 switch (state) {
1025 dvi_patch_skew_dvp_low(); 1104 case VIA_STATE_ON:
1105 value = 0x03;
1026 break; 1106 break;
1027 1107 case VIA_STATE_OFF:
1028 case INTERFACE_TMDS: 1108 value = 0x00;
1029 if (set_iga == IGA1)
1030 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1031 else
1032 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1033 break; 1109 break;
1110 default:
1111 return;
1034 } 1112 }
1035 1113
1036 if (set_iga == IGA2) { 1114 via_write_reg_mask(VIASR, 0x2A, value, 0x03);
1037 enable_second_display_channel();
1038 /* Disable LCD Scaling */
1039 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1040 }
1041} 1115}
1042 1116
1043static void set_lcd_output_path(int set_iga, int output_interface) 1117static void set_lvds2_state(u8 state)
1044{ 1118{
1045 DEBUG_MSG(KERN_INFO 1119 u8 value;
1046 "set_lcd_output_path, iga:%d,out_interface:%d\n",
1047 set_iga, output_interface);
1048 switch (set_iga) {
1049 case IGA1:
1050 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1051 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1052 1120
1053 disable_second_display_channel(); 1121 switch (state) {
1122 case VIA_STATE_ON:
1123 value = 0x0C;
1054 break; 1124 break;
1055 1125 case VIA_STATE_OFF:
1056 case IGA2: 1126 value = 0x00;
1057 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1058 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1059
1060 enable_second_display_channel();
1061 break; 1127 break;
1128 default:
1129 return;
1062 } 1130 }
1063 1131
1064 switch (output_interface) { 1132 via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
1065 case INTERFACE_DVP0: 1133}
1066 if (set_iga == IGA1) {
1067 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1068 } else {
1069 viafb_write_reg(CR91, VIACR, 0x00);
1070 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1071 }
1072 break;
1073
1074 case INTERFACE_DVP1:
1075 if (set_iga == IGA1)
1076 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1077 else {
1078 viafb_write_reg(CR91, VIACR, 0x00);
1079 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1080 }
1081 break;
1082 1134
1083 case INTERFACE_DFP_HIGH: 1135void via_set_state(u32 devices, u8 state)
1084 if (set_iga == IGA1) 1136{
1085 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); 1137 /*
1086 else { 1138 TODO: Can we enable/disable these devices? How?
1087 viafb_write_reg(CR91, VIACR, 0x00); 1139 if (devices & VIA_LDVP0)
1088 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); 1140 if (devices & VIA_LDVP1)
1089 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); 1141 */
1090 } 1142 if (devices & VIA_DVP0)
1091 break; 1143 set_dvp0_state(state);
1144 if (devices & VIA_CRT)
1145 set_crt_state(state);
1146 if (devices & VIA_DVP1)
1147 set_dvp1_state(state);
1148 if (devices & VIA_LVDS1)
1149 set_lvds1_state(state);
1150 if (devices & VIA_LVDS2)
1151 set_lvds2_state(state);
1152}
1092 1153
1093 case INTERFACE_DFP_LOW: 1154void via_set_sync_polarity(u32 devices, u8 polarity)
1094 if (set_iga == IGA1) 1155{
1095 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); 1156 if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
1096 else { 1157 printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
1097 viafb_write_reg(CR91, VIACR, 0x00); 1158 polarity);
1098 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); 1159 return;
1099 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); 1160 }
1100 }
1101 1161
1102 break; 1162 if (devices & VIA_CRT)
1163 via_write_misc_reg_mask(polarity << 6, 0xC0);
1164 if (devices & VIA_DVP1)
1165 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
1166 if (devices & VIA_LVDS1)
1167 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
1168 if (devices & VIA_LVDS2)
1169 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
1170}
1103 1171
1104 case INTERFACE_DFP: 1172u32 via_parse_odev(char *input, char **end)
1105 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) 1173{
1106 || (UNICHROME_P4M890 == 1174 char *ptr = input;
1107 viaparinfo->chip_info->gfx_chip_name)) 1175 u32 odev = 0;
1108 viafb_write_reg_mask(CR97, VIACR, 0x84, 1176 bool next = true;
1109 BIT7 + BIT2 + BIT1 + BIT0); 1177 int i, len;
1110 if (set_iga == IGA1) { 1178
1111 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); 1179 while (next) {
1112 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); 1180 next = false;
1113 } else { 1181 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1114 viafb_write_reg(CR91, VIACR, 0x00); 1182 len = strlen(device_mapping[i].name);
1115 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); 1183 if (!strncmp(ptr, device_mapping[i].name, len)) {
1116 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); 1184 odev |= device_mapping[i].device;
1185 ptr += len;
1186 if (*ptr == ',') {
1187 ptr++;
1188 next = true;
1189 }
1190 }
1117 } 1191 }
1118 break; 1192 }
1119 1193
1120 case INTERFACE_LVDS0: 1194 *end = ptr;
1121 case INTERFACE_LVDS0LVDS1: 1195 return odev;
1122 if (set_iga == IGA1) 1196}
1123 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1124 else
1125 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1126 1197
1127 break; 1198void via_odev_to_seq(struct seq_file *m, u32 odev)
1199{
1200 int i, count = 0;
1128 1201
1129 case INTERFACE_LVDS1: 1202 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1130 if (set_iga == IGA1) 1203 if (odev & device_mapping[i].device) {
1131 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); 1204 if (count > 0)
1132 else 1205 seq_putc(m, ',');
1133 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); 1206
1134 break; 1207 seq_puts(m, device_mapping[i].name);
1208 count++;
1209 }
1135 } 1210 }
1211
1212 seq_putc(m, '\n');
1136} 1213}
1137 1214
1138static void load_fix_bit_crtc_reg(void) 1215static void load_fix_bit_crtc_reg(void)
@@ -1352,6 +1429,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1352 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 1429 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1353 } 1430 }
1354 1431
1432 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1433 iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
1434 iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
1435 iga1_fifo_high_threshold =
1436 VX900_IGA1_FIFO_HIGH_THRESHOLD;
1437 iga1_display_queue_expire_num =
1438 VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1439 }
1440
1355 /* Set Display FIFO Depath Select */ 1441 /* Set Display FIFO Depath Select */
1356 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 1442 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1357 viafb_load_reg_num = 1443 viafb_load_reg_num =
@@ -1492,6 +1578,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1492 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; 1578 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1493 } 1579 }
1494 1580
1581 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1582 iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
1583 iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
1584 iga2_fifo_high_threshold =
1585 VX900_IGA2_FIFO_HIGH_THRESHOLD;
1586 iga2_display_queue_expire_num =
1587 VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1588 }
1589
1495 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { 1590 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1496 /* Set Display FIFO Depath Select */ 1591 /* Set Display FIFO Depath Select */
1497 reg_value = 1592 reg_value =
@@ -1612,6 +1707,7 @@ u32 viafb_get_clk_value(int clk)
1612 break; 1707 break;
1613 1708
1614 case UNICHROME_VX855: 1709 case UNICHROME_VX855:
1710 case UNICHROME_VX900:
1615 value = vx855_encode_pll(pll_value[i].vx855_pll); 1711 value = vx855_encode_pll(pll_value[i].vx855_pll);
1616 break; 1712 break;
1617 } 1713 }
@@ -1645,6 +1741,7 @@ void viafb_set_vclock(u32 clk, int set_iga)
1645 case UNICHROME_P4M900: 1741 case UNICHROME_P4M900:
1646 case UNICHROME_VX800: 1742 case UNICHROME_VX800:
1647 case UNICHROME_VX855: 1743 case UNICHROME_VX855:
1744 case UNICHROME_VX900:
1648 via_write_reg(VIASR, SR44, (clk & 0x0000FF)); 1745 via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1649 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8); 1746 via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1650 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16); 1747 via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
@@ -1671,6 +1768,7 @@ void viafb_set_vclock(u32 clk, int set_iga)
1671 case UNICHROME_P4M900: 1768 case UNICHROME_P4M900:
1672 case UNICHROME_VX800: 1769 case UNICHROME_VX800:
1673 case UNICHROME_VX855: 1770 case UNICHROME_VX855:
1771 case UNICHROME_VX900:
1674 via_write_reg(VIASR, SR4A, (clk & 0x0000FF)); 1772 via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1675 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8); 1773 via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1676 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16); 1774 via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
@@ -1688,8 +1786,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
1688 } 1786 }
1689 1787
1690 if (set_iga == IGA2) { 1788 if (set_iga == IGA2) {
1691 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); 1789 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1692 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); 1790 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1693 } 1791 }
1694 1792
1695 /* Fire! */ 1793 /* Fire! */
@@ -1937,7 +2035,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1937 int index = 0; 2035 int index = 0;
1938 int h_addr, v_addr; 2036 int h_addr, v_addr;
1939 u32 pll_D_N; 2037 u32 pll_D_N;
1940 u8 polarity = 0;
1941 2038
1942 for (i = 0; i < video_mode->mode_array; i++) { 2039 for (i = 0; i < video_mode->mode_array; i++) {
1943 index = i; 2040 index = i;
@@ -1964,14 +2061,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1964 2061
1965 h_addr = crt_reg.hor_addr; 2062 h_addr = crt_reg.hor_addr;
1966 v_addr = crt_reg.ver_addr; 2063 v_addr = crt_reg.ver_addr;
1967
1968 /* update polarity for CRT timing */
1969 if (crt_table[index].h_sync_polarity == NEGATIVE)
1970 polarity |= BIT6;
1971 if (crt_table[index].v_sync_polarity == NEGATIVE)
1972 polarity |= BIT7;
1973 via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1974
1975 if (set_iga == IGA1) { 2064 if (set_iga == IGA1) {
1976 viafb_unlock_crt(); 2065 viafb_unlock_crt();
1977 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */ 2066 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
@@ -2004,7 +2093,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
2004 2093
2005} 2094}
2006 2095
2007void viafb_init_chip_info(int chip_type) 2096void __devinit viafb_init_chip_info(int chip_type)
2008{ 2097{
2009 init_gfx_chip_info(chip_type); 2098 init_gfx_chip_info(chip_type);
2010 init_tmds_chip_info(); 2099 init_tmds_chip_info();
@@ -2071,7 +2160,7 @@ void viafb_update_device_setting(int hres, int vres,
2071 } 2160 }
2072} 2161}
2073 2162
2074static void init_gfx_chip_info(int chip_type) 2163static void __devinit init_gfx_chip_info(int chip_type)
2075{ 2164{
2076 u8 tmp; 2165 u8 tmp;
2077 2166
@@ -2111,6 +2200,7 @@ static void init_gfx_chip_info(int chip_type)
2111 switch (viaparinfo->chip_info->gfx_chip_name) { 2200 switch (viaparinfo->chip_info->gfx_chip_name) {
2112 case UNICHROME_VX800: 2201 case UNICHROME_VX800:
2113 case UNICHROME_VX855: 2202 case UNICHROME_VX855:
2203 case UNICHROME_VX900:
2114 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; 2204 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2115 break; 2205 break;
2116 case UNICHROME_K8M890: 2206 case UNICHROME_K8M890:
@@ -2123,7 +2213,7 @@ static void init_gfx_chip_info(int chip_type)
2123 } 2213 }
2124} 2214}
2125 2215
2126static void init_tmds_chip_info(void) 2216static void __devinit init_tmds_chip_info(void)
2127{ 2217{
2128 viafb_tmds_trasmitter_identify(); 2218 viafb_tmds_trasmitter_identify();
2129 2219
@@ -2168,7 +2258,7 @@ static void init_tmds_chip_info(void)
2168 &viaparinfo->shared->tmds_setting_info); 2258 &viaparinfo->shared->tmds_setting_info);
2169} 2259}
2170 2260
2171static void init_lvds_chip_info(void) 2261static void __devinit init_lvds_chip_info(void)
2172{ 2262{
2173 viafb_lvds_trasmitter_identify(); 2263 viafb_lvds_trasmitter_identify();
2174 viafb_init_lcd_size(); 2264 viafb_init_lcd_size();
@@ -2202,7 +2292,7 @@ static void init_lvds_chip_info(void)
2202 viaparinfo->chip_info->lvds_chip_info.output_interface); 2292 viaparinfo->chip_info->lvds_chip_info.output_interface);
2203} 2293}
2204 2294
2205void viafb_init_dac(int set_iga) 2295void __devinit viafb_init_dac(int set_iga)
2206{ 2296{
2207 int i; 2297 int i;
2208 u8 tmp; 2298 u8 tmp;
@@ -2275,11 +2365,24 @@ static void set_display_channel(void)
2275 } 2365 }
2276} 2366}
2277 2367
2368static u8 get_sync(struct fb_info *info)
2369{
2370 u8 polarity = 0;
2371
2372 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
2373 polarity |= VIA_HSYNC_NEGATIVE;
2374 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
2375 polarity |= VIA_VSYNC_NEGATIVE;
2376 return polarity;
2377}
2378
2278int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, 2379int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2279 struct VideoModeTable *vmode_tbl1, int video_bpp1) 2380 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2280{ 2381{
2281 int i, j; 2382 int i, j;
2282 int port; 2383 int port;
2384 u32 devices = viaparinfo->shared->iga1_devices
2385 | viaparinfo->shared->iga2_devices;
2283 u8 value, index, mask; 2386 u8 value, index, mask;
2284 struct crt_mode_table *crt_timing; 2387 struct crt_mode_table *crt_timing;
2285 struct crt_mode_table *crt_timing1 = NULL; 2388 struct crt_mode_table *crt_timing1 = NULL;
@@ -2322,11 +2425,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2322 break; 2425 break;
2323 2426
2324 case UNICHROME_VX855: 2427 case UNICHROME_VX855:
2428 case UNICHROME_VX900:
2325 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); 2429 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2326 break; 2430 break;
2327 } 2431 }
2328 2432
2329 device_off(); 2433 device_off();
2434 via_set_state(devices, VIA_STATE_OFF);
2330 2435
2331 /* Fill VPIT Parameters */ 2436 /* Fill VPIT Parameters */
2332 /* Write Misc Register */ 2437 /* Write Misc Register */
@@ -2337,7 +2442,6 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2337 via_write_reg(VIASR, i, VPIT.SR[i - 1]); 2442 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2338 2443
2339 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); 2444 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2340 viafb_set_iga_path();
2341 2445
2342 /* Write CRTC */ 2446 /* Write CRTC */
2343 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1); 2447 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
@@ -2377,6 +2481,13 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2377 via_set_primary_color_depth(viaparinfo->depth); 2481 via_set_primary_color_depth(viaparinfo->depth);
2378 via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth 2482 via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2379 : viaparinfo->depth); 2483 : viaparinfo->depth);
2484 via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2485 via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2486 if (viaparinfo->shared->iga2_devices)
2487 enable_second_display_channel();
2488 else
2489 disable_second_display_channel();
2490
2380 /* Update Refresh Rate Setting */ 2491 /* Update Refresh Rate Setting */
2381 2492
2382 /* Clear On Screen */ 2493 /* Clear On Screen */
@@ -2394,8 +2505,6 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2394 viaparinfo->crt_setting_info->iga_path); 2505 viaparinfo->crt_setting_info->iga_path);
2395 } 2506 }
2396 2507
2397 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2398
2399 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode 2508 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2400 to 8 alignment (1368),there is several pixels (2 pixels) 2509 to 8 alignment (1368),there is several pixels (2 pixels)
2401 on right side of screen. */ 2510 on right side of screen. */
@@ -2482,10 +2591,16 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2482 viafb_DeviceStatus = CRT_Device; 2591 viafb_DeviceStatus = CRT_Device;
2483 } 2592 }
2484 device_on(); 2593 device_on();
2594 if (!viafb_dual_fb)
2595 via_set_sync_polarity(devices, get_sync(viafbinfo));
2596 else {
2597 via_set_sync_polarity(viaparinfo->shared->iga1_devices,
2598 get_sync(viafbinfo));
2599 via_set_sync_polarity(viaparinfo->shared->iga2_devices,
2600 get_sync(viafbinfo1));
2601 }
2485 2602
2486 if (viafb_SAMM_ON == 1) 2603 via_set_state(devices, VIA_STATE_ON);
2487 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2488
2489 device_screen_on(); 2604 device_screen_on();
2490 return 1; 2605 return 1;
2491} 2606}
@@ -2526,31 +2641,18 @@ int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2526 2641
2527static void device_off(void) 2642static void device_off(void)
2528{ 2643{
2529 viafb_crt_disable();
2530 viafb_dvi_disable(); 2644 viafb_dvi_disable();
2531 viafb_lcd_disable(); 2645 viafb_lcd_disable();
2532} 2646}
2533 2647
2534static void device_on(void) 2648static void device_on(void)
2535{ 2649{
2536 if (viafb_CRT_ON == 1)
2537 viafb_crt_enable();
2538 if (viafb_DVI_ON == 1) 2650 if (viafb_DVI_ON == 1)
2539 viafb_dvi_enable(); 2651 viafb_dvi_enable();
2540 if (viafb_LCD_ON == 1) 2652 if (viafb_LCD_ON == 1)
2541 viafb_lcd_enable(); 2653 viafb_lcd_enable();
2542} 2654}
2543 2655
2544void viafb_crt_disable(void)
2545{
2546 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2547}
2548
2549void viafb_crt_enable(void)
2550{
2551 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2552}
2553
2554static void enable_second_display_channel(void) 2656static void enable_second_display_channel(void)
2555{ 2657{
2556 /* to enable second display channel. */ 2658 /* to enable second display channel. */
@@ -2567,7 +2669,6 @@ static void disable_second_display_channel(void)
2567 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); 2669 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2568} 2670}
2569 2671
2570
2571void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ 2672void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2572 *p_gfx_dpa_setting) 2673 *p_gfx_dpa_setting)
2573{ 2674{
@@ -2652,4 +2753,9 @@ void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2652 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); 2753 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2653 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; 2754 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2654 var->vsync_len = crt_reg.ver_sync_end; 2755 var->vsync_len = crt_reg.ver_sync_end;
2756 var->sync = 0;
2757 if (crt_timing[index].h_sync_polarity == POSITIVE)
2758 var->sync |= FB_SYNC_HOR_HIGH_ACT;
2759 if (crt_timing[index].v_sync_polarity == POSITIVE)
2760 var->sync |= FB_SYNC_VERT_HIGH_ACT;
2655} 2761}
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index c44399895294..668d534542ef 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -22,6 +22,8 @@
22#ifndef __HW_H__ 22#ifndef __HW_H__
23#define __HW_H__ 23#define __HW_H__
24 24
25#include <linux/seq_file.h>
26
25#include "viamode.h" 27#include "viamode.h"
26#include "global.h" 28#include "global.h"
27#include "via_modesetting.h" 29#include "via_modesetting.h"
@@ -30,6 +32,25 @@
30#define viafb_write_reg(i, p, d) via_write_reg(p, i, d) 32#define viafb_write_reg(i, p, d) via_write_reg(p, i, d)
31#define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m) 33#define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m)
32 34
35/* VIA output devices */
36#define VIA_LDVP0 0x00000001
37#define VIA_LDVP1 0x00000002
38#define VIA_DVP0 0x00000004
39#define VIA_CRT 0x00000010
40#define VIA_DVP1 0x00000020
41#define VIA_LVDS1 0x00000040
42#define VIA_LVDS2 0x00000080
43
44/* VIA output device power states */
45#define VIA_STATE_ON 0
46#define VIA_STATE_STANDBY 1
47#define VIA_STATE_SUSPEND 2
48#define VIA_STATE_OFF 3
49
50/* VIA output device sync polarity */
51#define VIA_HSYNC_NEGATIVE 0x01
52#define VIA_VSYNC_NEGATIVE 0x02
53
33/*************************************************** 54/***************************************************
34* Definition IGA1 Design Method of CRTC Registers * 55* Definition IGA1 Design Method of CRTC Registers *
35****************************************************/ 56****************************************************/
@@ -341,6 +362,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
341#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 362#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
342#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 363#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
343 364
365/* For VT3410 */
366#define VX900_IGA1_FIFO_MAX_DEPTH 400
367#define VX900_IGA1_FIFO_THRESHOLD 320
368#define VX900_IGA1_FIFO_HIGH_THRESHOLD 320
369#define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
370
371#define VX900_IGA2_FIFO_MAX_DEPTH 192
372#define VX900_IGA2_FIFO_THRESHOLD 160
373#define VX900_IGA2_FIFO_HIGH_THRESHOLD 160
374#define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
375
344#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 376#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
345#define IGA1_FIFO_THRESHOLD_REG_NUM 2 377#define IGA1_FIFO_THRESHOLD_REG_NUM 2
346#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 378#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
@@ -858,6 +890,8 @@ struct iga2_crtc_timing {
858#define VX800_FUNCTION3 0x3353 890#define VX800_FUNCTION3 0x3353
859/* VT3409 chipset*/ 891/* VT3409 chipset*/
860#define VX855_FUNCTION3 0x3409 892#define VX855_FUNCTION3 0x3409
893/* VT3410 chipset*/
894#define VX900_FUNCTION3 0x3410
861 895
862#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) 896#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
863 897
@@ -873,6 +907,11 @@ struct pci_device_id_info {
873 u32 chip_index; 907 u32 chip_index;
874}; 908};
875 909
910struct via_device_mapping {
911 u32 device;
912 const char *name;
913};
914
876extern unsigned int viafb_second_virtual_xres; 915extern unsigned int viafb_second_virtual_xres;
877extern int viafb_SAMM_ON; 916extern int viafb_SAMM_ON;
878extern int viafb_dual_fb; 917extern int viafb_dual_fb;
@@ -881,9 +920,6 @@ extern int viafb_LCD_ON;
881extern int viafb_DVI_ON; 920extern int viafb_DVI_ON;
882extern int viafb_hotplug; 921extern int viafb_hotplug;
883 922
884void viafb_set_output_path(int device, int set_iga,
885 int output_interface);
886
887void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 923void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
888 struct VideoModeTable *video_mode, int bpp_byte, int set_iga); 924 struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
889 925
@@ -891,8 +927,11 @@ void viafb_set_vclock(u32 CLK, int set_iga);
891void viafb_load_reg(int timing_value, int viafb_load_reg_num, 927void viafb_load_reg(int timing_value, int viafb_load_reg_num,
892 struct io_register *reg, 928 struct io_register *reg,
893 int io_type); 929 int io_type);
894void viafb_crt_disable(void); 930void via_set_source(u32 devices, u8 iga);
895void viafb_crt_enable(void); 931void via_set_state(u32 devices, u8 state);
932void via_set_sync_polarity(u32 devices, u8 polarity);
933u32 via_parse_odev(char *input, char **end);
934void via_odev_to_seq(struct seq_file *m, u32 odev);
896void init_ad9389(void); 935void init_ad9389(void);
897/* Access I/O Function */ 936/* Access I/O Function */
898void viafb_lock_crt(void); 937void viafb_lock_crt(void);
@@ -908,8 +947,8 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
908 struct VideoModeTable *vmode_tbl1, int video_bpp1); 947 struct VideoModeTable *vmode_tbl1, int video_bpp1);
909void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, 948void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
910 struct VideoModeTable *vmode_tbl); 949 struct VideoModeTable *vmode_tbl);
911void viafb_init_chip_info(int chip_type); 950void __devinit viafb_init_chip_info(int chip_type);
912void viafb_init_dac(int set_iga); 951void __devinit viafb_init_dac(int set_iga);
913int viafb_get_pixclock(int hres, int vres, int vmode_refresh); 952int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
914int viafb_get_refresh(int hres, int vres, u32 float_refresh); 953int viafb_get_refresh(int hres, int vres, u32 float_refresh);
915void viafb_update_device_setting(int hres, int vres, int bpp, 954void viafb_update_device_setting(int hres, int vres, int bpp,
diff --git a/drivers/video/via/ioctl.c b/drivers/video/via/ioctl.c
index 4d553d0b8d7a..ea1c51428823 100644
--- a/drivers/video/via/ioctl.c
+++ b/drivers/video/via/ioctl.c
@@ -94,6 +94,7 @@ int viafb_ioctl_hotplug(int hres, int vres, int bpp)
94 viafb_CRT_ON = 0; 94 viafb_CRT_ON = 0;
95 viafb_LCD_ON = 0; 95 viafb_LCD_ON = 0;
96 viafb_DeviceStatus = DVI_Device; 96 viafb_DeviceStatus = DVI_Device;
97 viafb_set_iga_path();
97 return viafb_DeviceStatus; 98 return viafb_DeviceStatus;
98 } 99 }
99 status = 1; 100 status = 1;
@@ -107,6 +108,7 @@ int viafb_ioctl_hotplug(int hres, int vres, int bpp)
107 viafb_LCD_ON = 0; 108 viafb_LCD_ON = 0;
108 109
109 viafb_DeviceStatus = CRT_Device; 110 viafb_DeviceStatus = CRT_Device;
111 viafb_set_iga_path();
110 return viafb_DeviceStatus; 112 return viafb_DeviceStatus;
111 } 113 }
112 114
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index fc25ae30c5f6..3425c3969806 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -21,10 +21,16 @@
21#include <linux/via-core.h> 21#include <linux/via-core.h>
22#include <linux/via_i2c.h> 22#include <linux/via_i2c.h>
23#include "global.h" 23#include "global.h"
24#include "lcdtbl.h"
25 24
26#define viafb_compact_res(x, y) (((x)<<16)|(y)) 25#define viafb_compact_res(x, y) (((x)<<16)|(y))
27 26
27/* CLE266 Software Power Sequence */
28/* {Mask}, {Data}, {Delay} */
29int PowerSequenceOn[3][3] = { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06},
30 {0x19, 0x1FE, 0x01} };
31int PowerSequenceOff[3][3] = { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00},
32 {0xD2, 0x19, 0x01} };
33
28static struct _lcd_scaling_factor lcd_scaling_factor = { 34static struct _lcd_scaling_factor lcd_scaling_factor = {
29 /* LCD Horizontal Scaling Factor Register */ 35 /* LCD Horizontal Scaling Factor Register */
30 {LCD_HOR_SCALING_FACTOR_REG_NUM, 36 {LCD_HOR_SCALING_FACTOR_REG_NUM,
@@ -42,7 +48,7 @@ static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
42 48
43static int check_lvds_chip(int device_id_subaddr, int device_id); 49static int check_lvds_chip(int device_id_subaddr, int device_id);
44static bool lvds_identify_integratedlvds(void); 50static bool lvds_identify_integratedlvds(void);
45static void fp_id_to_vindex(int panel_id); 51static void __devinit fp_id_to_vindex(int panel_id);
46static int lvds_register_read(int index); 52static int lvds_register_read(int index);
47static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, 53static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
48 int panel_vres); 54 int panel_vres);
@@ -84,7 +90,7 @@ static int check_lvds_chip(int device_id_subaddr, int device_id)
84 return FAIL; 90 return FAIL;
85} 91}
86 92
87void viafb_init_lcd_size(void) 93void __devinit viafb_init_lcd_size(void)
88{ 94{
89 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n"); 95 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
90 96
@@ -144,7 +150,7 @@ static bool lvds_identify_integratedlvds(void)
144 return true; 150 return true;
145} 151}
146 152
147int viafb_lvds_trasmitter_identify(void) 153int __devinit viafb_lvds_trasmitter_identify(void)
148{ 154{
149 if (viafb_lvds_identify_vt1636(VIA_PORT_31)) { 155 if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
150 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31; 156 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
@@ -185,7 +191,7 @@ int viafb_lvds_trasmitter_identify(void)
185 return FAIL; 191 return FAIL;
186} 192}
187 193
188static void fp_id_to_vindex(int panel_id) 194static void __devinit fp_id_to_vindex(int panel_id)
189{ 195{
190 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n"); 196 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
191 197
@@ -436,6 +442,7 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
436 case UNICHROME_CN750: 442 case UNICHROME_CN750:
437 case UNICHROME_VX800: 443 case UNICHROME_VX800:
438 case UNICHROME_VX855: 444 case UNICHROME_VX855:
445 case UNICHROME_VX900:
439 reg_value = 446 reg_value =
440 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres); 447 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
441 /* Horizontal scaling enabled */ 448 /* Horizontal scaling enabled */
@@ -479,6 +486,7 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
479 case UNICHROME_CN750: 486 case UNICHROME_CN750:
480 case UNICHROME_VX800: 487 case UNICHROME_VX800:
481 case UNICHROME_VX855: 488 case UNICHROME_VX855:
489 case UNICHROME_VX900:
482 reg_value = 490 reg_value =
483 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres); 491 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
484 /* Vertical scaling enabled */ 492 /* Vertical scaling enabled */
@@ -655,9 +663,6 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
655 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); 663 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
656 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); 664 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
657 viafb_set_vclock(pll_D_N, set_iga); 665 viafb_set_vclock(pll_D_N, set_iga);
658
659 viafb_set_output_path(DEVICE_LCD, set_iga,
660 plvds_chip_info->output_interface);
661 lcd_patch_skew(plvds_setting_info, plvds_chip_info); 666 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
662 667
663 /* If K8M800, enable LCD Prefetch Mode. */ 668 /* If K8M800, enable LCD Prefetch Mode. */
@@ -700,9 +705,6 @@ static void integrated_lvds_disable(struct lvds_setting_information
700 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); 705 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
701 } 706 }
702 707
703 /* Turn DFP High/Low Pad off. */
704 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
705
706 /* Power off LVDS channel. */ 708 /* Power off LVDS channel. */
707 switch (plvds_chip_info->output_interface) { 709 switch (plvds_chip_info->output_interface) {
708 case INTERFACE_LVDS0: 710 case INTERFACE_LVDS0:
@@ -758,9 +760,6 @@ static void integrated_lvds_enable(struct lvds_setting_information
758 break; 760 break;
759 } 761 }
760 762
761 /* Turn DFP High/Low pad on. */
762 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
763
764 /* Power on LVDS channel. */ 763 /* Power on LVDS channel. */
765 switch (plvds_chip_info->output_interface) { 764 switch (plvds_chip_info->output_interface) {
766 case INTERFACE_LVDS0: 765 case INTERFACE_LVDS0:
@@ -809,29 +808,48 @@ void viafb_lcd_disable(void)
809 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info, 808 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
810 &viaparinfo->chip_info->lvds_chip_info); 809 &viaparinfo->chip_info->lvds_chip_info);
811 } else { 810 } else {
812 /* DFP-HL pad off */
813 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
814 /* Backlight off */ 811 /* Backlight off */
815 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20); 812 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
816 /* 24 bit DI data paht off */ 813 /* 24 bit DI data paht off */
817 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80); 814 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
818 /* Simultaneout disabled */
819 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
820 } 815 }
821 816
822 /* Disable expansion bit */ 817 /* Disable expansion bit */
823 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01); 818 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
824 /* CRT path set to IGA1 */
825 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
826 /* Simultaneout disabled */ 819 /* Simultaneout disabled */
827 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08); 820 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
828 /* IGA2 path disabled */ 821}
829 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
830 822
823static void set_lcd_output_path(int set_iga, int output_interface)
824{
825 switch (output_interface) {
826 case INTERFACE_DFP:
827 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
828 || (UNICHROME_P4M890 ==
829 viaparinfo->chip_info->gfx_chip_name))
830 viafb_write_reg_mask(CR97, VIACR, 0x84,
831 BIT7 + BIT2 + BIT1 + BIT0);
832 case INTERFACE_DVP0:
833 case INTERFACE_DVP1:
834 case INTERFACE_DFP_HIGH:
835 case INTERFACE_DFP_LOW:
836 if (set_iga == IGA2)
837 viafb_write_reg(CR91, VIACR, 0x00);
838 break;
839 }
831} 840}
832 841
833void viafb_lcd_enable(void) 842void viafb_lcd_enable(void)
834{ 843{
844 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
845 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
846 set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
847 viaparinfo->chip_info->lvds_chip_info.output_interface);
848 if (viafb_LCD2_ON)
849 set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
850 viaparinfo->chip_info->
851 lvds_chip_info2.output_interface);
852
835 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { 853 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
836 /* DI1 pad on */ 854 /* DI1 pad on */
837 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30); 855 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
@@ -855,39 +873,13 @@ void viafb_lcd_enable(void)
855 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info, 873 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
856 &viaparinfo->chip_info->lvds_chip_info); 874 &viaparinfo->chip_info->lvds_chip_info);
857 } else { 875 } else {
858 /* DFP-HL pad on */
859 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
860 /* Backlight on */ 876 /* Backlight on */
861 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20); 877 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
862 /* 24 bit DI data paht on */ 878 /* 24 bit DI data paht on */
863 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80); 879 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
864
865 /* Set data source selection bit by iga path */
866 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
867 /* DFP-H set to IGA1 */
868 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
869 /* DFP-L set to IGA1 */
870 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
871 } else {
872 /* DFP-H set to IGA2 */
873 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
874 /* DFP-L set to IGA2 */
875 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
876 }
877 /* LCD enabled */ 880 /* LCD enabled */
878 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48); 881 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
879 } 882 }
880
881 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
882 /* CRT path set to IGA2 */
883 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
884 /* IGA2 path disabled */
885 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
886 /* IGA2 path enabled */
887 } else { /* IGA2 */
888 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
889 }
890
891} 883}
892 884
893static void lcd_powersequence_off(void) 885static void lcd_powersequence_off(void)
@@ -993,7 +985,7 @@ static void check_diport_of_integrated_lvds(
993 plvds_chip_info->output_interface); 985 plvds_chip_info->output_interface);
994} 986}
995 987
996void viafb_init_lvds_output_interface(struct lvds_chip_information 988void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
997 *plvds_chip_info, 989 *plvds_chip_info,
998 struct lvds_setting_information 990 struct lvds_setting_information
999 *plvds_setting_info) 991 *plvds_setting_info)
diff --git a/drivers/video/via/lcd.h b/drivers/video/via/lcd.h
index b348efc360b8..c7909fe29550 100644
--- a/drivers/video/via/lcd.h
+++ b/drivers/video/via/lcd.h
@@ -71,15 +71,15 @@ void viafb_enable_lvds_vt1636(struct lvds_setting_information
71 struct lvds_chip_information *plvds_chip_info); 71 struct lvds_chip_information *plvds_chip_info);
72void viafb_lcd_disable(void); 72void viafb_lcd_disable(void);
73void viafb_lcd_enable(void); 73void viafb_lcd_enable(void);
74void viafb_init_lcd_size(void); 74void __devinit viafb_init_lcd_size(void);
75void viafb_init_lvds_output_interface(struct lvds_chip_information 75void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
76 *plvds_chip_info, 76 *plvds_chip_info,
77 struct lvds_setting_information 77 struct lvds_setting_information
78 *plvds_setting_info); 78 *plvds_setting_info);
79void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, 79void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
80 struct lvds_setting_information *plvds_setting_info, 80 struct lvds_setting_information *plvds_setting_info,
81 struct lvds_chip_information *plvds_chip_info); 81 struct lvds_chip_information *plvds_chip_info);
82int viafb_lvds_trasmitter_identify(void); 82int __devinit viafb_lvds_trasmitter_identify(void);
83void viafb_init_lvds_output_interface(struct lvds_chip_information 83void viafb_init_lvds_output_interface(struct lvds_chip_information
84 *plvds_chip_info, 84 *plvds_chip_info,
85 struct lvds_setting_information 85 struct lvds_setting_information
diff --git a/drivers/video/via/lcdtbl.h b/drivers/video/via/lcdtbl.h
deleted file mode 100644
index 6f3dd800be59..000000000000
--- a/drivers/video/via/lcdtbl.h
+++ /dev/null
@@ -1,591 +0,0 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __LCDTBL_H__
22#define __LCDTBL_H__
23
24#include "share.h"
25
26/* CLE266 Software Power Sequence */
27/* {Mask}, {Data}, {Delay} */
28int PowerSequenceOn[3][3] =
29 { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01} };
30int PowerSequenceOff[3][3] =
31 { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01} };
32
33/* ++++++ P880 ++++++ */
34/* Panel 1600x1200 */
35struct io_reg P880_LCD_RES_6X4_16X12[] = {
36 /*IGA2 Horizontal Total */
37 {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08},
38 /*IGA2 Horizontal Blank End */
39 {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00},
40 {VIACR, CR5D, 0x40, 0x40},
41 /*IGA2 Horizontal Total Shadow */
42 {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00},
43 /*IGA2 Horizontal Blank End Shadow */
44 {VIACR, CR6E, 0xFF, 0x5E},
45 /*IGA2 Offset */
46 {VIACR, CR66, 0xFF, 0xD6}, {VIACR, CR67, 0x03, 0x00},
47 /*VCLK*/ {VIASR, SR44, 0xFF, 0x7D}, {VIASR, SR45, 0xFF, 0x8C},
48 {VIASR, SR46, 0xFF, 0x02}
49
50};
51
52#define NUM_TOTAL_P880_LCD_RES_6X4_16X12 ARRAY_SIZE(P880_LCD_RES_6X4_16X12)
53
54struct io_reg P880_LCD_RES_7X4_16X12[] = {
55 /*IGA2 Horizontal Total */
56 {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08},
57 /*IGA2 Horizontal Blank End */
58 {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00},
59 {VIACR, CR5D, 0x40, 0x40},
60 /*IGA2 Horizontal Total Shadow */
61 {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00},
62 /*IGA2 Horizontal Blank End Shadow */
63 {VIACR, CR6E, 0xFF, 0x78},
64 /*IGA2 Offset */
65 {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00},
66 /*VCLK*/ {VIASR, SR44, 0xFF, 0x78}, {VIASR, SR45, 0xFF, 0x8C},
67 {VIASR, SR46, 0xFF, 0x01}
68
69};
70
71#define NUM_TOTAL_P880_LCD_RES_7X4_16X12 ARRAY_SIZE(P880_LCD_RES_7X4_16X12)
72
73struct io_reg P880_LCD_RES_8X6_16X12[] = {
74 /*IGA2 Horizontal Total */
75 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
76 /*IGA2 Horizontal Blank End */
77 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
78 {VIACR, CR5D, 0x40, 0x40},
79 /*IGA2 Horizontal Total Shadow */
80 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00},
81 /*IGA2 Horizontal Blank End Shadow */
82 {VIACR, CR6E, 0xFF, 0x83},
83 /*IGA2 Offset */
84 {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00},
85 /*VCLK*/ {VIASR, SR44, 0xFF, 0x6D}, {VIASR, SR45, 0xFF, 0x88},
86 {VIASR, SR46, 0xFF, 0x03}
87
88};
89
90#define NUM_TOTAL_P880_LCD_RES_8X6_16X12 ARRAY_SIZE(P880_LCD_RES_8X6_16X12)
91
92struct io_reg P880_LCD_RES_10X7_16X12[] = {
93 /*IGA2 Horizontal Total */
94 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
95 /*IGA2 Horizontal Blank End */
96 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
97 {VIACR, CR5D, 0x40, 0x40},
98 /*IGA2 Horizontal Total Shadow */
99 {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00},
100 /*IGA2 Horizontal Blank End Shadow */
101 {VIACR, CR6E, 0xFF, 0xAF},
102 /*IGA2 Offset */
103 {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00},
104 /*VCLK*/ {VIASR, SR44, 0xFF, 0x92}, {VIASR, SR45, 0xFF, 0x88},
105 {VIASR, SR46, 0xFF, 0x03}
106
107};
108
109#define NUM_TOTAL_P880_LCD_RES_10X7_16X12 ARRAY_SIZE(P880_LCD_RES_10X7_16X12)
110
111struct io_reg P880_LCD_RES_12X10_16X12[] = {
112 /*IGA2 Horizontal Total */
113 {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08},
114 /*IGA2 Horizontal Blank End */
115 {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00},
116 {VIACR, CR5D, 0x40, 0x40},
117 /*IGA2 Horizontal Total Shadow */
118 {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00},
119 /*IGA2 Horizontal Blank End Shadow */
120 {VIACR, CR6E, 0xFF, 0xD4},
121 /*IGA2 Offset */
122 {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00},
123 /*VCLK*/ {VIASR, SR44, 0xFF, 0xF6}, {VIASR, SR45, 0xFF, 0x88},
124 {VIASR, SR46, 0xFF, 0x05}
125
126};
127
128#define NUM_TOTAL_P880_LCD_RES_12X10_16X12 ARRAY_SIZE(P880_LCD_RES_12X10_16X12)
129
130/* Panel 1400x1050 */
131struct io_reg P880_LCD_RES_6X4_14X10[] = {
132 /* 640x480 */
133 /* IGA2 Horizontal Total */
134 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
135 /* IGA2 Horizontal Blank End */
136 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
137 {VIACR, CR5D, 0x40, 0x24},
138 /* IGA2 Horizontal Total Shadow */
139 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44},
140 /* IGA2 Horizontal Blank End Shadow */
141 {VIACR, CR6E, 0xFF, 0x63},
142 /* IGA2 Offset */
143 {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00},
144 /* VCLK */
145 {VIASR, SR44, 0xFF, 0xC6}, {VIASR, SR45, 0xFF, 0x8C},
146 {VIASR, SR46, 0xFF, 0x05}
147};
148
149#define NUM_TOTAL_P880_LCD_RES_6X4_14X10 ARRAY_SIZE(P880_LCD_RES_6X4_14X10)
150
151struct io_reg P880_LCD_RES_8X6_14X10[] = {
152 /* 800x600 */
153 /* IGA2 Horizontal Total */
154 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
155 /* IGA2 Horizontal Blank End */
156 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
157 {VIACR, CR5D, 0x40, 0x24},
158 /* IGA2 Horizontal Total Shadow */
159 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44},
160 /* IGA2 Horizontal Blank End Shadow */
161 {VIACR, CR6E, 0xFF, 0x83},
162 /* IGA2 Offset */
163 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
164 /* VCLK */
165 {VIASR, SR44, 0xFF, 0x06}, {VIASR, SR45, 0xFF, 0x8D},
166 {VIASR, SR46, 0xFF, 0x05}
167};
168
169#define NUM_TOTAL_P880_LCD_RES_8X6_14X10 ARRAY_SIZE(P880_LCD_RES_8X6_14X10)
170
171/* ++++++ K400 ++++++ */
172/* Panel 1600x1200 */
173struct io_reg K400_LCD_RES_6X4_16X12[] = {
174 /*IGA2 Horizontal Total */
175 {VIACR, CR50, 0xFF, 0x73}, {VIACR, CR55, 0x0F, 0x08},
176 /*IGA2 Horizontal Blank End */
177 {VIACR, CR53, 0xFF, 0x73}, {VIACR, CR54, 0x38, 0x00},
178 {VIACR, CR5D, 0x40, 0x40},
179 /*IGA2 Horizontal Total Shadow */
180 {VIACR, CR6D, 0xFF, 0x5A}, {VIACR, CR71, 0x08, 0x00},
181 /*IGA2 Horizontal Blank End Shadow */
182 {VIACR, CR6E, 0xFF, 0x5E},
183 /*IGA2 Offset */
184 {VIACR, CR66, 0xFF, 0xDA}, {VIACR, CR67, 0x03, 0x00},
185 /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x7F}
186};
187
188#define NUM_TOTAL_K400_LCD_RES_6X4_16X12 ARRAY_SIZE(K400_LCD_RES_6X4_16X12)
189
190struct io_reg K400_LCD_RES_7X4_16X12[] = {
191 /*IGA2 Horizontal Total */
192 {VIACR, CR50, 0xFF, 0x67}, {VIACR, CR55, 0x0F, 0x08},
193 /*IGA2 Horizontal Blank End */
194 {VIACR, CR53, 0xFF, 0x67}, {VIACR, CR54, 0x38, 0x00},
195 {VIACR, CR5D, 0x40, 0x40},
196 /*IGA2 Horizontal Total Shadow */
197 {VIACR, CR6D, 0xFF, 0x74}, {VIACR, CR71, 0x08, 0x00},
198 /*IGA2 Horizontal Blank End Shadow */
199 {VIACR, CR6E, 0xFF, 0x78},
200 /*IGA2 Offset */
201 {VIACR, CR66, 0xFF, 0xF5}, {VIACR, CR67, 0x03, 0x00},
202 /*VCLK*/ {VIASR, SR46, 0xFF, 0x46}, {VIASR, SR47, 0xFF, 0x3D}
203};
204
205#define NUM_TOTAL_K400_LCD_RES_7X4_16X12 ARRAY_SIZE(K400_LCD_RES_7X4_16X12)
206
207struct io_reg K400_LCD_RES_8X6_16X12[] = {
208 /*IGA2 Horizontal Total */
209 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
210 /*IGA2 Horizontal Blank End */
211 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
212 {VIACR, CR5D, 0x40, 0x40},
213 /*IGA2 Horizontal Total Shadow */
214 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x00},
215 /*IGA2 Horizontal Blank End Shadow */
216 {VIACR, CR6E, 0xFF, 0x83},
217 /*IGA2 Offset */
218 {VIACR, CR66, 0xFF, 0xE1}, {VIACR, CR67, 0x03, 0x00},
219 /*VCLK*/ {VIASR, SR46, 0xFF, 0x85}, {VIASR, SR47, 0xFF, 0x6F}
220};
221
222#define NUM_TOTAL_K400_LCD_RES_8X6_16X12 ARRAY_SIZE(K400_LCD_RES_8X6_16X12)
223
224struct io_reg K400_LCD_RES_10X7_16X12[] = {
225 /*IGA2 Horizontal Total */
226 {VIACR, CR50, 0xFF, 0x65}, {VIACR, CR55, 0x0F, 0x08},
227 /*IGA2 Horizontal Blank End */
228 {VIACR, CR53, 0xFF, 0x65}, {VIACR, CR54, 0x38, 0x00},
229 {VIACR, CR5D, 0x40, 0x40},
230 /*IGA2 Horizontal Total Shadow */
231 {VIACR, CR6D, 0xFF, 0xAB}, {VIACR, CR71, 0x08, 0x00},
232 /*IGA2 Horizontal Blank End Shadow */
233 {VIACR, CR6E, 0xFF, 0xAF},
234 /*IGA2 Offset */
235 {VIACR, CR66, 0xFF, 0xF0}, {VIACR, CR67, 0x03, 0x00},
236 /*VCLK*/ {VIASR, SR46, 0xFF, 0x45}, {VIASR, SR47, 0xFF, 0x4A}
237};
238
239#define NUM_TOTAL_K400_LCD_RES_10X7_16X12 ARRAY_SIZE(K400_LCD_RES_10X7_16X12)
240
241struct io_reg K400_LCD_RES_12X10_16X12[] = {
242 /*IGA2 Horizontal Total */
243 {VIACR, CR50, 0xFF, 0x7D}, {VIACR, CR55, 0x0F, 0x08},
244 /*IGA2 Horizontal Blank End */
245 {VIACR, CR53, 0xFF, 0x7D}, {VIACR, CR54, 0x38, 0x00},
246 {VIACR, CR5D, 0x40, 0x40},
247 /*IGA2 Horizontal Total Shadow */
248 {VIACR, CR6D, 0xFF, 0xD0}, {VIACR, CR71, 0x08, 0x00},
249 /*IGA2 Horizontal Blank End Shadow */
250 {VIACR, CR6E, 0xFF, 0xD4},
251 /*IGA2 Offset */
252 {VIACR, CR66, 0xFF, 0xFA}, {VIACR, CR67, 0x03, 0x00},
253 /*VCLK*/ {VIASR, SR46, 0xFF, 0x47}, {VIASR, SR47, 0xFF, 0x7C}
254};
255
256#define NUM_TOTAL_K400_LCD_RES_12X10_16X12 ARRAY_SIZE(K400_LCD_RES_12X10_16X12)
257
258/* Panel 1400x1050 */
259struct io_reg K400_LCD_RES_6X4_14X10[] = {
260 /* 640x400 */
261 /* IGA2 Horizontal Total */
262 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
263 /* IGA2 Horizontal Blank End */
264 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
265 {VIACR, CR5D, 0x40, 0x24},
266 /* IGA2 Horizontal Total Shadow */
267 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x44},
268 /* IGA2 Horizontal Blank End Shadow */
269 {VIACR, CR6E, 0xFF, 0x63},
270 /* IGA2 Offset */
271 {VIACR, CR66, 0xFF, 0xB4}, {VIACR, CR67, 0x03, 0x00},
272 /* VCLK */
273 {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19}
274};
275
276#define NUM_TOTAL_K400_LCD_RES_6X4_14X10 ARRAY_SIZE(K400_LCD_RES_6X4_14X10)
277
278struct io_reg K400_LCD_RES_8X6_14X10[] = {
279 /* 800x600 */
280 /* IGA2 Horizontal Total */
281 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
282 /* IGA2 Horizontal Blank End */
283 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
284 {VIACR, CR5D, 0x40, 0x24},
285 /* IGA2 Horizontal Total Shadow */
286 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x44},
287 /* IGA2 Horizontal Blank End Shadow */
288 {VIACR, CR6E, 0xFF, 0x83},
289 /* IGA2 Offset */
290 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
291 /* VCLK */
292 {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21}
293};
294
295#define NUM_TOTAL_K400_LCD_RES_8X6_14X10 ARRAY_SIZE(K400_LCD_RES_8X6_14X10)
296
297struct io_reg K400_LCD_RES_10X7_14X10[] = {
298 /* 1024x768 */
299 /* IGA2 Horizontal Total */
300 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
301 /* IGA2 Horizontal Blank End */
302 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
303 {VIACR, CR5D, 0x40, 0x24},
304 /* IGA2 Horizontal Total Shadow */
305 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44},
306 /* IGA2 Horizontal Blank End Shadow */
307 {VIACR, CR6E, 0xFF, 0xA7},
308 /* IGA2 Offset */
309 {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04},
310 /* VCLK */
311 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
312};
313
314#define NUM_TOTAL_K400_LCD_RES_10X7_14X10 ARRAY_SIZE(K400_LCD_RES_10X7_14X10)
315
316struct io_reg K400_LCD_RES_12X10_14X10[] = {
317 /* 1280x768, 1280x960, 1280x1024 */
318 /* IGA2 Horizontal Total */
319 {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56},
320 /* IGA2 Horizontal Blank End */
321 {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75},
322 {VIACR, CR5D, 0x40, 0x24},
323 /* IGA2 Horizontal Total Shadow */
324 {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44},
325 /* IGA2 Horizontal Blank End Shadow */
326 {VIACR, CR6E, 0xFF, 0xD2},
327 /* IGA2 Offset */
328 {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04},
329 /* VCLK */
330 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79}
331};
332
333#define NUM_TOTAL_K400_LCD_RES_12X10_14X10 ARRAY_SIZE(K400_LCD_RES_12X10_14X10)
334
335/* ++++++ K400 ++++++ */
336/* Panel 1366x768 */
337struct io_reg K400_LCD_RES_6X4_1366X7[] = {
338 /* 640x400 */
339 /* IGA2 Horizontal Total */
340 {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35},
341 /* IGA2 Horizontal Blank End */
342 {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B},
343 {VIACR, CR5D, 0x40, 0x13},
344 /* IGA2 Horizontal Total Shadow */
345 {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23},
346 /* IGA2 Horizontal Blank End Shadow */
347 {VIACR, CR6E, 0xFF, 0x64},
348 /* IGA2 Offset */
349 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
350 /* VCLK */
351 {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C}
352};
353
354#define NUM_TOTAL_K400_LCD_RES_6X4_1366X7 ARRAY_SIZE(K400_LCD_RES_6X4_1366X7)
355
356struct io_reg K400_LCD_RES_7X4_1366X7[] = {
357 /* IGA2 Horizontal Total */
358 {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35},
359 /* IGA2 Horizontal Blank End */
360 {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B},
361 {VIACR, CR5D, 0x40, 0x13},
362 /* IGA2 Horizontal Total Shadow */
363 {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23},
364 /* IGA2 Horizontal Blank End Shadow */
365 {VIACR, CR6E, 0xFF, 0x75},
366 /* IGA2 Offset */
367 {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00},
368 /* VCLK */
369 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10}
370};
371
372#define NUM_TOTAL_K400_LCD_RES_7X4_1366X7 ARRAY_SIZE(K400_LCD_RES_7X4_1366X7)
373
374struct io_reg K400_LCD_RES_8X6_1366X7[] = {
375 /* 800x600 */
376 /* IGA2 Horizontal Total */
377 {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35},
378 /* IGA2 Horizontal Blank End */
379 {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B},
380 {VIACR, CR5D, 0x40, 0x13},
381 /* IGA2 Horizontal Total Shadow */
382 {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23},
383 /* IGA2 Horizontal Blank End Shadow */
384 {VIACR, CR6E, 0xFF, 0x82},
385 /* IGA2 Offset */
386 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
387 /* VCLK */
388 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9}
389};
390
391#define NUM_TOTAL_K400_LCD_RES_8X6_1366X7 ARRAY_SIZE(K400_LCD_RES_8X6_1366X7)
392
393struct io_reg K400_LCD_RES_10X7_1366X7[] = {
394 /* 1024x768 */
395 /* IGA2 Horizontal Total */
396 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x56},
397 /* IGA2 Horizontal Blank End */
398 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x75},
399 {VIACR, CR5D, 0x40, 0x24},
400 /* IGA2 Horizontal Total Shadow */
401 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x44},
402 /* IGA2 Horizontal Blank End Shadow */
403 {VIACR, CR6E, 0xFF, 0xA7},
404 /* IGA2 Offset */
405 {VIACR, CR66, 0xFF, 0xC3}, {VIACR, CR67, 0x03, 0x04},
406 /* VCLK */
407 {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
408};
409
410#define NUM_TOTAL_K400_LCD_RES_10X7_1366X7 ARRAY_SIZE(K400_LCD_RES_10X7_1366X7)
411
412struct io_reg K400_LCD_RES_12X10_1366X7[] = {
413 /* 1280x768, 1280x960, 1280x1024 */
414 /* IGA2 Horizontal Total */
415 {VIACR, CR50, 0xFF, 0x97}, {VIACR, CR55, 0x0F, 0x56},
416 /* IGA2 Horizontal Blank End */
417 {VIACR, CR53, 0xFF, 0x97}, {VIACR, CR54, 0x38, 0x75},
418 {VIACR, CR5D, 0x40, 0x24},
419 /* IGA2 Horizontal Total Shadow */
420 {VIACR, CR6D, 0xFF, 0xCE}, {VIACR, CR71, 0x08, 0x44},
421 /* IGA2 Horizontal Blank End Shadow */
422 {VIACR, CR6E, 0xFF, 0xD2},
423 /* IGA2 Offset */
424 {VIACR, CR66, 0xFF, 0xC9}, {VIACR, CR67, 0x03, 0x04},
425 /* VCLK */
426 {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0x79}
427};
428
429#define NUM_TOTAL_K400_LCD_RES_12X10_1366X7\
430 ARRAY_SIZE(K400_LCD_RES_12X10_1366X7)
431
432/* ++++++ K400 ++++++ */
433/* Panel 1280x1024 */
434struct io_reg K400_LCD_RES_6X4_12X10[] = {
435 /*IGA2 Horizontal Total */
436 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
437 /*IGA2 Horizontal Blank End */
438 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
439 {VIACR, CR5D, 0x40, 0x1C},
440 /*IGA2 Horizontal Total Shadow */
441 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x34},
442 /*IGA2 Horizontal Blank End Shadow */
443 {VIACR, CR6E, 0xFF, 0x63},
444 /*IGA2 Offset */
445 {VIACR, CR66, 0xFF, 0xAA}, {VIACR, CR67, 0x03, 0x00},
446 /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x19}
447};
448
449#define NUM_TOTAL_K400_LCD_RES_6X4_12X10 ARRAY_SIZE(K400_LCD_RES_6X4_12X10)
450
451struct io_reg K400_LCD_RES_7X4_12X10[] = {
452 /*IGA2 Horizontal Total */
453 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
454 /*IGA2 Horizontal Blank End */
455 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
456 {VIACR, CR5D, 0x40, 0x1C},
457 /*IGA2 Horizontal Total Shadow */
458 {VIACR, CR6D, 0xFF, 0x68}, {VIACR, CR71, 0x08, 0x34},
459 /*IGA2 Horizontal Blank End Shadow */
460 {VIACR, CR6E, 0xFF, 0x6C},
461 /*IGA2 Offset */
462 {VIACR, CR66, 0xFF, 0xA8}, {VIACR, CR67, 0x03, 0x00},
463 /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0xED}
464};
465
466#define NUM_TOTAL_K400_LCD_RES_7X4_12X10 ARRAY_SIZE(K400_LCD_RES_7X4_12X10)
467
468struct io_reg K400_LCD_RES_8X6_12X10[] = {
469 /*IGA2 Horizontal Total */
470 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
471 /*IGA2 Horizontal Blank End */
472 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
473 {VIACR, CR5D, 0x40, 0x1C},
474 /*IGA2 Horizontal Total Shadow */
475 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x34},
476 /*IGA2 Horizontal Blank End Shadow */
477 {VIACR, CR6E, 0xFF, 0x83},
478 /*IGA2 Offset */
479 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x00},
480 /*VCLK*/ {VIASR, SR46, 0xFF, 0x07}, {VIASR, SR47, 0xFF, 0x21}
481};
482
483#define NUM_TOTAL_K400_LCD_RES_8X6_12X10 ARRAY_SIZE(K400_LCD_RES_8X6_12X10)
484
485struct io_reg K400_LCD_RES_10X7_12X10[] = {
486 /*IGA2 Horizontal Total */
487 {VIACR, CR50, 0xFF, 0x9D}, {VIACR, CR55, 0x0F, 0x46},
488 /*IGA2 Horizontal Blank End */
489 {VIACR, CR53, 0xFF, 0x9D}, {VIACR, CR54, 0x38, 0x74},
490 {VIACR, CR5D, 0x40, 0x1C},
491 /*IGA2 Horizontal Total Shadow */
492 {VIACR, CR6D, 0xFF, 0xA3}, {VIACR, CR71, 0x08, 0x34},
493 /*IGA2 Horizontal Blank End Shadow */
494 {VIACR, CR6E, 0xFF, 0xA7},
495 /*IGA2 Offset */
496 {VIACR, CR66, 0xFF, 0xBE}, {VIACR, CR67, 0x03, 0x04},
497 /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x1E}
498};
499
500#define NUM_TOTAL_K400_LCD_RES_10X7_12X10 ARRAY_SIZE(K400_LCD_RES_10X7_12X10)
501
502/* ++++++ K400 ++++++ */
503/* Panel 1024x768 */
504struct io_reg K400_LCD_RES_6X4_10X7[] = {
505 /*IGA2 Horizontal Total */
506 {VIACR, CR50, 0xFF, 0x47}, {VIACR, CR55, 0x0F, 0x35},
507 /*IGA2 Horizontal Blank End */
508 {VIACR, CR53, 0xFF, 0x47}, {VIACR, CR54, 0x38, 0x2B},
509 {VIACR, CR5D, 0x40, 0x13},
510 /*IGA2 Horizontal Total Shadow */
511 {VIACR, CR6D, 0xFF, 0x60}, {VIACR, CR71, 0x08, 0x23},
512 /*IGA2 Horizontal Blank End Shadow */
513 {VIACR, CR6E, 0xFF, 0x64},
514 /*IGA2 Offset */
515 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
516 /*VCLK*/ {VIASR, SR46, 0xFF, 0x87}, {VIASR, SR47, 0xFF, 0x4C}
517};
518
519#define NUM_TOTAL_K400_LCD_RES_6X4_10X7 ARRAY_SIZE(K400_LCD_RES_6X4_10X7)
520
521struct io_reg K400_LCD_RES_7X4_10X7[] = {
522 /*IGA2 Horizontal Total */
523 {VIACR, CR50, 0xFF, 0x3B}, {VIACR, CR55, 0x0F, 0x35},
524 /*IGA2 Horizontal Blank End */
525 {VIACR, CR53, 0xFF, 0x3B}, {VIACR, CR54, 0x38, 0x2B},
526 {VIACR, CR5D, 0x40, 0x13},
527 /*IGA2 Horizontal Total Shadow */
528 {VIACR, CR6D, 0xFF, 0x71}, {VIACR, CR71, 0x08, 0x23},
529 /*IGA2 Horizontal Blank End Shadow */
530 {VIACR, CR6E, 0xFF, 0x75},
531 /*IGA2 Offset */
532 {VIACR, CR66, 0xFF, 0x96}, {VIACR, CR67, 0x03, 0x00},
533 /*VCLK*/ {VIASR, SR46, 0xFF, 0x05}, {VIASR, SR47, 0xFF, 0x10}
534};
535
536#define NUM_TOTAL_K400_LCD_RES_7X4_10X7 ARRAY_SIZE(K400_LCD_RES_7X4_10X7)
537
538struct io_reg K400_LCD_RES_8X6_10X7[] = {
539 /*IGA2 Horizontal Total */
540 {VIACR, CR50, 0xFF, 0x37}, {VIACR, CR55, 0x0F, 0x35},
541 /*IGA2 Horizontal Blank End */
542 {VIACR, CR53, 0xFF, 0x37}, {VIACR, CR54, 0x38, 0x2B},
543 {VIACR, CR5D, 0x40, 0x13},
544 /*IGA2 Horizontal Total Shadow */
545 {VIACR, CR6D, 0xFF, 0x7E}, {VIACR, CR71, 0x08, 0x23},
546 /*IGA2 Horizontal Blank End Shadow */
547 {VIACR, CR6E, 0xFF, 0x82},
548 /*IGA2 Offset */
549 {VIACR, CR66, 0xFF, 0x8C}, {VIACR, CR67, 0x03, 0x00},
550 /*VCLK*/ {VIASR, SR46, 0xFF, 0x84}, {VIASR, SR47, 0xFF, 0xB9}
551};
552
553#define NUM_TOTAL_K400_LCD_RES_8X6_10X7 ARRAY_SIZE(K400_LCD_RES_8X6_10X7)
554
555/* ++++++ K400 ++++++ */
556/* Panel 800x600 */
557struct io_reg K400_LCD_RES_6X4_8X6[] = {
558 /*IGA2 Horizontal Total */
559 {VIACR, CR50, 0xFF, 0x1A}, {VIACR, CR55, 0x0F, 0x34},
560 /*IGA2 Horizontal Blank End */
561 {VIACR, CR53, 0xFF, 0x1A}, {VIACR, CR54, 0x38, 0xE3},
562 {VIACR, CR5D, 0x40, 0x12},
563 /*IGA2 Horizontal Total Shadow */
564 {VIACR, CR6D, 0xFF, 0x5F}, {VIACR, CR71, 0x08, 0x22},
565 /*IGA2 Horizontal Blank End Shadow */
566 {VIACR, CR6E, 0xFF, 0x63},
567 /*IGA2 Offset */
568 {VIACR, CR66, 0xFF, 0x6E}, {VIACR, CR67, 0x03, 0x00},
569 /*VCLK*/ {VIASR, SR46, 0xFF, 0x86}, {VIASR, SR47, 0xFF, 0xB3}
570};
571
572#define NUM_TOTAL_K400_LCD_RES_6X4_8X6 ARRAY_SIZE(K400_LCD_RES_6X4_8X6)
573
574struct io_reg K400_LCD_RES_7X4_8X6[] = {
575 /*IGA2 Horizontal Total */
576 {VIACR, CR50, 0xFF, 0x1F}, {VIACR, CR55, 0x0F, 0x34},
577 /*IGA2 Horizontal Blank End */
578 {VIACR, CR53, 0xFF, 0x1F}, {VIACR, CR54, 0x38, 0xE3},
579 {VIACR, CR5D, 0x40, 0x12},
580 /*IGA2 Horizontal Total Shadow */
581 {VIACR, CR6D, 0xFF, 0x7F}, {VIACR, CR71, 0x08, 0x22},
582 /*IGA2 Horizontal Blank End Shadow */
583 {VIACR, CR6E, 0xFF, 0x83},
584 /*IGA2 Offset */
585 {VIACR, CR66, 0xFF, 0x78}, {VIACR, CR67, 0x03, 0x00},
586 /*VCLK*/ {VIASR, SR46, 0xFF, 0xC4}, {VIASR, SR47, 0xFF, 0x59}
587};
588
589#define NUM_TOTAL_K400_LCD_RES_7X4_8X6 ARRAY_SIZE(K400_LCD_RES_7X4_8X6)
590
591#endif /* __LCDTBL_H__ */
diff --git a/drivers/video/via/tbl1636.c b/drivers/video/via/tbl1636.c
deleted file mode 100644
index 2d8453429d4a..000000000000
--- a/drivers/video/via/tbl1636.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23struct IODATA COMMON_INIT_TBL_VT1636[] = {
24/* Index, Mask, Value */
25 /* Set panel power sequence timing */
26 {0x10, 0xC0, 0x00},
27 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
28 {0x0B, 0xFF, 0x40},
29 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
30 {0x0C, 0xFF, 0x31},
31 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
32 {0x0D, 0xFF, 0x31},
33 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
34 {0x0E, 0xFF, 0x68},
35 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
36 {0x0F, 0xFF, 0x68},
37 /* LVDS output power up */
38 {0x09, 0xA0, 0xA0},
39 /* turn on back light */
40 {0x10, 0x33, 0x13}
41};
42
43struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[] = {
44/* Index, Mask, Value */
45 {0x08, 0xF0, 0xE0} /* Input Data Mode Select */
46};
47
48struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[] = {
49/* Index, Mask, Value */
50 {0x08, 0xF0, 0x00} /* Input Data Mode Select */
51};
52
53struct IODATA DITHERING_ENABLE_TBL_VT1636[] = {
54/* Index, Mask, Value */
55 {0x0A, 0x70, 0x50}
56};
57
58struct IODATA DITHERING_DISABLE_TBL_VT1636[] = {
59/* Index, Mask, Value */
60 {0x0A, 0x70, 0x00}
61};
62
63struct IODATA VDD_ON_TBL_VT1636[] = {
64/* Index, Mask, Value */
65 {0x10, 0x20, 0x20}
66};
67
68struct IODATA VDD_OFF_TBL_VT1636[] = {
69/* Index, Mask, Value */
70 {0x10, 0x20, 0x00}
71};
diff --git a/drivers/video/via/tbl1636.h b/drivers/video/via/tbl1636.h
deleted file mode 100644
index d906055f1511..000000000000
--- a/drivers/video/via/tbl1636.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _TBL1636_H_
23#define _TBL1636_H_
24#include "hw.h"
25
26extern struct IODATA COMMON_INIT_TBL_VT1636[8];
27extern struct IODATA DUAL_CHANNEL_ENABLE_TBL_VT1636[1];
28extern struct IODATA SINGLE_CHANNEL_ENABLE_TBL_VT1636[1];
29extern struct IODATA DITHERING_ENABLE_TBL_VT1636[1];
30extern struct IODATA DITHERING_DISABLE_TBL_VT1636[1];
31extern struct IODATA VDD_ON_TBL_VT1636[1];
32extern struct IODATA VDD_OFF_TBL_VT1636[1];
33
34#endif /* _VIA_TBL1636_H_ */
diff --git a/drivers/video/via/via-core.c b/drivers/video/via/via-core.c
index 66f403033111..31e30338e893 100644
--- a/drivers/video/via/via-core.c
+++ b/drivers/video/via/via-core.c
@@ -20,7 +20,7 @@
20 * The default port config. 20 * The default port config.
21 */ 21 */
22static struct via_port_cfg adap_configs[] = { 22static struct via_port_cfg adap_configs[] = {
23 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_OFF, VIASR, 0x26 }, 23 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
24 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 }, 24 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
25 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 }, 25 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
26 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c }, 26 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c },
@@ -333,7 +333,7 @@ EXPORT_SYMBOL_GPL(viafb_dma_copy_out_sg);
333static u16 via_function3[] = { 333static u16 via_function3[] = {
334 CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3, 334 CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3,
335 CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3, 335 CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3,
336 P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, 336 P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, VX900_FUNCTION3,
337}; 337};
338 338
339/* Get the BIOS-configured framebuffer size from PCI configuration space 339/* Get the BIOS-configured framebuffer size from PCI configuration space
@@ -370,6 +370,7 @@ static int viafb_get_fb_size_from_pci(int chip_type)
370 case P4M900_FUNCTION3: 370 case P4M900_FUNCTION3:
371 case VX800_FUNCTION3: 371 case VX800_FUNCTION3:
372 case VX855_FUNCTION3: 372 case VX855_FUNCTION3:
373 case VX900_FUNCTION3:
373 /*case CN750_FUNCTION3: */ 374 /*case CN750_FUNCTION3: */
374 offset = 0xA0; 375 offset = 0xA0;
375 break; 376 break;
@@ -474,7 +475,10 @@ static int __devinit via_pci_setup_mmio(struct viafb_dev *vdev)
474 * Eventually we want to move away from mapping this 475 * Eventually we want to move away from mapping this
475 * entire region. 476 * entire region.
476 */ 477 */
477 vdev->fbmem_start = pci_resource_start(vdev->pdev, 0); 478 if (vdev->chip_type == UNICHROME_VX900)
479 vdev->fbmem_start = pci_resource_start(vdev->pdev, 2);
480 else
481 vdev->fbmem_start = pci_resource_start(vdev->pdev, 0);
478 ret = vdev->fbmem_len = viafb_get_fb_size_from_pci(vdev->chip_type); 482 ret = vdev->fbmem_len = viafb_get_fb_size_from_pci(vdev->chip_type);
479 if (ret < 0) 483 if (ret < 0)
480 goto out_unmap; 484 goto out_unmap;
@@ -635,6 +639,8 @@ static struct pci_device_id via_pci_table[] __devinitdata = {
635 .driver_data = UNICHROME_VX800 }, 639 .driver_data = UNICHROME_VX800 },
636 { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID), 640 { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID),
637 .driver_data = UNICHROME_VX855 }, 641 .driver_data = UNICHROME_VX855 },
642 { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX900_DID),
643 .driver_data = UNICHROME_VX900 },
638 { } 644 { }
639}; 645};
640MODULE_DEVICE_TABLE(pci, via_pci_table); 646MODULE_DEVICE_TABLE(pci, via_pci_table);
@@ -644,6 +650,10 @@ static struct pci_driver via_driver = {
644 .id_table = via_pci_table, 650 .id_table = via_pci_table,
645 .probe = via_pci_probe, 651 .probe = via_pci_probe,
646 .remove = __devexit_p(via_pci_remove), 652 .remove = __devexit_p(via_pci_remove),
653#ifdef CONFIG_PM
654 .suspend = viafb_suspend,
655 .resume = viafb_resume,
656#endif
647}; 657};
648 658
649static int __init via_core_init(void) 659static int __init via_core_init(void)
diff --git a/drivers/video/via/via_i2c.c b/drivers/video/via/via_i2c.c
index da9e4ca94b17..3844b558b7bd 100644
--- a/drivers/video/via/via_i2c.c
+++ b/drivers/video/via/via_i2c.c
@@ -114,6 +114,7 @@ static void via_i2c_setsda(void *data, int state)
114 114
115int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata) 115int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata)
116{ 116{
117 int ret;
117 u8 mm1[] = {0x00}; 118 u8 mm1[] = {0x00};
118 struct i2c_msg msgs[2]; 119 struct i2c_msg msgs[2];
119 120
@@ -126,11 +127,18 @@ int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata)
126 mm1[0] = index; 127 mm1[0] = index;
127 msgs[0].len = 1; msgs[1].len = 1; 128 msgs[0].len = 1; msgs[1].len = 1;
128 msgs[0].buf = mm1; msgs[1].buf = pdata; 129 msgs[0].buf = mm1; msgs[1].buf = pdata;
129 return i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); 130 ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2);
131 if (ret == 2)
132 ret = 0;
133 else if (ret >= 0)
134 ret = -EIO;
135
136 return ret;
130} 137}
131 138
132int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data) 139int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data)
133{ 140{
141 int ret;
134 u8 msg[2] = { index, data }; 142 u8 msg[2] = { index, data };
135 struct i2c_msg msgs; 143 struct i2c_msg msgs;
136 144
@@ -140,11 +148,18 @@ int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data)
140 msgs.addr = slave_addr / 2; 148 msgs.addr = slave_addr / 2;
141 msgs.len = 2; 149 msgs.len = 2;
142 msgs.buf = msg; 150 msgs.buf = msg;
143 return i2c_transfer(&via_i2c_par[adap].adapter, &msgs, 1); 151 ret = i2c_transfer(&via_i2c_par[adap].adapter, &msgs, 1);
152 if (ret == 1)
153 ret = 0;
154 else if (ret >= 0)
155 ret = -EIO;
156
157 return ret;
144} 158}
145 159
146int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len) 160int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len)
147{ 161{
162 int ret;
148 u8 mm1[] = {0x00}; 163 u8 mm1[] = {0x00};
149 struct i2c_msg msgs[2]; 164 struct i2c_msg msgs[2];
150 165
@@ -156,7 +171,13 @@ int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len
156 mm1[0] = index; 171 mm1[0] = index;
157 msgs[0].len = 1; msgs[1].len = buff_len; 172 msgs[0].len = 1; msgs[1].len = buff_len;
158 msgs[0].buf = mm1; msgs[1].buf = buff; 173 msgs[0].buf = mm1; msgs[1].buf = buff;
159 return i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2); 174 ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2);
175 if (ret == 2)
176 ret = 0;
177 else if (ret >= 0)
178 ret = -EIO;
179
180 return ret;
160} 181}
161 182
162/* 183/*
@@ -181,8 +202,8 @@ static int create_i2c_bus(struct i2c_adapter *adapter,
181 algo->setscl = via_i2c_setscl; 202 algo->setscl = via_i2c_setscl;
182 algo->getsda = via_i2c_getsda; 203 algo->getsda = via_i2c_getsda;
183 algo->getscl = via_i2c_getscl; 204 algo->getscl = via_i2c_getscl;
184 algo->udelay = 40; 205 algo->udelay = 10;
185 algo->timeout = 20; 206 algo->timeout = 2;
186 algo->data = adap_cfg; 207 algo->data = adap_cfg;
187 208
188 sprintf(adapter->name, "viafb i2c io_port idx 0x%02x", 209 sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index bdd0e4130f4e..d298cfccd6fc 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -56,6 +56,32 @@ static int viafb_pan_display(struct fb_var_screeninfo *var,
56 56
57static struct fb_ops viafb_ops; 57static struct fb_ops viafb_ops;
58 58
59/* supported output devices on each IGP
60 * only CX700, VX800, VX855, VX900 were documented
61 * VIA_CRT should be everywhere
62 * VIA_6C can be onle pre-CX700 (probably only on CLE266) as 6C is used for PLL
63 * source selection on CX700 and later
64 * K400 seems to support VIA_96, VIA_DVP1, VIA_LVDS{1,2} as in viamode.c
65 */
66static const u32 supported_odev_map[] = {
67 [UNICHROME_CLE266] = VIA_CRT | VIA_LDVP0 | VIA_LDVP1,
68 [UNICHROME_K400] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
69 | VIA_LVDS2,
70 [UNICHROME_K800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
71 | VIA_LVDS2,
72 [UNICHROME_PM800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
73 | VIA_LVDS2,
74 [UNICHROME_CN700] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
75 | VIA_LVDS2,
76 [UNICHROME_CX700] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
77 [UNICHROME_CN750] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
78 [UNICHROME_K8M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
79 [UNICHROME_P4M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
80 [UNICHROME_P4M900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
81 [UNICHROME_VX800] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
82 [UNICHROME_VX855] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
83 [UNICHROME_VX900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
84};
59 85
60static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth) 86static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth)
61{ 87{
@@ -332,22 +358,22 @@ static int viafb_blank(int blank_mode, struct fb_info *info)
332 case FB_BLANK_UNBLANK: 358 case FB_BLANK_UNBLANK:
333 /* Screen: On, HSync: On, VSync: On */ 359 /* Screen: On, HSync: On, VSync: On */
334 /* control CRT monitor power management */ 360 /* control CRT monitor power management */
335 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); 361 via_set_state(VIA_CRT, VIA_STATE_ON);
336 break; 362 break;
337 case FB_BLANK_HSYNC_SUSPEND: 363 case FB_BLANK_HSYNC_SUSPEND:
338 /* Screen: Off, HSync: Off, VSync: On */ 364 /* Screen: Off, HSync: Off, VSync: On */
339 /* control CRT monitor power management */ 365 /* control CRT monitor power management */
340 viafb_write_reg_mask(CR36, VIACR, 0x10, BIT4 + BIT5); 366 via_set_state(VIA_CRT, VIA_STATE_STANDBY);
341 break; 367 break;
342 case FB_BLANK_VSYNC_SUSPEND: 368 case FB_BLANK_VSYNC_SUSPEND:
343 /* Screen: Off, HSync: On, VSync: Off */ 369 /* Screen: Off, HSync: On, VSync: Off */
344 /* control CRT monitor power management */ 370 /* control CRT monitor power management */
345 viafb_write_reg_mask(CR36, VIACR, 0x20, BIT4 + BIT5); 371 via_set_state(VIA_CRT, VIA_STATE_SUSPEND);
346 break; 372 break;
347 case FB_BLANK_POWERDOWN: 373 case FB_BLANK_POWERDOWN:
348 /* Screen: Off, HSync: Off, VSync: Off */ 374 /* Screen: Off, HSync: Off, VSync: Off */
349 /* control CRT monitor power management */ 375 /* control CRT monitor power management */
350 viafb_write_reg_mask(CR36, VIACR, 0x30, BIT4 + BIT5); 376 via_set_state(VIA_CRT, VIA_STATE_OFF);
351 break; 377 break;
352 } 378 }
353 379
@@ -457,7 +483,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
457 if (copy_from_user(&gpu32, argp, sizeof(gpu32))) 483 if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
458 return -EFAULT; 484 return -EFAULT;
459 if (gpu32 & CRT_Device) 485 if (gpu32 & CRT_Device)
460 viafb_crt_enable(); 486 via_set_state(VIA_CRT, VIA_STATE_ON);
461 if (gpu32 & DVI_Device) 487 if (gpu32 & DVI_Device)
462 viafb_dvi_enable(); 488 viafb_dvi_enable();
463 if (gpu32 & LCD_Device) 489 if (gpu32 & LCD_Device)
@@ -467,7 +493,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
467 if (copy_from_user(&gpu32, argp, sizeof(gpu32))) 493 if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
468 return -EFAULT; 494 return -EFAULT;
469 if (gpu32 & CRT_Device) 495 if (gpu32 & CRT_Device)
470 viafb_crt_disable(); 496 via_set_state(VIA_CRT, VIA_STATE_OFF);
471 if (gpu32 & DVI_Device) 497 if (gpu32 & DVI_Device)
472 viafb_dvi_disable(); 498 viafb_dvi_disable();
473 if (gpu32 & LCD_Device) 499 if (gpu32 & LCD_Device)
@@ -787,7 +813,8 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
787 bg_color = cursor->image.bg_color; 813 bg_color = cursor->image.bg_color;
788 if (chip_name == UNICHROME_CX700 || 814 if (chip_name == UNICHROME_CX700 ||
789 chip_name == UNICHROME_VX800 || 815 chip_name == UNICHROME_VX800 ||
790 chip_name == UNICHROME_VX855) { 816 chip_name == UNICHROME_VX855 ||
817 chip_name == UNICHROME_VX900) {
791 fg_color = 818 fg_color =
792 ((info->cmap.red[fg_color] & 0xFFC0) << 14) | 819 ((info->cmap.red[fg_color] & 0xFFC0) << 14) |
793 ((info->cmap.green[fg_color] & 0xFFC0) << 4) | 820 ((info->cmap.green[fg_color] & 0xFFC0) << 4) |
@@ -961,7 +988,7 @@ static void retrieve_device_setting(struct viafb_ioctl_setting
961 setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode; 988 setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode;
962} 989}
963 990
964static int parse_active_dev(void) 991static int __init parse_active_dev(void)
965{ 992{
966 viafb_CRT_ON = STATE_OFF; 993 viafb_CRT_ON = STATE_OFF;
967 viafb_DVI_ON = STATE_OFF; 994 viafb_DVI_ON = STATE_OFF;
@@ -1031,7 +1058,7 @@ static int parse_active_dev(void)
1031 return 0; 1058 return 0;
1032} 1059}
1033 1060
1034static int parse_port(char *opt_str, int *output_interface) 1061static int __devinit parse_port(char *opt_str, int *output_interface)
1035{ 1062{
1036 if (!strncmp(opt_str, "DVP0", 4)) 1063 if (!strncmp(opt_str, "DVP0", 4))
1037 *output_interface = INTERFACE_DVP0; 1064 *output_interface = INTERFACE_DVP0;
@@ -1048,7 +1075,7 @@ static int parse_port(char *opt_str, int *output_interface)
1048 return 0; 1075 return 0;
1049} 1076}
1050 1077
1051static void parse_lcd_port(void) 1078static void __devinit parse_lcd_port(void)
1052{ 1079{
1053 parse_port(viafb_lcd_port, &viaparinfo->chip_info->lvds_chip_info. 1080 parse_port(viafb_lcd_port, &viaparinfo->chip_info->lvds_chip_info.
1054 output_interface); 1081 output_interface);
@@ -1061,7 +1088,7 @@ static void parse_lcd_port(void)
1061 output_interface); 1088 output_interface);
1062} 1089}
1063 1090
1064static void parse_dvi_port(void) 1091static void __devinit parse_dvi_port(void)
1065{ 1092{
1066 parse_port(viafb_dvi_port, &viaparinfo->chip_info->tmds_chip_info. 1093 parse_port(viafb_dvi_port, &viaparinfo->chip_info->tmds_chip_info.
1067 output_interface); 1094 output_interface);
@@ -1431,38 +1458,196 @@ static const struct file_operations viafb_vt1636_proc_fops = {
1431 .write = viafb_vt1636_proc_write, 1458 .write = viafb_vt1636_proc_write,
1432}; 1459};
1433 1460
1434static void viafb_init_proc(struct proc_dir_entry **viafb_entry) 1461#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
1462
1463static int viafb_sup_odev_proc_show(struct seq_file *m, void *v)
1435{ 1464{
1436 *viafb_entry = proc_mkdir("viafb", NULL); 1465 via_odev_to_seq(m, supported_odev_map[
1437 if (*viafb_entry) { 1466 viaparinfo->shared->chip_info.gfx_chip_name]);
1438 proc_create("dvp0", 0, *viafb_entry, &viafb_dvp0_proc_fops); 1467 return 0;
1439 proc_create("dvp1", 0, *viafb_entry, &viafb_dvp1_proc_fops); 1468}
1440 proc_create("dfph", 0, *viafb_entry, &viafb_dfph_proc_fops); 1469
1441 proc_create("dfpl", 0, *viafb_entry, &viafb_dfpl_proc_fops); 1470static int viafb_sup_odev_proc_open(struct inode *inode, struct file *file)
1442 if (VT1636_LVDS == viaparinfo->chip_info->lvds_chip_info. 1471{
1443 lvds_chip_name || VT1636_LVDS == 1472 return single_open(file, viafb_sup_odev_proc_show, NULL);
1444 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { 1473}
1445 proc_create("vt1636", 0, *viafb_entry, &viafb_vt1636_proc_fops); 1474
1446 } 1475static const struct file_operations viafb_sup_odev_proc_fops = {
1476 .owner = THIS_MODULE,
1477 .open = viafb_sup_odev_proc_open,
1478 .read = seq_read,
1479 .llseek = seq_lseek,
1480 .release = single_release,
1481};
1482
1483static ssize_t odev_update(const char __user *buffer, size_t count, u32 *odev)
1484{
1485 char buf[64], *ptr = buf;
1486 u32 devices;
1487 bool add, sub;
1488
1489 if (count < 1 || count > 63)
1490 return -EINVAL;
1491 if (copy_from_user(&buf[0], buffer, count))
1492 return -EFAULT;
1493 buf[count] = '\0';
1494 add = buf[0] == '+';
1495 sub = buf[0] == '-';
1496 if (add || sub)
1497 ptr++;
1498 devices = via_parse_odev(ptr, &ptr);
1499 if (*ptr == '\n')
1500 ptr++;
1501 if (*ptr != 0)
1502 return -EINVAL;
1503 if (add)
1504 *odev |= devices;
1505 else if (sub)
1506 *odev &= ~devices;
1507 else
1508 *odev = devices;
1509 return count;
1510}
1511
1512static int viafb_iga1_odev_proc_show(struct seq_file *m, void *v)
1513{
1514 via_odev_to_seq(m, viaparinfo->shared->iga1_devices);
1515 return 0;
1516}
1517
1518static int viafb_iga1_odev_proc_open(struct inode *inode, struct file *file)
1519{
1520 return single_open(file, viafb_iga1_odev_proc_show, NULL);
1521}
1522
1523static ssize_t viafb_iga1_odev_proc_write(struct file *file,
1524 const char __user *buffer, size_t count, loff_t *pos)
1525{
1526 u32 dev_on, dev_off, dev_old, dev_new;
1527 ssize_t res;
1528
1529 dev_old = dev_new = viaparinfo->shared->iga1_devices;
1530 res = odev_update(buffer, count, &dev_new);
1531 if (res != count)
1532 return res;
1533 dev_off = dev_old & ~dev_new;
1534 dev_on = dev_new & ~dev_old;
1535 viaparinfo->shared->iga1_devices = dev_new;
1536 viaparinfo->shared->iga2_devices &= ~dev_new;
1537 via_set_state(dev_off, VIA_STATE_OFF);
1538 via_set_source(dev_new, IGA1);
1539 via_set_state(dev_on, VIA_STATE_ON);
1540 return res;
1541}
1542
1543static const struct file_operations viafb_iga1_odev_proc_fops = {
1544 .owner = THIS_MODULE,
1545 .open = viafb_iga1_odev_proc_open,
1546 .read = seq_read,
1547 .llseek = seq_lseek,
1548 .release = single_release,
1549 .write = viafb_iga1_odev_proc_write,
1550};
1551
1552static int viafb_iga2_odev_proc_show(struct seq_file *m, void *v)
1553{
1554 via_odev_to_seq(m, viaparinfo->shared->iga2_devices);
1555 return 0;
1556}
1447 1557
1558static int viafb_iga2_odev_proc_open(struct inode *inode, struct file *file)
1559{
1560 return single_open(file, viafb_iga2_odev_proc_show, NULL);
1561}
1562
1563static ssize_t viafb_iga2_odev_proc_write(struct file *file,
1564 const char __user *buffer, size_t count, loff_t *pos)
1565{
1566 u32 dev_on, dev_off, dev_old, dev_new;
1567 ssize_t res;
1568
1569 dev_old = dev_new = viaparinfo->shared->iga2_devices;
1570 res = odev_update(buffer, count, &dev_new);
1571 if (res != count)
1572 return res;
1573 dev_off = dev_old & ~dev_new;
1574 dev_on = dev_new & ~dev_old;
1575 viaparinfo->shared->iga2_devices = dev_new;
1576 viaparinfo->shared->iga1_devices &= ~dev_new;
1577 via_set_state(dev_off, VIA_STATE_OFF);
1578 via_set_source(dev_new, IGA2);
1579 via_set_state(dev_on, VIA_STATE_ON);
1580 return res;
1581}
1582
1583static const struct file_operations viafb_iga2_odev_proc_fops = {
1584 .owner = THIS_MODULE,
1585 .open = viafb_iga2_odev_proc_open,
1586 .read = seq_read,
1587 .llseek = seq_lseek,
1588 .release = single_release,
1589 .write = viafb_iga2_odev_proc_write,
1590};
1591
1592#define IS_VT1636(lvds_chip) ((lvds_chip).lvds_chip_name == VT1636_LVDS)
1593static void viafb_init_proc(struct viafb_shared *shared)
1594{
1595 struct proc_dir_entry *iga1_entry, *iga2_entry,
1596 *viafb_entry = proc_mkdir("viafb", NULL);
1597
1598 shared->proc_entry = viafb_entry;
1599 if (viafb_entry) {
1600#ifdef CONFIG_FB_VIA_DIRECT_PROCFS
1601 proc_create("dvp0", 0, viafb_entry, &viafb_dvp0_proc_fops);
1602 proc_create("dvp1", 0, viafb_entry, &viafb_dvp1_proc_fops);
1603 proc_create("dfph", 0, viafb_entry, &viafb_dfph_proc_fops);
1604 proc_create("dfpl", 0, viafb_entry, &viafb_dfpl_proc_fops);
1605 if (IS_VT1636(shared->chip_info.lvds_chip_info)
1606 || IS_VT1636(shared->chip_info.lvds_chip_info2))
1607 proc_create("vt1636", 0, viafb_entry,
1608 &viafb_vt1636_proc_fops);
1609#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
1610
1611 proc_create("supported_output_devices", 0, viafb_entry,
1612 &viafb_sup_odev_proc_fops);
1613 iga1_entry = proc_mkdir("iga1", viafb_entry);
1614 shared->iga1_proc_entry = iga1_entry;
1615 proc_create("output_devices", 0, iga1_entry,
1616 &viafb_iga1_odev_proc_fops);
1617 iga2_entry = proc_mkdir("iga2", viafb_entry);
1618 shared->iga2_proc_entry = iga2_entry;
1619 proc_create("output_devices", 0, iga2_entry,
1620 &viafb_iga2_odev_proc_fops);
1448 } 1621 }
1449} 1622}
1450static void viafb_remove_proc(struct proc_dir_entry *viafb_entry) 1623static void viafb_remove_proc(struct viafb_shared *shared)
1451{ 1624{
1452 struct chip_information *chip_info = &viaparinfo->shared->chip_info; 1625 struct proc_dir_entry *viafb_entry = shared->proc_entry,
1626 *iga1_entry = shared->iga1_proc_entry,
1627 *iga2_entry = shared->iga2_proc_entry;
1453 1628
1629 if (!viafb_entry)
1630 return;
1631
1632 remove_proc_entry("output_devices", iga2_entry);
1633 remove_proc_entry("iga2", viafb_entry);
1634 remove_proc_entry("output_devices", iga1_entry);
1635 remove_proc_entry("iga1", viafb_entry);
1636 remove_proc_entry("supported_output_devices", viafb_entry);
1637
1638#ifdef CONFIG_FB_VIA_DIRECT_PROCFS
1454 remove_proc_entry("dvp0", viafb_entry);/* parent dir */ 1639 remove_proc_entry("dvp0", viafb_entry);/* parent dir */
1455 remove_proc_entry("dvp1", viafb_entry); 1640 remove_proc_entry("dvp1", viafb_entry);
1456 remove_proc_entry("dfph", viafb_entry); 1641 remove_proc_entry("dfph", viafb_entry);
1457 remove_proc_entry("dfpl", viafb_entry); 1642 remove_proc_entry("dfpl", viafb_entry);
1458 if (chip_info->lvds_chip_info.lvds_chip_name == VT1636_LVDS 1643 if (IS_VT1636(shared->chip_info.lvds_chip_info)
1459 || chip_info->lvds_chip_info2.lvds_chip_name == VT1636_LVDS) 1644 || IS_VT1636(shared->chip_info.lvds_chip_info2))
1460 remove_proc_entry("vt1636", viafb_entry); 1645 remove_proc_entry("vt1636", viafb_entry);
1646#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
1461 1647
1462 remove_proc_entry("viafb", NULL); 1648 remove_proc_entry("viafb", NULL);
1463} 1649}
1464 1650#undef IS_VT1636
1465#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
1466 1651
1467static int parse_mode(const char *str, u32 *xres, u32 *yres) 1652static int parse_mode(const char *str, u32 *xres, u32 *yres)
1468{ 1653{
@@ -1486,6 +1671,47 @@ static int parse_mode(const char *str, u32 *xres, u32 *yres)
1486} 1671}
1487 1672
1488 1673
1674#ifdef CONFIG_PM
1675int viafb_suspend(struct pci_dev *pdev, pm_message_t state)
1676{
1677 if (state.event == PM_EVENT_SUSPEND) {
1678 acquire_console_sem();
1679 fb_set_suspend(viafbinfo, 1);
1680
1681 viafb_sync(viafbinfo);
1682
1683 pci_save_state(pdev);
1684 pci_disable_device(pdev);
1685 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1686 release_console_sem();
1687 }
1688
1689 return 0;
1690}
1691
1692int viafb_resume(struct pci_dev *pdev)
1693{
1694 acquire_console_sem();
1695 pci_set_power_state(pdev, PCI_D0);
1696 pci_restore_state(pdev);
1697 if (pci_enable_device(pdev))
1698 goto fail;
1699 pci_set_master(pdev);
1700 if (viaparinfo->shared->vdev->engine_mmio)
1701 viafb_reset_engine(viaparinfo);
1702 viafb_set_par(viafbinfo);
1703 if (viafb_dual_fb)
1704 viafb_set_par(viafbinfo1);
1705 fb_set_suspend(viafbinfo, 0);
1706
1707fail:
1708 release_console_sem();
1709 return 0;
1710}
1711
1712#endif
1713
1714
1489int __devinit via_fb_pci_probe(struct viafb_dev *vdev) 1715int __devinit via_fb_pci_probe(struct viafb_dev *vdev)
1490{ 1716{
1491 u32 default_xres, default_yres; 1717 u32 default_xres, default_yres;
@@ -1544,7 +1770,7 @@ int __devinit via_fb_pci_probe(struct viafb_dev *vdev)
1544 viafbinfo->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1770 viafbinfo->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1545 1771
1546 viafbinfo->pseudo_palette = pseudo_pal; 1772 viafbinfo->pseudo_palette = pseudo_pal;
1547 if (viafb_accel && !viafb_init_engine(viafbinfo)) { 1773 if (viafb_accel && !viafb_setup_engine(viafbinfo)) {
1548 viafbinfo->flags |= FBINFO_HWACCEL_COPYAREA | 1774 viafbinfo->flags |= FBINFO_HWACCEL_COPYAREA |
1549 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; 1775 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT;
1550 default_var.accel_flags = FB_ACCELF_TEXT; 1776 default_var.accel_flags = FB_ACCELF_TEXT;
@@ -1671,9 +1897,7 @@ int __devinit via_fb_pci_probe(struct viafb_dev *vdev)
1671 viafbinfo->node, viafbinfo->fix.id, default_var.xres, 1897 viafbinfo->node, viafbinfo->fix.id, default_var.xres,
1672 default_var.yres, default_var.bits_per_pixel); 1898 default_var.yres, default_var.bits_per_pixel);
1673 1899
1674#ifdef CONFIG_FB_VIA_DIRECT_PROCFS 1900 viafb_init_proc(viaparinfo->shared);
1675 viafb_init_proc(&viaparinfo->shared->proc_entry);
1676#endif
1677 viafb_init_dac(IGA2); 1901 viafb_init_dac(IGA2);
1678 return 0; 1902 return 0;
1679 1903
@@ -1700,9 +1924,7 @@ void __devexit via_fb_pci_remove(struct pci_dev *pdev)
1700 unregister_framebuffer(viafbinfo); 1924 unregister_framebuffer(viafbinfo);
1701 if (viafb_dual_fb) 1925 if (viafb_dual_fb)
1702 unregister_framebuffer(viafbinfo1); 1926 unregister_framebuffer(viafbinfo1);
1703#ifdef CONFIG_FB_VIA_DIRECT_PROCFS 1927 viafb_remove_proc(viaparinfo->shared);
1704 viafb_remove_proc(viaparinfo->shared->proc_entry);
1705#endif
1706 framebuffer_release(viafbinfo); 1928 framebuffer_release(viafbinfo);
1707 if (viafb_dual_fb) 1929 if (viafb_dual_fb)
1708 framebuffer_release(viafbinfo1); 1930 framebuffer_release(viafbinfo1);
diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h
index 52a35fabba91..4960e3da6645 100644
--- a/drivers/video/via/viafbdev.h
+++ b/drivers/video/via/viafbdev.h
@@ -40,7 +40,12 @@
40#define VIAFB_NUM_I2C 5 40#define VIAFB_NUM_I2C 5
41 41
42struct viafb_shared { 42struct viafb_shared {
43 u32 iga1_devices;
44 u32 iga2_devices;
45
43 struct proc_dir_entry *proc_entry; /*viafb proc entry */ 46 struct proc_dir_entry *proc_entry; /*viafb proc entry */
47 struct proc_dir_entry *iga1_proc_entry;
48 struct proc_dir_entry *iga2_proc_entry;
44 struct viafb_dev *vdev; /* Global dev info */ 49 struct viafb_dev *vdev; /* Global dev info */
45 50
46 /* All the information will be needed to set engine */ 51 /* All the information will be needed to set engine */
@@ -103,4 +108,6 @@ void via_fb_pci_remove(struct pci_dev *pdev);
103/* Temporary */ 108/* Temporary */
104int viafb_init(void); 109int viafb_init(void);
105void viafb_exit(void); 110void viafb_exit(void);
111int viafb_suspend(struct pci_dev *pdev, pm_message_t state);
112int viafb_resume(struct pci_dev *pdev);
106#endif /* __VIAFBDEV_H__ */ 113#endif /* __VIAFBDEV_H__ */
diff --git a/drivers/video/via/vt1636.c b/drivers/video/via/vt1636.c
index d65bf1aee87c..60e4192c2b34 100644
--- a/drivers/video/via/vt1636.c
+++ b/drivers/video/via/vt1636.c
@@ -23,6 +23,34 @@
23#include <linux/via_i2c.h> 23#include <linux/via_i2c.h>
24#include "global.h" 24#include "global.h"
25 25
26static const struct IODATA common_init_data[] = {
27/* Index, Mask, Value */
28 /* Set panel power sequence timing */
29 {0x10, 0xC0, 0x00},
30 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
31 {0x0B, 0xFF, 0x40},
32 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
33 {0x0C, 0xFF, 0x31},
34 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
35 {0x0D, 0xFF, 0x31},
36 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
37 {0x0E, 0xFF, 0x68},
38 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
39 {0x0F, 0xFF, 0x68},
40 /* LVDS output power up */
41 {0x09, 0xA0, 0xA0},
42 /* turn on back light */
43 {0x10, 0x33, 0x13}
44};
45
46/* Index, Mask, Value */
47static const struct IODATA dual_channel_enable_data = {0x08, 0xF0, 0xE0};
48static const struct IODATA single_channel_enable_data = {0x08, 0xF0, 0x00};
49static const struct IODATA dithering_enable_data = {0x0A, 0x70, 0x50};
50static const struct IODATA dithering_disable_data = {0x0A, 0x70, 0x00};
51static const struct IODATA vdd_on_data = {0x10, 0x20, 0x20};
52static const struct IODATA vdd_off_data = {0x10, 0x20, 0x00};
53
26u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information 54u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
27 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info, 55 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
28 u8 index) 56 u8 index)
@@ -55,108 +83,41 @@ void viafb_init_lvds_vt1636(struct lvds_setting_information
55 int reg_num, i; 83 int reg_num, i;
56 84
57 /* Common settings: */ 85 /* Common settings: */
58 reg_num = ARRAY_SIZE(COMMON_INIT_TBL_VT1636); 86 reg_num = ARRAY_SIZE(common_init_data);
59 87 for (i = 0; i < reg_num; i++)
60 for (i = 0; i < reg_num; i++) {
61 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, 88 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
62 plvds_chip_info, 89 plvds_chip_info, common_init_data[i]);
63 COMMON_INIT_TBL_VT1636[i]);
64 }
65 90
66 /* Input Data Mode Select */ 91 /* Input Data Mode Select */
67 if (plvds_setting_info->device_lcd_dualedge) { 92 if (plvds_setting_info->device_lcd_dualedge)
68 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, 93 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
69 plvds_chip_info, 94 plvds_chip_info, dual_channel_enable_data);
70 DUAL_CHANNEL_ENABLE_TBL_VT1636[0]); 95 else
71 } else {
72 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, 96 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
73 plvds_chip_info, 97 plvds_chip_info, single_channel_enable_data);
74 SINGLE_CHANNEL_ENABLE_TBL_VT1636[0]);
75 }
76 98
77 if (plvds_setting_info->LCDDithering) { 99 if (plvds_setting_info->LCDDithering)
78 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, 100 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
79 plvds_chip_info, 101 plvds_chip_info, dithering_enable_data);
80 DITHERING_ENABLE_TBL_VT1636[0]); 102 else
81 } else {
82 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, 103 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
83 plvds_chip_info, 104 plvds_chip_info, dithering_disable_data);
84 DITHERING_DISABLE_TBL_VT1636[0]);
85 }
86} 105}
87 106
88void viafb_enable_lvds_vt1636(struct lvds_setting_information 107void viafb_enable_lvds_vt1636(struct lvds_setting_information
89 *plvds_setting_info, 108 *plvds_setting_info,
90 struct lvds_chip_information *plvds_chip_info) 109 struct lvds_chip_information *plvds_chip_info)
91{ 110{
92
93 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info, 111 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
94 VDD_ON_TBL_VT1636[0]); 112 vdd_on_data);
95
96 /* Pad on: */
97 switch (plvds_chip_info->output_interface) {
98 case INTERFACE_DVP0:
99 {
100 viafb_write_reg_mask(SR1E, VIASR, 0xC0, 0xC0);
101 break;
102 }
103
104 case INTERFACE_DVP1:
105 {
106 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
107 break;
108 }
109
110 case INTERFACE_DFP_LOW:
111 {
112 viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x03);
113 break;
114 }
115
116 case INTERFACE_DFP_HIGH:
117 {
118 viafb_write_reg_mask(SR2A, VIASR, 0x03, 0x0C);
119 break;
120 }
121
122 }
123} 113}
124 114
125void viafb_disable_lvds_vt1636(struct lvds_setting_information 115void viafb_disable_lvds_vt1636(struct lvds_setting_information
126 *plvds_setting_info, 116 *plvds_setting_info,
127 struct lvds_chip_information *plvds_chip_info) 117 struct lvds_chip_information *plvds_chip_info)
128{ 118{
129
130 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info, 119 viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
131 VDD_OFF_TBL_VT1636[0]); 120 vdd_off_data);
132
133 /* Pad off: */
134 switch (plvds_chip_info->output_interface) {
135 case INTERFACE_DVP0:
136 {
137 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0xC0);
138 break;
139 }
140
141 case INTERFACE_DVP1:
142 {
143 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
144 break;
145 }
146
147 case INTERFACE_DFP_LOW:
148 {
149 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x03);
150 break;
151 }
152
153 case INTERFACE_DFP_HIGH:
154 {
155 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0C);
156 break;
157 }
158
159 }
160} 121}
161 122
162bool viafb_lvds_identify_vt1636(u8 i2c_adapter) 123bool viafb_lvds_identify_vt1636(u8 i2c_adapter)
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 16:32:08 -0400