12 files changed, 64 insertions, 47 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index f524b3bf68c8..a35212b7346e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -707,7 +707,7 @@ config FORCE_MAX_ZONEORDER
 
 config MATH_EMULATION
         bool "Math emulation"
-        depends on 4xx || 8xx || E200 || E500
+        depends on 4xx || 8xx || E200 || PPC_83xx || E500
         ---help---
           Some PowerPC chips designed for embedded applications do not have
           a floating-point unit and therefore do not implement the
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 9d1614c3ce67..b742013bb9da 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -833,7 +833,7 @@ static struct cpu_spec cpu_specs[] = {
                 .pvr_mask               = 0x7fff0000,
                 .pvr_value              = 0x00840000,
                 .cpu_name               = "e300c2",
-                .cpu_features           = CPU_FTRS_E300,
+                .cpu_features           = CPU_FTRS_E300C2,
                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
@@ -1136,8 +1136,7 @@ static struct cpu_spec cpu_specs[] = {
                 .pvr_mask               = 0xff000fff,
                 .pvr_value              = 0x53000890,
                 .cpu_name               = "440SPe Rev. A",
-                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-                        CPU_FTR_USE_TB,
+                .cpu_features           = CPU_FTRS_44X,
                 .cpu_user_features      = COMMON_USER_BOOKE,
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index d88e182e40b3..9417cf5b4b7e 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -437,6 +437,13 @@ Alignment:
 /* Floating-point unavailable */
         . = 0x800
 FPUnavailable:
+BEGIN_FTR_SECTION
+/*
+ * Certain Freescale cores don't have a FPU and treat fp instructions
+ * as a FP Unavailable exception.  Redirect to illegal/emulation handling.
+ */
+        b       ProgramCheck
+END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
         EXCEPTION_PROLOG
         bne     load_up_fpu             /* if from user, just load it up */
         addi    r3,r1,STACK_FRAME_OVERHEAD
diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c
index 8a06724e029e..e921514e655b 100644
--- a/arch/powerpc/kernel/of_device.c
+++ b/arch/powerpc/kernel/of_device.c
@@ -109,9 +109,7 @@ int of_device_register(struct of_device *ofdev)
         if (rc)
                 return rc;
 
-        device_create_file(&ofdev->dev, &dev_attr_devspec);
-
-        return 0;
+        return device_create_file(&ofdev->dev, &dev_attr_devspec);
 }
 
 void of_device_unregister(struct of_device *ofdev)
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 9179f0739ea2..95776b6af4e2 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -208,7 +208,7 @@ EXPORT_SYMBOL(mmu_hash_lock); /* For MOL */
 extern long *intercept_table;
 EXPORT_SYMBOL(intercept_table);
 #endif /* CONFIG_PPC_STD_MMU_32 */
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_DCR_NATIVE
 EXPORT_SYMBOL(__mtdcr);
 EXPORT_SYMBOL(__mfdcr);
 #endif
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 0d4e203fa7a0..fde820e52d03 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -782,6 +782,8 @@ void __kprobes program_check_exception(struct pt_regs *regs)
         unsigned int reason = get_reason(regs);
         extern int do_mathemu(struct pt_regs *regs);
 
+        /* We can now get here via a FP Unavailable exception if the core
+         * has no FPU, in that case no reason flags will be set */
 #ifdef CONFIG_MATH_EMULATION
         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
          * but there seems to be a hardware bug on the 405GP (RevD)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 6cc34597a620..04d4917eb303 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -5,7 +5,8 @@ endif
 obj-$(CONFIG_MPIC)              += mpic.o
 obj-$(CONFIG_PPC_INDIRECT_PCI)  += indirect_pci.o
 obj-$(CONFIG_PPC_MPC106)        += grackle.o
-obj-$(CONFIG_PPC_DCR)           += dcr.o dcr-low.o
+obj-$(CONFIG_PPC_DCR)           += dcr.o
+obj-$(CONFIG_PPC_DCR_NATIVE)    += dcr-low.o
 obj-$(CONFIG_U3_DART)           += dart_iommu.o
 obj-$(CONFIG_MMIO_NVRAM)        += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)           += fsl_soc.o
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 782adbf1f7aa..7384b8086b75 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
+#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -296,6 +297,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_E300   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
             CPU_FTR_COMMON)
+#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 #define CPU_FTRS_8XX    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
@@ -366,7 +370,8 @@ enum {
             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
-            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
+            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
+            CPU_FTRS_CLASSIC32 |
 #else
             CPU_FTRS_GENERIC_32 |
 #endif
@@ -405,7 +410,8 @@ enum {
             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
-            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
+            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
+            CPU_FTRS_CLASSIC32 &
 #else
             CPU_FTRS_GENERIC_32 &
 #endif
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index fd4a5f5e33d1..d7a1bc1551c6 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -20,8 +20,7 @@
 #ifndef _ASM_POWERPC_DCR_NATIVE_H
 #define _ASM_POWERPC_DCR_NATIVE_H
 #ifdef __KERNEL__
-
-#include <asm/reg.h>
+#ifndef __ASSEMBLY__
 
 typedef struct {} dcr_host_t;
 
@@ -32,7 +31,41 @@ typedef struct {} dcr_host_t;
 #define dcr_read(host, dcr_n)           mfdcr(dcr_n)
 #define dcr_write(host, dcr_n, value)   mtdcr(dcr_n, value)
 
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn)                                               \
+        ({unsigned int rval;                                    \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mfdcr %0," __stringify(rn)        \
+                              : "=r" (rval));                   \
+        else                                                    \
+                rval = __mfdcr(rn);                             \
+        rval;})
+
+#define mtdcr(rn, v)                                            \
+do {                                                            \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mtdcr " __stringify(rn) ",%0"     \
+                              : : "r" (v));                     \
+        else                                                    \
+                __mtdcr(rn, v);                                 \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+#define mfdcri(base, reg)                       \
+({                                              \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mfdcr(base ## _CFGDATA);                        \
+})
+
+#define mtdcri(base, reg, data)                 \
+do {                                            \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mtdcr(base ## _CFGDATA, data);          \
+} while (0)
 
+#endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_NATIVE_H */
 
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
index 473f2c7fd892..b66c5e6941f0 100644
--- a/include/asm-powerpc/dcr.h
+++ b/include/asm-powerpc/dcr.h
@@ -20,6 +20,7 @@
 #ifndef _ASM_POWERPC_DCR_H
 #define _ASM_POWERPC_DCR_H
 #ifdef __KERNEL__
+#ifdef CONFIG_PPC_DCR
 
 #ifdef CONFIG_PPC_DCR_NATIVE
 #include <asm/dcr-native.h>
@@ -38,5 +39,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
                                      unsigned int index);
 #endif /* CONFIG_PPC_MERGE */
 
+#endif /* CONFIG_PPC_DCR */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 602fbadeaf48..a263fc1e65c4 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -9,41 +9,9 @@
 #ifndef __ASM_PPC_REG_BOOKE_H__
 #define __ASM_PPC_REG_BOOKE_H__
 
-#ifndef __ASSEMBLY__
-/* Device Control Registers */
-void __mtdcr(int reg, unsigned int val);
-unsigned int __mfdcr(int reg);
-#define mfdcr(rn)                                               \
-        ({unsigned int rval;                                    \
-        if (__builtin_constant_p(rn))                           \
-                asm volatile("mfdcr %0," __stringify(rn)        \
-                              : "=r" (rval));                   \
-        else                                                    \
-                rval = __mfdcr(rn);                             \
-        rval;})
-
-#define mtdcr(rn, v)                                            \
-do {                                                            \
-        if (__builtin_constant_p(rn))                           \
-                asm volatile("mtdcr " __stringify(rn) ",%0"     \
-                              : : "r" (v));                     \
-        else                                                    \
-                __mtdcr(rn, v);                                 \
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-#define mfdcri(base, reg)                       \
-({                                              \
-        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-        mfdcr(base ## _CFGDATA);                        \
-})
-
-#define mtdcri(base, reg, data)                 \
-do {                                            \
-        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
-        mtdcr(base ## _CFGDATA, data);          \
-} while (0)
+#include <asm/dcr.h>
 
+#ifndef __ASSEMBLY__
 /* Performance Monitor Registers */
 #define mfpmr(rn)       ({unsigned int rval; \
                         asm volatile("mfpmr %0," __stringify(rn) \
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 3da29e2d524a..abb64c437f6f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -19,6 +19,7 @@
 #define _FSL_DEVICE_H_
 
 #include <linux/types.h>
+#include <linux/phy.h>
 
 /*
  * Some conventions on how we handle peripherals on Freescale chips