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-rw-r--r--arch/mips/au1000/pb1550/Makefile7
-rw-r--r--arch/mips/au1000/pb1550/board_setup.c16
-rw-r--r--arch/mips/au1000/pb1550/init.c20
-rw-r--r--arch/mips/au1000/pb1550/irqmap.c6
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h51
5 files changed, 49 insertions, 51 deletions
diff --git a/arch/mips/au1000/pb1550/Makefile b/arch/mips/au1000/pb1550/Makefile
index aa35bc6cb8cf..7d8beca87fa5 100644
--- a/arch/mips/au1000/pb1550/Makefile
+++ b/arch/mips/au1000/pb1550/Makefile
@@ -1,9 +1,8 @@
1# 1#
2# Copyright 2000 MontaVista Software Inc. 2# Copyright 2000, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. 3# Author: MontaVista Software, Inc. <source@mvista.com>
4# ppopov@mvista.com or source@mvista.com
5# 4#
6# Makefile for the Alchemy Semiconductor PB1000 board. 5# Makefile for the Alchemy Semiconductor Pb1550 board.
7# 6#
8 7
9lib-y := init.o board_setup.o irqmap.o 8lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/au1000/pb1550/board_setup.c
index 45d60872b565..0ed76b64b6ab 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/au1000/pb1550/board_setup.c
@@ -3,9 +3,8 @@
3 * BRIEF MODULE DESCRIPTION 3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1550 board setup. 4 * Alchemy Pb1550 board setup.
5 * 5 *
6 * Copyright 2000 MontaVista Software Inc. 6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * ppopov@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -35,15 +34,16 @@
35 34
36void board_reset(void) 35void board_reset(void)
37{ 36{
38 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 37 /* Hit BCSR.SYSTEM[RESET] */
39 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); 38 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
40} 39}
41 40
42void __init board_setup(void) 41void __init board_setup(void)
43{ 42{
44 u32 pin_func; 43 u32 pin_func;
45 44
46 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, 45 /*
46 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
47 * but it is board specific code, so put it here. 47 * but it is board specific code, so put it here.
48 */ 48 */
49 pin_func = au_readl(SYS_PINFUNC); 49 pin_func = au_readl(SYS_PINFUNC);
@@ -51,8 +51,8 @@ void __init board_setup(void)
51 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; 51 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
52 au_writel(pin_func, SYS_PINFUNC); 52 au_writel(pin_func, SYS_PINFUNC);
53 53
54 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ 54 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
55 au_sync(); 55 au_sync();
56 56
57 printk("AMD Alchemy Pb1550 Board\n"); 57 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
58} 58}
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index f6b2fc587980..1b5f58434bb7 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -1,11 +1,10 @@
1/* 1/*
2 * 2 *
3 * BRIEF MODULE DESCRIPTION 3 * BRIEF MODULE DESCRIPTION
4 * PB1550 board setup 4 * Pb1550 board setup
5 * 5 *
6 * Copyright 2001 MontaVista Software Inc. 6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * ppopov@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -45,16 +44,15 @@ void __init prom_init(void)
45 unsigned char *memsize_str; 44 unsigned char *memsize_str;
46 unsigned long memsize; 45 unsigned long memsize;
47 46
48 prom_argc = (int) fw_arg0; 47 prom_argc = (int)fw_arg0;
49 prom_argv = (char **) fw_arg1; 48 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **) fw_arg2; 49 prom_envp = (char **)fw_arg2;
51 50
52 prom_init_cmdline(); 51 prom_init_cmdline();
53 memsize_str = prom_getenv("memsize"); 52 memsize_str = prom_getenv("memsize");
54 if (!memsize_str) { 53 if (!memsize_str)
55 memsize = 0x08000000; 54 memsize = 0x08000000;
56 } else { 55 else
57 memsize = simple_strtol(memsize_str, NULL, 0); 56 memsize = strict_strtol(memsize_str, 0, NULL);
58 }
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 58}
diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/au1000/pb1550/irqmap.c
index e1dac37af08a..a02a4d1fa899 100644
--- a/arch/mips/au1000/pb1550/irqmap.c
+++ b/arch/mips/au1000/pb1550/irqmap.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table 3 * Au1xx0 IRQ map table
4 * 4 *
5 * Copyright 2003 Embedded Edge, LLC 5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com 6 * dan@embeddededge.com
@@ -31,8 +31,8 @@
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33char irq_tab_alchemy[][5] __initdata = { 33char irq_tab_alchemy[][5] __initdata = {
34 [12] = { -1, INTB, INTC, INTD, INTA}, /* IDSEL 12 - PCI slot 2 (left) */ 34 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
35 [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ 35 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
36}; 36};
37 37
38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index c2ab0e2df4ae..6704a11497db 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -30,15 +30,15 @@
30#include <linux/types.h> 30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h> 31#include <asm/mach-au1x00/au1xxx_psc.h>
32 32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37 37
38#define SPI_PSC_BASE PSC0_BASE_ADDR 38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR 39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000 43#define BCSR_PHYS_ADDR 0xAF000000
44 44
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
129#define BCSR_SYSTEM_POWEROFF 0x4000 129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000 130#define BCSR_SYSTEM_RESET 0x8000
131 131
132#define PCMCIA_MAX_SOCK 1 132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134 134
135/* VPP/VCC */ 135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT)\ 136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138 138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS 140#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
144#define PB1550_USER_ONLY 144#define PB1550_USER_ONLY
145#endif 145#endif
146 146
147/* Timing values as described in databook, * ns value stripped of 147/*
148 * Timing values as described in databook, * ns value stripped of
148 * lower 2 bits. 149 * lower 2 bits.
149 * These defines are here rather than an SOC1550 generic file because 150 * These defines are here rather than an SOC1550 generic file because
150 * the parts chosen on another board may be different and may require 151 * the parts chosen on another board may be different and may require
151 * different timings. 152 * different timings.
152 */ 153 */
153#define NAND_T_H (18 >> 2) 154#define NAND_T_H (18 >> 2)
154#define NAND_T_PUL (30 >> 2) 155#define NAND_T_PUL (30 >> 2)
155#define NAND_T_SU (30 >> 2) 156#define NAND_T_SU (30 >> 2)
156#define NAND_T_WH (30 >> 2) 157#define NAND_T_WH (30 >> 2)
157 158
158/* Bitfield shift amounts */ 159/* Bitfield shift amounts */
159#define NAND_T_H_SHIFT 0 160#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
161#define NAND_T_SU_SHIFT 8 162#define NAND_T_SU_SHIFT 8
162#define NAND_T_WH_SHIFT 12 163#define NAND_T_WH_SHIFT 12
163 164
164#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 165#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
165 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 166 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 167 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 168 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
168 169
169#define NAND_CS 1 170#define NAND_CS 1
170 171
171/* should be done by yamon */ 172/* Should be done by YAMON */
172#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 173#define NAND_STCFG 0x00400005 /* 8-bit NAND */
173#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 174#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
174#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 175#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
175 176
176#endif /* __ASM_PB1550_H */ 177#endif /* __ASM_PB1550_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 00:44:34 -0500