aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/scsi/libata-bmdma.c234
-rw-r--r--drivers/scsi/libata-core.c234
2 files changed, 234 insertions, 234 deletions
diff --git a/drivers/scsi/libata-bmdma.c b/drivers/scsi/libata-bmdma.c
index 96b4d2160df8..a00a78b30836 100644
--- a/drivers/scsi/libata-bmdma.c
+++ b/drivers/scsi/libata-bmdma.c
@@ -418,6 +418,240 @@ u8 ata_altstatus(struct ata_port *ap)
418 return inb(ap->ioaddr.altstatus_addr); 418 return inb(ap->ioaddr.altstatus_addr);
419} 419}
420 420
421/**
422 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
423 * @qc: Info associated with this ATA transaction.
424 *
425 * LOCKING:
426 * spin_lock_irqsave(host_set lock)
427 */
428
429static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
430{
431 struct ata_port *ap = qc->ap;
432 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
433 u8 dmactl;
434 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
435
436 /* load PRD table addr. */
437 mb(); /* make sure PRD table writes are visible to controller */
438 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
439
440 /* specify data direction, triple-check start bit is clear */
441 dmactl = readb(mmio + ATA_DMA_CMD);
442 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
443 if (!rw)
444 dmactl |= ATA_DMA_WR;
445 writeb(dmactl, mmio + ATA_DMA_CMD);
446
447 /* issue r/w command */
448 ap->ops->exec_command(ap, &qc->tf);
449}
450
451/**
452 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
453 * @qc: Info associated with this ATA transaction.
454 *
455 * LOCKING:
456 * spin_lock_irqsave(host_set lock)
457 */
458
459static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
460{
461 struct ata_port *ap = qc->ap;
462 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
463 u8 dmactl;
464
465 /* start host DMA transaction */
466 dmactl = readb(mmio + ATA_DMA_CMD);
467 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
468
469 /* Strictly, one may wish to issue a readb() here, to
470 * flush the mmio write. However, control also passes
471 * to the hardware at this point, and it will interrupt
472 * us when we are to resume control. So, in effect,
473 * we don't care when the mmio write flushes.
474 * Further, a read of the DMA status register _immediately_
475 * following the write may not be what certain flaky hardware
476 * is expected, so I think it is best to not add a readb()
477 * without first all the MMIO ATA cards/mobos.
478 * Or maybe I'm just being paranoid.
479 */
480}
481
482/**
483 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
484 * @qc: Info associated with this ATA transaction.
485 *
486 * LOCKING:
487 * spin_lock_irqsave(host_set lock)
488 */
489
490static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
491{
492 struct ata_port *ap = qc->ap;
493 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
494 u8 dmactl;
495
496 /* load PRD table addr. */
497 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
498
499 /* specify data direction, triple-check start bit is clear */
500 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
501 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
502 if (!rw)
503 dmactl |= ATA_DMA_WR;
504 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
505
506 /* issue r/w command */
507 ap->ops->exec_command(ap, &qc->tf);
508}
509
510/**
511 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
512 * @qc: Info associated with this ATA transaction.
513 *
514 * LOCKING:
515 * spin_lock_irqsave(host_set lock)
516 */
517
518static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
519{
520 struct ata_port *ap = qc->ap;
521 u8 dmactl;
522
523 /* start host DMA transaction */
524 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
525 outb(dmactl | ATA_DMA_START,
526 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
527}
528
529
530/**
531 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
532 * @qc: Info associated with this ATA transaction.
533 *
534 * Writes the ATA_DMA_START flag to the DMA command register.
535 *
536 * May be used as the bmdma_start() entry in ata_port_operations.
537 *
538 * LOCKING:
539 * spin_lock_irqsave(host_set lock)
540 */
541void ata_bmdma_start(struct ata_queued_cmd *qc)
542{
543 if (qc->ap->flags & ATA_FLAG_MMIO)
544 ata_bmdma_start_mmio(qc);
545 else
546 ata_bmdma_start_pio(qc);
547}
548
549
550/**
551 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
552 * @qc: Info associated with this ATA transaction.
553 *
554 * Writes address of PRD table to device's PRD Table Address
555 * register, sets the DMA control register, and calls
556 * ops->exec_command() to start the transfer.
557 *
558 * May be used as the bmdma_setup() entry in ata_port_operations.
559 *
560 * LOCKING:
561 * spin_lock_irqsave(host_set lock)
562 */
563void ata_bmdma_setup(struct ata_queued_cmd *qc)
564{
565 if (qc->ap->flags & ATA_FLAG_MMIO)
566 ata_bmdma_setup_mmio(qc);
567 else
568 ata_bmdma_setup_pio(qc);
569}
570
571
572/**
573 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
574 * @ap: Port associated with this ATA transaction.
575 *
576 * Clear interrupt and error flags in DMA status register.
577 *
578 * May be used as the irq_clear() entry in ata_port_operations.
579 *
580 * LOCKING:
581 * spin_lock_irqsave(host_set lock)
582 */
583
584void ata_bmdma_irq_clear(struct ata_port *ap)
585{
586 if (!ap->ioaddr.bmdma_addr)
587 return;
588
589 if (ap->flags & ATA_FLAG_MMIO) {
590 void __iomem *mmio =
591 ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
592 writeb(readb(mmio), mmio);
593 } else {
594 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
595 outb(inb(addr), addr);
596 }
597}
598
599
600/**
601 * ata_bmdma_status - Read PCI IDE BMDMA status
602 * @ap: Port associated with this ATA transaction.
603 *
604 * Read and return BMDMA status register.
605 *
606 * May be used as the bmdma_status() entry in ata_port_operations.
607 *
608 * LOCKING:
609 * spin_lock_irqsave(host_set lock)
610 */
611
612u8 ata_bmdma_status(struct ata_port *ap)
613{
614 u8 host_stat;
615 if (ap->flags & ATA_FLAG_MMIO) {
616 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
617 host_stat = readb(mmio + ATA_DMA_STATUS);
618 } else
619 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
620 return host_stat;
621}
622
623
624/**
625 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
626 * @qc: Command we are ending DMA for
627 *
628 * Clears the ATA_DMA_START flag in the dma control register
629 *
630 * May be used as the bmdma_stop() entry in ata_port_operations.
631 *
632 * LOCKING:
633 * spin_lock_irqsave(host_set lock)
634 */
635
636void ata_bmdma_stop(struct ata_queued_cmd *qc)
637{
638 struct ata_port *ap = qc->ap;
639 if (ap->flags & ATA_FLAG_MMIO) {
640 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
641
642 /* clear start/stop bit */
643 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
644 mmio + ATA_DMA_CMD);
645 } else {
646 /* clear start/stop bit */
647 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
648 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
649 }
650
651 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
652 ata_altstatus(ap); /* dummy read */
653}
654
421#ifdef CONFIG_PCI 655#ifdef CONFIG_PCI
422static struct ata_probe_ent * 656static struct ata_probe_ent *
423ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port) 657ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index 0314abd97f2d..f3c115b55681 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -4065,240 +4065,6 @@ unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
4065} 4065}
4066 4066
4067/** 4067/**
4068 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
4069 * @qc: Info associated with this ATA transaction.
4070 *
4071 * LOCKING:
4072 * spin_lock_irqsave(host_set lock)
4073 */
4074
4075static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
4076{
4077 struct ata_port *ap = qc->ap;
4078 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4079 u8 dmactl;
4080 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4081
4082 /* load PRD table addr. */
4083 mb(); /* make sure PRD table writes are visible to controller */
4084 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
4085
4086 /* specify data direction, triple-check start bit is clear */
4087 dmactl = readb(mmio + ATA_DMA_CMD);
4088 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4089 if (!rw)
4090 dmactl |= ATA_DMA_WR;
4091 writeb(dmactl, mmio + ATA_DMA_CMD);
4092
4093 /* issue r/w command */
4094 ap->ops->exec_command(ap, &qc->tf);
4095}
4096
4097/**
4098 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
4099 * @qc: Info associated with this ATA transaction.
4100 *
4101 * LOCKING:
4102 * spin_lock_irqsave(host_set lock)
4103 */
4104
4105static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
4106{
4107 struct ata_port *ap = qc->ap;
4108 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4109 u8 dmactl;
4110
4111 /* start host DMA transaction */
4112 dmactl = readb(mmio + ATA_DMA_CMD);
4113 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
4114
4115 /* Strictly, one may wish to issue a readb() here, to
4116 * flush the mmio write. However, control also passes
4117 * to the hardware at this point, and it will interrupt
4118 * us when we are to resume control. So, in effect,
4119 * we don't care when the mmio write flushes.
4120 * Further, a read of the DMA status register _immediately_
4121 * following the write may not be what certain flaky hardware
4122 * is expected, so I think it is best to not add a readb()
4123 * without first all the MMIO ATA cards/mobos.
4124 * Or maybe I'm just being paranoid.
4125 */
4126}
4127
4128/**
4129 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
4130 * @qc: Info associated with this ATA transaction.
4131 *
4132 * LOCKING:
4133 * spin_lock_irqsave(host_set lock)
4134 */
4135
4136static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
4137{
4138 struct ata_port *ap = qc->ap;
4139 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4140 u8 dmactl;
4141
4142 /* load PRD table addr. */
4143 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
4144
4145 /* specify data direction, triple-check start bit is clear */
4146 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4147 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4148 if (!rw)
4149 dmactl |= ATA_DMA_WR;
4150 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4151
4152 /* issue r/w command */
4153 ap->ops->exec_command(ap, &qc->tf);
4154}
4155
4156/**
4157 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
4158 * @qc: Info associated with this ATA transaction.
4159 *
4160 * LOCKING:
4161 * spin_lock_irqsave(host_set lock)
4162 */
4163
4164static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
4165{
4166 struct ata_port *ap = qc->ap;
4167 u8 dmactl;
4168
4169 /* start host DMA transaction */
4170 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4171 outb(dmactl | ATA_DMA_START,
4172 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4173}
4174
4175
4176/**
4177 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
4178 * @qc: Info associated with this ATA transaction.
4179 *
4180 * Writes the ATA_DMA_START flag to the DMA command register.
4181 *
4182 * May be used as the bmdma_start() entry in ata_port_operations.
4183 *
4184 * LOCKING:
4185 * spin_lock_irqsave(host_set lock)
4186 */
4187void ata_bmdma_start(struct ata_queued_cmd *qc)
4188{
4189 if (qc->ap->flags & ATA_FLAG_MMIO)
4190 ata_bmdma_start_mmio(qc);
4191 else
4192 ata_bmdma_start_pio(qc);
4193}
4194
4195
4196/**
4197 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
4198 * @qc: Info associated with this ATA transaction.
4199 *
4200 * Writes address of PRD table to device's PRD Table Address
4201 * register, sets the DMA control register, and calls
4202 * ops->exec_command() to start the transfer.
4203 *
4204 * May be used as the bmdma_setup() entry in ata_port_operations.
4205 *
4206 * LOCKING:
4207 * spin_lock_irqsave(host_set lock)
4208 */
4209void ata_bmdma_setup(struct ata_queued_cmd *qc)
4210{
4211 if (qc->ap->flags & ATA_FLAG_MMIO)
4212 ata_bmdma_setup_mmio(qc);
4213 else
4214 ata_bmdma_setup_pio(qc);
4215}
4216
4217
4218/**
4219 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
4220 * @ap: Port associated with this ATA transaction.
4221 *
4222 * Clear interrupt and error flags in DMA status register.
4223 *
4224 * May be used as the irq_clear() entry in ata_port_operations.
4225 *
4226 * LOCKING:
4227 * spin_lock_irqsave(host_set lock)
4228 */
4229
4230void ata_bmdma_irq_clear(struct ata_port *ap)
4231{
4232 if (!ap->ioaddr.bmdma_addr)
4233 return;
4234
4235 if (ap->flags & ATA_FLAG_MMIO) {
4236 void __iomem *mmio =
4237 ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
4238 writeb(readb(mmio), mmio);
4239 } else {
4240 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
4241 outb(inb(addr), addr);
4242 }
4243}
4244
4245
4246/**
4247 * ata_bmdma_status - Read PCI IDE BMDMA status
4248 * @ap: Port associated with this ATA transaction.
4249 *
4250 * Read and return BMDMA status register.
4251 *
4252 * May be used as the bmdma_status() entry in ata_port_operations.
4253 *
4254 * LOCKING:
4255 * spin_lock_irqsave(host_set lock)
4256 */
4257
4258u8 ata_bmdma_status(struct ata_port *ap)
4259{
4260 u8 host_stat;
4261 if (ap->flags & ATA_FLAG_MMIO) {
4262 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4263 host_stat = readb(mmio + ATA_DMA_STATUS);
4264 } else
4265 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
4266 return host_stat;
4267}
4268
4269
4270/**
4271 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
4272 * @qc: Command we are ending DMA for
4273 *
4274 * Clears the ATA_DMA_START flag in the dma control register
4275 *
4276 * May be used as the bmdma_stop() entry in ata_port_operations.
4277 *
4278 * LOCKING:
4279 * spin_lock_irqsave(host_set lock)
4280 */
4281
4282void ata_bmdma_stop(struct ata_queued_cmd *qc)
4283{
4284 struct ata_port *ap = qc->ap;
4285 if (ap->flags & ATA_FLAG_MMIO) {
4286 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4287
4288 /* clear start/stop bit */
4289 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4290 mmio + ATA_DMA_CMD);
4291 } else {
4292 /* clear start/stop bit */
4293 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4294 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4295 }
4296
4297 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4298 ata_altstatus(ap); /* dummy read */
4299}
4300
4301/**
4302 * ata_host_intr - Handle host interrupt for given (port, task) 4068 * ata_host_intr - Handle host interrupt for given (port, task)
4303 * @ap: Port on which interrupt arrived (possibly...) 4069 * @ap: Port on which interrupt arrived (possibly...)
4304 * @qc: Taskfile currently active in engine 4070 * @qc: Taskfile currently active in engine
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 20:42:54 -0500