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-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index cfabeb974a56..41fe8aec0a12 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -279,6 +279,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
279 return ret; 279 return ret;
280 280
281 if (limits.vco2.maxfreq) { 281 if (limits.vco2.maxfreq) {
282 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
283 pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P);
284
282 reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00; 285 reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
283 reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00; 286 reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
284 nv_wr32(dev, pll_reg, 0x10000611); 287 nv_wr32(dev, pll_reg, 0x10000611);
@@ -286,6 +289,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
286 nv_wr32(dev, pll_reg + 8, 289 nv_wr32(dev, pll_reg + 8,
287 reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2); 290 reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
288 } else { 291 } else {
292 NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n",
293 pclk, ret, pll.N1, pll.M1, pll.log2P);
294
289 reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000; 295 reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
290 nv_wr32(dev, pll_reg, 0x50000610); 296 nv_wr32(dev, pll_reg, 0x50000610);
291 nv_wr32(dev, pll_reg + 4, reg1 | 297 nv_wr32(dev, pll_reg + 4, reg1 |