diff options
-rw-r--r-- | arch/mips/au1000/common/irq.c | 7 | ||||
-rw-r--r-- | arch/mips/au1000/common/time.c | 8 | ||||
-rw-r--r-- | include/asm-mips/mach-au1x00/au1000.h | 12 |
3 files changed, 7 insertions, 20 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 3c7714f057ac..5528e1412b50 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c | |||
@@ -1,7 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | 2 | * Copyright 2001, 2007-2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. | 3 | * Author: MontaVista Software, Inc. <source@mvista.com> |
4 | * ppopov@mvista.com or source@mvista.com | ||
5 | * | 4 | * |
6 | * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) | 5 | * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) |
7 | * | 6 | * |
@@ -591,7 +590,7 @@ void __init arch_init_irq(void) | |||
591 | imp++; | 590 | imp++; |
592 | } | 591 | } |
593 | 592 | ||
594 | set_c0_status(ALLINTS); | 593 | set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); |
595 | 594 | ||
596 | /* Board specific IRQ initialization. | 595 | /* Board specific IRQ initialization. |
597 | */ | 596 | */ |
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index e122bbc6cd88..1966964590ab 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com | 3 | * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> |
4 | * Copied and modified Carsten Langgaard's time.c | 4 | * Copied and modified Carsten Langgaard's time.c |
5 | * | 5 | * |
6 | * Carsten Langgaard, carstenl@mips.com | 6 | * Carsten Langgaard, carstenl@mips.com |
@@ -265,12 +265,8 @@ void __init plat_time_init(void) | |||
265 | * Check to ensure we really have a 32KHz oscillator before | 265 | * Check to ensure we really have a 32KHz oscillator before |
266 | * we do this. | 266 | * we do this. |
267 | */ | 267 | */ |
268 | if (no_au1xxx_32khz) { | 268 | if (no_au1xxx_32khz) |
269 | printk("WARNING: no 32KHz clock found.\n"); | 269 | printk("WARNING: no 32KHz clock found.\n"); |
270 | |||
271 | /* Ensure we get CPO_COUNTER interrupts. */ | ||
272 | set_c0_status(IE_IRQ5); | ||
273 | } | ||
274 | else { | 270 | else { |
275 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); | 271 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); |
276 | au_writel(0, SYS_TOYWRITE); | 272 | au_writel(0, SYS_TOYWRITE); |
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 5bb57bf2b9d7..a88637a93e01 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h | |||
@@ -3,9 +3,8 @@ | |||
3 | * BRIEF MODULE DESCRIPTION | 3 | * BRIEF MODULE DESCRIPTION |
4 | * Include file for Alchemy Semiconductor's Au1k CPU. | 4 | * Include file for Alchemy Semiconductor's Au1k CPU. |
5 | * | 5 | * |
6 | * Copyright 2000,2001 MontaVista Software Inc. | 6 | * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. |
7 | * Author: MontaVista Software, Inc. | 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
8 | * ppopov@mvista.com or source@mvista.com | ||
9 | * | 8 | * |
10 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
11 | * under the terms of the GNU General Public License as published by the | 10 | * under the terms of the GNU General Public License as published by the |
@@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
117 | 116 | ||
118 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | 117 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
119 | 118 | ||
120 | #ifdef CONFIG_PM | ||
121 | /* no CP0 timer irq */ | ||
122 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) | ||
123 | #else | ||
124 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | ||
125 | #endif | ||
126 | |||
127 | /* | 119 | /* |
128 | * SDRAM Register Offsets | 120 | * SDRAM Register Offsets |
129 | */ | 121 | */ |