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-rw-r--r--arch/arm/mach-omap2/devices.c187
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c156
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c219
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c280
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h11
-rw-r--r--drivers/spi/omap2_mcspi.c222
6 files changed, 774 insertions, 301 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e0f0ef952bc9..71f099b85e7c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -15,6 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/slab.h>
18 19
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include <mach/irqs.h> 21#include <mach/irqs.h>
@@ -279,163 +280,55 @@ static inline void omap_init_audio(void) {}
279 280
280#include <plat/mcspi.h> 281#include <plat/mcspi.h>
281 282
282#define OMAP2_MCSPI1_BASE 0x48098000 283struct omap_device_pm_latency omap_mcspi_latency[] = {
283#define OMAP2_MCSPI2_BASE 0x4809a000 284 [0] = {
284#define OMAP2_MCSPI3_BASE 0x480b8000 285 .deactivate_func = omap_device_idle_hwmods,
285#define OMAP2_MCSPI4_BASE 0x480ba000 286 .activate_func = omap_device_enable_hwmods,
286 287 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
287#define OMAP4_MCSPI1_BASE 0x48098100
288#define OMAP4_MCSPI2_BASE 0x4809a100
289#define OMAP4_MCSPI3_BASE 0x480b8100
290#define OMAP4_MCSPI4_BASE 0x480ba100
291
292static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
293 .num_cs = 4,
294};
295
296static struct resource omap2_mcspi1_resources[] = {
297 {
298 .start = OMAP2_MCSPI1_BASE,
299 .end = OMAP2_MCSPI1_BASE + 0xff,
300 .flags = IORESOURCE_MEM,
301 },
302};
303
304static struct platform_device omap2_mcspi1 = {
305 .name = "omap2_mcspi",
306 .id = 1,
307 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
308 .resource = omap2_mcspi1_resources,
309 .dev = {
310 .platform_data = &omap2_mcspi1_config,
311 },
312};
313
314static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
315 .num_cs = 2,
316};
317
318static struct resource omap2_mcspi2_resources[] = {
319 {
320 .start = OMAP2_MCSPI2_BASE,
321 .end = OMAP2_MCSPI2_BASE + 0xff,
322 .flags = IORESOURCE_MEM,
323 },
324};
325
326static struct platform_device omap2_mcspi2 = {
327 .name = "omap2_mcspi",
328 .id = 2,
329 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
330 .resource = omap2_mcspi2_resources,
331 .dev = {
332 .platform_data = &omap2_mcspi2_config,
333 },
334};
335
336#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
337 defined(CONFIG_ARCH_OMAP4)
338static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
339 .num_cs = 2,
340};
341
342static struct resource omap2_mcspi3_resources[] = {
343 {
344 .start = OMAP2_MCSPI3_BASE,
345 .end = OMAP2_MCSPI3_BASE + 0xff,
346 .flags = IORESOURCE_MEM,
347 },
348};
349
350static struct platform_device omap2_mcspi3 = {
351 .name = "omap2_mcspi",
352 .id = 3,
353 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
354 .resource = omap2_mcspi3_resources,
355 .dev = {
356 .platform_data = &omap2_mcspi3_config,
357 },
358};
359#endif
360
361#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
362static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
363 .num_cs = 1,
364};
365
366static struct resource omap2_mcspi4_resources[] = {
367 {
368 .start = OMAP2_MCSPI4_BASE,
369 .end = OMAP2_MCSPI4_BASE + 0xff,
370 .flags = IORESOURCE_MEM,
371 },
372};
373
374static struct platform_device omap2_mcspi4 = {
375 .name = "omap2_mcspi",
376 .id = 4,
377 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
378 .resource = omap2_mcspi4_resources,
379 .dev = {
380 .platform_data = &omap2_mcspi4_config,
381 }, 288 },
382}; 289};
383#endif
384 290
385#ifdef CONFIG_ARCH_OMAP4 291static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
386static inline void omap4_mcspi_fixup(void)
387{ 292{
388 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; 293 struct omap_device *od;
389 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; 294 char *name = "omap2_mcspi";
390 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; 295 struct omap2_mcspi_platform_config *pdata;
391 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; 296 static int spi_num;
392 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; 297 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
393 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; 298
394 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; 299 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
395 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; 300 if (!pdata) {
396} 301 pr_err("Memory allocation for McSPI device failed\n");
397#else 302 return -ENOMEM;
398static inline void omap4_mcspi_fixup(void) 303 }
399{
400}
401#endif
402 304
403#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ 305 pdata->num_cs = mcspi_attrib->num_chipselect;
404 defined(CONFIG_ARCH_OMAP4) 306 switch (oh->class->rev) {
405static inline void omap2_mcspi3_init(void) 307 case OMAP2_MCSPI_REV:
406{ 308 case OMAP3_MCSPI_REV:
407 platform_device_register(&omap2_mcspi3); 309 pdata->regs_offset = 0;
408} 310 break;
409#else 311 case OMAP4_MCSPI_REV:
410static inline void omap2_mcspi3_init(void) 312 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
411{ 313 break;
412} 314 default:
413#endif 315 pr_err("Invalid McSPI Revision value\n");
316 return -EINVAL;
317 }
414 318
415#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 319 spi_num++;
416static inline void omap2_mcspi4_init(void) 320 od = omap_device_build(name, spi_num, oh, pdata,
417{ 321 sizeof(*pdata), omap_mcspi_latency,
418 platform_device_register(&omap2_mcspi4); 322 ARRAY_SIZE(omap_mcspi_latency), 0);
419} 323 WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
420#else 324 name, oh->name);
421static inline void omap2_mcspi4_init(void) 325 kfree(pdata);
422{ 326 return 0;
423} 327}
424#endif
425 328
426static void omap_init_mcspi(void) 329static void omap_init_mcspi(void)
427{ 330{
428 if (cpu_is_omap44xx()) 331 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
429 omap4_mcspi_fixup();
430
431 platform_device_register(&omap2_mcspi1);
432 platform_device_register(&omap2_mcspi2);
433
434 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
435 omap2_mcspi3_init();
436
437 if (cpu_is_omap343x() || cpu_is_omap44xx())
438 omap2_mcspi4_init();
439} 332}
440 333
441#else 334#else
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b85c630b64d6..7fffd340c76f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,6 +18,7 @@
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h>
21 22
22#include "omap_hwmod_common_data.h" 23#include "omap_hwmod_common_data.h"
23 24
@@ -44,6 +45,8 @@ static struct omap_hwmod omap2420_gpio2_hwmod;
44static struct omap_hwmod omap2420_gpio3_hwmod; 45static struct omap_hwmod omap2420_gpio3_hwmod;
45static struct omap_hwmod omap2420_gpio4_hwmod; 46static struct omap_hwmod omap2420_gpio4_hwmod;
46static struct omap_hwmod omap2420_dma_system_hwmod; 47static struct omap_hwmod omap2420_dma_system_hwmod;
48static struct omap_hwmod omap2420_mcspi1_hwmod;
49static struct omap_hwmod omap2420_mcspi2_hwmod;
47 50
48/* L3 -> L4_CORE interface */ 51/* L3 -> L4_CORE interface */
49static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { 52static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -88,6 +91,42 @@ static struct omap_hwmod omap2420_uart3_hwmod;
88static struct omap_hwmod omap2420_i2c1_hwmod; 91static struct omap_hwmod omap2420_i2c1_hwmod;
89static struct omap_hwmod omap2420_i2c2_hwmod; 92static struct omap_hwmod omap2420_i2c2_hwmod;
90 93
94/* l4 core -> mcspi1 interface */
95static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
96 {
97 .pa_start = 0x48098000,
98 .pa_end = 0x480980ff,
99 .flags = ADDR_TYPE_RT,
100 },
101};
102
103static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
104 .master = &omap2420_l4_core_hwmod,
105 .slave = &omap2420_mcspi1_hwmod,
106 .clk = "mcspi1_ick",
107 .addr = omap2420_mcspi1_addr_space,
108 .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
109 .user = OCP_USER_MPU | OCP_USER_SDMA,
110};
111
112/* l4 core -> mcspi2 interface */
113static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
114 {
115 .pa_start = 0x4809a000,
116 .pa_end = 0x4809a0ff,
117 .flags = ADDR_TYPE_RT,
118 },
119};
120
121static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
122 .master = &omap2420_l4_core_hwmod,
123 .slave = &omap2420_mcspi2_hwmod,
124 .clk = "mcspi2_ick",
125 .addr = omap2420_mcspi2_addr_space,
126 .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
127 .user = OCP_USER_MPU | OCP_USER_SDMA,
128};
129
91/* L4_CORE -> L4_WKUP interface */ 130/* L4_CORE -> L4_WKUP interface */
92static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { 131static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
93 .master = &omap2420_l4_core_hwmod, 132 .master = &omap2420_l4_core_hwmod,
@@ -864,6 +903,119 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
864 .flags = HWMOD_NO_IDLEST, 903 .flags = HWMOD_NO_IDLEST,
865}; 904};
866 905
906/*
907 * 'mcspi' class
908 * multichannel serial port interface (mcspi) / master/slave synchronous serial
909 * bus
910 */
911
912static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
913 .rev_offs = 0x0000,
914 .sysc_offs = 0x0010,
915 .syss_offs = 0x0014,
916 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
917 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
918 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
919 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
920 .sysc_fields = &omap_hwmod_sysc_type1,
921};
922
923static struct omap_hwmod_class omap2420_mcspi_class = {
924 .name = "mcspi",
925 .sysc = &omap2420_mcspi_sysc,
926 .rev = OMAP2_MCSPI_REV,
927};
928
929/* mcspi1 */
930static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
931 { .irq = 65 },
932};
933
934static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
935 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
936 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
937 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
938 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
939 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
940 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
941 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
942 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
943};
944
945static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
946 &omap2420_l4_core__mcspi1,
947};
948
949static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
950 .num_chipselect = 4,
951};
952
953static struct omap_hwmod omap2420_mcspi1_hwmod = {
954 .name = "mcspi1_hwmod",
955 .mpu_irqs = omap2420_mcspi1_mpu_irqs,
956 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
957 .sdma_reqs = omap2420_mcspi1_sdma_reqs,
958 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
959 .main_clk = "mcspi1_fck",
960 .prcm = {
961 .omap2 = {
962 .module_offs = CORE_MOD,
963 .prcm_reg_id = 1,
964 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
965 .idlest_reg_id = 1,
966 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
967 },
968 },
969 .slaves = omap2420_mcspi1_slaves,
970 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
971 .class = &omap2420_mcspi_class,
972 .dev_attr = &omap_mcspi1_dev_attr,
973 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
974};
975
976/* mcspi2 */
977static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
978 { .irq = 66 },
979};
980
981static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
982 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
983 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
984 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
985 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
986};
987
988static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
989 &omap2420_l4_core__mcspi2,
990};
991
992static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
993 .num_chipselect = 2,
994};
995
996static struct omap_hwmod omap2420_mcspi2_hwmod = {
997 .name = "mcspi2_hwmod",
998 .mpu_irqs = omap2420_mcspi2_mpu_irqs,
999 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
1000 .sdma_reqs = omap2420_mcspi2_sdma_reqs,
1001 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
1002 .main_clk = "mcspi2_fck",
1003 .prcm = {
1004 .omap2 = {
1005 .module_offs = CORE_MOD,
1006 .prcm_reg_id = 1,
1007 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1008 .idlest_reg_id = 1,
1009 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1010 },
1011 },
1012 .slaves = omap2420_mcspi2_slaves,
1013 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1014 .class = &omap2420_mcspi_class,
1015 .dev_attr = &omap_mcspi2_dev_attr,
1016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1017};
1018
867static __initdata struct omap_hwmod *omap2420_hwmods[] = { 1019static __initdata struct omap_hwmod *omap2420_hwmods[] = {
868 &omap2420_l3_main_hwmod, 1020 &omap2420_l3_main_hwmod,
869 &omap2420_l4_core_hwmod, 1021 &omap2420_l4_core_hwmod,
@@ -885,6 +1037,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
885 1037
886 /* dma_system class*/ 1038 /* dma_system class*/
887 &omap2420_dma_system_hwmod, 1039 &omap2420_dma_system_hwmod,
1040
1041 /* mcspi class */
1042 &omap2420_mcspi1_hwmod,
1043 &omap2420_mcspi2_hwmod,
888 NULL, 1044 NULL,
889}; 1045};
890 1046
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcde13ba..60fe4aac1f50 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,6 +18,7 @@
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h>
21 22
22#include "omap_hwmod_common_data.h" 23#include "omap_hwmod_common_data.h"
23 24
@@ -45,6 +46,9 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
45static struct omap_hwmod omap2430_gpio4_hwmod; 46static struct omap_hwmod omap2430_gpio4_hwmod;
46static struct omap_hwmod omap2430_gpio5_hwmod; 47static struct omap_hwmod omap2430_gpio5_hwmod;
47static struct omap_hwmod omap2430_dma_system_hwmod; 48static struct omap_hwmod omap2430_dma_system_hwmod;
49static struct omap_hwmod omap2430_mcspi1_hwmod;
50static struct omap_hwmod omap2430_mcspi2_hwmod;
51static struct omap_hwmod omap2430_mcspi3_hwmod;
48 52
49/* L3 -> L4_CORE interface */ 53/* L3 -> L4_CORE interface */
50static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 54static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -223,6 +227,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
223static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { 227static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
224}; 228};
225 229
230/* l4 core -> mcspi1 interface */
231static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
232 {
233 .pa_start = 0x48098000,
234 .pa_end = 0x480980ff,
235 .flags = ADDR_TYPE_RT,
236 },
237};
238
239static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
240 .master = &omap2430_l4_core_hwmod,
241 .slave = &omap2430_mcspi1_hwmod,
242 .clk = "mcspi1_ick",
243 .addr = omap2430_mcspi1_addr_space,
244 .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
245 .user = OCP_USER_MPU | OCP_USER_SDMA,
246};
247
248/* l4 core -> mcspi2 interface */
249static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
250 {
251 .pa_start = 0x4809a000,
252 .pa_end = 0x4809a0ff,
253 .flags = ADDR_TYPE_RT,
254 },
255};
256
257static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
258 .master = &omap2430_l4_core_hwmod,
259 .slave = &omap2430_mcspi2_hwmod,
260 .clk = "mcspi2_ick",
261 .addr = omap2430_mcspi2_addr_space,
262 .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l4 core -> mcspi3 interface */
267static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
268 {
269 .pa_start = 0x480b8000,
270 .pa_end = 0x480b80ff,
271 .flags = ADDR_TYPE_RT,
272 },
273};
274
275static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
276 .master = &omap2430_l4_core_hwmod,
277 .slave = &omap2430_mcspi3_hwmod,
278 .clk = "mcspi3_ick",
279 .addr = omap2430_mcspi3_addr_space,
280 .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
281 .user = OCP_USER_MPU | OCP_USER_SDMA,
282};
283
226/* L4 WKUP */ 284/* L4 WKUP */
227static struct omap_hwmod omap2430_l4_wkup_hwmod = { 285static struct omap_hwmod omap2430_l4_wkup_hwmod = {
228 .name = "l4_wkup", 286 .name = "l4_wkup",
@@ -919,6 +977,162 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
919 .flags = HWMOD_NO_IDLEST, 977 .flags = HWMOD_NO_IDLEST,
920}; 978};
921 979
980/*
981 * 'mcspi' class
982 * multichannel serial port interface (mcspi) / master/slave synchronous serial
983 * bus
984 */
985
986static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
987 .rev_offs = 0x0000,
988 .sysc_offs = 0x0010,
989 .syss_offs = 0x0014,
990 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
991 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
992 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
993 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
994 .sysc_fields = &omap_hwmod_sysc_type1,
995};
996
997static struct omap_hwmod_class omap2430_mcspi_class = {
998 .name = "mcspi",
999 .sysc = &omap2430_mcspi_sysc,
1000 .rev = OMAP2_MCSPI_REV,
1001};
1002
1003/* mcspi1 */
1004static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
1005 { .irq = 65 },
1006};
1007
1008static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
1009 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1010 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1011 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1012 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1013 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1014 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1015 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1016 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1017};
1018
1019static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1020 &omap2430_l4_core__mcspi1,
1021};
1022
1023static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1024 .num_chipselect = 4,
1025};
1026
1027static struct omap_hwmod omap2430_mcspi1_hwmod = {
1028 .name = "mcspi1_hwmod",
1029 .mpu_irqs = omap2430_mcspi1_mpu_irqs,
1030 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
1031 .sdma_reqs = omap2430_mcspi1_sdma_reqs,
1032 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
1033 .main_clk = "mcspi1_fck",
1034 .prcm = {
1035 .omap2 = {
1036 .module_offs = CORE_MOD,
1037 .prcm_reg_id = 1,
1038 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1039 .idlest_reg_id = 1,
1040 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1041 },
1042 },
1043 .slaves = omap2430_mcspi1_slaves,
1044 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1045 .class = &omap2430_mcspi_class,
1046 .dev_attr = &omap_mcspi1_dev_attr,
1047 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1048};
1049
1050/* mcspi2 */
1051static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
1052 { .irq = 66 },
1053};
1054
1055static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
1056 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1057 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1058 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1059 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1060};
1061
1062static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1063 &omap2430_l4_core__mcspi2,
1064};
1065
1066static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1067 .num_chipselect = 2,
1068};
1069
1070static struct omap_hwmod omap2430_mcspi2_hwmod = {
1071 .name = "mcspi2_hwmod",
1072 .mpu_irqs = omap2430_mcspi2_mpu_irqs,
1073 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
1074 .sdma_reqs = omap2430_mcspi2_sdma_reqs,
1075 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
1076 .main_clk = "mcspi2_fck",
1077 .prcm = {
1078 .omap2 = {
1079 .module_offs = CORE_MOD,
1080 .prcm_reg_id = 1,
1081 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1082 .idlest_reg_id = 1,
1083 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1084 },
1085 },
1086 .slaves = omap2430_mcspi2_slaves,
1087 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1088 .class = &omap2430_mcspi_class,
1089 .dev_attr = &omap_mcspi2_dev_attr,
1090 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1091};
1092
1093/* mcspi3 */
1094static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1095 { .irq = 91 },
1096};
1097
1098static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1099 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1100 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1101 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1102 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1103};
1104
1105static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1106 &omap2430_l4_core__mcspi3,
1107};
1108
1109static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1110 .num_chipselect = 2,
1111};
1112
1113static struct omap_hwmod omap2430_mcspi3_hwmod = {
1114 .name = "mcspi3_hwmod",
1115 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
1116 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
1117 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
1118 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
1119 .main_clk = "mcspi3_fck",
1120 .prcm = {
1121 .omap2 = {
1122 .module_offs = CORE_MOD,
1123 .prcm_reg_id = 2,
1124 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1125 .idlest_reg_id = 2,
1126 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1127 },
1128 },
1129 .slaves = omap2430_mcspi3_slaves,
1130 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1131 .class = &omap2430_mcspi_class,
1132 .dev_attr = &omap_mcspi3_dev_attr,
1133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1134};
1135
922static __initdata struct omap_hwmod *omap2430_hwmods[] = { 1136static __initdata struct omap_hwmod *omap2430_hwmods[] = {
923 &omap2430_l3_main_hwmod, 1137 &omap2430_l3_main_hwmod,
924 &omap2430_l4_core_hwmod, 1138 &omap2430_l4_core_hwmod,
@@ -941,6 +1155,11 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
941 1155
942 /* dma_system class*/ 1156 /* dma_system class*/
943 &omap2430_dma_system_hwmod, 1157 &omap2430_dma_system_hwmod,
1158
1159 /* mcspi class */
1160 &omap2430_mcspi1_hwmod,
1161 &omap2430_mcspi2_hwmod,
1162 &omap2430_mcspi3_hwmod,
944 NULL, 1163 NULL,
945}; 1164};
946 1165
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d8181334f86..800eda4adb54 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,6 +22,7 @@
22#include <plat/i2c.h> 22#include <plat/i2c.h>
23#include <plat/gpio.h> 23#include <plat/gpio.h>
24#include <plat/smartreflex.h> 24#include <plat/smartreflex.h>
25#include <plat/mcspi.h>
25 26
26#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
27 28
@@ -55,6 +56,10 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
55static struct omap_hwmod omap3xxx_gpio6_hwmod; 56static struct omap_hwmod omap3xxx_gpio6_hwmod;
56static struct omap_hwmod omap34xx_sr1_hwmod; 57static struct omap_hwmod omap34xx_sr1_hwmod;
57static struct omap_hwmod omap34xx_sr2_hwmod; 58static struct omap_hwmod omap34xx_sr2_hwmod;
59static struct omap_hwmod omap34xx_mcspi1;
60static struct omap_hwmod omap34xx_mcspi2;
61static struct omap_hwmod omap34xx_mcspi3;
62static struct omap_hwmod omap34xx_mcspi4;
58 63
59static struct omap_hwmod omap3xxx_dma_system_hwmod; 64static struct omap_hwmod omap3xxx_dma_system_hwmod;
60 65
@@ -1356,6 +1361,275 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
1356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1361 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1357}; 1362};
1358 1363
1364/* l4 core -> mcspi1 interface */
1365static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
1366 {
1367 .pa_start = 0x48098000,
1368 .pa_end = 0x480980ff,
1369 .flags = ADDR_TYPE_RT,
1370 },
1371};
1372
1373static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
1374 .master = &omap3xxx_l4_core_hwmod,
1375 .slave = &omap34xx_mcspi1,
1376 .clk = "mcspi1_ick",
1377 .addr = omap34xx_mcspi1_addr_space,
1378 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
1379 .user = OCP_USER_MPU | OCP_USER_SDMA,
1380};
1381
1382/* l4 core -> mcspi2 interface */
1383static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
1384 {
1385 .pa_start = 0x4809a000,
1386 .pa_end = 0x4809a0ff,
1387 .flags = ADDR_TYPE_RT,
1388 },
1389};
1390
1391static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
1392 .master = &omap3xxx_l4_core_hwmod,
1393 .slave = &omap34xx_mcspi2,
1394 .clk = "mcspi2_ick",
1395 .addr = omap34xx_mcspi2_addr_space,
1396 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
1397 .user = OCP_USER_MPU | OCP_USER_SDMA,
1398};
1399
1400/* l4 core -> mcspi3 interface */
1401static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
1402 {
1403 .pa_start = 0x480b8000,
1404 .pa_end = 0x480b80ff,
1405 .flags = ADDR_TYPE_RT,
1406 },
1407};
1408
1409static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
1410 .master = &omap3xxx_l4_core_hwmod,
1411 .slave = &omap34xx_mcspi3,
1412 .clk = "mcspi3_ick",
1413 .addr = omap34xx_mcspi3_addr_space,
1414 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
1415 .user = OCP_USER_MPU | OCP_USER_SDMA,
1416};
1417
1418/* l4 core -> mcspi4 interface */
1419static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
1420 {
1421 .pa_start = 0x480ba000,
1422 .pa_end = 0x480ba0ff,
1423 .flags = ADDR_TYPE_RT,
1424 },
1425};
1426
1427static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
1428 .master = &omap3xxx_l4_core_hwmod,
1429 .slave = &omap34xx_mcspi4,
1430 .clk = "mcspi4_ick",
1431 .addr = omap34xx_mcspi4_addr_space,
1432 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
1433 .user = OCP_USER_MPU | OCP_USER_SDMA,
1434};
1435
1436/*
1437 * 'mcspi' class
1438 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1439 * bus
1440 */
1441
1442static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1443 .rev_offs = 0x0000,
1444 .sysc_offs = 0x0010,
1445 .syss_offs = 0x0014,
1446 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1447 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1448 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1450 .sysc_fields = &omap_hwmod_sysc_type1,
1451};
1452
1453static struct omap_hwmod_class omap34xx_mcspi_class = {
1454 .name = "mcspi",
1455 .sysc = &omap34xx_mcspi_sysc,
1456 .rev = OMAP3_MCSPI_REV,
1457};
1458
1459/* mcspi1 */
1460static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
1461 { .name = "irq", .irq = 65 },
1462};
1463
1464static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
1465 { .name = "tx0", .dma_req = 35 },
1466 { .name = "rx0", .dma_req = 36 },
1467 { .name = "tx1", .dma_req = 37 },
1468 { .name = "rx1", .dma_req = 38 },
1469 { .name = "tx2", .dma_req = 39 },
1470 { .name = "rx2", .dma_req = 40 },
1471 { .name = "tx3", .dma_req = 41 },
1472 { .name = "rx3", .dma_req = 42 },
1473};
1474
1475static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
1476 &omap34xx_l4_core__mcspi1,
1477};
1478
1479static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1480 .num_chipselect = 4,
1481};
1482
1483static struct omap_hwmod omap34xx_mcspi1 = {
1484 .name = "mcspi1",
1485 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
1486 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
1487 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
1488 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
1489 .main_clk = "mcspi1_fck",
1490 .prcm = {
1491 .omap2 = {
1492 .module_offs = CORE_MOD,
1493 .prcm_reg_id = 1,
1494 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1495 .idlest_reg_id = 1,
1496 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1497 },
1498 },
1499 .slaves = omap34xx_mcspi1_slaves,
1500 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
1501 .class = &omap34xx_mcspi_class,
1502 .dev_attr = &omap_mcspi1_dev_attr,
1503 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1504};
1505
1506/* mcspi2 */
1507static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
1508 { .name = "irq", .irq = 66 },
1509};
1510
1511static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
1512 { .name = "tx0", .dma_req = 43 },
1513 { .name = "rx0", .dma_req = 44 },
1514 { .name = "tx1", .dma_req = 45 },
1515 { .name = "rx1", .dma_req = 46 },
1516};
1517
1518static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
1519 &omap34xx_l4_core__mcspi2,
1520};
1521
1522static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1523 .num_chipselect = 2,
1524};
1525
1526static struct omap_hwmod omap34xx_mcspi2 = {
1527 .name = "mcspi2",
1528 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
1529 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
1530 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
1531 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
1532 .main_clk = "mcspi2_fck",
1533 .prcm = {
1534 .omap2 = {
1535 .module_offs = CORE_MOD,
1536 .prcm_reg_id = 1,
1537 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1538 .idlest_reg_id = 1,
1539 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1540 },
1541 },
1542 .slaves = omap34xx_mcspi2_slaves,
1543 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
1544 .class = &omap34xx_mcspi_class,
1545 .dev_attr = &omap_mcspi2_dev_attr,
1546 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1547};
1548
1549/* mcspi3 */
1550static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1551 { .name = "irq", .irq = 91 }, /* 91 */
1552};
1553
1554static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1555 { .name = "tx0", .dma_req = 15 },
1556 { .name = "rx0", .dma_req = 16 },
1557 { .name = "tx1", .dma_req = 23 },
1558 { .name = "rx1", .dma_req = 24 },
1559};
1560
1561static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
1562 &omap34xx_l4_core__mcspi3,
1563};
1564
1565static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1566 .num_chipselect = 2,
1567};
1568
1569static struct omap_hwmod omap34xx_mcspi3 = {
1570 .name = "mcspi3",
1571 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1572 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
1573 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1574 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
1575 .main_clk = "mcspi3_fck",
1576 .prcm = {
1577 .omap2 = {
1578 .module_offs = CORE_MOD,
1579 .prcm_reg_id = 1,
1580 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1581 .idlest_reg_id = 1,
1582 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1583 },
1584 },
1585 .slaves = omap34xx_mcspi3_slaves,
1586 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
1587 .class = &omap34xx_mcspi_class,
1588 .dev_attr = &omap_mcspi3_dev_attr,
1589 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1590};
1591
1592/* SPI4 */
1593static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1594 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1595};
1596
1597static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1598 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1599 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1600};
1601
1602static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
1603 &omap34xx_l4_core__mcspi4,
1604};
1605
1606static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1607 .num_chipselect = 1,
1608};
1609
1610static struct omap_hwmod omap34xx_mcspi4 = {
1611 .name = "mcspi4",
1612 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1613 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
1614 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1615 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
1616 .main_clk = "mcspi4_fck",
1617 .prcm = {
1618 .omap2 = {
1619 .module_offs = CORE_MOD,
1620 .prcm_reg_id = 1,
1621 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1622 .idlest_reg_id = 1,
1623 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1624 },
1625 },
1626 .slaves = omap34xx_mcspi4_slaves,
1627 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
1628 .class = &omap34xx_mcspi_class,
1629 .dev_attr = &omap_mcspi4_dev_attr,
1630 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1631};
1632
1359static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 1633static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1360 &omap3xxx_l3_main_hwmod, 1634 &omap3xxx_l3_main_hwmod,
1361 &omap3xxx_l4_core_hwmod, 1635 &omap3xxx_l4_core_hwmod,
@@ -1387,6 +1661,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1387 1661
1388 /* dma_system class*/ 1662 /* dma_system class*/
1389 &omap3xxx_dma_system_hwmod, 1663 &omap3xxx_dma_system_hwmod,
1664
1665 /* mcspi class */
1666 &omap34xx_mcspi1,
1667 &omap34xx_mcspi2,
1668 &omap34xx_mcspi3,
1669 &omap34xx_mcspi4,
1390 NULL, 1670 NULL,
1391}; 1671};
1392 1672
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..3d51b18131cc 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,8 +1,19 @@
1#ifndef _OMAP2_MCSPI_H 1#ifndef _OMAP2_MCSPI_H
2#define _OMAP2_MCSPI_H 2#define _OMAP2_MCSPI_H
3 3
4#define OMAP2_MCSPI_REV 0
5#define OMAP3_MCSPI_REV 1
6#define OMAP4_MCSPI_REV 2
7
8#define OMAP4_MCSPI_REG_OFFSET 0x100
9
4struct omap2_mcspi_platform_config { 10struct omap2_mcspi_platform_config {
5 unsigned short num_cs; 11 unsigned short num_cs;
12 unsigned int regs_offset;
13};
14
15struct omap2_mcspi_dev_attr {
16 unsigned short num_chipselect;
6}; 17};
7 18
8struct omap2_mcspi_device_config { 19struct omap2_mcspi_device_config {
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index f076cc5c6fb0..36501adc125d 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation 4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com> 6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,7 @@
33#include <linux/clk.h> 33#include <linux/clk.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
36 37
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38 39
@@ -46,7 +47,6 @@
46#define OMAP2_MCSPI_MAX_CTRL 4 47#define OMAP2_MCSPI_MAX_CTRL 4
47 48
48#define OMAP2_MCSPI_REVISION 0x00 49#define OMAP2_MCSPI_REVISION 0x00
49#define OMAP2_MCSPI_SYSCONFIG 0x10
50#define OMAP2_MCSPI_SYSSTATUS 0x14 50#define OMAP2_MCSPI_SYSSTATUS 0x14
51#define OMAP2_MCSPI_IRQSTATUS 0x18 51#define OMAP2_MCSPI_IRQSTATUS 0x18
52#define OMAP2_MCSPI_IRQENABLE 0x1c 52#define OMAP2_MCSPI_IRQENABLE 0x1c
@@ -63,13 +63,6 @@
63 63
64/* per-register bitmasks: */ 64/* per-register bitmasks: */
65 65
66#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
70
71#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
72
73#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 66#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74#define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 67#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 68#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
@@ -122,13 +115,12 @@ struct omap2_mcspi {
122 spinlock_t lock; 115 spinlock_t lock;
123 struct list_head msg_queue; 116 struct list_head msg_queue;
124 struct spi_master *master; 117 struct spi_master *master;
125 struct clk *ick;
126 struct clk *fck;
127 /* Virtual base address of the controller */ 118 /* Virtual base address of the controller */
128 void __iomem *base; 119 void __iomem *base;
129 unsigned long phys; 120 unsigned long phys;
130 /* SPI1 has 4 channels, while SPI2 has 2 */ 121 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma *dma_channels; 122 struct omap2_mcspi_dma *dma_channels;
123 struct device *dev;
132}; 124};
133 125
134struct omap2_mcspi_cs { 126struct omap2_mcspi_cs {
@@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
144 * corresponding registers are modified. 136 * corresponding registers are modified.
145 */ 137 */
146struct omap2_mcspi_regs { 138struct omap2_mcspi_regs {
147 u32 sysconfig;
148 u32 modulctrl; 139 u32 modulctrl;
149 u32 wakeupenable; 140 u32 wakeupenable;
150 struct list_head cs; 141 struct list_head cs;
@@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
268 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, 259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
269 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); 260 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
270 261
271 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
272 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
273
274 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, 262 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
275 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); 263 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
276 264
@@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
280} 268}
281static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) 269static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
282{ 270{
283 clk_disable(mcspi->ick); 271 pm_runtime_put_sync(mcspi->dev);
284 clk_disable(mcspi->fck);
285} 272}
286 273
287static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) 274static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
288{ 275{
289 if (clk_enable(mcspi->ick)) 276 return pm_runtime_get_sync(mcspi->dev);
290 return -ENODEV;
291 if (clk_enable(mcspi->fck))
292 return -ENODEV;
293
294 omap2_mcspi_restore_ctx(mcspi);
295
296 return 0;
297} 277}
298 278
299static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 279static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
819 return ret; 799 return ret;
820 } 800 }
821 801
822 if (omap2_mcspi_enable_clocks(mcspi)) 802 ret = omap2_mcspi_enable_clocks(mcspi);
823 return -ENODEV; 803 if (ret < 0)
804 return ret;
824 805
825 ret = omap2_mcspi_setup_transfer(spi, NULL); 806 ret = omap2_mcspi_setup_transfer(spi, NULL);
826 omap2_mcspi_disable_clocks(mcspi); 807 omap2_mcspi_disable_clocks(mcspi);
@@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
863 struct omap2_mcspi *mcspi; 844 struct omap2_mcspi *mcspi;
864 845
865 mcspi = container_of(work, struct omap2_mcspi, work); 846 mcspi = container_of(work, struct omap2_mcspi, work);
866 spin_lock_irq(&mcspi->lock);
867 847
868 if (omap2_mcspi_enable_clocks(mcspi)) 848 if (omap2_mcspi_enable_clocks(mcspi) < 0)
869 goto out; 849 return;
850
851 spin_lock_irq(&mcspi->lock);
870 852
871 /* We only enable one channel at a time -- the one whose message is 853 /* We only enable one channel at a time -- the one whose message is
872 * at the head of the queue -- although this controller would gladly 854 * at the head of the queue -- although this controller would gladly
@@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
979 spin_lock_irq(&mcspi->lock); 961 spin_lock_irq(&mcspi->lock);
980 } 962 }
981 963
982 omap2_mcspi_disable_clocks(mcspi);
983
984out:
985 spin_unlock_irq(&mcspi->lock); 964 spin_unlock_irq(&mcspi->lock);
965
966 omap2_mcspi_disable_clocks(mcspi);
986} 967}
987 968
988static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) 969static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
@@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
1058 return 0; 1039 return 0;
1059} 1040}
1060 1041
1061static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) 1042static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1062{ 1043{
1063 struct spi_master *master = mcspi->master; 1044 struct spi_master *master = mcspi->master;
1064 u32 tmp; 1045 u32 tmp;
1046 int ret = 0;
1065 1047
1066 if (omap2_mcspi_enable_clocks(mcspi)) 1048 ret = omap2_mcspi_enable_clocks(mcspi);
1067 return -1; 1049 if (ret < 0)
1068 1050 return ret;
1069 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
1070 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
1071 do {
1072 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
1073 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
1074
1075 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
1076 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
1077 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
1078 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
1079 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
1080 1051
1081 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1052 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1082 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); 1053 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
@@ -1087,91 +1058,26 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
1087 return 0; 1058 return 0;
1088} 1059}
1089 1060
1090static u8 __initdata spi1_rxdma_id [] = { 1061static int omap_mcspi_runtime_resume(struct device *dev)
1091 OMAP24XX_DMA_SPI1_RX0, 1062{
1092 OMAP24XX_DMA_SPI1_RX1, 1063 struct omap2_mcspi *mcspi;
1093 OMAP24XX_DMA_SPI1_RX2, 1064 struct spi_master *master;
1094 OMAP24XX_DMA_SPI1_RX3,
1095};
1096
1097static u8 __initdata spi1_txdma_id [] = {
1098 OMAP24XX_DMA_SPI1_TX0,
1099 OMAP24XX_DMA_SPI1_TX1,
1100 OMAP24XX_DMA_SPI1_TX2,
1101 OMAP24XX_DMA_SPI1_TX3,
1102};
1103
1104static u8 __initdata spi2_rxdma_id[] = {
1105 OMAP24XX_DMA_SPI2_RX0,
1106 OMAP24XX_DMA_SPI2_RX1,
1107};
1108
1109static u8 __initdata spi2_txdma_id[] = {
1110 OMAP24XX_DMA_SPI2_TX0,
1111 OMAP24XX_DMA_SPI2_TX1,
1112};
1113
1114#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1115 || defined(CONFIG_ARCH_OMAP4)
1116static u8 __initdata spi3_rxdma_id[] = {
1117 OMAP24XX_DMA_SPI3_RX0,
1118 OMAP24XX_DMA_SPI3_RX1,
1119};
1120 1065
1121static u8 __initdata spi3_txdma_id[] = { 1066 master = dev_get_drvdata(dev);
1122 OMAP24XX_DMA_SPI3_TX0, 1067 mcspi = spi_master_get_devdata(master);
1123 OMAP24XX_DMA_SPI3_TX1, 1068 omap2_mcspi_restore_ctx(mcspi);
1124};
1125#endif
1126 1069
1127#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1070 return 0;
1128static u8 __initdata spi4_rxdma_id[] = { 1071}
1129 OMAP34XX_DMA_SPI4_RX0,
1130};
1131 1072
1132static u8 __initdata spi4_txdma_id[] = {
1133 OMAP34XX_DMA_SPI4_TX0,
1134};
1135#endif
1136 1073
1137static int __init omap2_mcspi_probe(struct platform_device *pdev) 1074static int __init omap2_mcspi_probe(struct platform_device *pdev)
1138{ 1075{
1139 struct spi_master *master; 1076 struct spi_master *master;
1077 struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
1140 struct omap2_mcspi *mcspi; 1078 struct omap2_mcspi *mcspi;
1141 struct resource *r; 1079 struct resource *r;
1142 int status = 0, i; 1080 int status = 0, i;
1143 const u8 *rxdma_id, *txdma_id;
1144 unsigned num_chipselect;
1145
1146 switch (pdev->id) {
1147 case 1:
1148 rxdma_id = spi1_rxdma_id;
1149 txdma_id = spi1_txdma_id;
1150 num_chipselect = 4;
1151 break;
1152 case 2:
1153 rxdma_id = spi2_rxdma_id;
1154 txdma_id = spi2_txdma_id;
1155 num_chipselect = 2;
1156 break;
1157#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1158 || defined(CONFIG_ARCH_OMAP4)
1159 case 3:
1160 rxdma_id = spi3_rxdma_id;
1161 txdma_id = spi3_txdma_id;
1162 num_chipselect = 2;
1163 break;
1164#endif
1165#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1166 case 4:
1167 rxdma_id = spi4_rxdma_id;
1168 txdma_id = spi4_txdma_id;
1169 num_chipselect = 1;
1170 break;
1171#endif
1172 default:
1173 return -EINVAL;
1174 }
1175 1081
1176 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1082 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1177 if (master == NULL) { 1083 if (master == NULL) {
@@ -1188,7 +1094,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1188 master->setup = omap2_mcspi_setup; 1094 master->setup = omap2_mcspi_setup;
1189 master->transfer = omap2_mcspi_transfer; 1095 master->transfer = omap2_mcspi_transfer;
1190 master->cleanup = omap2_mcspi_cleanup; 1096 master->cleanup = omap2_mcspi_cleanup;
1191 master->num_chipselect = num_chipselect; 1097 master->num_chipselect = pdata->num_cs;
1192 1098
1193 dev_set_drvdata(&pdev->dev, master); 1099 dev_set_drvdata(&pdev->dev, master);
1194 1100
@@ -1206,49 +1112,62 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1206 goto err1; 1112 goto err1;
1207 } 1113 }
1208 1114
1115 r->start += pdata->regs_offset;
1116 r->end += pdata->regs_offset;
1209 mcspi->phys = r->start; 1117 mcspi->phys = r->start;
1210 mcspi->base = ioremap(r->start, r->end - r->start + 1); 1118 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1211 if (!mcspi->base) { 1119 if (!mcspi->base) {
1212 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); 1120 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1213 status = -ENOMEM; 1121 status = -ENOMEM;
1214 goto err1aa; 1122 goto err2;
1215 } 1123 }
1216 1124
1125 mcspi->dev = &pdev->dev;
1217 INIT_WORK(&mcspi->work, omap2_mcspi_work); 1126 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1218 1127
1219 spin_lock_init(&mcspi->lock); 1128 spin_lock_init(&mcspi->lock);
1220 INIT_LIST_HEAD(&mcspi->msg_queue); 1129 INIT_LIST_HEAD(&mcspi->msg_queue);
1221 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); 1130 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1222 1131
1223 mcspi->ick = clk_get(&pdev->dev, "ick");
1224 if (IS_ERR(mcspi->ick)) {
1225 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1226 status = PTR_ERR(mcspi->ick);
1227 goto err1a;
1228 }
1229 mcspi->fck = clk_get(&pdev->dev, "fck");
1230 if (IS_ERR(mcspi->fck)) {
1231 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1232 status = PTR_ERR(mcspi->fck);
1233 goto err2;
1234 }
1235
1236 mcspi->dma_channels = kcalloc(master->num_chipselect, 1132 mcspi->dma_channels = kcalloc(master->num_chipselect,
1237 sizeof(struct omap2_mcspi_dma), 1133 sizeof(struct omap2_mcspi_dma),
1238 GFP_KERNEL); 1134 GFP_KERNEL);
1239 1135
1240 if (mcspi->dma_channels == NULL) 1136 if (mcspi->dma_channels == NULL)
1241 goto err3; 1137 goto err2;
1138
1139 for (i = 0; i < master->num_chipselect; i++) {
1140 char dma_ch_name[14];
1141 struct resource *dma_res;
1142
1143 sprintf(dma_ch_name, "rx%d", i);
1144 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1145 dma_ch_name);
1146 if (!dma_res) {
1147 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1148 status = -ENODEV;
1149 break;
1150 }
1242 1151
1243 for (i = 0; i < num_chipselect; i++) {
1244 mcspi->dma_channels[i].dma_rx_channel = -1; 1152 mcspi->dma_channels[i].dma_rx_channel = -1;
1245 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; 1153 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1154 sprintf(dma_ch_name, "tx%d", i);
1155 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1156 dma_ch_name);
1157 if (!dma_res) {
1158 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1159 status = -ENODEV;
1160 break;
1161 }
1162
1246 mcspi->dma_channels[i].dma_tx_channel = -1; 1163 mcspi->dma_channels[i].dma_tx_channel = -1;
1247 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; 1164 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1248 } 1165 }
1249 1166
1250 if (omap2_mcspi_reset(mcspi) < 0) 1167 pm_runtime_enable(&pdev->dev);
1251 goto err4; 1168
1169 if (status || omap2_mcspi_master_setup(mcspi) < 0)
1170 goto err3;
1252 1171
1253 status = spi_register_master(master); 1172 status = spi_register_master(master);
1254 if (status < 0) 1173 if (status < 0)
@@ -1257,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
1257 return status; 1176 return status;
1258 1177
1259err4: 1178err4:
1260 kfree(mcspi->dma_channels); 1179 spi_master_put(master);
1261err3: 1180err3:
1262 clk_put(mcspi->fck); 1181 kfree(mcspi->dma_channels);
1263err2: 1182err2:
1264 clk_put(mcspi->ick);
1265err1a:
1266 iounmap(mcspi->base);
1267err1aa:
1268 release_mem_region(r->start, (r->end - r->start) + 1); 1183 release_mem_region(r->start, (r->end - r->start) + 1);
1184 iounmap(mcspi->base);
1269err1: 1185err1:
1270 spi_master_put(master);
1271 return status; 1186 return status;
1272} 1187}
1273 1188
@@ -1283,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1283 mcspi = spi_master_get_devdata(master); 1198 mcspi = spi_master_get_devdata(master);
1284 dma_channels = mcspi->dma_channels; 1199 dma_channels = mcspi->dma_channels;
1285 1200
1286 clk_put(mcspi->fck); 1201 omap2_mcspi_disable_clocks(mcspi);
1287 clk_put(mcspi->ick);
1288
1289 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1290 release_mem_region(r->start, (r->end - r->start) + 1); 1203 release_mem_region(r->start, (r->end - r->start) + 1);
1291 1204
@@ -1336,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev)
1336 1249
1337static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1250static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1338 .resume = omap2_mcspi_resume, 1251 .resume = omap2_mcspi_resume,
1252 .runtime_resume = omap_mcspi_runtime_resume,
1339}; 1253};
1340 1254
1341static struct platform_driver omap2_mcspi_driver = { 1255static struct platform_driver omap2_mcspi_driver = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 20:13:29 -0500