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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index e5a3c301b7a9..8516e1b2329a 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -483,8 +483,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
483 atom_execute_table(rdev->mode_info.atom_context, 483 atom_execute_table(rdev->mode_info.atom_context,
484 index, (uint32_t *)&adjust_pll_args); 484 index, (uint32_t *)&adjust_pll_args);
485 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; 485 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
486 } else 486 } else {
487 adjusted_clock = mode->clock; 487 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
488 if (ASIC_IS_AVIVO(rdev) &&
489 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
490 adjusted_clock = mode->clock * 2;
491 else
492 adjusted_clock = mode->clock;
493 }
488 494
489 if (radeon_crtc->crtc_id == 0) 495 if (radeon_crtc->crtc_id == 0)
490 pll = &rdev->clock.p1pll; 496 pll = &rdev->clock.p1pll;