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-rw-r--r--arch/arm/boot/compressed/head.S82
-rw-r--r--arch/arm/kernel/entry-header.S18
-rw-r--r--arch/arm/kernel/head.S15
-rw-r--r--arch/arm/kernel/setup.c4
-rw-r--r--arch/arm/kernel/smp.c3
-rw-r--r--arch/arm/kernel/sys_arm.c5
-rw-r--r--arch/arm/kernel/traps.c2
-rw-r--r--arch/arm/lib/backtrace.S2
-rw-r--r--arch/arm/mach-iop3xx/iop331-setup.c4
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-sa1100/assabet.c1
-rw-r--r--arch/arm/mach-sa1100/collie_pm.c278
-rw-r--r--arch/arm/mm/Kconfig8
-rw-r--r--arch/arm/mm/proc-arm1020.S1
-rw-r--r--arch/arm/mm/proc-arm1020e.S1
-rw-r--r--arch/arm/mm/proc-arm1022.S1
-rw-r--r--arch/arm/mm/proc-arm1026.S1
-rw-r--r--arch/arm/mm/proc-arm6_7.S1
-rw-r--r--arch/arm/mm/proc-arm720.S1
-rw-r--r--arch/arm/mm/proc-arm920.S1
-rw-r--r--arch/arm/mm/proc-arm922.S1
-rw-r--r--arch/arm/mm/proc-arm925.S1
-rw-r--r--arch/arm/mm/proc-arm926.S1
-rw-r--r--arch/arm/mm/proc-sa110.S1
-rw-r--r--arch/arm/mm/proc-sa1100.S1
-rw-r--r--arch/arm/mm/proc-v6.S1
-rw-r--r--arch/arm/mm/proc-xscale.S1
-rw-r--r--arch/arm/vfp/entry.S1
-rw-r--r--arch/arm/vfp/vfphw.S4
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h100
-rw-r--r--include/asm-arm/assembler.h27
-rw-r--r--include/asm-arm/pgalloc.h5
-rw-r--r--include/asm-arm/pgtable-hwdef.h88
-rw-r--r--include/asm-arm/pgtable.h80
-rw-r--r--include/asm-arm/tlb.h9
-rw-r--r--include/asm-arm/tlbflush.h9
-rw-r--r--include/linux/clk.h4
37 files changed, 597 insertions, 168 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index db3389d8e027..491c7e4c9ac6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
358 str r1, [r0] 358 str r1, [r0]
359 mov pc, lr 359 mov pc, lr
360 360
361__armv4_cache_on: 361__armv4_mmu_cache_on:
362 mov r12, lr 362 mov r12, lr
363 bl __setup_mmu 363 bl __setup_mmu
364 mov r0, #0 364 mov r0, #0
@@ -367,24 +367,24 @@ __armv4_cache_on:
367 mrc p15, 0, r0, c1, c0, 0 @ read control reg 367 mrc p15, 0, r0, c1, c0, 0 @ read control reg
368 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 368 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
369 orr r0, r0, #0x0030 369 orr r0, r0, #0x0030
370 bl __common_cache_on 370 bl __common_mmu_cache_on
371 mov r0, #0 371 mov r0, #0
372 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 372 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
373 mov pc, r12 373 mov pc, r12
374 374
375__arm6_cache_on: 375__arm6_mmu_cache_on:
376 mov r12, lr 376 mov r12, lr
377 bl __setup_mmu 377 bl __setup_mmu
378 mov r0, #0 378 mov r0, #0
379 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 379 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
380 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 380 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
381 mov r0, #0x30 381 mov r0, #0x30
382 bl __common_cache_on 382 bl __common_mmu_cache_on
383 mov r0, #0 383 mov r0, #0
384 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 384 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
385 mov pc, r12 385 mov pc, r12
386 386
387__common_cache_on: 387__common_mmu_cache_on:
388#ifndef DEBUG 388#ifndef DEBUG
389 orr r0, r0, #0x000d @ Write buffer, mmu 389 orr r0, r0, #0x000d @ Write buffer, mmu
390#endif 390#endif
@@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types
471proc_types: 471proc_types:
472 .word 0x41560600 @ ARM6/610 472 .word 0x41560600 @ ARM6/610
473 .word 0xffffffe0 473 .word 0xffffffe0
474 b __arm6_cache_off @ works, but slow 474 b __arm6_mmu_cache_off @ works, but slow
475 b __arm6_cache_off 475 b __arm6_mmu_cache_off
476 mov pc, lr 476 mov pc, lr
477@ b __arm6_cache_on @ untested 477@ b __arm6_mmu_cache_on @ untested
478@ b __arm6_cache_off 478@ b __arm6_mmu_cache_off
479@ b __armv3_cache_flush 479@ b __armv3_mmu_cache_flush
480 480
481 .word 0x00000000 @ old ARM ID 481 .word 0x00000000 @ old ARM ID
482 .word 0x0000f000 482 .word 0x0000f000
@@ -486,14 +486,14 @@ proc_types:
486 486
487 .word 0x41007000 @ ARM7/710 487 .word 0x41007000 @ ARM7/710
488 .word 0xfff8fe00 488 .word 0xfff8fe00
489 b __arm7_cache_off 489 b __arm7_mmu_cache_off
490 b __arm7_cache_off 490 b __arm7_mmu_cache_off
491 mov pc, lr 491 mov pc, lr
492 492
493 .word 0x41807200 @ ARM720T (writethrough) 493 .word 0x41807200 @ ARM720T (writethrough)
494 .word 0xffffff00 494 .word 0xffffff00
495 b __armv4_cache_on 495 b __armv4_mmu_cache_on
496 b __armv4_cache_off 496 b __armv4_mmu_cache_off
497 mov pc, lr 497 mov pc, lr
498 498
499 .word 0x00007000 @ ARM7 IDs 499 .word 0x00007000 @ ARM7 IDs
@@ -506,41 +506,41 @@ proc_types:
506 506
507 .word 0x4401a100 @ sa110 / sa1100 507 .word 0x4401a100 @ sa110 / sa1100
508 .word 0xffffffe0 508 .word 0xffffffe0
509 b __armv4_cache_on 509 b __armv4_mmu_cache_on
510 b __armv4_cache_off 510 b __armv4_mmu_cache_off
511 b __armv4_cache_flush 511 b __armv4_mmu_cache_flush
512 512
513 .word 0x6901b110 @ sa1110 513 .word 0x6901b110 @ sa1110
514 .word 0xfffffff0 514 .word 0xfffffff0
515 b __armv4_cache_on 515 b __armv4_mmu_cache_on
516 b __armv4_cache_off 516 b __armv4_mmu_cache_off
517 b __armv4_cache_flush 517 b __armv4_mmu_cache_flush
518 518
519 @ These match on the architecture ID 519 @ These match on the architecture ID
520 520
521 .word 0x00020000 @ ARMv4T 521 .word 0x00020000 @ ARMv4T
522 .word 0x000f0000 522 .word 0x000f0000
523 b __armv4_cache_on 523 b __armv4_mmu_cache_on
524 b __armv4_cache_off 524 b __armv4_mmu_cache_off
525 b __armv4_cache_flush 525 b __armv4_mmu_cache_flush
526 526
527 .word 0x00050000 @ ARMv5TE 527 .word 0x00050000 @ ARMv5TE
528 .word 0x000f0000 528 .word 0x000f0000
529 b __armv4_cache_on 529 b __armv4_mmu_cache_on
530 b __armv4_cache_off 530 b __armv4_mmu_cache_off
531 b __armv4_cache_flush 531 b __armv4_mmu_cache_flush
532 532
533 .word 0x00060000 @ ARMv5TEJ 533 .word 0x00060000 @ ARMv5TEJ
534 .word 0x000f0000 534 .word 0x000f0000
535 b __armv4_cache_on 535 b __armv4_mmu_cache_on
536 b __armv4_cache_off 536 b __armv4_mmu_cache_off
537 b __armv4_cache_flush 537 b __armv4_mmu_cache_flush
538 538
539 .word 0x00070000 @ ARMv6 539 .word 0x00070000 @ ARMv6
540 .word 0x000f0000 540 .word 0x000f0000
541 b __armv4_cache_on 541 b __armv4_mmu_cache_on
542 b __armv4_cache_off 542 b __armv4_mmu_cache_off
543 b __armv6_cache_flush 543 b __armv6_mmu_cache_flush
544 544
545 .word 0 @ unrecognised type 545 .word 0 @ unrecognised type
546 .word 0 546 .word 0
@@ -562,7 +562,7 @@ proc_types:
562cache_off: mov r3, #12 @ cache_off function 562cache_off: mov r3, #12 @ cache_off function
563 b call_cache_fn 563 b call_cache_fn
564 564
565__armv4_cache_off: 565__armv4_mmu_cache_off:
566 mrc p15, 0, r0, c1, c0 566 mrc p15, 0, r0, c1, c0
567 bic r0, r0, #0x000d 567 bic r0, r0, #0x000d
568 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 568 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
@@ -571,15 +571,15 @@ __armv4_cache_off:
571 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 571 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
572 mov pc, lr 572 mov pc, lr
573 573
574__arm6_cache_off: 574__arm6_mmu_cache_off:
575 mov r0, #0x00000030 @ ARM6 control reg. 575 mov r0, #0x00000030 @ ARM6 control reg.
576 b __armv3_cache_off 576 b __armv3_mmu_cache_off
577 577
578__arm7_cache_off: 578__arm7_mmu_cache_off:
579 mov r0, #0x00000070 @ ARM7 control reg. 579 mov r0, #0x00000070 @ ARM7 control reg.
580 b __armv3_cache_off 580 b __armv3_mmu_cache_off
581 581
582__armv3_cache_off: 582__armv3_mmu_cache_off:
583 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 583 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
584 mov r0, #0 584 mov r0, #0
585 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 585 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
@@ -601,7 +601,7 @@ cache_clean_flush:
601 mov r3, #16 601 mov r3, #16
602 b call_cache_fn 602 b call_cache_fn
603 603
604__armv6_cache_flush: 604__armv6_mmu_cache_flush:
605 mov r1, #0 605 mov r1, #0
606 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 606 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
607 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 607 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
@@ -609,7 +609,7 @@ __armv6_cache_flush:
609 mcr p15, 0, r1, c7, c10, 4 @ drain WB 609 mcr p15, 0, r1, c7, c10, 4 @ drain WB
610 mov pc, lr 610 mov pc, lr
611 611
612__armv4_cache_flush: 612__armv4_mmu_cache_flush:
613 mov r2, #64*1024 @ default: 32K dcache size (*2) 613 mov r2, #64*1024 @ default: 32K dcache size (*2)
614 mov r11, #32 @ default: 32 byte line size 614 mov r11, #32 @ default: 32 byte line size
615 mrc p15, 0, r3, c0, c0, 1 @ read cache type 615 mrc p15, 0, r3, c0, c0, 1 @ read cache type
@@ -637,7 +637,7 @@ no_cache_id:
637 mcr p15, 0, r1, c7, c10, 4 @ drain WB 637 mcr p15, 0, r1, c7, c10, 4 @ drain WB
638 mov pc, lr 638 mov pc, lr
639 639
640__armv3_cache_flush: 640__armv3_mmu_cache_flush:
641 mov r1, #0 641 mov r1, #0
642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
643 mov pc, lr 643 mov pc, lr
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 55c99cdab7d6..f1c2fd5b63e4 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -37,24 +37,6 @@
37#endif 37#endif
38 .endm 38 .endm
39 39
40#if __LINUX_ARM_ARCH__ >= 6
41 .macro disable_irq
42 cpsid i
43 .endm
44
45 .macro enable_irq
46 cpsie i
47 .endm
48#else
49 .macro disable_irq
50 msr cpsr_c, #PSR_I_BIT | SVC_MODE
51 .endm
52
53 .macro enable_irq
54 msr cpsr_c, #SVC_MODE
55 .endm
56#endif
57
58 .macro get_thread_info, rd 40 .macro get_thread_info, rd
59 mov \rd, sp, lsr #13 41 mov \rd, sp, lsr #13
60 mov \rd, \rd, lsl #13 42 mov \rd, \rd, lsl #13
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 84277fe818a1..53b6901f70a6 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -81,6 +81,7 @@
81ENTRY(stext) 81ENTRY(stext)
82 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode 82 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
83 @ and irqs disabled 83 @ and irqs disabled
84 mrc p15, 0, r9, c0, c0 @ get processor id
84 bl __lookup_processor_type @ r5=procinfo r9=cpuid 85 bl __lookup_processor_type @ r5=procinfo r9=cpuid
85 movs r10, r5 @ invalid processor (r5=0)? 86 movs r10, r5 @ invalid processor (r5=0)?
86 beq __error_p @ yes, error 'p' 87 beq __error_p @ yes, error 'p'
@@ -155,6 +156,7 @@ ENTRY(secondary_startup)
155 * as it has already been validated by the primary processor. 156 * as it has already been validated by the primary processor.
156 */ 157 */
157 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC 158 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
159 mrc p15, 0, r9, c0, c0 @ get processor id
158 bl __lookup_processor_type 160 bl __lookup_processor_type
159 movs r10, r5 @ invalid processor? 161 movs r10, r5 @ invalid processor?
160 moveq r0, #'p' @ yes, error 'p' 162 moveq r0, #'p' @ yes, error 'p'
@@ -449,19 +451,19 @@ __error:
449 * (and therefore, we are not in the correct address space). We have to 451 * (and therefore, we are not in the correct address space). We have to
450 * calculate the offset. 452 * calculate the offset.
451 * 453 *
454 * r9 = cpuid
452 * Returns: 455 * Returns:
453 * r3, r4, r6 corrupted 456 * r3, r4, r6 corrupted
454 * r5 = proc_info pointer in physical address space 457 * r5 = proc_info pointer in physical address space
455 * r9 = cpuid 458 * r9 = cpuid (preserved)
456 */ 459 */
457 .type __lookup_processor_type, %function 460 .type __lookup_processor_type, %function
458__lookup_processor_type: 461__lookup_processor_type:
459 adr r3, 3f 462 adr r3, 3f
460 ldmda r3, {r5, r6, r9} 463 ldmda r3, {r5 - r7}
461 sub r3, r3, r9 @ get offset between virt&phys 464 sub r3, r3, r7 @ get offset between virt&phys
462 add r5, r5, r3 @ convert virt addresses to 465 add r5, r5, r3 @ convert virt addresses to
463 add r6, r6, r3 @ physical address space 466 add r6, r6, r3 @ physical address space
464 mrc p15, 0, r9, c0, c0 @ get processor id
4651: ldmia r5, {r3, r4} @ value, mask 4671: ldmia r5, {r3, r4} @ value, mask
466 and r4, r4, r9 @ mask wanted bits 468 and r4, r4, r9 @ mask wanted bits
467 teq r3, r4 469 teq r3, r4
@@ -476,10 +478,11 @@ __lookup_processor_type:
476 * This provides a C-API version of the above function. 478 * This provides a C-API version of the above function.
477 */ 479 */
478ENTRY(lookup_processor_type) 480ENTRY(lookup_processor_type)
479 stmfd sp!, {r4 - r6, r9, lr} 481 stmfd sp!, {r4 - r7, r9, lr}
482 mov r9, r0
480 bl __lookup_processor_type 483 bl __lookup_processor_type
481 mov r0, r5 484 mov r0, r5
482 ldmfd sp!, {r4 - r6, r9, pc} 485 ldmfd sp!, {r4 - r7, r9, pc}
483 486
484/* 487/*
485 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for 488 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 08974cbe9824..b7cd280bfd63 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -278,7 +278,7 @@ int cpu_architecture(void)
278 * These functions re-use the assembly code in head.S, which 278 * These functions re-use the assembly code in head.S, which
279 * already provide the required functionality. 279 * already provide the required functionality.
280 */ 280 */
281extern struct proc_info_list *lookup_processor_type(void); 281extern struct proc_info_list *lookup_processor_type(unsigned int);
282extern struct machine_desc *lookup_machine_type(unsigned int); 282extern struct machine_desc *lookup_machine_type(unsigned int);
283 283
284static void __init setup_processor(void) 284static void __init setup_processor(void)
@@ -290,7 +290,7 @@ static void __init setup_processor(void)
290 * types. The linker builds this table for us from the 290 * types. The linker builds this table for us from the
291 * entries in arch/arm/mm/proc-*.S 291 * entries in arch/arm/mm/proc-*.S
292 */ 292 */
293 list = lookup_processor_type(); 293 list = lookup_processor_type(processor_id);
294 if (!list) { 294 if (!list) {
295 printk("CPU configuration botched (ID %08x), unable " 295 printk("CPU configuration botched (ID %08x), unable "
296 "to continue.\n", processor_id); 296 "to continue.\n", processor_id);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 02aa300c4633..1370d726dc10 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -337,9 +337,6 @@ void __init smp_prepare_boot_cpu(void)
337 unsigned int cpu = smp_processor_id(); 337 unsigned int cpu = smp_processor_id();
338 338
339 per_cpu(cpu_data, cpu).idle = current; 339 per_cpu(cpu_data, cpu).idle = current;
340
341 cpu_set(cpu, cpu_present_map);
342 cpu_set(cpu, cpu_online_map);
343} 340}
344 341
345static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg) 342static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index a491de2d9024..8170af471439 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third,
234 */ 234 */
235asmlinkage int sys_fork(struct pt_regs *regs) 235asmlinkage int sys_fork(struct pt_regs *regs)
236{ 236{
237#ifdef CONFIG_MMU
237 return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL); 238 return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
239#else
240 /* can not support in nommu mode */
241 return(-EINVAL);
242#endif
238} 243}
239 244
240/* Clone a task - this clones the calling program thread. 245/* Clone a task - this clones the calling program thread.
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 03924bcc6129..d566d5f4574d 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -506,7 +506,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
506 if (!pmd_present(*pmd)) 506 if (!pmd_present(*pmd))
507 goto bad_access; 507 goto bad_access;
508 pte = pte_offset_map_lock(mm, pmd, addr, &ptl); 508 pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
509 if (!pte_present(*pte) || !pte_write(*pte)) { 509 if (!pte_present(*pte) || !pte_dirty(*pte)) {
510 pte_unmap_unlock(pte, ptl); 510 pte_unmap_unlock(pte, ptl);
511 goto bad_access; 511 goto bad_access;
512 } 512 }
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index 68a21c0f3f52..3bdc8c6949c5 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -29,7 +29,7 @@ ENTRY(__backtrace)
29 29
30ENTRY(c_backtrace) 30ENTRY(c_backtrace)
31 31
32#ifndef CONFIG_FRAME_POINTER 32#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK)
33 mov pc, lr 33 mov pc, lr
34#else 34#else
35 35
diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c
index 2d6abe5be14d..7b7b6eea3846 100644
--- a/arch/arm/mach-iop3xx/iop331-setup.c
+++ b/arch/arm/mach-iop3xx/iop331-setup.c
@@ -103,7 +103,7 @@ static struct plat_serial8250_port iop33x_uart1_data[] = {
103 103
104static struct platform_device iop33x_uart0 = { 104static struct platform_device iop33x_uart0 = {
105 .name = "serial8250", 105 .name = "serial8250",
106 .id = 0, 106 .id = PLAT8250_DEV_PLATFORM,
107 .dev.platform_data = iop33x_uart0_data, 107 .dev.platform_data = iop33x_uart0_data,
108 .num_resources = 2, 108 .num_resources = 2,
109 .resource = iop33x_uart0_resources, 109 .resource = iop33x_uart0_resources,
@@ -111,7 +111,7 @@ static struct platform_device iop33x_uart0 = {
111 111
112static struct platform_device iop33x_uart1 = { 112static struct platform_device iop33x_uart1 = {
113 .name = "serial8250", 113 .name = "serial8250",
114 .id = 1, 114 .id = PLAT8250_DEV_PLATFORM1,
115 .dev.platform_data = iop33x_uart1_data, 115 .dev.platform_data = iop33x_uart1_data,
116 .num_resources = 2, 116 .num_resources = 2,
117 .resource = iop33x_uart1_resources, 117 .resource = iop33x_uart1_resources,
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 24dd374224af..0884bc7c23b7 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -167,7 +167,7 @@ void __init omap_serial_init()
167 167
168static struct platform_device serial_device = { 168static struct platform_device serial_device = {
169 .name = "serial8250", 169 .name = "serial8250",
170 .id = 0, 170 .id = PLAT8250_DEV_PLATFORM,
171 .dev = { 171 .dev = {
172 .platform_data = serial_platform_data, 172 .platform_data = serial_platform_data,
173 }, 173 },
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index a599bb0d4ab8..c58f12ba7a93 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -26,6 +26,7 @@
26#include <asm/irq.h> 26#include <asm/irq.h>
27#include <asm/setup.h> 27#include <asm/setup.h>
28#include <asm/page.h> 28#include <asm/page.h>
29#include <asm/pgtable-hwdef.h>
29#include <asm/pgtable.h> 30#include <asm/pgtable.h>
30#include <asm/tlbflush.h> 31#include <asm/tlbflush.h>
31 32
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c
new file mode 100644
index 000000000000..696d7d29c8a5
--- /dev/null
+++ b/arch/arm/mach-sa1100/collie_pm.c
@@ -0,0 +1,278 @@
1/*
2 * Based on spitz_pm.c and sharp code.
3 *
4 * Copyright (C) 2001 SHARP
5 * Copyright 2005 Pavel Machek <pavel@suse.cz>
6 *
7 * Distribute under GPLv2.
8 *
9 * Li-ion batteries are angry beasts, and they like to explode. This driver is not finished,
10 * and sometimes charges them when it should not. If it makes angry lithium to come your way...
11 * ...well, you have been warned.
12 */
13
14#include <linux/module.h>
15#include <linux/stat.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22
23#include <asm/irq.h>
24#include <asm/mach-types.h>
25#include <asm/hardware.h>
26#include <asm/hardware/scoop.h>
27#include <asm/dma.h>
28#include <asm/arch/collie.h>
29#include <asm/mach/sharpsl_param.h>
30#include <asm/hardware/sharpsl_pm.h>
31
32#include "../drivers/mfd/ucb1x00.h"
33
34static struct ucb1x00 *ucb;
35static int ad_revise;
36
37#define ADCtoPower(x) ((330 * x * 2) / 1024)
38
39static void collie_charger_init(void)
40{
41 int err;
42
43 if (sharpsl_param.adadj != -1) {
44 ad_revise = sharpsl_param.adadj;
45 }
46
47 /* Register interrupt handler. */
48 if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, SA_INTERRUPT,
49 "ACIN", sharpsl_ac_isr))) {
50 printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN);
51 return;
52 }
53 if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, SA_INTERRUPT,
54 "CO", sharpsl_chrg_full_isr))) {
55 free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr);
56 printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO);
57 return;
58 }
59
60 ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON |
61 COLLIE_TC35143_GPIO_BBAT_ON);
62 return;
63}
64
65static void collie_measure_temp(int on)
66{
67 if (on)
68 ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
69 else
70 ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
71}
72
73static void collie_charge(int on)
74{
75 if (on) {
76 printk("Should start charger\n");
77 } else {
78 printk("Should stop charger\n");
79 }
80#ifdef I_AM_SURE
81
82 /* Zaurus seems to contain LTC1731 ; it should know when to
83 * stop charging itself, so setting charge on should be
84 * relatively harmless (as long as it is not done too often).
85 */
86#define CF_BUF_CTRL_BASE 0xF0800000
87#define SCOOP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr)))
88#define SCOOP_REG_GPWR SCOOP_REG(SCOOP_GPWR)
89
90 if (on) {
91 set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
92 } else {
93 reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
94 }
95#endif
96}
97
98static void collie_discharge(int on)
99{
100}
101
102static void collie_discharge1(int on)
103{
104}
105
106static void collie_presuspend(void)
107{
108}
109
110static void collie_postsuspend(void)
111{
112}
113
114static int collie_should_wakeup(unsigned int resume_on_alarm)
115{
116 return 0;
117}
118
119static unsigned long collie_charger_wakeup(void)
120{
121 return 0;
122}
123
124int collie_read_backup_battery(void)
125{
126 int voltage;
127
128 ucb1x00_adc_enable(ucb);
129
130 /* Gives 75..130 */
131 ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0);
132 voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
133
134 ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
135 ucb1x00_adc_disable(ucb);
136
137 printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage);
138
139 return ADCtoPower(voltage);
140}
141
142int collie_read_main_battery(void)
143{
144 int voltage, voltage_rev, voltage_volts;
145
146 ucb1x00_adc_enable(ucb);
147 ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
148 ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0);
149 /* gives values 160..255 with battery removed... and
150 145..255 with battery inserted. (on AC), goes as low as
151 80 on DC. */
152 voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
153
154 ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON);
155 ucb1x00_adc_disable(ucb);
156
157 voltage_rev = voltage + ((ad_revise * voltage) / 652);
158 voltage_volts = ADCtoPower(voltage_rev);
159
160 printk("Main battery = %d(%d)\n", voltage_volts, voltage);
161
162 if (voltage != -1)
163 return voltage_volts;
164 else
165 return voltage;
166}
167
168int collie_read_temp(void)
169{
170 int voltage;
171
172 /* According to Sharp, temp must be > 973, main battery must be < 465,
173 FIXME: sharpsl_pm.c has both conditions negated? FIXME: values
174 are way out of range? */
175
176 ucb1x00_adc_enable(ucb);
177 ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
178 /* >1010 = battery removed, 460 = 22C ?, higer = lower temp ? */
179 voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC);
180 ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
181 ucb1x00_adc_disable(ucb);
182
183 printk("Battery temp = %d\n", voltage);
184 return voltage;
185}
186
187static unsigned long read_devdata(int which)
188{
189 switch (which) {
190 case SHARPSL_BATT_VOLT:
191 return collie_read_main_battery();
192 case SHARPSL_BATT_TEMP:
193 return collie_read_temp();
194 case SHARPSL_ACIN_VOLT:
195 return 0x1;
196 case SHARPSL_STATUS_ACIN: {
197 int ret = GPLR & COLLIE_GPIO_AC_IN;
198 printk("AC status = %d\n", ret);
199 return ret;
200 }
201 case SHARPSL_STATUS_FATAL: {
202 int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW;
203 printk("Fatal bat = %d\n", ret);
204 return ret;
205 }
206 default:
207 return ~0;
208 }
209}
210
211struct battery_thresh collie_battery_levels[] = {
212 { 368, 100},
213 { 358, 25},
214 { 356, 5},
215 { 0, 0},
216};
217
218struct sharpsl_charger_machinfo collie_pm_machinfo = {
219 .init = collie_charger_init,
220 .read_devdata = read_devdata,
221 .discharge = collie_discharge,
222 .discharge1 = collie_discharge1,
223 .charge = collie_charge,
224 .measure_temp = collie_measure_temp,
225 .presuspend = collie_presuspend,
226 .postsuspend = collie_postsuspend,
227 .charger_wakeup = collie_charger_wakeup,
228 .should_wakeup = collie_should_wakeup,
229 .bat_levels = 3,
230 .bat_levels_noac = collie_battery_levels,
231 .bat_levels_acin = collie_battery_levels,
232 .status_high_acin = 368,
233 .status_low_acin = 358,
234 .status_high_noac = 368,
235 .status_low_noac = 358,
236};
237
238static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
239{
240 sharpsl_pm.machinfo = &collie_pm_machinfo;
241 ucb = pdev->ucb;
242 return 0;
243}
244
245static struct ucb1x00_driver collie_pm_ucb_driver = {
246 .add = collie_pm_ucb_add,
247};
248
249static struct platform_device *collie_pm_device;
250
251static int __init collie_pm_init(void)
252{
253 int ret;
254
255 collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
256 if (!collie_pm_device)
257 return -ENOMEM;
258
259 collie_pm_device->dev.platform_data = &collie_pm_machinfo;
260 ret = platform_device_add(collie_pm_device);
261
262 if (ret)
263 platform_device_put(collie_pm_device);
264
265 if (!ret)
266 ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
267
268 return ret;
269}
270
271static void __exit collie_pm_exit(void)
272{
273 ucb1x00_unregister_driver(&collie_pm_ucb_driver);
274 platform_device_unregister(collie_pm_device);
275}
276
277module_init(collie_pm_init);
278module_exit(collie_pm_exit);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index eaaec90db972..e680c5fd93b5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -266,12 +266,18 @@ config CPU_32v6K
266# This defines the compiler instruction set which depends on the machine type. 266# This defines the compiler instruction set which depends on the machine type.
267config CPU_32v3 267config CPU_32v3
268 bool 268 bool
269 select TLS_REG_EMUL if SMP
270 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
269 271
270config CPU_32v4 272config CPU_32v4
271 bool 273 bool
274 select TLS_REG_EMUL if SMP
275 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
272 276
273config CPU_32v5 277config CPU_32v5
274 bool 278 bool
279 select TLS_REG_EMUL if SMP
280 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
275 281
276config CPU_32v6 282config CPU_32v6
277 bool 283 bool
@@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE
417 423
418config TLS_REG_EMUL 424config TLS_REG_EMUL
419 bool 425 bool
420 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
421 help 426 help
422 An SMP system using a pre-ARMv6 processor (there are apparently 427 An SMP system using a pre-ARMv6 processor (there are apparently
423 a few prototypes like that in existence) and therefore access to 428 a few prototypes like that in existence) and therefore access to
@@ -436,7 +441,6 @@ config HAS_TLS_REG
436 441
437config NEEDS_SYSCALL_FOR_CMPXCHG 442config NEEDS_SYSCALL_FOR_CMPXCHG
438 bool 443 bool
439 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
440 help 444 help
441 SMP on a pre-ARMv6 processor? Well OK then. 445 SMP on a pre-ARMv6 processor? Well OK then.
442 Forget about fast user space cmpxchg support. 446 Forget about fast user space cmpxchg support.
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 3aa80094012c..959588884fa5 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,6 +29,7 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 767d158f211a..be6d081ff2b7 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,6 +29,7 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 6ca639094d6f..f778545d57a2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/procinfo.h> 23#include <asm/procinfo.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 10317e4f55d2..148c111fde73 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/procinfo.h> 23#include <asm/procinfo.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 8e7e1e70ab05..540359b475d0 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18#include <asm/procinfo.h> 19#include <asm/procinfo.h>
19#include <asm/ptrace.h> 20#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 471286fdf78f..26f00ee2ad9a 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -34,6 +34,7 @@
34#include <linux/init.h> 34#include <linux/init.h>
35#include <asm/assembler.h> 35#include <asm/assembler.h>
36#include <asm/asm-offsets.h> 36#include <asm/asm-offsets.h>
37#include <asm/pgtable-hwdef.h>
37#include <asm/pgtable.h> 38#include <asm/pgtable.h>
38#include <asm/procinfo.h> 39#include <asm/procinfo.h>
39#include <asm/ptrace.h> 40#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 950d3b664c1e..a17f79e0199c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,6 +28,7 @@
28#include <linux/config.h> 28#include <linux/config.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/pgtable-hwdef.h>
31#include <asm/pgtable.h> 32#include <asm/pgtable.h>
32#include <asm/procinfo.h> 33#include <asm/procinfo.h>
33#include <asm/page.h> 34#include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 410b032faa3b..bbde4a024a48 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,6 +29,7 @@
29#include <linux/config.h> 29#include <linux/config.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <asm/assembler.h> 31#include <asm/assembler.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/page.h> 35#include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 6dd2be7cd050..224ce226a01b 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -51,6 +51,7 @@
51#include <linux/config.h> 51#include <linux/config.h>
52#include <linux/init.h> 52#include <linux/init.h>
53#include <asm/assembler.h> 53#include <asm/assembler.h>
54#include <asm/pgtable-hwdef.h>
54#include <asm/pgtable.h> 55#include <asm/pgtable.h>
55#include <asm/procinfo.h> 56#include <asm/procinfo.h>
56#include <asm/page.h> 57#include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 022e86842041..4e2a087cf388 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,6 +28,7 @@
28#include <linux/config.h> 28#include <linux/config.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/pgtable-hwdef.h>
31#include <asm/pgtable.h> 32#include <asm/pgtable.h>
32#include <asm/procinfo.h> 33#include <asm/procinfo.h>
33#include <asm/page.h> 34#include <asm/page.h>
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bd330c4075a1..c916a6cae404 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -18,6 +18,7 @@
18#include <asm/asm-offsets.h> 18#include <asm/asm-offsets.h>
19#include <asm/procinfo.h> 19#include <asm/procinfo.h>
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/ptrace.h> 23#include <asm/ptrace.h>
23 24
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 91b89124c0d7..41f21f2dd8ff 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -23,6 +23,7 @@
23#include <asm/asm-offsets.h> 23#include <asm/asm-offsets.h>
24#include <asm/procinfo.h> 24#include <asm/procinfo.h>
25#include <asm/hardware.h> 25#include <asm/hardware.h>
26#include <asm/pgtable-hwdef.h>
26#include <asm/pgtable.h> 27#include <asm/pgtable.h>
27 28
28/* 29/*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 92f3ca31b7b9..9a7e7c096aa9 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -14,6 +14,7 @@
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/hardware/arm_scu.h> 15#include <asm/hardware/arm_scu.h>
16#include <asm/procinfo.h> 16#include <asm/procinfo.h>
17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18 19
19#include "proc-macros.S" 20#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index b50f87a0ee76..29bcc4dd6517 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -25,6 +25,7 @@
25#include <asm/assembler.h> 25#include <asm/assembler.h>
26#include <asm/procinfo.h> 26#include <asm/procinfo.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/pgtable-hwdef.h>
28#include <asm/page.h> 29#include <asm/page.h>
29#include <asm/ptrace.h> 30#include <asm/ptrace.h>
30#include "proc-macros.S" 31#include "proc-macros.S"
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 9ab1abfbe7ad..7b595547c1c8 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -18,6 +18,7 @@
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/assembler.h>
21#include <asm/vfpmacros.h> 22#include <asm/vfpmacros.h>
22 23
23 .globl do_vfp 24 .globl do_vfp
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index de4ca1223c58..b7ed57e00cd4 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -102,7 +102,6 @@ vfp_support_entry:
102 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading 102 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
103 @ nonexistant reg on rev0 103 @ nonexistant reg on rev0
104 VFPFSTMIA r4 @ save the working registers 104 VFPFSTMIA r4 @ save the working registers
105 add r4, r4, #8*16+4
106 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 105 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
107 @ and point r4 at the word at the 106 @ and point r4 at the word at the
108 @ start of the register dump 107 @ start of the register dump
@@ -111,10 +110,9 @@ no_old_VFP_process:
111 DBGSTR1 "load state %p", r10 110 DBGSTR1 "load state %p", r10
112 str r10, [r3] @ update the last_VFP_context pointer 111 str r10, [r3] @ update the last_VFP_context pointer
113 @ Load the saved state back into the VFP 112 @ Load the saved state back into the VFP
114 add r4, r10, #8*16+4
115 ldmia r4, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
116 VFPFLDMIA r10 @ reload the working registers while 113 VFPFLDMIA r10 @ reload the working registers while
117 @ FPEXC is in a safe state 114 @ FPEXC is in a safe state
115 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
118 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write? 116 tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
119 VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing 117 VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
120 @ nonexistant reg on rev0 118 @ nonexistant reg on rev0
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 9bfffdbf1e0b..2910d359f919 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -172,6 +172,7 @@
172#define AT91_PMC_MDIV_4 (3 << 8) 172#define AT91_PMC_MDIV_4 (3 << 8)
173 173
174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ 174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
175
175#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 176#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
176#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 177#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
177#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 178#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
@@ -286,8 +287,32 @@
286#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 287#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
287 288
288#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 289#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
290#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
291#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
292#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
293#define AT91_MC_ABTSZ_BYTE (0 << 8)
294#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
295#define AT91_MC_ABTSZ_WORD (2 << 8)
296#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
297#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
298#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
299#define AT91_MC_ABTTYP_FETCH (2 << 10)
300#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
301#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
302#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
303#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
304#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
305#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
306#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
307#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
308
289#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 309#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
310
290#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 311#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
312#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
313#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
314#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
315#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
291 316
292/* External Bus Interface (EBI) registers */ 317/* External Bus Interface (EBI) registers */
293#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 318#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
@@ -309,8 +334,10 @@
309/* Static Memory Controller (SMC) registers */ 334/* Static Memory Controller (SMC) registers */
310#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 335#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
311#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 336#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
337#define AT91_SMC_NWS_(x) ((x) << 0)
312#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 338#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
313#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ 339#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
340#define AT91_SMC_TDF_(x) ((x) << 8)
314#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ 341#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
315#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ 342#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
316#define AT91_SMC_DBW_16 (1 << 13) 343#define AT91_SMC_DBW_16 (1 << 13)
@@ -322,7 +349,78 @@
322#define AT91_SMC_ACSS_2 (2 << 16) 349#define AT91_SMC_ACSS_2 (2 << 16)
323#define AT91_SMC_ACSS_3 (3 << 16) 350#define AT91_SMC_ACSS_3 (3 << 16)
324#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ 351#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
352#define AT91_SMC_RWSETUP_(x) ((x) << 24)
325#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 353#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
326 354#define AT91_SMC_RWHOLD_(x) ((x) << 28)
355
356/* SDRAM Controller registers */
357#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
358#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
359#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
360#define AT91_SDRAMC_MODE_NOP (1 << 0)
361#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
362#define AT91_SDRAMC_MODE_LMR (3 << 0)
363#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
364#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
365#define AT91_SDRAMC_DBW_32 (0 << 4)
366#define AT91_SDRAMC_DBW_16 (1 << 4)
367
368#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
369#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
370
371#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
372#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
373#define AT91_SDRAMC_NC_8 (0 << 0)
374#define AT91_SDRAMC_NC_9 (1 << 0)
375#define AT91_SDRAMC_NC_10 (2 << 0)
376#define AT91_SDRAMC_NC_11 (3 << 0)
377#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
378#define AT91_SDRAMC_NR_11 (0 << 2)
379#define AT91_SDRAMC_NR_12 (1 << 2)
380#define AT91_SDRAMC_NR_13 (2 << 2)
381#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
382#define AT91_SDRAMC_NB_2 (0 << 4)
383#define AT91_SDRAMC_NB_4 (1 << 4)
384#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
385#define AT91_SDRAMC_CAS_2 (2 << 5)
386#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
387#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
388#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
389#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
390#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
391#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
392
393#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
394#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
395#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
396#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
397#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
398#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
399
400/* Burst Flash Controller register */
401#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
402#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
403#define AT91_BFC_BFCOM_DISABLED (0 << 0)
404#define AT91_BFC_BFCOM_ASYNC (1 << 0)
405#define AT91_BFC_BFCOM_BURST (2 << 0)
406#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
407#define AT91_BFC_BFCC_MCK (1 << 2)
408#define AT91_BFC_BFCC_DIV2 (2 << 2)
409#define AT91_BFC_BFCC_DIV4 (3 << 2)
410#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
411#define AT91_BFC_PAGES (7 << 8) /* Page Size */
412#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
413#define AT91_BFC_PAGES_16 (1 << 8)
414#define AT91_BFC_PAGES_32 (2 << 8)
415#define AT91_BFC_PAGES_64 (3 << 8)
416#define AT91_BFC_PAGES_128 (4 << 8)
417#define AT91_BFC_PAGES_256 (5 << 8)
418#define AT91_BFC_PAGES_512 (6 << 8)
419#define AT91_BFC_PAGES_1024 (7 << 8)
420#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
421#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
422#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
423#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
424#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
327 425
328#endif 426#endif
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index f31ac92b6c7f..d53bafa9bf1c 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -80,16 +80,33 @@
80 instr regs 80 instr regs
81 81
82/* 82/*
83 * Save the current IRQ state and disable IRQs. Note that this macro 83 * Enable and disable interrupts
84 * assumes FIQs are enabled, and that the processor is in SVC mode.
85 */ 84 */
86 .macro save_and_disable_irqs, oldcpsr
87 mrs \oldcpsr, cpsr
88#if __LINUX_ARM_ARCH__ >= 6 85#if __LINUX_ARM_ARCH__ >= 6
86 .macro disable_irq
89 cpsid i 87 cpsid i
88 .endm
89
90 .macro enable_irq
91 cpsie i
92 .endm
90#else 93#else
91 msr cpsr_c, #PSR_I_BIT | MODE_SVC 94 .macro disable_irq
95 msr cpsr_c, #PSR_I_BIT | SVC_MODE
96 .endm
97
98 .macro enable_irq
99 msr cpsr_c, #SVC_MODE
100 .endm
92#endif 101#endif
102
103/*
104 * Save the current IRQ state and disable IRQs. Note that this macro
105 * assumes FIQs are enabled, and that the processor is in SVC mode.
106 */
107 .macro save_and_disable_irqs, oldcpsr
108 mrs \oldcpsr, cpsr
109 disable_irq
93 .endm 110 .endm
94 111
95/* 112/*
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index bc18ff405181..c4ac2e67768d 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -10,10 +10,15 @@
10#ifndef _ASMARM_PGALLOC_H 10#ifndef _ASMARM_PGALLOC_H
11#define _ASMARM_PGALLOC_H 11#define _ASMARM_PGALLOC_H
12 12
13#include <asm/domain.h>
14#include <asm/pgtable-hwdef.h>
13#include <asm/processor.h> 15#include <asm/processor.h>
14#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
15#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
16 18
19#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
20#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
21
17/* 22/*
18 * Since we have only two-level page tables, these are trivial 23 * Since we have only two-level page tables, these are trivial
19 */ 24 */
diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h
new file mode 100644
index 000000000000..1d033495cc75
--- /dev/null
+++ b/include/asm-arm/pgtable-hwdef.h
@@ -0,0 +1,88 @@
1/*
2 * linux/include/asm-arm/pgtable-hwdef.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_PGTABLE_HWDEF_H
11#define _ASMARM_PGTABLE_HWDEF_H
12
13/*
14 * Hardware page table definitions.
15 *
16 * + Level 1 descriptor (PMD)
17 * - common
18 */
19#define PMD_TYPE_MASK (3 << 0)
20#define PMD_TYPE_FAULT (0 << 0)
21#define PMD_TYPE_TABLE (1 << 0)
22#define PMD_TYPE_SECT (2 << 0)
23#define PMD_BIT4 (1 << 4)
24#define PMD_DOMAIN(x) ((x) << 5)
25#define PMD_PROTECTION (1 << 9) /* v5 */
26/*
27 * - section
28 */
29#define PMD_SECT_BUFFERABLE (1 << 2)
30#define PMD_SECT_CACHEABLE (1 << 3)
31#define PMD_SECT_AP_WRITE (1 << 10)
32#define PMD_SECT_AP_READ (1 << 11)
33#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
34#define PMD_SECT_APX (1 << 15) /* v6 */
35#define PMD_SECT_S (1 << 16) /* v6 */
36#define PMD_SECT_nG (1 << 17) /* v6 */
37#define PMD_SECT_SUPER (1 << 18) /* v6 */
38
39#define PMD_SECT_UNCACHED (0)
40#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
41#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
42#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
43#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
44#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
45#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
46
47/*
48 * - coarse table (not used)
49 */
50
51/*
52 * + Level 2 descriptor (PTE)
53 * - common
54 */
55#define PTE_TYPE_MASK (3 << 0)
56#define PTE_TYPE_FAULT (0 << 0)
57#define PTE_TYPE_LARGE (1 << 0)
58#define PTE_TYPE_SMALL (2 << 0)
59#define PTE_TYPE_EXT (3 << 0) /* v5 */
60#define PTE_BUFFERABLE (1 << 2)
61#define PTE_CACHEABLE (1 << 3)
62
63/*
64 * - extended small page/tiny page
65 */
66#define PTE_EXT_XN (1 << 0) /* v6 */
67#define PTE_EXT_AP_MASK (3 << 4)
68#define PTE_EXT_AP0 (1 << 4)
69#define PTE_EXT_AP1 (2 << 4)
70#define PTE_EXT_AP_UNO_SRO (0 << 4)
71#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
72#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
73#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
74#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
75#define PTE_EXT_APX (1 << 9) /* v6 */
76#define PTE_EXT_SHARED (1 << 10) /* v6 */
77#define PTE_EXT_NG (1 << 11) /* v6 */
78
79/*
80 * - small page
81 */
82#define PTE_SMALL_AP_MASK (0xff << 4)
83#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
84#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
85#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
86#define PTE_SMALL_AP_URW_SRW (0xff << 4)
87
88#endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 70e00d08345e..e595ae24efe2 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -137,81 +137,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) 137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
138 138
139/* 139/*
140 * Hardware page table definitions.
141 *
142 * + Level 1 descriptor (PMD)
143 * - common
144 */
145#define PMD_TYPE_MASK (3 << 0)
146#define PMD_TYPE_FAULT (0 << 0)
147#define PMD_TYPE_TABLE (1 << 0)
148#define PMD_TYPE_SECT (2 << 0)
149#define PMD_BIT4 (1 << 4)
150#define PMD_DOMAIN(x) ((x) << 5)
151#define PMD_PROTECTION (1 << 9) /* v5 */
152/*
153 * - section
154 */
155#define PMD_SECT_BUFFERABLE (1 << 2)
156#define PMD_SECT_CACHEABLE (1 << 3)
157#define PMD_SECT_AP_WRITE (1 << 10)
158#define PMD_SECT_AP_READ (1 << 11)
159#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
160#define PMD_SECT_APX (1 << 15) /* v6 */
161#define PMD_SECT_S (1 << 16) /* v6 */
162#define PMD_SECT_nG (1 << 17) /* v6 */
163#define PMD_SECT_SUPER (1 << 18) /* v6 */
164
165#define PMD_SECT_UNCACHED (0)
166#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
167#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
168#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
169#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
170#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
171#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
172
173/*
174 * - coarse table (not used)
175 */
176
177/*
178 * + Level 2 descriptor (PTE)
179 * - common
180 */
181#define PTE_TYPE_MASK (3 << 0)
182#define PTE_TYPE_FAULT (0 << 0)
183#define PTE_TYPE_LARGE (1 << 0)
184#define PTE_TYPE_SMALL (2 << 0)
185#define PTE_TYPE_EXT (3 << 0) /* v5 */
186#define PTE_BUFFERABLE (1 << 2)
187#define PTE_CACHEABLE (1 << 3)
188
189/*
190 * - extended small page/tiny page
191 */
192#define PTE_EXT_XN (1 << 0) /* v6 */
193#define PTE_EXT_AP_MASK (3 << 4)
194#define PTE_EXT_AP0 (1 << 4)
195#define PTE_EXT_AP1 (2 << 4)
196#define PTE_EXT_AP_UNO_SRO (0 << 4)
197#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
198#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
199#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
200#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
201#define PTE_EXT_APX (1 << 9) /* v6 */
202#define PTE_EXT_SHARED (1 << 10) /* v6 */
203#define PTE_EXT_NG (1 << 11) /* v6 */
204
205/*
206 * - small page
207 */
208#define PTE_SMALL_AP_MASK (0xff << 4)
209#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
210#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
211#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
212#define PTE_SMALL_AP_URW_SRW (0xff << 4)
213
214/*
215 * "Linux" PTE definitions. 140 * "Linux" PTE definitions.
216 * 141 *
217 * We keep two sets of PTEs - the hardware and the linux version. 142 * We keep two sets of PTEs - the hardware and the linux version.
@@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
236 161
237#ifndef __ASSEMBLY__ 162#ifndef __ASSEMBLY__
238 163
239#include <asm/domain.h>
240
241#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
242#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
243
244/* 164/*
245 * The following macros handle the cache and bufferable bits... 165 * The following macros handle the cache and bufferable bits...
246 */ 166 */
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index f49bfb78c221..cb740025d413 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -19,6 +19,14 @@
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22
23#ifndef CONFIG_MMU
24
25#include <linux/pagemap.h>
26#include <asm-generic/tlb.h>
27
28#else /* !CONFIG_MMU */
29
22#include <asm/pgalloc.h> 30#include <asm/pgalloc.h>
23 31
24/* 32/*
@@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
82 90
83#define tlb_migrate_finish(mm) do { } while (0) 91#define tlb_migrate_finish(mm) do { } while (0)
84 92
93#endif /* CONFIG_MMU */
85#endif 94#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 0c2acc944a0a..728992451dd1 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -11,6 +11,13 @@
11#define _ASMARM_TLBFLUSH_H 11#define _ASMARM_TLBFLUSH_H
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14
15#ifndef CONFIG_MMU
16
17#define tlb_flush(tlb) ((void) tlb)
18
19#else /* CONFIG_MMU */
20
14#include <asm/glue.h> 21#include <asm/glue.h>
15 22
16#define TLB_V3_PAGE (1 << 0) 23#define TLB_V3_PAGE (1 << 0)
@@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte
423 430
424#endif 431#endif
425 432
433#endif /* CONFIG_MMU */
434
426#endif 435#endif
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 12848f81bb37..5ca8c6fddb56 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -8,8 +8,8 @@
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11#ifndef ASMARM_CLOCK_H 11#ifndef __LINUX_CLK_H
12#define ASMARM_CLOCK_H 12#define __LINUX_CLK_H
13 13
14struct device; 14struct device;
15 15
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 01:16:46 -0500