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-rw-r--r--drivers/net/skge.c472
-rw-r--r--drivers/net/skge.h113
2 files changed, 279 insertions, 306 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index cd4e92beb1b5..210029a73642 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -88,8 +88,8 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
88static int skge_up(struct net_device *dev); 88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev); 89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge); 90static void skge_tx_clean(struct skge_port *skge);
91static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93static void genesis_get_stats(struct skge_port *skge, u64 *data); 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data); 94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port); 95static void yukon_init(struct skge_hw *hw, int port);
@@ -632,30 +632,30 @@ static int skge_set_coalesce(struct net_device *dev,
632static void skge_led_on(struct skge_hw *hw, int port) 632static void skge_led_on(struct skge_hw *hw, int port)
633{ 633{
634 if (hw->chip_id == CHIP_ID_GENESIS) { 634 if (hw->chip_id == CHIP_ID_GENESIS) {
635 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); 635 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
636 skge_write8(hw, B0_LED, LED_STAT_ON); 636 skge_write8(hw, B0_LED, LED_STAT_ON);
637 637
638 skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON); 638 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
639 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100); 639 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
640 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); 640 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
641 641
642 switch (hw->phy_type) { 642 switch (hw->phy_type) {
643 case SK_PHY_BCOM: 643 case SK_PHY_BCOM:
644 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, 644 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
645 PHY_B_PEC_LED_ON); 645 PHY_B_PEC_LED_ON);
646 break; 646 break;
647 case SK_PHY_LONE: 647 case SK_PHY_LONE:
648 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG, 648 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
649 0x0800); 649 0x0800);
650 break; 650 break;
651 default: 651 default:
652 skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON); 652 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
653 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100); 653 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
654 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START); 654 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
655 } 655 }
656 } else { 656 } else {
657 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, 658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
659 PHY_M_LED_MO_DUP(MO_LED_ON) | 659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) | 660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) | 661 PHY_M_LED_MO_100(MO_LED_ON) |
@@ -667,28 +667,28 @@ static void skge_led_on(struct skge_hw *hw, int port)
667static void skge_led_off(struct skge_hw *hw, int port) 667static void skge_led_off(struct skge_hw *hw, int port)
668{ 668{
669 if (hw->chip_id == CHIP_ID_GENESIS) { 669 if (hw->chip_id == CHIP_ID_GENESIS) {
670 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF); 670 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
671 skge_write8(hw, B0_LED, LED_STAT_OFF); 671 skge_write8(hw, B0_LED, LED_STAT_OFF);
672 672
673 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0); 673 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
674 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF); 674 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
675 675
676 switch (hw->phy_type) { 676 switch (hw->phy_type) {
677 case SK_PHY_BCOM: 677 case SK_PHY_BCOM:
678 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, 678 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
679 PHY_B_PEC_LED_OFF); 679 PHY_B_PEC_LED_OFF);
680 break; 680 break;
681 case SK_PHY_LONE: 681 case SK_PHY_LONE:
682 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG, 682 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
683 PHY_L_LC_LEDT); 683 PHY_L_LC_LEDT);
684 break; 684 break;
685 default: 685 default:
686 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0); 686 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
687 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF); 687 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
688 } 688 }
689 } else { 689 } else {
690 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 690 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
691 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, 691 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
692 PHY_M_LED_MO_DUP(MO_LED_OFF) | 692 PHY_M_LED_MO_DUP(MO_LED_OFF) |
693 PHY_M_LED_MO_10(MO_LED_OFF) | 693 PHY_M_LED_MO_10(MO_LED_OFF) |
694 PHY_M_LED_MO_100(MO_LED_OFF) | 694 PHY_M_LED_MO_100(MO_LED_OFF) |
@@ -908,17 +908,17 @@ static void skge_link_down(struct skge_port *skge)
908 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); 908 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
909} 909}
910 910
911static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg) 911static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
912{ 912{
913 int i; 913 int i;
914 u16 v; 914 u16 v;
915 915
916 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 916 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
917 v = skge_xm_read16(hw, port, XM_PHY_DATA); 917 v = xm_read16(hw, port, XM_PHY_DATA);
918 if (hw->phy_type != SK_PHY_XMAC) { 918 if (hw->phy_type != SK_PHY_XMAC) {
919 for (i = 0; i < PHY_RETRIES; i++) { 919 for (i = 0; i < PHY_RETRIES; i++) {
920 udelay(1); 920 udelay(1);
921 if (skge_xm_read16(hw, port, XM_MMU_CMD) 921 if (xm_read16(hw, port, XM_MMU_CMD)
922 & XM_MMU_PHY_RDY) 922 & XM_MMU_PHY_RDY)
923 goto ready; 923 goto ready;
924 } 924 }
@@ -927,19 +927,19 @@ static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg)
927 hw->dev[port]->name); 927 hw->dev[port]->name);
928 return 0; 928 return 0;
929 ready: 929 ready:
930 v = skge_xm_read16(hw, port, XM_PHY_DATA); 930 v = xm_read16(hw, port, XM_PHY_DATA);
931 } 931 }
932 932
933 return v; 933 return v;
934} 934}
935 935
936static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 936static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
937{ 937{
938 int i; 938 int i;
939 939
940 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 940 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
941 for (i = 0; i < PHY_RETRIES; i++) { 941 for (i = 0; i < PHY_RETRIES; i++) {
942 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 942 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
943 goto ready; 943 goto ready;
944 cpu_relax(); 944 cpu_relax();
945 } 945 }
@@ -948,10 +948,10 @@ static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
948 948
949 949
950 ready: 950 ready:
951 skge_xm_write16(hw, port, XM_PHY_DATA, val); 951 xm_write16(hw, port, XM_PHY_DATA, val);
952 for (i = 0; i < PHY_RETRIES; i++) { 952 for (i = 0; i < PHY_RETRIES; i++) {
953 udelay(1); 953 udelay(1);
954 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 954 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
955 return; 955 return;
956 } 956 }
957 printk(KERN_WARNING PFX "%s: phy write timed out\n", 957 printk(KERN_WARNING PFX "%s: phy write timed out\n",
@@ -992,20 +992,20 @@ static void genesis_reset(struct skge_hw *hw, int port)
992 u64 zero = 0; 992 u64 zero = 0;
993 993
994 /* reset the statistics module */ 994 /* reset the statistics module */
995 skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 995 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
996 skge_xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ 996 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
997 skge_xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 997 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
998 skge_xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 998 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
999 skge_xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 999 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1000 1000
1001 /* disable all PHY IRQs */ 1001 /* disable all PHY IRQs */
1002 if (hw->phy_type == SK_PHY_BCOM) 1002 if (hw->phy_type == SK_PHY_BCOM)
1003 skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 1003 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1004 1004
1005 skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero); 1005 xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
1006 for (i = 0; i < 15; i++) 1006 for (i = 0; i < 15; i++)
1007 skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero); 1007 xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
1008 skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero); 1008 xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
1009} 1009}
1010 1010
1011 1011
@@ -1033,14 +1033,14 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1033 1033
1034 1034
1035 /* initialize Rx, Tx and Link LED */ 1035 /* initialize Rx, Tx and Link LED */
1036 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); 1036 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1037 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 1037 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
1038 1038
1039 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); 1039 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1040 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START); 1040 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
1041 1041
1042 /* Unreset the XMAC. */ 1042 /* Unreset the XMAC. */
1043 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1043 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1044 1044
1045 /* 1045 /*
1046 * Perform additional initialization for external PHYs, 1046 * Perform additional initialization for external PHYs,
@@ -1060,13 +1060,13 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1060 skge_read32(hw, B2_GP_IO); 1060 skge_read32(hw, B2_GP_IO);
1061 1061
1062 /* Enable GMII mode on the XMAC. */ 1062 /* Enable GMII mode on the XMAC. */
1063 skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1063 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1064 1064
1065 id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1); 1065 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1066 1066
1067 /* Optimize MDIO transfer by suppressing preamble. */ 1067 /* Optimize MDIO transfer by suppressing preamble. */
1068 skge_xm_write16(hw, port, XM_MMU_CMD, 1068 xm_write16(hw, port, XM_MMU_CMD,
1069 skge_xm_read16(hw, port, XM_MMU_CMD) 1069 xm_read16(hw, port, XM_MMU_CMD)
1070 | XM_MMU_NO_PRE); 1070 | XM_MMU_NO_PRE);
1071 1071
1072 if (id1 == PHY_BCOM_ID1_C0) { 1072 if (id1 == PHY_BCOM_ID1_C0) {
@@ -1075,7 +1075,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1075 * Write magic patterns to reserved registers. 1075 * Write magic patterns to reserved registers.
1076 */ 1076 */
1077 for (i = 0; i < ARRAY_SIZE(C0hack); i++) 1077 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1078 skge_xm_phy_write(hw, port, 1078 xm_phy_write(hw, port,
1079 C0hack[i].reg, C0hack[i].val); 1079 C0hack[i].reg, C0hack[i].val);
1080 1080
1081 } else if (id1 == PHY_BCOM_ID1_A1) { 1081 } else if (id1 == PHY_BCOM_ID1_A1) {
@@ -1084,7 +1084,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1084 * Write magic patterns to reserved registers. 1084 * Write magic patterns to reserved registers.
1085 */ 1085 */
1086 for (i = 0; i < ARRAY_SIZE(A1hack); i++) 1086 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1087 skge_xm_phy_write(hw, port, 1087 xm_phy_write(hw, port,
1088 A1hack[i].reg, A1hack[i].val); 1088 A1hack[i].reg, A1hack[i].val);
1089 } 1089 }
1090 1090
@@ -1092,23 +1092,23 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1092 * Workaround BCOM Errata (#10523) for all BCom PHYs. 1092 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1093 * Disable Power Management after reset. 1093 * Disable Power Management after reset.
1094 */ 1094 */
1095 r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); 1095 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1096 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM); 1096 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
1097 } 1097 }
1098 1098
1099 /* Dummy read */ 1099 /* Dummy read */
1100 skge_xm_read16(hw, port, XM_ISRC); 1100 xm_read16(hw, port, XM_ISRC);
1101 1101
1102 r = skge_xm_read32(hw, port, XM_MODE); 1102 r = xm_read32(hw, port, XM_MODE);
1103 skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA); 1103 xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
1104 1104
1105 /* We don't need the FCS appended to the packet. */ 1105 /* We don't need the FCS appended to the packet. */
1106 r = skge_xm_read16(hw, port, XM_RX_CMD); 1106 r = xm_read16(hw, port, XM_RX_CMD);
1107 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS); 1107 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
1108 1108
1109 /* We want short frames padded to 60 bytes. */ 1109 /* We want short frames padded to 60 bytes. */
1110 r = skge_xm_read16(hw, port, XM_TX_CMD); 1110 r = xm_read16(hw, port, XM_TX_CMD);
1111 skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD); 1111 xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
1112 1112
1113 /* 1113 /*
1114 * Enable the reception of all error frames. This is is 1114 * Enable the reception of all error frames. This is is
@@ -1124,19 +1124,19 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1124 * case the XMAC will start transfering frames out of the 1124 * case the XMAC will start transfering frames out of the
1125 * RX FIFO as soon as the FIFO threshold is reached. 1125 * RX FIFO as soon as the FIFO threshold is reached.
1126 */ 1126 */
1127 r = skge_xm_read32(hw, port, XM_MODE); 1127 r = xm_read32(hw, port, XM_MODE);
1128 skge_xm_write32(hw, port, XM_MODE, 1128 xm_write32(hw, port, XM_MODE,
1129 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT| 1129 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1130 XM_MD_RX_ERR|XM_MD_RX_IRLE); 1130 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1131 1131
1132 skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr); 1132 xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1133 skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr); 1133 xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
1134 1134
1135 /* 1135 /*
1136 * Bump up the transmit threshold. This helps hold off transmit 1136 * Bump up the transmit threshold. This helps hold off transmit
1137 * underruns when we're blasting traffic from both ports at once. 1137 * underruns when we're blasting traffic from both ports at once.
1138 */ 1138 */
1139 skge_xm_write16(hw, port, XM_TX_THR, 512); 1139 xm_write16(hw, port, XM_TX_THR, 512);
1140 1140
1141 /* Configure MAC arbiter */ 1141 /* Configure MAC arbiter */
1142 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1142 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
@@ -1153,18 +1153,18 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1153 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1153 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1154 1154
1155 /* Configure Rx MAC FIFO */ 1155 /* Configure Rx MAC FIFO */
1156 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 1156 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1157 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 1157 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1158 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 1158 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1159 1159
1160 /* Configure Tx MAC FIFO */ 1160 /* Configure Tx MAC FIFO */
1161 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 1161 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1162 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 1162 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1163 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 1163 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1164 1164
1165 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 1165 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1166 /* Enable frame flushing if jumbo frames used */ 1166 /* Enable frame flushing if jumbo frames used */
1167 skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); 1167 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1168 } else { 1168 } else {
1169 /* enable timeout timers if normal frames */ 1169 /* enable timeout timers if normal frames */
1170 skge_write16(hw, B3_PA_CTRL, 1170 skge_write16(hw, B3_PA_CTRL,
@@ -1172,11 +1172,11 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1172 } 1172 }
1173 1173
1174 1174
1175 r = skge_xm_read16(hw, port, XM_RX_CMD); 1175 r = xm_read16(hw, port, XM_RX_CMD);
1176 if (hw->dev[port]->mtu > ETH_DATA_LEN) 1176 if (hw->dev[port]->mtu > ETH_DATA_LEN)
1177 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK); 1177 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
1178 else 1178 else
1179 skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK)); 1179 xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
1180 1180
1181 switch (hw->phy_type) { 1181 switch (hw->phy_type) {
1182 case SK_PHY_XMAC: 1182 case SK_PHY_XMAC:
@@ -1198,7 +1198,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1198 break; 1198 break;
1199 } 1199 }
1200 1200
1201 skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1); 1201 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
1202 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG; 1202 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1203 } else { 1203 } else {
1204 ctrl2 = 0; 1204 ctrl2 = 0;
@@ -1206,7 +1206,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1206 ctrl2 |= PHY_CT_DUP_MD; 1206 ctrl2 |= PHY_CT_DUP_MD;
1207 } 1207 }
1208 1208
1209 skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2); 1209 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
1210 break; 1210 break;
1211 1211
1212 case SK_PHY_BCOM: 1212 case SK_PHY_BCOM:
@@ -1253,27 +1253,27 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1253 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */ 1253 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1254 } 1254 }
1255 1255
1256 skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2); 1256 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1257 skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3); 1257 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
1258 1258
1259 if (skge->netdev->mtu > ETH_DATA_LEN) { 1259 if (skge->netdev->mtu > ETH_DATA_LEN) {
1260 ctrl4 |= PHY_B_PEC_HIGH_LA; 1260 ctrl4 |= PHY_B_PEC_HIGH_LA;
1261 ctrl5 |= PHY_B_AC_LONG_PACK; 1261 ctrl5 |= PHY_B_AC_LONG_PACK;
1262 1262
1263 skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5); 1263 xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
1264 } 1264 }
1265 1265
1266 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4); 1266 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1267 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1); 1267 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
1268 break; 1268 break;
1269 } 1269 }
1270 spin_unlock_bh(&hw->phy_lock); 1270 spin_unlock_bh(&hw->phy_lock);
1271 1271
1272 /* Clear MIB counters */ 1272 /* Clear MIB counters */
1273 skge_xm_write16(hw, port, XM_STAT_CMD, 1273 xm_write16(hw, port, XM_STAT_CMD,
1274 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1274 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1275 /* Clear two times according to Errata #3 */ 1275 /* Clear two times according to Errata #3 */
1276 skge_xm_write16(hw, port, XM_STAT_CMD, 1276 xm_write16(hw, port, XM_STAT_CMD,
1277 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1277 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1278 1278
1279 /* Start polling for link status */ 1279 /* Start polling for link status */
@@ -1293,12 +1293,12 @@ static void genesis_stop(struct skge_port *skge)
1293 * If the transfer stucks at the MAC the STOP command will not 1293 * If the transfer stucks at the MAC the STOP command will not
1294 * terminate if we don't flush the XMAC's transmit FIFO ! 1294 * terminate if we don't flush the XMAC's transmit FIFO !
1295 */ 1295 */
1296 skge_xm_write32(hw, port, XM_MODE, 1296 xm_write32(hw, port, XM_MODE,
1297 skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF); 1297 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1298 1298
1299 1299
1300 /* Reset the MAC */ 1300 /* Reset the MAC */
1301 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1301 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1302 1302
1303 /* For external PHYs there must be special handling */ 1303 /* For external PHYs there must be special handling */
1304 if (hw->phy_type != SK_PHY_XMAC) { 1304 if (hw->phy_type != SK_PHY_XMAC) {
@@ -1315,11 +1315,11 @@ static void genesis_stop(struct skge_port *skge)
1315 skge_read32(hw, B2_GP_IO); 1315 skge_read32(hw, B2_GP_IO);
1316 } 1316 }
1317 1317
1318 skge_xm_write16(hw, port, XM_MMU_CMD, 1318 xm_write16(hw, port, XM_MMU_CMD,
1319 skge_xm_read16(hw, port, XM_MMU_CMD) 1319 xm_read16(hw, port, XM_MMU_CMD)
1320 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1320 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1321 1321
1322 skge_xm_read16(hw, port, XM_MMU_CMD); 1322 xm_read16(hw, port, XM_MMU_CMD);
1323} 1323}
1324 1324
1325 1325
@@ -1330,11 +1330,11 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
1330 int i; 1330 int i;
1331 unsigned long timeout = jiffies + HZ; 1331 unsigned long timeout = jiffies + HZ;
1332 1332
1333 skge_xm_write16(hw, port, 1333 xm_write16(hw, port,
1334 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); 1334 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1335 1335
1336 /* wait for update to complete */ 1336 /* wait for update to complete */
1337 while (skge_xm_read16(hw, port, XM_STAT_CMD) 1337 while (xm_read16(hw, port, XM_STAT_CMD)
1338 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { 1338 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1339 if (time_after(jiffies, timeout)) 1339 if (time_after(jiffies, timeout))
1340 break; 1340 break;
@@ -1342,26 +1342,26 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
1342 } 1342 }
1343 1343
1344 /* special case for 64 bit octet counter */ 1344 /* special case for 64 bit octet counter */
1345 data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32 1345 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1346 | skge_xm_read32(hw, port, XM_TXO_OK_LO); 1346 | xm_read32(hw, port, XM_TXO_OK_LO);
1347 data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32 1347 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1348 | skge_xm_read32(hw, port, XM_RXO_OK_LO); 1348 | xm_read32(hw, port, XM_RXO_OK_LO);
1349 1349
1350 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1350 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1351 data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset); 1351 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1352} 1352}
1353 1353
1354static void genesis_mac_intr(struct skge_hw *hw, int port) 1354static void genesis_mac_intr(struct skge_hw *hw, int port)
1355{ 1355{
1356 struct skge_port *skge = netdev_priv(hw->dev[port]); 1356 struct skge_port *skge = netdev_priv(hw->dev[port]);
1357 u16 status = skge_xm_read16(hw, port, XM_ISRC); 1357 u16 status = xm_read16(hw, port, XM_ISRC);
1358 1358
1359 pr_debug("genesis_intr status %x\n", status); 1359 pr_debug("genesis_intr status %x\n", status);
1360 if (hw->phy_type == SK_PHY_XMAC) { 1360 if (hw->phy_type == SK_PHY_XMAC) {
1361 /* LInk down, start polling for state change */ 1361 /* LInk down, start polling for state change */
1362 if (status & XM_IS_INP_ASS) { 1362 if (status & XM_IS_INP_ASS) {
1363 skge_xm_write16(hw, port, XM_IMSK, 1363 xm_write16(hw, port, XM_IMSK,
1364 skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS); 1364 xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
1365 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); 1365 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1366 } 1366 }
1367 else if (status & XM_IS_AND) 1367 else if (status & XM_IS_AND)
@@ -1369,41 +1369,41 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
1369 } 1369 }
1370 1370
1371 if (status & XM_IS_TXF_UR) { 1371 if (status & XM_IS_TXF_UR) {
1372 skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF); 1372 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1373 ++skge->net_stats.tx_fifo_errors; 1373 ++skge->net_stats.tx_fifo_errors;
1374 } 1374 }
1375 if (status & XM_IS_RXF_OV) { 1375 if (status & XM_IS_RXF_OV) {
1376 skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF); 1376 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1377 ++skge->net_stats.rx_fifo_errors; 1377 ++skge->net_stats.rx_fifo_errors;
1378 } 1378 }
1379} 1379}
1380 1380
1381static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1381static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1382{ 1382{
1383 int i; 1383 int i;
1384 1384
1385 skge_gma_write16(hw, port, GM_SMI_DATA, val); 1385 gma_write16(hw, port, GM_SMI_DATA, val);
1386 skge_gma_write16(hw, port, GM_SMI_CTRL, 1386 gma_write16(hw, port, GM_SMI_CTRL,
1387 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 1387 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1388 for (i = 0; i < PHY_RETRIES; i++) { 1388 for (i = 0; i < PHY_RETRIES; i++) {
1389 udelay(1); 1389 udelay(1);
1390 1390
1391 if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 1391 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1392 break; 1392 break;
1393 } 1393 }
1394} 1394}
1395 1395
1396static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg) 1396static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1397{ 1397{
1398 int i; 1398 int i;
1399 1399
1400 skge_gma_write16(hw, port, GM_SMI_CTRL, 1400 gma_write16(hw, port, GM_SMI_CTRL,
1401 GM_SMI_CT_PHY_AD(hw->phy_addr) 1401 GM_SMI_CT_PHY_AD(hw->phy_addr)
1402 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 1402 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1403 1403
1404 for (i = 0; i < PHY_RETRIES; i++) { 1404 for (i = 0; i < PHY_RETRIES; i++) {
1405 udelay(1); 1405 udelay(1);
1406 if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 1406 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1407 goto ready; 1407 goto ready;
1408 } 1408 }
1409 1409
@@ -1411,7 +1411,7 @@ static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1411 hw->dev[port]->name); 1411 hw->dev[port]->name);
1412 return 0; 1412 return 0;
1413 ready: 1413 ready:
1414 return skge_gma_read16(hw, port, GM_SMI_DATA); 1414 return gma_read16(hw, port, GM_SMI_DATA);
1415} 1415}
1416 1416
1417static void genesis_link_down(struct skge_port *skge) 1417static void genesis_link_down(struct skge_port *skge)
@@ -1421,12 +1421,12 @@ static void genesis_link_down(struct skge_port *skge)
1421 1421
1422 pr_debug("genesis_link_down\n"); 1422 pr_debug("genesis_link_down\n");
1423 1423
1424 skge_xm_write16(hw, port, XM_MMU_CMD, 1424 xm_write16(hw, port, XM_MMU_CMD,
1425 skge_xm_read16(hw, port, XM_MMU_CMD) 1425 xm_read16(hw, port, XM_MMU_CMD)
1426 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1426 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1427 1427
1428 /* dummy read to ensure writing */ 1428 /* dummy read to ensure writing */
1429 (void) skge_xm_read16(hw, port, XM_MMU_CMD); 1429 (void) xm_read16(hw, port, XM_MMU_CMD);
1430 1430
1431 skge_link_down(skge); 1431 skge_link_down(skge);
1432} 1432}
@@ -1439,7 +1439,7 @@ static void genesis_link_up(struct skge_port *skge)
1439 u32 mode, msk; 1439 u32 mode, msk;
1440 1440
1441 pr_debug("genesis_link_up\n"); 1441 pr_debug("genesis_link_up\n");
1442 cmd = skge_xm_read16(hw, port, XM_MMU_CMD); 1442 cmd = xm_read16(hw, port, XM_MMU_CMD);
1443 1443
1444 /* 1444 /*
1445 * enabling pause frame reception is required for 1000BT 1445 * enabling pause frame reception is required for 1000BT
@@ -1452,9 +1452,9 @@ static void genesis_link_up(struct skge_port *skge)
1452 /* Enable Pause Frame Reception */ 1452 /* Enable Pause Frame Reception */
1453 cmd &= ~XM_MMU_IGN_PF; 1453 cmd &= ~XM_MMU_IGN_PF;
1454 1454
1455 skge_xm_write16(hw, port, XM_MMU_CMD, cmd); 1455 xm_write16(hw, port, XM_MMU_CMD, cmd);
1456 1456
1457 mode = skge_xm_read32(hw, port, XM_MODE); 1457 mode = xm_read32(hw, port, XM_MODE);
1458 if (skge->flow_control == FLOW_MODE_SYMMETRIC || 1458 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1459 skge->flow_control == FLOW_MODE_LOC_SEND) { 1459 skge->flow_control == FLOW_MODE_LOC_SEND) {
1460 /* 1460 /*
@@ -1468,10 +1468,10 @@ static void genesis_link_up(struct skge_port *skge)
1468 /* XM_PAUSE_DA = '010000C28001' (default) */ 1468 /* XM_PAUSE_DA = '010000C28001' (default) */
1469 /* XM_MAC_PTIME = 0xffff (maximum) */ 1469 /* XM_MAC_PTIME = 0xffff (maximum) */
1470 /* remember this value is defined in big endian (!) */ 1470 /* remember this value is defined in big endian (!) */
1471 skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 1471 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1472 1472
1473 mode |= XM_PAUSE_MODE; 1473 mode |= XM_PAUSE_MODE;
1474 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 1474 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1475 } else { 1475 } else {
1476 /* 1476 /*
1477 * disable pause frame generation is required for 1000BT 1477 * disable pause frame generation is required for 1000BT
@@ -1480,20 +1480,20 @@ static void genesis_link_up(struct skge_port *skge)
1480 /* Disable Pause Mode in Mode Register */ 1480 /* Disable Pause Mode in Mode Register */
1481 mode &= ~XM_PAUSE_MODE; 1481 mode &= ~XM_PAUSE_MODE;
1482 1482
1483 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 1483 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1484 } 1484 }
1485 1485
1486 skge_xm_write32(hw, port, XM_MODE, mode); 1486 xm_write32(hw, port, XM_MODE, mode);
1487 1487
1488 msk = XM_DEF_MSK; 1488 msk = XM_DEF_MSK;
1489 if (hw->phy_type != SK_PHY_XMAC) 1489 if (hw->phy_type != SK_PHY_XMAC)
1490 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */ 1490 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1491 1491
1492 skge_xm_write16(hw, port, XM_IMSK, msk); 1492 xm_write16(hw, port, XM_IMSK, msk);
1493 skge_xm_read16(hw, port, XM_ISRC); 1493 xm_read16(hw, port, XM_ISRC);
1494 1494
1495 /* get MMU Command Reg. */ 1495 /* get MMU Command Reg. */
1496 cmd = skge_xm_read16(hw, port, XM_MMU_CMD); 1496 cmd = xm_read16(hw, port, XM_MMU_CMD);
1497 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 1497 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1498 cmd |= XM_MMU_GMII_FD; 1498 cmd |= XM_MMU_GMII_FD;
1499 1499
@@ -1502,15 +1502,15 @@ static void genesis_link_up(struct skge_port *skge)
1502 * Workaround BCOM Errata (#10523) for all BCom Phys 1502 * Workaround BCOM Errata (#10523) for all BCom Phys
1503 * Enable Power Management after link up 1503 * Enable Power Management after link up
1504 */ 1504 */
1505 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1505 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1506 skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1506 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1507 & ~PHY_B_AC_DIS_PM); 1507 & ~PHY_B_AC_DIS_PM);
1508 skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK, 1508 xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
1509 PHY_B_DEF_MSK); 1509 PHY_B_DEF_MSK);
1510 } 1510 }
1511 1511
1512 /* enable Rx/Tx */ 1512 /* enable Rx/Tx */
1513 skge_xm_write16(hw, port, XM_MMU_CMD, 1513 xm_write16(hw, port, XM_MMU_CMD,
1514 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1514 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1515 skge_link_up(skge); 1515 skge_link_up(skge);
1516} 1516}
@@ -1520,7 +1520,7 @@ static void genesis_bcom_intr(struct skge_port *skge)
1520{ 1520{
1521 struct skge_hw *hw = skge->hw; 1521 struct skge_hw *hw = skge->hw;
1522 int port = skge->port; 1522 int port = skge->port;
1523 u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 1523 u16 stat = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1524 1524
1525 pr_debug("genesis_bcom intr stat=%x\n", stat); 1525 pr_debug("genesis_bcom intr stat=%x\n", stat);
1526 1526
@@ -1528,16 +1528,16 @@ static void genesis_bcom_intr(struct skge_port *skge)
1528 * enable and disable loopback mode if "NO HCD" occurs. 1528 * enable and disable loopback mode if "NO HCD" occurs.
1529 */ 1529 */
1530 if (stat & PHY_B_IS_NO_HDCL) { 1530 if (stat & PHY_B_IS_NO_HDCL) {
1531 u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL); 1531 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1532 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, 1532 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1533 ctrl | PHY_CT_LOOP); 1533 ctrl | PHY_CT_LOOP);
1534 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, 1534 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1535 ctrl & ~PHY_CT_LOOP); 1535 ctrl & ~PHY_CT_LOOP);
1536 } 1536 }
1537 1537
1538 stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT); 1538 stat = xm_phy_read(hw, port, PHY_BCOM_STAT);
1539 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) { 1539 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
1540 u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); 1540 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1541 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev)) 1541 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1542 genesis_link_down(skge); 1542 genesis_link_down(skge);
1543 1543
@@ -1590,7 +1590,7 @@ static void skge_link_timer(unsigned long __arg)
1590 else { 1590 else {
1591 int i; 1591 int i;
1592 for (i = 0; i < 3; i++) 1592 for (i = 0; i < 3; i++)
1593 if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS) 1593 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1594 break; 1594 break;
1595 1595
1596 if (i == 3) 1596 if (i == 3)
@@ -1610,7 +1610,7 @@ static void yukon_init(struct skge_hw *hw, int port)
1610 1610
1611 pr_debug("yukon_init\n"); 1611 pr_debug("yukon_init\n");
1612 if (skge->autoneg == AUTONEG_ENABLE) { 1612 if (skge->autoneg == AUTONEG_ENABLE) {
1613 u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 1613 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1614 1614
1615 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 1615 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1616 PHY_M_EC_MAC_S_MSK); 1616 PHY_M_EC_MAC_S_MSK);
@@ -1622,15 +1622,15 @@ static void yukon_init(struct skge_hw *hw, int port)
1622 else 1622 else
1623 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 1623 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1624 1624
1625 skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 1625 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1626 } 1626 }
1627 1627
1628 ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL); 1628 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1629 if (skge->autoneg == AUTONEG_DISABLE) 1629 if (skge->autoneg == AUTONEG_DISABLE)
1630 ctrl &= ~PHY_CT_ANE; 1630 ctrl &= ~PHY_CT_ANE;
1631 1631
1632 ctrl |= PHY_CT_RESET; 1632 ctrl |= PHY_CT_RESET;
1633 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1633 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1634 1634
1635 ctrl = 0; 1635 ctrl = 0;
1636 ct1000 = 0; 1636 ct1000 = 0;
@@ -1707,10 +1707,10 @@ static void yukon_init(struct skge_hw *hw, int port)
1707 } 1707 }
1708 1708
1709 if (hw->chip_id != CHIP_ID_YUKON_FE) 1709 if (hw->chip_id != CHIP_ID_YUKON_FE)
1710 skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 1710 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1711 1711
1712 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 1712 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1713 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1713 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1714 1714
1715 /* Setup Phy LED's */ 1715 /* Setup Phy LED's */
1716 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 1716 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
@@ -1720,8 +1720,8 @@ static void yukon_init(struct skge_hw *hw, int port)
1720 /* on 88E3082 these bits are at 11..9 (shifted left) */ 1720 /* on 88E3082 these bits are at 11..9 (shifted left) */
1721 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 1721 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1722 1722
1723 skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, 1723 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1724 ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR) 1724 ((gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
1725 1725
1726 & ~PHY_M_FELP_LED1_MSK) 1726 & ~PHY_M_FELP_LED1_MSK)
1727 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL))); 1727 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
@@ -1735,7 +1735,7 @@ static void yukon_init(struct skge_hw *hw, int port)
1735 1735
1736 /* disable blink mode (LED_DUPLEX) on collisions */ 1736 /* disable blink mode (LED_DUPLEX) on collisions */
1737 ctrl |= PHY_M_LEDC_DP_CTRL; 1737 ctrl |= PHY_M_LEDC_DP_CTRL;
1738 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 1738 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1739 1739
1740 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) { 1740 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1741 /* turn on 100 Mbps LED (LED_LINK100) */ 1741 /* turn on 100 Mbps LED (LED_LINK100) */
@@ -1743,25 +1743,25 @@ static void yukon_init(struct skge_hw *hw, int port)
1743 } 1743 }
1744 1744
1745 if (ledover) 1745 if (ledover)
1746 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 1746 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1747 1747
1748 /* Enable phy interrupt on autonegotiation complete (or link up) */ 1748 /* Enable phy interrupt on autonegotiation complete (or link up) */
1749 if (skge->autoneg == AUTONEG_ENABLE) 1749 if (skge->autoneg == AUTONEG_ENABLE)
1750 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 1750 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1751 else 1751 else
1752 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1752 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1753} 1753}
1754 1754
1755static void yukon_reset(struct skge_hw *hw, int port) 1755static void yukon_reset(struct skge_hw *hw, int port)
1756{ 1756{
1757 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 1757 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1758 skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 1758 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1759 skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0); 1759 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1760 skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0); 1760 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1761 skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0); 1761 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1762 1762
1763 skge_gma_write16(hw, port, GM_RX_CTRL, 1763 gma_write16(hw, port, GM_RX_CTRL,
1764 skge_gma_read16(hw, port, GM_RX_CTRL) 1764 gma_read16(hw, port, GM_RX_CTRL)
1765 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 1765 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1766} 1766}
1767 1767
@@ -1779,8 +1779,8 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1779 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); 1779 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1780 1780
1781 /* hard reset */ 1781 /* hard reset */
1782 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET); 1782 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1783 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET); 1783 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1784 1784
1785 /* WA code for COMA mode -- clear PHY reset */ 1785 /* WA code for COMA mode -- clear PHY reset */
1786 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1786 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
@@ -1795,13 +1795,13 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1795 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 1795 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1796 1796
1797 /* Clear GMC reset */ 1797 /* Clear GMC reset */
1798 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 1798 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1799 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 1799 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1800 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 1800 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1801 if (skge->autoneg == AUTONEG_DISABLE) { 1801 if (skge->autoneg == AUTONEG_DISABLE) {
1802 reg = GM_GPCR_AU_ALL_DIS; 1802 reg = GM_GPCR_AU_ALL_DIS;
1803 skge_gma_write16(hw, port, GM_GP_CTRL, 1803 gma_write16(hw, port, GM_GP_CTRL,
1804 skge_gma_read16(hw, port, GM_GP_CTRL) | reg); 1804 gma_read16(hw, port, GM_GP_CTRL) | reg);
1805 1805
1806 switch (skge->speed) { 1806 switch (skge->speed) {
1807 case SPEED_1000: 1807 case SPEED_1000:
@@ -1817,7 +1817,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1817 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 1817 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1818 switch (skge->flow_control) { 1818 switch (skge->flow_control) {
1819 case FLOW_MODE_NONE: 1819 case FLOW_MODE_NONE:
1820 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1820 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1821 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 1821 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1822 break; 1822 break;
1823 case FLOW_MODE_LOC_SEND: 1823 case FLOW_MODE_LOC_SEND:
@@ -1825,7 +1825,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1825 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 1825 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1826 } 1826 }
1827 1827
1828 skge_gma_write16(hw, port, GM_GP_CTRL, reg); 1828 gma_write16(hw, port, GM_GP_CTRL, reg);
1829 skge_read16(hw, GMAC_IRQ_SRC); 1829 skge_read16(hw, GMAC_IRQ_SRC);
1830 1830
1831 spin_lock_bh(&hw->phy_lock); 1831 spin_lock_bh(&hw->phy_lock);
@@ -1833,25 +1833,25 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1833 spin_unlock_bh(&hw->phy_lock); 1833 spin_unlock_bh(&hw->phy_lock);
1834 1834
1835 /* MIB clear */ 1835 /* MIB clear */
1836 reg = skge_gma_read16(hw, port, GM_PHY_ADDR); 1836 reg = gma_read16(hw, port, GM_PHY_ADDR);
1837 skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 1837 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1838 1838
1839 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 1839 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1840 skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 1840 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1841 skge_gma_write16(hw, port, GM_PHY_ADDR, reg); 1841 gma_write16(hw, port, GM_PHY_ADDR, reg);
1842 1842
1843 /* transmit control */ 1843 /* transmit control */
1844 skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 1844 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1845 1845
1846 /* receive control reg: unicast + multicast + no FCS */ 1846 /* receive control reg: unicast + multicast + no FCS */
1847 skge_gma_write16(hw, port, GM_RX_CTRL, 1847 gma_write16(hw, port, GM_RX_CTRL,
1848 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 1848 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1849 1849
1850 /* transmit flow control */ 1850 /* transmit flow control */
1851 skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 1851 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1852 1852
1853 /* transmit parameter */ 1853 /* transmit parameter */
1854 skge_gma_write16(hw, port, GM_TX_PARAM, 1854 gma_write16(hw, port, GM_TX_PARAM,
1855 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 1855 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1856 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 1856 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1857 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 1857 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
@@ -1861,33 +1861,33 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
1861 if (hw->dev[port]->mtu > 1500) 1861 if (hw->dev[port]->mtu > 1500)
1862 reg |= GM_SMOD_JUMBO_ENA; 1862 reg |= GM_SMOD_JUMBO_ENA;
1863 1863
1864 skge_gma_write16(hw, port, GM_SERIAL_MODE, reg); 1864 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1865 1865
1866 /* physical address: used for pause frames */ 1866 /* physical address: used for pause frames */
1867 skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 1867 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1868 /* virtual address for data */ 1868 /* virtual address for data */
1869 skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 1869 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1870 1870
1871 /* enable interrupt mask for counter overflows */ 1871 /* enable interrupt mask for counter overflows */
1872 skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 1872 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1873 skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 1873 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1874 skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 1874 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1875 1875
1876 /* Initialize Mac Fifo */ 1876 /* Initialize Mac Fifo */
1877 1877
1878 /* Configure Rx MAC FIFO */ 1878 /* Configure Rx MAC FIFO */
1879 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 1879 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1880 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 1880 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1881 if (hw->chip_id == CHIP_ID_YUKON_LITE && 1881 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1882 chip_rev(hw) == CHIP_REV_YU_LITE_A3) 1882 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1883 reg &= ~GMF_RX_F_FL_ON; 1883 reg &= ~GMF_RX_F_FL_ON;
1884 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 1884 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1885 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg); 1885 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1886 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); 1886 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1887 1887
1888 /* Configure Tx MAC FIFO */ 1888 /* Configure Tx MAC FIFO */
1889 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1889 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1890 skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1890 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1891} 1891}
1892 1892
1893static void yukon_stop(struct skge_port *skge) 1893static void yukon_stop(struct skge_port *skge)
@@ -1901,14 +1901,14 @@ static void yukon_stop(struct skge_port *skge)
1901 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); 1901 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1902 } 1902 }
1903 1903
1904 skge_gma_write16(hw, port, GM_GP_CTRL, 1904 gma_write16(hw, port, GM_GP_CTRL,
1905 skge_gma_read16(hw, port, GM_GP_CTRL) 1905 gma_read16(hw, port, GM_GP_CTRL)
1906 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA)); 1906 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1907 skge_gma_read16(hw, port, GM_GP_CTRL); 1907 gma_read16(hw, port, GM_GP_CTRL);
1908 1908
1909 /* set GPHY Control reset */ 1909 /* set GPHY Control reset */
1910 skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET); 1910 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1911 skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET); 1911 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1912} 1912}
1913 1913
1914static void yukon_get_stats(struct skge_port *skge, u64 *data) 1914static void yukon_get_stats(struct skge_port *skge, u64 *data)
@@ -1917,29 +1917,29 @@ static void yukon_get_stats(struct skge_port *skge, u64 *data)
1917 int port = skge->port; 1917 int port = skge->port;
1918 int i; 1918 int i;
1919 1919
1920 data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32 1920 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1921 | skge_gma_read32(hw, port, GM_TXO_OK_LO); 1921 | gma_read32(hw, port, GM_TXO_OK_LO);
1922 data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32 1922 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1923 | skge_gma_read32(hw, port, GM_RXO_OK_LO); 1923 | gma_read32(hw, port, GM_RXO_OK_LO);
1924 1924
1925 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1925 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1926 data[i] = skge_gma_read32(hw, port, 1926 data[i] = gma_read32(hw, port,
1927 skge_stats[i].gma_offset); 1927 skge_stats[i].gma_offset);
1928} 1928}
1929 1929
1930static void yukon_mac_intr(struct skge_hw *hw, int port) 1930static void yukon_mac_intr(struct skge_hw *hw, int port)
1931{ 1931{
1932 struct skge_port *skge = netdev_priv(hw->dev[port]); 1932 struct skge_port *skge = netdev_priv(hw->dev[port]);
1933 u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC)); 1933 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1934 1934
1935 pr_debug("yukon_intr status %x\n", status); 1935 pr_debug("yukon_intr status %x\n", status);
1936 if (status & GM_IS_RX_FF_OR) { 1936 if (status & GM_IS_RX_FF_OR) {
1937 ++skge->net_stats.rx_fifo_errors; 1937 ++skge->net_stats.rx_fifo_errors;
1938 skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO); 1938 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1939 } 1939 }
1940 if (status & GM_IS_TX_FF_UR) { 1940 if (status & GM_IS_TX_FF_UR) {
1941 ++skge->net_stats.tx_fifo_errors; 1941 ++skge->net_stats.tx_fifo_errors;
1942 skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU); 1942 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1943 } 1943 }
1944 1944
1945} 1945}
@@ -1970,15 +1970,15 @@ static void yukon_link_up(struct skge_port *skge)
1970 /* Enable Transmit FIFO Underrun */ 1970 /* Enable Transmit FIFO Underrun */
1971 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK); 1971 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1972 1972
1973 reg = skge_gma_read16(hw, port, GM_GP_CTRL); 1973 reg = gma_read16(hw, port, GM_GP_CTRL);
1974 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 1974 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1975 reg |= GM_GPCR_DUP_FULL; 1975 reg |= GM_GPCR_DUP_FULL;
1976 1976
1977 /* enable Rx/Tx */ 1977 /* enable Rx/Tx */
1978 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 1978 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1979 skge_gma_write16(hw, port, GM_GP_CTRL, reg); 1979 gma_write16(hw, port, GM_GP_CTRL, reg);
1980 1980
1981 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 1981 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1982 skge_link_up(skge); 1982 skge_link_up(skge);
1983} 1983}
1984 1984
@@ -1988,16 +1988,16 @@ static void yukon_link_down(struct skge_port *skge)
1988 int port = skge->port; 1988 int port = skge->port;
1989 1989
1990 pr_debug("yukon_link_down\n"); 1990 pr_debug("yukon_link_down\n");
1991 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 1991 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1992 skge_gm_phy_write(hw, port, GM_GP_CTRL, 1992 gm_phy_write(hw, port, GM_GP_CTRL,
1993 skge_gm_phy_read(hw, port, GM_GP_CTRL) 1993 gm_phy_read(hw, port, GM_GP_CTRL)
1994 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); 1994 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1995 1995
1996 if (hw->chip_id != CHIP_ID_YUKON_FE && 1996 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1997 skge->flow_control == FLOW_MODE_REM_SEND) { 1997 skge->flow_control == FLOW_MODE_REM_SEND) {
1998 /* restore Asymmetric Pause bit */ 1998 /* restore Asymmetric Pause bit */
1999 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 1999 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2000 skge_gm_phy_read(hw, port, 2000 gm_phy_read(hw, port,
2001 PHY_MARV_AUNE_ADV) 2001 PHY_MARV_AUNE_ADV)
2002 | PHY_M_AN_ASP); 2002 | PHY_M_AN_ASP);
2003 2003
@@ -2016,19 +2016,19 @@ static void yukon_phy_intr(struct skge_port *skge)
2016 const char *reason = NULL; 2016 const char *reason = NULL;
2017 u16 istatus, phystat; 2017 u16 istatus, phystat;
2018 2018
2019 istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2019 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2020 phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2020 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2021 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat); 2021 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
2022 2022
2023 if (istatus & PHY_M_IS_AN_COMPL) { 2023 if (istatus & PHY_M_IS_AN_COMPL) {
2024 if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 2024 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2025 & PHY_M_AN_RF) { 2025 & PHY_M_AN_RF) {
2026 reason = "remote fault"; 2026 reason = "remote fault";
2027 goto failed; 2027 goto failed;
2028 } 2028 }
2029 2029
2030 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC) 2030 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
2031 && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT) 2031 && (gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
2032 & PHY_B_1000S_MSF)) { 2032 & PHY_B_1000S_MSF)) {
2033 reason = "master/slave fault"; 2033 reason = "master/slave fault";
2034 goto failed; 2034 goto failed;
@@ -2064,9 +2064,9 @@ static void yukon_phy_intr(struct skge_port *skge)
2064 2064
2065 if (skge->flow_control == FLOW_MODE_NONE || 2065 if (skge->flow_control == FLOW_MODE_NONE ||
2066 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 2066 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2067 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2067 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2068 else 2068 else
2069 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2069 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2070 yukon_link_up(skge); 2070 yukon_link_up(skge);
2071 return; 2071 return;
2072 } 2072 }
@@ -2229,12 +2229,12 @@ static int skge_down(struct net_device *dev)
2229 yukon_stop(skge); 2229 yukon_stop(skge);
2230 2230
2231 /* Disable Force Sync bit and Enable Alloc bit */ 2231 /* Disable Force Sync bit and Enable Alloc bit */
2232 skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL), 2232 skge_write8(hw, SK_REG(port, TXA_CTRL),
2233 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2233 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2234 2234
2235 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2235 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2236 skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L); 2236 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2237 skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L); 2237 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2238 2238
2239 /* Reset PCI FIFO */ 2239 /* Reset PCI FIFO */
2240 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 2240 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
@@ -2249,13 +2249,13 @@ static int skge_down(struct net_device *dev)
2249 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 2249 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2250 2250
2251 if (hw->chip_id == CHIP_ID_GENESIS) { 2251 if (hw->chip_id == CHIP_ID_GENESIS) {
2252 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2252 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2253 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2253 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2254 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP); 2254 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2255 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP); 2255 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
2256 } else { 2256 } else {
2257 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2257 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2258 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2258 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2259 } 2259 }
2260 2260
2261 /* turn off led's */ 2261 /* turn off led's */
@@ -2451,7 +2451,7 @@ static void genesis_set_multicast(struct net_device *dev)
2451 u32 mode; 2451 u32 mode;
2452 u8 filter[8]; 2452 u8 filter[8];
2453 2453
2454 mode = skge_xm_read32(hw, port, XM_MODE); 2454 mode = xm_read32(hw, port, XM_MODE);
2455 mode |= XM_MD_ENA_HASH; 2455 mode |= XM_MD_ENA_HASH;
2456 if (dev->flags & IFF_PROMISC) 2456 if (dev->flags & IFF_PROMISC)
2457 mode |= XM_MD_ENA_PROM; 2457 mode |= XM_MD_ENA_PROM;
@@ -2470,9 +2470,9 @@ static void genesis_set_multicast(struct net_device *dev)
2470 } 2470 }
2471 } 2471 }
2472 2472
2473 skge_xm_outhash(hw, port, XM_HSM, filter); 2473 xm_outhash(hw, port, XM_HSM, filter);
2474 2474
2475 skge_xm_write32(hw, port, XM_MODE, mode); 2475 xm_write32(hw, port, XM_MODE, mode);
2476} 2476}
2477 2477
2478static void yukon_set_multicast(struct net_device *dev) 2478static void yukon_set_multicast(struct net_device *dev)
@@ -2486,7 +2486,7 @@ static void yukon_set_multicast(struct net_device *dev)
2486 2486
2487 memset(filter, 0, sizeof(filter)); 2487 memset(filter, 0, sizeof(filter));
2488 2488
2489 reg = skge_gma_read16(hw, port, GM_RX_CTRL); 2489 reg = gma_read16(hw, port, GM_RX_CTRL);
2490 reg |= GM_RXCR_UCF_ENA; 2490 reg |= GM_RXCR_UCF_ENA;
2491 2491
2492 if (dev->flags & IFF_PROMISC) /* promiscious */ 2492 if (dev->flags & IFF_PROMISC) /* promiscious */
@@ -2506,16 +2506,16 @@ static void yukon_set_multicast(struct net_device *dev)
2506 } 2506 }
2507 2507
2508 2508
2509 skge_gma_write16(hw, port, GM_MC_ADDR_H1, 2509 gma_write16(hw, port, GM_MC_ADDR_H1,
2510 (u16)filter[0] | ((u16)filter[1] << 8)); 2510 (u16)filter[0] | ((u16)filter[1] << 8));
2511 skge_gma_write16(hw, port, GM_MC_ADDR_H2, 2511 gma_write16(hw, port, GM_MC_ADDR_H2,
2512 (u16)filter[2] | ((u16)filter[3] << 8)); 2512 (u16)filter[2] | ((u16)filter[3] << 8));
2513 skge_gma_write16(hw, port, GM_MC_ADDR_H3, 2513 gma_write16(hw, port, GM_MC_ADDR_H3,
2514 (u16)filter[4] | ((u16)filter[5] << 8)); 2514 (u16)filter[4] | ((u16)filter[5] << 8));
2515 skge_gma_write16(hw, port, GM_MC_ADDR_H4, 2515 gma_write16(hw, port, GM_MC_ADDR_H4,
2516 (u16)filter[6] | ((u16)filter[7] << 8)); 2516 (u16)filter[6] | ((u16)filter[7] << 8));
2517 2517
2518 skge_gma_write16(hw, port, GM_RX_CTRL, reg); 2518 gma_write16(hw, port, GM_RX_CTRL, reg);
2519} 2519}
2520 2520
2521static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 2521static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
@@ -2679,11 +2679,11 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
2679 : (port == 0 ? "(port A)": "(port B")); 2679 : (port == 0 ? "(port A)": "(port B"));
2680 2680
2681 if (hw->chip_id == CHIP_ID_GENESIS) 2681 if (hw->chip_id == CHIP_ID_GENESIS)
2682 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), 2682 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2683 MFF_CLR_PERR); 2683 MFF_CLR_PERR);
2684 else 2684 else
2685 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ 2685 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2686 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), 2686 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2687 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0) 2687 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)
2688 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 2688 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2689} 2689}
@@ -2715,9 +2715,9 @@ static void skge_error_irq(struct skge_hw *hw)
2715 if (hw->chip_id == CHIP_ID_GENESIS) { 2715 if (hw->chip_id == CHIP_ID_GENESIS) {
2716 /* clear xmac errors */ 2716 /* clear xmac errors */
2717 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 2717 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2718 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT); 2718 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2719 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) 2719 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2720 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT); 2720 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2721 } else { 2721 } else {
2722 /* Timestamp (unused) overflow */ 2722 /* Timestamp (unused) overflow */
2723 if (hwstatus & IS_IRQ_TIST_OV) 2723 if (hwstatus & IS_IRQ_TIST_OV)
@@ -3000,8 +3000,8 @@ static int skge_reset(struct skge_hw *hw)
3000 skge_write8(hw, B0_POWER_CTRL, 3000 skge_write8(hw, B0_POWER_CTRL,
3001 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 3001 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3002 for (i = 0; i < ports; i++) { 3002 for (i = 0; i < ports; i++) {
3003 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3003 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3004 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3004 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3005 } 3005 }
3006 } 3006 }
3007 3007
@@ -3012,7 +3012,7 @@ static int skge_reset(struct skge_hw *hw)
3012 3012
3013 /* enable the Tx Arbiters */ 3013 /* enable the Tx Arbiters */
3014 for (i = 0; i < ports; i++) 3014 for (i = 0; i < ports; i++)
3015 skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB); 3015 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3016 3016
3017 /* Initialize ram interface */ 3017 /* Initialize ram interface */
3018 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 3018 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index aad3aece30b5..2669b80b2de8 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -488,7 +488,7 @@ enum {
488 PA_ENA_TO_TX1 | PA_ENA_TO_TX2) 488 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
489 489
490 490
491/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 491/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
492/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 492/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
493/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 493/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
494/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 494/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
@@ -511,7 +511,7 @@ enum {
511/* 511/*
512 * Bank 4 - 5 512 * Bank 4 - 5
513 */ 513 */
514/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 514/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
515enum { 515enum {
516 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 516 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
517 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 517 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
@@ -2892,114 +2892,87 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2892} 2892}
2893 2893
2894/* MAC Related Registers inside the device. */ 2894/* MAC Related Registers inside the device. */
2895#define SKGEMAC_REG(port,reg) (((port)<<7)+(reg)) 2895#define SK_REG(port,reg) (((port)<<7)+(reg))
2896 2896#define SK_XMAC_REG(port, reg) \
2897/* PCI config space can be accessed via memory mapped space */
2898#define SKGEPCI_REG(reg) ((reg)+ 0x380)
2899
2900#define SKGEXM_REG(port, reg) \
2901 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1) 2897 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2902 2898
2903static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg) 2899static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2904{
2905 return skge_read32(hw, SKGEXM_REG(port,reg));
2906}
2907
2908static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
2909{
2910 return skge_read16(hw, SKGEXM_REG(port,reg));
2911}
2912
2913static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg)
2914{ 2900{
2915 return skge_read8(hw, SKGEXM_REG(port,reg)); 2901 u32 v;
2902 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2903 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2904 return v;
2916} 2905}
2917 2906
2918static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v) 2907static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2919{ 2908{
2920 skge_write32(hw, SKGEXM_REG(port,r), v); 2909 return skge_read16(hw, SK_XMAC_REG(port,reg));
2921} 2910}
2922 2911
2923static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v) 2912static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2924{ 2913{
2925 skge_write16(hw, SKGEXM_REG(port,r), v); 2914 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2915 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2926} 2916}
2927 2917
2928static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v) 2918static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2929{ 2919{
2930 skge_write8(hw, SKGEXM_REG(port,r), v); 2920 skge_write16(hw, SK_XMAC_REG(port,r), v);
2931} 2921}
2932 2922
2933static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg, 2923static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2934 const u8 *hash) 2924 const u8 *hash)
2935{ 2925{
2936 skge_xm_write16(hw, port, reg, 2926 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2937 (u16)hash[0] | ((u16)hash[1] << 8)); 2927 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2938 skge_xm_write16(hw, port, reg+2, 2928 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2939 (u16)hash[2] | ((u16)hash[3] << 8)); 2929 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2940 skge_xm_write16(hw, port, reg+4,
2941 (u16)hash[4] | ((u16)hash[5] << 8));
2942 skge_xm_write16(hw, port, reg+6,
2943 (u16)hash[6] | ((u16)hash[7] << 8));
2944} 2930}
2945 2931
2946static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg, 2932static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2947 const u8 *addr) 2933 const u8 *addr)
2948{ 2934{
2949 skge_xm_write16(hw, port, reg, 2935 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2950 (u16)addr[0] | ((u16)addr[1] << 8)); 2936 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2951 skge_xm_write16(hw, port, reg, 2937 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2952 (u16)addr[2] | ((u16)addr[3] << 8));
2953 skge_xm_write16(hw, port, reg,
2954 (u16)addr[4] | ((u16)addr[5] << 8));
2955} 2938}
2956 2939
2940#define SK_GMAC_REG(port,reg) \
2941 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2957 2942
2958#define SKGEGMA_REG(port,reg) \ 2943static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2959 ((reg) + BASE_GMAC_1 + \
2960 (port) * (BASE_GMAC_2-BASE_GMAC_1))
2961
2962static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
2963{
2964 return skge_read16(hw, SKGEGMA_REG(port,reg));
2965}
2966
2967static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg)
2968{ 2944{
2969 return (u32) skge_read16(hw, SKGEGMA_REG(port,reg)) 2945 return skge_read16(hw, SK_GMAC_REG(port,reg));
2970 | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16);
2971} 2946}
2972 2947
2973static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg) 2948static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2974{ 2949{
2975 return skge_read8(hw, SKGEGMA_REG(port,reg)); 2950 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2951 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2976} 2952}
2977 2953
2978static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v) 2954static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2979{ 2955{
2980 skge_write16(hw, SKGEGMA_REG(port,r), v); 2956 skge_write16(hw, SK_GMAC_REG(port,r), v);
2981} 2957}
2982 2958
2983static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v) 2959static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
2984{ 2960{
2985 skge_write16(hw, SKGEGMA_REG(port, r), (u16) v); 2961 skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
2986 skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16)); 2962 skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
2987} 2963}
2988 2964
2989static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v) 2965static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
2990{ 2966{
2991 skge_write8(hw, SKGEGMA_REG(port,r), v); 2967 skge_write8(hw, SK_GMAC_REG(port,r), v);
2992} 2968}
2993 2969
2994static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg, 2970static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2995 const u8 *addr) 2971 const u8 *addr)
2996{ 2972{
2997 skge_gma_write16(hw, port, reg, 2973 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2998 (u16) addr[0] | ((u16) addr[1] << 8)); 2974 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2999 skge_gma_write16(hw, port, reg+4, 2975 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
3000 (u16) addr[2] | ((u16) addr[3] << 8));
3001 skge_gma_write16(hw, port, reg+8,
3002 (u16) addr[4] | ((u16) addr[5] << 8));
3003} 2976}
3004 2977
3005#endif 2978#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 07:33:07 -0500