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-rw-r--r--Documentation/feature-removal-schedule.txt9
-rw-r--r--arch/mips/Kconfig21
-rw-r--r--arch/mips/Makefile6
-rw-r--r--arch/mips/configs/atlas_defconfig1
-rw-r--r--arch/mips/configs/bigsur_defconfig1
-rw-r--r--arch/mips/configs/capcella_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig1
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/ddb5476_defconfig916
-rw-r--r--arch/mips/configs/ddb5477_defconfig1
-rw-r--r--arch/mips/configs/decstation_defconfig1
-rw-r--r--arch/mips/configs/e55_defconfig1
-rw-r--r--arch/mips/configs/ev64120_defconfig1
-rw-r--r--arch/mips/configs/ev96100_defconfig1
-rw-r--r--arch/mips/configs/ip22_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/ip32_defconfig1
-rw-r--r--arch/mips/configs/it8172_defconfig1
-rw-r--r--arch/mips/configs/ivr_defconfig1
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig1
-rw-r--r--arch/mips/configs/jmr3927_defconfig1
-rw-r--r--arch/mips/configs/lasat200_defconfig1
-rw-r--r--arch/mips/configs/malta_defconfig1
-rw-r--r--arch/mips/configs/mipssim_defconfig1
-rw-r--r--arch/mips/configs/mpc30x_defconfig1
-rw-r--r--arch/mips/configs/ocelot_3_defconfig1
-rw-r--r--arch/mips/configs/ocelot_c_defconfig1
-rw-r--r--arch/mips/configs/ocelot_defconfig1
-rw-r--r--arch/mips/configs/ocelot_g_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-v2pci_defconfig1
-rw-r--r--arch/mips/configs/qemu_defconfig1
-rw-r--r--arch/mips/configs/rbhma4500_defconfig1
-rw-r--r--arch/mips/configs/rm200_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/configs/sead_defconfig1
-rw-r--r--arch/mips/configs/tb0226_defconfig1
-rw-r--r--arch/mips/configs/tb0229_defconfig1
-rw-r--r--arch/mips/configs/tb0287_defconfig1
-rw-r--r--arch/mips/configs/workpad_defconfig1
-rw-r--r--arch/mips/configs/wrppmc_defconfig1
-rw-r--r--arch/mips/configs/yosemite_defconfig1
-rw-r--r--arch/mips/ddb5xxx/common/prom.c5
-rw-r--r--arch/mips/ddb5xxx/ddb5476/Makefile9
-rw-r--r--arch/mips/ddb5xxx/ddb5476/dbg_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5476/irq.c165
-rw-r--r--arch/mips/ddb5xxx/ddb5476/nile4_pic.c190
-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c321
-rw-r--r--arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c109
-rw-r--r--arch/mips/defconfig1
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/ops-ddb5476.c286
-rw-r--r--arch/mips/pci/pci-ddb5476.c93
-rw-r--r--drivers/net/tulip/tulip_core.c8
-rw-r--r--include/asm-mips/ddb5xxx/ddb5476.h157
-rw-r--r--include/asm-mips/ddb5xxx/ddb5xxx.h4
63 files changed, 2 insertions, 2480 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 8fa7a384f250..f50cf8fac3f0 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -212,15 +212,6 @@ Who: Greg Kroah-Hartman <gregkh@suse.de>
212 212
213--------------------------- 213---------------------------
214 214
215What: Support for NEC DDB5476 evaluation boards.
216When: June 2006
217Why: Board specific code doesn't build anymore since ~2.6.0 and no
218 users have complained indicating there is no more need for these
219 boards. This should really be considered a last call.
220Who: Ralf Baechle <ralf@linux-mips.org>
221
222---------------------------
223
224What: USB driver API moves to EXPORT_SYMBOL_GPL 215What: USB driver API moves to EXPORT_SYMBOL_GPL
225When: Febuary 2008 216When: Febuary 2008
226Files: include/linux/usb.h, drivers/usb/core/driver.c 217Files: include/linux/usb.h, drivers/usb/core/driver.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c3c8e7a15af3..138aac48d5d4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -469,27 +469,6 @@ config PNX8550_JBS
469 select PNX8550 469 select PNX8550
470 select SYS_SUPPORTS_LITTLE_ENDIAN 470 select SYS_SUPPORTS_LITTLE_ENDIAN
471 471
472config DDB5476
473 bool "NEC DDB Vrc-5476"
474 select DDB5XXX_COMMON
475 select DMA_NONCOHERENT
476 select HAVE_STD_PC_SERIAL_PORT
477 select HW_HAS_PCI
478 select IRQ_CPU
479 select I8259
480 select ISA
481 select SYS_HAS_CPU_R5432
482 select SYS_SUPPORTS_32BIT_KERNEL
483 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
484 select SYS_SUPPORTS_LITTLE_ENDIAN
485 help
486 This enables support for the R5432-based NEC DDB Vrc-5476
487 evaluation board.
488
489 Features : kernel debugging, serial terminal, NFS root fs, on-board
490 ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
491 IDE controller, PS2 keyboard, PS2 mouse, etc.
492
493config DDB5477 472config DDB5477
494 bool "NEC DDB Vrc-5477" 473 bool "NEC DDB Vrc-5477"
495 select DDB5XXX_COMMON 474 select DDB5XXX_COMMON
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8d1026cd0738..e0cab2850a72 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -404,12 +404,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
404core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ 404core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
405 405
406# 406#
407# NEC DDB Vrc-5476
408#
409core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/
410load-$(CONFIG_DDB5476) += 0xffffffff80080000
411
412#
413# NEC DDB Vrc-5477 407# NEC DDB Vrc-5477
414# 408#
415core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ 409core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 7b6de36e5b74..d72acc84c481 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_ATLAS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 633cafe20418..4677cbbc2b46 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index bd150ec8559f..4e1937bffc80 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index ad83025420ec..7ac532070c42 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_COBALT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index ba3c7b9464bf..0efaf64ca27d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1000=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 321a4d00ce94..7b7a2de63495 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 97471008f3ae..53da5d81d2d9 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1200=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index fbcc1738ff90..408af0e2c2aa 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1500=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index d014cdd3e705..f8db553dfb41 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1550=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig
deleted file mode 100644
index 90cabf5419ad..000000000000
--- a/arch/mips/configs/ddb5476_defconfig
+++ /dev/null
@@ -1,916 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc2
4# Mon Apr 24 14:51:00 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_MIPS_COBALT is not set
25# CONFIG_MACH_DECSTATION is not set
26# CONFIG_MIPS_EV64120 is not set
27# CONFIG_MIPS_EV96100 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set
44CONFIG_DDB5476=y
45# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM200_PCI is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65CONFIG_RWSEM_GENERIC_SPINLOCK=y
66CONFIG_GENERIC_FIND_NEXT_BIT=y
67CONFIG_GENERIC_HWEIGHT=y
68CONFIG_GENERIC_CALIBRATE_DELAY=y
69CONFIG_DMA_NONCOHERENT=y
70CONFIG_DMA_NEED_PCI_MAP_STATE=y
71CONFIG_I8259=y
72# CONFIG_CPU_BIG_ENDIAN is not set
73CONFIG_CPU_LITTLE_ENDIAN=y
74CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
75CONFIG_IRQ_CPU=y
76CONFIG_DDB5XXX_COMMON=y
77CONFIG_MIPS_L1_CACHE_SHIFT=5
78CONFIG_HAVE_STD_PC_SERIAL_PORT=y
79
80#
81# CPU selection
82#
83# CONFIG_CPU_MIPS32_R1 is not set
84# CONFIG_CPU_MIPS32_R2 is not set
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94CONFIG_CPU_R5432=y
95# CONFIG_CPU_R6000 is not set
96# CONFIG_CPU_NEVADA is not set
97# CONFIG_CPU_R8000 is not set
98# CONFIG_CPU_R10000 is not set
99# CONFIG_CPU_RM7000 is not set
100# CONFIG_CPU_RM9000 is not set
101# CONFIG_CPU_SB1 is not set
102CONFIG_SYS_HAS_CPU_R5432=y
103CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
104CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
107
108#
109# Kernel type
110#
111CONFIG_32BIT=y
112# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set
117# CONFIG_MIPS_MT is not set
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y
122CONFIG_ARCH_FLATMEM_ENABLE=y
123CONFIG_SELECT_MEMORY_MODEL=y
124CONFIG_FLATMEM_MANUAL=y
125# CONFIG_DISCONTIGMEM_MANUAL is not set
126# CONFIG_SPARSEMEM_MANUAL is not set
127CONFIG_FLATMEM=y
128CONFIG_FLAT_NODE_MEM_MAP=y
129# CONFIG_SPARSEMEM_STATIC is not set
130CONFIG_SPLIT_PTLOCK_CPUS=4
131CONFIG_PREEMPT_NONE=y
132# CONFIG_PREEMPT_VOLUNTARY is not set
133# CONFIG_PREEMPT is not set
134
135#
136# Code maturity level options
137#
138CONFIG_EXPERIMENTAL=y
139CONFIG_BROKEN_ON_SMP=y
140CONFIG_INIT_ENV_ARG_LIMIT=32
141
142#
143# General setup
144#
145CONFIG_LOCALVERSION=""
146CONFIG_LOCALVERSION_AUTO=y
147CONFIG_SWAP=y
148CONFIG_SYSVIPC=y
149# CONFIG_POSIX_MQUEUE is not set
150# CONFIG_BSD_PROCESS_ACCT is not set
151CONFIG_SYSCTL=y
152# CONFIG_AUDIT is not set
153# CONFIG_IKCONFIG is not set
154CONFIG_RELAY=y
155CONFIG_INITRAMFS_SOURCE=""
156# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
157CONFIG_EMBEDDED=y
158CONFIG_KALLSYMS=y
159# CONFIG_KALLSYMS_EXTRA_PASS is not set
160CONFIG_HOTPLUG=y
161CONFIG_PRINTK=y
162CONFIG_BUG=y
163CONFIG_ELF_CORE=y
164CONFIG_BASE_FULL=y
165CONFIG_FUTEX=y
166CONFIG_EPOLL=y
167CONFIG_SHMEM=y
168CONFIG_SLAB=y
169# CONFIG_TINY_SHMEM is not set
170CONFIG_BASE_SMALL=0
171# CONFIG_SLOB is not set
172
173#
174# Loadable module support
175#
176# CONFIG_MODULES is not set
177
178#
179# Block layer
180#
181# CONFIG_LBD is not set
182# CONFIG_BLK_DEV_IO_TRACE is not set
183# CONFIG_LSF is not set
184
185#
186# IO Schedulers
187#
188CONFIG_IOSCHED_NOOP=y
189CONFIG_IOSCHED_AS=y
190CONFIG_IOSCHED_DEADLINE=y
191CONFIG_IOSCHED_CFQ=y
192CONFIG_DEFAULT_AS=y
193# CONFIG_DEFAULT_DEADLINE is not set
194# CONFIG_DEFAULT_CFQ is not set
195# CONFIG_DEFAULT_NOOP is not set
196CONFIG_DEFAULT_IOSCHED="anticipatory"
197
198#
199# Bus options (PCI, PCMCIA, EISA, ISA, TC)
200#
201CONFIG_HW_HAS_PCI=y
202CONFIG_PCI=y
203CONFIG_ISA=y
204CONFIG_MMU=y
205
206#
207# PCCARD (PCMCIA/CardBus) support
208#
209# CONFIG_PCCARD is not set
210
211#
212# PCI Hotplug Support
213#
214# CONFIG_HOTPLUG_PCI is not set
215
216#
217# Executable file formats
218#
219CONFIG_BINFMT_ELF=y
220# CONFIG_BINFMT_MISC is not set
221CONFIG_TRAD_SIGNALS=y
222
223#
224# Networking
225#
226CONFIG_NET=y
227
228#
229# Networking options
230#
231# CONFIG_NETDEBUG is not set
232CONFIG_PACKET=y
233# CONFIG_PACKET_MMAP is not set
234CONFIG_UNIX=y
235CONFIG_XFRM=y
236CONFIG_XFRM_USER=y
237CONFIG_NET_KEY=y
238CONFIG_INET=y
239# CONFIG_IP_MULTICAST is not set
240# CONFIG_IP_ADVANCED_ROUTER is not set
241CONFIG_IP_FIB_HASH=y
242CONFIG_IP_PNP=y
243# CONFIG_IP_PNP_DHCP is not set
244CONFIG_IP_PNP_BOOTP=y
245# CONFIG_IP_PNP_RARP is not set
246# CONFIG_NET_IPIP is not set
247# CONFIG_NET_IPGRE is not set
248# CONFIG_ARPD is not set
249# CONFIG_SYN_COOKIES is not set
250# CONFIG_INET_AH is not set
251# CONFIG_INET_ESP is not set
252# CONFIG_INET_IPCOMP is not set
253# CONFIG_INET_XFRM_TUNNEL is not set
254# CONFIG_INET_TUNNEL is not set
255CONFIG_INET_DIAG=y
256CONFIG_INET_TCP_DIAG=y
257# CONFIG_TCP_CONG_ADVANCED is not set
258CONFIG_TCP_CONG_BIC=y
259# CONFIG_IPV6 is not set
260# CONFIG_INET6_XFRM_TUNNEL is not set
261# CONFIG_INET6_TUNNEL is not set
262# CONFIG_NETFILTER is not set
263
264#
265# DCCP Configuration (EXPERIMENTAL)
266#
267# CONFIG_IP_DCCP is not set
268
269#
270# SCTP Configuration (EXPERIMENTAL)
271#
272# CONFIG_IP_SCTP is not set
273
274#
275# TIPC Configuration (EXPERIMENTAL)
276#
277# CONFIG_TIPC is not set
278# CONFIG_ATM is not set
279# CONFIG_BRIDGE is not set
280# CONFIG_VLAN_8021Q is not set
281# CONFIG_DECNET is not set
282# CONFIG_LLC2 is not set
283# CONFIG_IPX is not set
284# CONFIG_ATALK is not set
285# CONFIG_X25 is not set
286# CONFIG_LAPB is not set
287# CONFIG_NET_DIVERT is not set
288# CONFIG_ECONET is not set
289# CONFIG_WAN_ROUTER is not set
290
291#
292# QoS and/or fair queueing
293#
294# CONFIG_NET_SCHED is not set
295
296#
297# Network testing
298#
299# CONFIG_NET_PKTGEN is not set
300# CONFIG_HAMRADIO is not set
301# CONFIG_IRDA is not set
302# CONFIG_BT is not set
303CONFIG_IEEE80211=y
304# CONFIG_IEEE80211_DEBUG is not set
305CONFIG_IEEE80211_CRYPT_WEP=y
306CONFIG_IEEE80211_CRYPT_CCMP=y
307CONFIG_IEEE80211_SOFTMAC=y
308# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
309CONFIG_WIRELESS_EXT=y
310
311#
312# Device Drivers
313#
314
315#
316# Generic Driver Options
317#
318CONFIG_STANDALONE=y
319CONFIG_PREVENT_FIRMWARE_BUILD=y
320CONFIG_FW_LOADER=y
321
322#
323# Connector - unified userspace <-> kernelspace linker
324#
325CONFIG_CONNECTOR=y
326CONFIG_PROC_EVENTS=y
327
328#
329# Memory Technology Devices (MTD)
330#
331# CONFIG_MTD is not set
332
333#
334# Parallel port support
335#
336# CONFIG_PARPORT is not set
337
338#
339# Plug and Play support
340#
341# CONFIG_PNP is not set
342
343#
344# Block devices
345#
346# CONFIG_BLK_CPQ_DA is not set
347# CONFIG_BLK_CPQ_CISS_DA is not set
348# CONFIG_BLK_DEV_DAC960 is not set
349# CONFIG_BLK_DEV_UMEM is not set
350# CONFIG_BLK_DEV_COW_COMMON is not set
351# CONFIG_BLK_DEV_LOOP is not set
352# CONFIG_BLK_DEV_NBD is not set
353# CONFIG_BLK_DEV_SX8 is not set
354# CONFIG_BLK_DEV_RAM is not set
355# CONFIG_BLK_DEV_INITRD is not set
356CONFIG_CDROM_PKTCDVD=y
357CONFIG_CDROM_PKTCDVD_BUFFERS=8
358# CONFIG_CDROM_PKTCDVD_WCACHE is not set
359CONFIG_ATA_OVER_ETH=y
360
361#
362# ATA/ATAPI/MFM/RLL support
363#
364CONFIG_IDE=y
365CONFIG_BLK_DEV_IDE=y
366
367#
368# Please see Documentation/ide.txt for help/info on IDE drives
369#
370# CONFIG_BLK_DEV_IDE_SATA is not set
371CONFIG_BLK_DEV_IDEDISK=y
372# CONFIG_IDEDISK_MULTI_MODE is not set
373# CONFIG_BLK_DEV_IDECD is not set
374# CONFIG_BLK_DEV_IDETAPE is not set
375# CONFIG_BLK_DEV_IDEFLOPPY is not set
376# CONFIG_IDE_TASK_IOCTL is not set
377
378#
379# IDE chipset support/bugfixes
380#
381CONFIG_IDE_GENERIC=y
382# CONFIG_BLK_DEV_IDEPCI is not set
383# CONFIG_IDE_ARM is not set
384# CONFIG_IDE_CHIPSETS is not set
385# CONFIG_BLK_DEV_IDEDMA is not set
386# CONFIG_IDEDMA_AUTO is not set
387# CONFIG_BLK_DEV_HD is not set
388
389#
390# SCSI device support
391#
392CONFIG_RAID_ATTRS=y
393# CONFIG_SCSI is not set
394
395#
396# Old CD-ROM drivers (not SCSI, not IDE)
397#
398# CONFIG_CD_NO_IDESCSI is not set
399
400#
401# Multi-device support (RAID and LVM)
402#
403# CONFIG_MD is not set
404
405#
406# Fusion MPT device support
407#
408# CONFIG_FUSION is not set
409
410#
411# IEEE 1394 (FireWire) support
412#
413# CONFIG_IEEE1394 is not set
414
415#
416# I2O device support
417#
418# CONFIG_I2O is not set
419
420#
421# Network device support
422#
423CONFIG_NETDEVICES=y
424# CONFIG_DUMMY is not set
425# CONFIG_BONDING is not set
426# CONFIG_EQUALIZER is not set
427# CONFIG_TUN is not set
428
429#
430# ARCnet devices
431#
432# CONFIG_ARCNET is not set
433
434#
435# PHY device support
436#
437CONFIG_PHYLIB=y
438
439#
440# MII PHY device drivers
441#
442CONFIG_MARVELL_PHY=y
443CONFIG_DAVICOM_PHY=y
444CONFIG_QSEMI_PHY=y
445CONFIG_LXT_PHY=y
446CONFIG_CICADA_PHY=y
447
448#
449# Ethernet (10 or 100Mbit)
450#
451CONFIG_NET_ETHERNET=y
452# CONFIG_MII is not set
453# CONFIG_HAPPYMEAL is not set
454# CONFIG_SUNGEM is not set
455# CONFIG_CASSINI is not set
456# CONFIG_NET_VENDOR_3COM is not set
457# CONFIG_NET_VENDOR_SMC is not set
458# CONFIG_DM9000 is not set
459# CONFIG_NET_VENDOR_RACAL is not set
460
461#
462# Tulip family network device support
463#
464# CONFIG_NET_TULIP is not set
465# CONFIG_AT1700 is not set
466# CONFIG_DEPCA is not set
467# CONFIG_HP100 is not set
468# CONFIG_NET_ISA is not set
469# CONFIG_NET_PCI is not set
470
471#
472# Ethernet (1000 Mbit)
473#
474# CONFIG_ACENIC is not set
475# CONFIG_DL2K is not set
476# CONFIG_E1000 is not set
477# CONFIG_NS83820 is not set
478# CONFIG_HAMACHI is not set
479# CONFIG_YELLOWFIN is not set
480# CONFIG_R8169 is not set
481# CONFIG_SIS190 is not set
482# CONFIG_SKGE is not set
483# CONFIG_SKY2 is not set
484# CONFIG_SK98LIN is not set
485# CONFIG_TIGON3 is not set
486# CONFIG_BNX2 is not set
487
488#
489# Ethernet (10000 Mbit)
490#
491# CONFIG_CHELSIO_T1 is not set
492# CONFIG_IXGB is not set
493# CONFIG_S2IO is not set
494
495#
496# Token Ring devices
497#
498# CONFIG_TR is not set
499
500#
501# Wireless LAN (non-hamradio)
502#
503# CONFIG_NET_RADIO is not set
504
505#
506# Wan interfaces
507#
508# CONFIG_WAN is not set
509# CONFIG_FDDI is not set
510# CONFIG_HIPPI is not set
511# CONFIG_PPP is not set
512# CONFIG_SLIP is not set
513# CONFIG_SHAPER is not set
514# CONFIG_NETCONSOLE is not set
515# CONFIG_NETPOLL is not set
516# CONFIG_NET_POLL_CONTROLLER is not set
517
518#
519# ISDN subsystem
520#
521# CONFIG_ISDN is not set
522
523#
524# Telephony Support
525#
526# CONFIG_PHONE is not set
527
528#
529# Input device support
530#
531CONFIG_INPUT=y
532
533#
534# Userland interfaces
535#
536CONFIG_INPUT_MOUSEDEV=y
537CONFIG_INPUT_MOUSEDEV_PSAUX=y
538CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
539CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
540# CONFIG_INPUT_JOYDEV is not set
541# CONFIG_INPUT_TSDEV is not set
542# CONFIG_INPUT_EVDEV is not set
543# CONFIG_INPUT_EVBUG is not set
544
545#
546# Input Device Drivers
547#
548# CONFIG_INPUT_KEYBOARD is not set
549# CONFIG_INPUT_MOUSE is not set
550# CONFIG_INPUT_JOYSTICK is not set
551# CONFIG_INPUT_TOUCHSCREEN is not set
552# CONFIG_INPUT_MISC is not set
553
554#
555# Hardware I/O ports
556#
557CONFIG_SERIO=y
558# CONFIG_SERIO_I8042 is not set
559CONFIG_SERIO_SERPORT=y
560# CONFIG_SERIO_PCIPS2 is not set
561# CONFIG_SERIO_LIBPS2 is not set
562CONFIG_SERIO_RAW=y
563# CONFIG_GAMEPORT is not set
564
565#
566# Character devices
567#
568CONFIG_VT=y
569CONFIG_VT_CONSOLE=y
570CONFIG_HW_CONSOLE=y
571# CONFIG_SERIAL_NONSTANDARD is not set
572
573#
574# Serial drivers
575#
576CONFIG_SERIAL_8250=y
577CONFIG_SERIAL_8250_CONSOLE=y
578CONFIG_SERIAL_8250_PCI=y
579CONFIG_SERIAL_8250_NR_UARTS=4
580CONFIG_SERIAL_8250_RUNTIME_UARTS=4
581# CONFIG_SERIAL_8250_EXTENDED is not set
582
583#
584# Non-8250 serial port support
585#
586CONFIG_SERIAL_CORE=y
587CONFIG_SERIAL_CORE_CONSOLE=y
588# CONFIG_SERIAL_JSM is not set
589CONFIG_UNIX98_PTYS=y
590CONFIG_LEGACY_PTYS=y
591CONFIG_LEGACY_PTY_COUNT=256
592
593#
594# IPMI
595#
596# CONFIG_IPMI_HANDLER is not set
597
598#
599# Watchdog Cards
600#
601# CONFIG_WATCHDOG is not set
602# CONFIG_RTC is not set
603# CONFIG_GEN_RTC is not set
604# CONFIG_DTLK is not set
605# CONFIG_R3964 is not set
606# CONFIG_APPLICOM is not set
607
608#
609# Ftape, the floppy tape device driver
610#
611# CONFIG_DRM is not set
612# CONFIG_RAW_DRIVER is not set
613
614#
615# TPM devices
616#
617# CONFIG_TCG_TPM is not set
618# CONFIG_TELCLOCK is not set
619
620#
621# I2C support
622#
623# CONFIG_I2C is not set
624
625#
626# SPI support
627#
628# CONFIG_SPI is not set
629# CONFIG_SPI_MASTER is not set
630
631#
632# Dallas's 1-wire bus
633#
634# CONFIG_W1 is not set
635
636#
637# Hardware Monitoring support
638#
639# CONFIG_HWMON is not set
640# CONFIG_HWMON_VID is not set
641
642#
643# Misc devices
644#
645
646#
647# Multimedia devices
648#
649# CONFIG_VIDEO_DEV is not set
650
651#
652# Digital Video Broadcasting Devices
653#
654# CONFIG_DVB is not set
655
656#
657# Graphics support
658#
659CONFIG_FB=y
660# CONFIG_FB_CFB_FILLRECT is not set
661# CONFIG_FB_CFB_COPYAREA is not set
662# CONFIG_FB_CFB_IMAGEBLIT is not set
663# CONFIG_FB_MACMODES is not set
664CONFIG_FB_FIRMWARE_EDID=y
665# CONFIG_FB_MODE_HELPERS is not set
666# CONFIG_FB_TILEBLITTING is not set
667# CONFIG_FB_CIRRUS is not set
668# CONFIG_FB_PM2 is not set
669# CONFIG_FB_CYBER2000 is not set
670# CONFIG_FB_ASILIANT is not set
671# CONFIG_FB_IMSTT is not set
672# CONFIG_FB_S1D13XXX is not set
673# CONFIG_FB_NVIDIA is not set
674# CONFIG_FB_RIVA is not set
675# CONFIG_FB_MATROX is not set
676# CONFIG_FB_RADEON is not set
677# CONFIG_FB_ATY128 is not set
678# CONFIG_FB_ATY is not set
679# CONFIG_FB_SAVAGE is not set
680# CONFIG_FB_SIS is not set
681# CONFIG_FB_NEOMAGIC is not set
682# CONFIG_FB_KYRO is not set
683# CONFIG_FB_3DFX is not set
684# CONFIG_FB_VOODOO1 is not set
685# CONFIG_FB_SMIVGX is not set
686# CONFIG_FB_TRIDENT is not set
687# CONFIG_FB_VIRTUAL is not set
688
689#
690# Console display driver support
691#
692# CONFIG_VGA_CONSOLE is not set
693# CONFIG_MDA_CONSOLE is not set
694CONFIG_DUMMY_CONSOLE=y
695# CONFIG_FRAMEBUFFER_CONSOLE is not set
696
697#
698# Logo configuration
699#
700# CONFIG_LOGO is not set
701# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
702
703#
704# Sound
705#
706# CONFIG_SOUND is not set
707
708#
709# USB support
710#
711CONFIG_USB_ARCH_HAS_HCD=y
712CONFIG_USB_ARCH_HAS_OHCI=y
713CONFIG_USB_ARCH_HAS_EHCI=y
714# CONFIG_USB is not set
715
716#
717# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
718#
719
720#
721# USB Gadget Support
722#
723# CONFIG_USB_GADGET is not set
724
725#
726# MMC/SD Card support
727#
728# CONFIG_MMC is not set
729
730#
731# LED devices
732#
733# CONFIG_NEW_LEDS is not set
734
735#
736# LED drivers
737#
738
739#
740# LED Triggers
741#
742
743#
744# InfiniBand support
745#
746# CONFIG_INFINIBAND is not set
747
748#
749# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
750#
751
752#
753# Real Time Clock
754#
755# CONFIG_RTC_CLASS is not set
756
757#
758# File systems
759#
760CONFIG_EXT2_FS=y
761# CONFIG_EXT2_FS_XATTR is not set
762# CONFIG_EXT2_FS_XIP is not set
763# CONFIG_EXT3_FS is not set
764# CONFIG_REISERFS_FS is not set
765# CONFIG_JFS_FS is not set
766# CONFIG_FS_POSIX_ACL is not set
767# CONFIG_XFS_FS is not set
768# CONFIG_OCFS2_FS is not set
769# CONFIG_MINIX_FS is not set
770# CONFIG_ROMFS_FS is not set
771CONFIG_INOTIFY=y
772# CONFIG_QUOTA is not set
773CONFIG_DNOTIFY=y
774# CONFIG_AUTOFS_FS is not set
775# CONFIG_AUTOFS4_FS is not set
776CONFIG_FUSE_FS=y
777
778#
779# CD-ROM/DVD Filesystems
780#
781# CONFIG_ISO9660_FS is not set
782# CONFIG_UDF_FS is not set
783
784#
785# DOS/FAT/NT Filesystems
786#
787# CONFIG_MSDOS_FS is not set
788# CONFIG_VFAT_FS is not set
789# CONFIG_NTFS_FS is not set
790
791#
792# Pseudo filesystems
793#
794CONFIG_PROC_FS=y
795CONFIG_PROC_KCORE=y
796CONFIG_SYSFS=y
797# CONFIG_TMPFS is not set
798# CONFIG_HUGETLB_PAGE is not set
799CONFIG_RAMFS=y
800# CONFIG_CONFIGFS_FS is not set
801
802#
803# Miscellaneous filesystems
804#
805# CONFIG_ADFS_FS is not set
806# CONFIG_AFFS_FS is not set
807# CONFIG_HFS_FS is not set
808# CONFIG_HFSPLUS_FS is not set
809# CONFIG_BEFS_FS is not set
810# CONFIG_BFS_FS is not set
811# CONFIG_EFS_FS is not set
812# CONFIG_CRAMFS is not set
813# CONFIG_VXFS_FS is not set
814# CONFIG_HPFS_FS is not set
815# CONFIG_QNX4FS_FS is not set
816# CONFIG_SYSV_FS is not set
817# CONFIG_UFS_FS is not set
818
819#
820# Network File Systems
821#
822CONFIG_NFS_FS=y
823# CONFIG_NFS_V3 is not set
824# CONFIG_NFS_V4 is not set
825# CONFIG_NFS_DIRECTIO is not set
826# CONFIG_NFSD is not set
827CONFIG_ROOT_NFS=y
828CONFIG_LOCKD=y
829CONFIG_NFS_COMMON=y
830CONFIG_SUNRPC=y
831# CONFIG_RPCSEC_GSS_KRB5 is not set
832# CONFIG_RPCSEC_GSS_SPKM3 is not set
833# CONFIG_SMB_FS is not set
834# CONFIG_CIFS is not set
835# CONFIG_NCP_FS is not set
836# CONFIG_CODA_FS is not set
837# CONFIG_AFS_FS is not set
838# CONFIG_9P_FS is not set
839
840#
841# Partition Types
842#
843# CONFIG_PARTITION_ADVANCED is not set
844CONFIG_MSDOS_PARTITION=y
845
846#
847# Native Language Support
848#
849# CONFIG_NLS is not set
850
851#
852# Profiling support
853#
854# CONFIG_PROFILING is not set
855
856#
857# Kernel hacking
858#
859# CONFIG_PRINTK_TIME is not set
860# CONFIG_MAGIC_SYSRQ is not set
861# CONFIG_DEBUG_KERNEL is not set
862CONFIG_LOG_BUF_SHIFT=14
863# CONFIG_DEBUG_FS is not set
864# CONFIG_UNWIND_INFO is not set
865CONFIG_CROSSCOMPILE=y
866CONFIG_CMDLINE="ip=any"
867
868#
869# Security options
870#
871CONFIG_KEYS=y
872CONFIG_KEYS_DEBUG_PROC_KEYS=y
873# CONFIG_SECURITY is not set
874
875#
876# Cryptographic options
877#
878CONFIG_CRYPTO=y
879CONFIG_CRYPTO_HMAC=y
880CONFIG_CRYPTO_NULL=y
881CONFIG_CRYPTO_MD4=y
882CONFIG_CRYPTO_MD5=y
883CONFIG_CRYPTO_SHA1=y
884CONFIG_CRYPTO_SHA256=y
885CONFIG_CRYPTO_SHA512=y
886CONFIG_CRYPTO_WP512=y
887CONFIG_CRYPTO_TGR192=y
888CONFIG_CRYPTO_DES=y
889CONFIG_CRYPTO_BLOWFISH=y
890CONFIG_CRYPTO_TWOFISH=y
891CONFIG_CRYPTO_SERPENT=y
892CONFIG_CRYPTO_AES=y
893CONFIG_CRYPTO_CAST5=y
894CONFIG_CRYPTO_CAST6=y
895CONFIG_CRYPTO_TEA=y
896CONFIG_CRYPTO_ARC4=y
897CONFIG_CRYPTO_KHAZAD=y
898CONFIG_CRYPTO_ANUBIS=y
899CONFIG_CRYPTO_DEFLATE=y
900CONFIG_CRYPTO_MICHAEL_MIC=y
901CONFIG_CRYPTO_CRC32C=y
902# CONFIG_CRYPTO_TEST is not set
903
904#
905# Hardware crypto devices
906#
907
908#
909# Library routines
910#
911# CONFIG_CRC_CCITT is not set
912CONFIG_CRC16=y
913CONFIG_CRC32=y
914CONFIG_LIBCRC32C=y
915CONFIG_ZLIB_INFLATE=y
916CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index fc30ace3d737..6e19990139d7 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45CONFIG_DDB5477=y 44CONFIG_DDB5477=y
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 0775d7364cab..f237754a8a13 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -41,7 +41,6 @@ CONFIG_MACH_DECSTATION=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 8f9de1c3bf1e..b06d9f1e519a 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index b97c90fa5491..46086893674e 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_EV64120=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig
index 708b0d6896d8..63c46ef26d01 100644
--- a/arch/mips/configs/ev96100_defconfig
+++ b/arch/mips/configs/ev96100_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_EV96100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index f7b0beb5752f..f72ba3f1b7f5 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index b4ae9cd15ba3..9ac2acc05ad7 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index a95c2e847f68..826b0183eb49 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
index 87c5cde49e59..e44481f7e487 100644
--- a/arch/mips/configs/it8172_defconfig
+++ b/arch/mips/configs/it8172_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_ITE8172=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
index 1346b683b287..f8722d0ba935 100644
--- a/arch/mips/configs/ivr_defconfig
+++ b/arch/mips/configs/ivr_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_IVR=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index d2d1a7776362..1eeca9fd5b27 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index ba23db03ba95..407d8d71200c 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 7500332c9b5c..48c67d8dd1f1 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -41,7 +41,6 @@ CONFIG_LASAT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 1aac4901c57e..fd1c73f8780b 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_MALTA=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 011120c5033e..67fb9fa10870 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_SIM=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index ca0baa29483c..c9607976d132 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index a8d26596ca8e..af43e464871e 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_3=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index a1d6d7ff93fb..e1a9a9a750ea 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_C=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 4b72b0a2fb4b..09a96619aedf 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index 232f13a41938..9c02f974b882 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_G=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 55da4eb76f7b..d803c16dccb8 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1100=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 348581d91b52..0cb83a181e8d 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1500=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 897f76c0c8ab..c6da473a64d3 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1550=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 6289dfa73f2f..746986db597d 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43CONFIG_PNX8550_JBS=y 43CONFIG_PNX8550_JBS=y
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index d8448fdb2514..6c3c72db4b9e 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42CONFIG_PNX8550_V2PCI=y 42CONFIG_PNX8550_V2PCI=y
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 99c43c9f1595..8c77992ab767 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index c55e8e6ff207..9bb4d94335cc 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 6013c6533ca5..7dd3438b5b1f 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 6b8441e18843..e872b83dddbf 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 94d04f7a5e6b..6048c0d60458 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS_SEAD=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index f84864d8ec33..b6d8e1afa191 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index aeb1e85f9ce7..4875cd38ff80 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 5f1ee08d9851..70392d50074a 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index ebc25edbf73d..cfd6434aa556 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46CONFIG_MACH_VR41XX=y 45CONFIG_MACH_VR41XX=y
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 03c880792163..8c0e636cb322 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -42,7 +42,6 @@ CONFIG_WR_PPMC=y
42# CONFIG_MIPS_XXS1500 is not set 42# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set 43# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set 44# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5476 is not set
46# CONFIG_DDB5477 is not set 45# CONFIG_DDB5477 is not set
47# CONFIG_MACH_VR41XX is not set 46# CONFIG_MACH_VR41XX is not set
48# CONFIG_PMC_YOSEMITE is not set 47# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 1c728f216fbd..eef270834797 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47CONFIG_PMC_YOSEMITE=y 46CONFIG_PMC_YOSEMITE=y
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
index 18eecbcdfca8..00c62c1c28a3 100644
--- a/arch/mips/ddb5xxx/common/prom.c
+++ b/arch/mips/ddb5xxx/common/prom.c
@@ -56,10 +56,7 @@ void __init prom_init(void)
56 56
57 mips_machgroup = MACH_GROUP_NEC_DDB; 57 mips_machgroup = MACH_GROUP_NEC_DDB;
58 58
59#if defined(CONFIG_DDB5476) 59#if defined(CONFIG_DDB5477)
60 mips_machtype = MACH_NEC_DDB5476;
61 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
62#elif defined(CONFIG_DDB5477)
63 ddb5477_runtime_detection(); 60 ddb5477_runtime_detection();
64 add_memory_region(0, board_ram_size, BOOT_MEM_RAM); 61 add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
65#endif 62#endif
diff --git a/arch/mips/ddb5xxx/ddb5476/Makefile b/arch/mips/ddb5xxx/ddb5476/Makefile
deleted file mode 100644
index ab0312cb47b4..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o vrc5476_irq.o
7obj-$(CONFIG_KGDB) += dbg_io.o
8
9EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c
deleted file mode 100644
index f2296a999953..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for DDB5476. We use the second serial port.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xa60002f8
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 1
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up baud rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5476/irq.c b/arch/mips/ddb5xxx/ddb5476/irq.c
deleted file mode 100644
index 7583a1f30711..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/irq.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * Re-write the whole thing to use new irq.c file.
8 * Copyright (C) 2001 MontaVista Software Inc.
9 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16
17#include <asm/i8259.h>
18#include <asm/io.h>
19#include <asm/ptrace.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
24#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
25#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
26
27#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
28#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
29#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
30
31#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
32#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
33
34#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
35#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
36
37#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
38#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
39
40static void m1543_irq_setup(void)
41{
42 /*
43 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
44 * the possible IO sources in the M1543 are in use by us. We will
45 * use the following mapping:
46 *
47 * IRQ1 - keyboard (default set by M1543)
48 * IRQ3 - reserved for UART B (default set by M1543) (note that
49 * the schematics for the DDB Vrc-5476 board seem to
50 * indicate that IRQ3 is connected to the DS1386
51 * watchdog timer interrupt output so we might have
52 * a conflict)
53 * IRQ4 - reserved for UART A (default set by M1543)
54 * IRQ5 - parallel (default set by M1543)
55 * IRQ8 - DS1386 time of day (RTC) interrupt
56 * IRQ9 - USB (hardwired in ddb_setup)
57 * IRQ10 - PMU (hardwired in ddb_setup)
58 * IRQ12 - mouse
59 * IRQ14,15 - IDE controller (need to be confirmed, jsun)
60 */
61
62 /*
63 * Assing mouse interrupt to IRQ12
64 */
65
66 /* Enter configuration mode */
67 outb(0x51, M1543_PNP_CONFIG);
68 outb(0x23, M1543_PNP_CONFIG);
69
70 /* Select logical device 7 (Keyboard) */
71 outb(0x07, M1543_PNP_INDEX);
72 outb(0x07, M1543_PNP_DATA);
73
74 /* Select IRQ12 */
75 outb(0x72, M1543_PNP_INDEX);
76 outb(0x0c, M1543_PNP_DATA);
77
78 /* Leave configration mode */
79 outb(0xbb, M1543_PNP_CONFIG);
80}
81
82static void nile4_irq_setup(void)
83{
84 int i;
85
86 /* Map all interrupts to CPU int #0 (IP2) */
87 nile4_map_irq_all(0);
88
89 /* PCI INTA#-E# must be level triggered */
90 nile4_set_pci_irq_level_or_edge(0, 1);
91 nile4_set_pci_irq_level_or_edge(1, 1);
92 nile4_set_pci_irq_level_or_edge(2, 1);
93 nile4_set_pci_irq_level_or_edge(3, 1);
94
95 /* PCI INTA#, B#, D# must be active low, INTC# must be active high */
96 nile4_set_pci_irq_polarity(0, 0);
97 nile4_set_pci_irq_polarity(1, 0);
98 nile4_set_pci_irq_polarity(2, 1);
99 nile4_set_pci_irq_polarity(3, 0);
100
101 for (i = 0; i < 16; i++)
102 nile4_clear_irq(i);
103
104 /* Enable CPU int #0 */
105 nile4_enable_irq_output(0);
106
107 /* memory resource acquire in ddb_setup */
108}
109
110static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
111static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
112
113extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
114extern void mips_cpu_irq_init(u32 irq_base);
115extern void vrc5476_irq_init(u32 irq_base);
116
117extern void vrc5476_irq_dispatch(struct pt_regs *regs);
118
119asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
120{
121 unsigned int pending = read_c0_cause() & read_c0_status();
122
123 if (pending & STATUSF_IP7)
124 do_IRQ(CPU_IRQ_BASE + 7, regs);
125 else if (pending & STATUSF_IP2)
126 vrc5476_irq_dispatch(regs);
127 else if (pending & STATUSF_IP3)
128 do_IRQ(CPU_IRQ_BASE + 3, regs);
129 else if (pending & STATUSF_IP4)
130 do_IRQ(CPU_IRQ_BASE + 4, regs);
131 else if (pending & STATUSF_IP5)
132 do_IRQ(CPU_IRQ_BASE + 5, regs);
133 else if (pending & STATUSF_IP6)
134 do_IRQ(CPU_IRQ_BASE + 6, regs);
135 else if (pending & STATUSF_IP0)
136 do_IRQ(CPU_IRQ_BASE, regs);
137 else if (pending & STATUSF_IP1)
138 do_IRQ(CPU_IRQ_BASE + 1, regs);
139
140 vrc5476_irq_dispatch(regs);
141}
142
143void __init arch_init_irq(void)
144{
145 /* hardware initialization */
146 nile4_irq_setup();
147 m1543_irq_setup();
148
149 /* controller setup */
150 init_i8259_irqs();
151 vrc5476_irq_init(VRC5476_IRQ_BASE);
152 mips_cpu_irq_init(CPU_IRQ_BASE);
153
154 /* setup cascade interrupts */
155 setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
156 setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
157
158 /* setup error interrupts for debugging */
159 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
160 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
161 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
162 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
163 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
164 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
165}
diff --git a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
deleted file mode 100644
index e930cee7944f..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15
16#include <asm/addrspace.h>
17
18#include <asm/ddb5xxx/ddb5xxx.h>
19
20
21/*
22 * Interrupt Programming
23 */
24void nile4_map_irq(int nile4_irq, int cpu_irq)
25{
26 u32 offset, t;
27
28 offset = DDB_INTCTRL;
29 if (nile4_irq >= 8) {
30 offset += 4;
31 nile4_irq -= 8;
32 }
33 t = ddb_in32(offset);
34 t &= ~(7 << (nile4_irq * 4));
35 t |= cpu_irq << (nile4_irq * 4);
36 ddb_out32(offset, t);
37}
38
39void nile4_map_irq_all(int cpu_irq)
40{
41 u32 all, t;
42
43 all = cpu_irq;
44 all |= all << 4;
45 all |= all << 8;
46 all |= all << 16;
47 t = ddb_in32(DDB_INTCTRL);
48 t &= 0x88888888;
49 t |= all;
50 ddb_out32(DDB_INTCTRL, t);
51 t = ddb_in32(DDB_INTCTRL + 4);
52 t &= 0x88888888;
53 t |= all;
54 ddb_out32(DDB_INTCTRL + 4, t);
55}
56
57void nile4_enable_irq(int nile4_irq)
58{
59 u32 offset, t;
60
61 offset = DDB_INTCTRL;
62 if (nile4_irq >= 8) {
63 offset += 4;
64 nile4_irq -= 8;
65 }
66 t = ddb_in32(offset);
67 t |= 8 << (nile4_irq * 4);
68 ddb_out32(offset, t);
69}
70
71void nile4_disable_irq(int nile4_irq)
72{
73 u32 offset, t;
74
75 offset = DDB_INTCTRL;
76 if (nile4_irq >= 8) {
77 offset += 4;
78 nile4_irq -= 8;
79 }
80 t = ddb_in32(offset);
81 t &= ~(8 << (nile4_irq * 4));
82 ddb_out32(offset, t);
83}
84
85void nile4_disable_irq_all(void)
86{
87 ddb_out32(DDB_INTCTRL, 0);
88 ddb_out32(DDB_INTCTRL + 4, 0);
89}
90
91u16 nile4_get_irq_stat(int cpu_irq)
92{
93 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
94}
95
96void nile4_enable_irq_output(int cpu_irq)
97{
98 u32 t;
99
100 t = ddb_in32(DDB_INTSTAT1 + 4);
101 t |= 1 << (16 + cpu_irq);
102 ddb_out32(DDB_INTSTAT1, t);
103}
104
105void nile4_disable_irq_output(int cpu_irq)
106{
107 u32 t;
108
109 t = ddb_in32(DDB_INTSTAT1 + 4);
110 t &= ~(1 << (16 + cpu_irq));
111 ddb_out32(DDB_INTSTAT1, t);
112}
113
114void nile4_set_pci_irq_polarity(int pci_irq, int high)
115{
116 u32 t;
117
118 t = ddb_in32(DDB_INTPPES);
119 if (high)
120 t &= ~(1 << (pci_irq * 2));
121 else
122 t |= 1 << (pci_irq * 2);
123 ddb_out32(DDB_INTPPES, t);
124}
125
126void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (level)
132 t |= 2 << (pci_irq * 2);
133 else
134 t &= ~(2 << (pci_irq * 2));
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_clear_irq(int nile4_irq)
139{
140 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
141}
142
143void nile4_clear_irq_mask(u32 mask)
144{
145 ddb_out32(DDB_INTCLR, mask);
146}
147
148u8 nile4_i8259_iack(void)
149{
150 u8 irq;
151 u32 reg;
152
153 /* Set window 0 for interrupt acknowledge */
154 reg = ddb_in32(DDB_PCIINIT0);
155
156 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
157 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
158 /* restore window 0 for PCI I/O space */
159 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
160 ddb_out32(DDB_PCIINIT0, reg);
161
162 /* i8269.c set the base vector to be 0x0 */
163 return irq + I8259_IRQ_BASE;
164}
165
166#if defined(CONFIG_RUNTIME_DEBUG)
167void nile4_dump_irq_status(void)
168{
169 printk(KERN_DEBUG "
170 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
171 (void *) ddb_in32(DDB_CPUSTAT));
172 printk(KERN_DEBUG "
173 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
174 (void *) ddb_in32(DDB_INTCTRL));
175 printk(KERN_DEBUG
176 "INTSTAT0 = %p:%p\n",
177 (void *) ddb_in32(DDB_INTSTAT0 + 4),
178 (void *) ddb_in32(DDB_INTSTAT0));
179 printk(KERN_DEBUG
180 "INTSTAT1 = %p:%p\n",
181 (void *) ddb_in32(DDB_INTSTAT1 + 4),
182 (void *) ddb_in32(DDB_INTSTAT1));
183 printk(KERN_DEBUG
184 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
185 (void *) ddb_in32(DDB_INTCLR));
186 printk(KERN_DEBUG
187 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
188 (void *) ddb_in32(DDB_INTPPES));
189}
190#endif
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
deleted file mode 100644
index 101021afb2e4..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15
16#include <asm/addrspace.h>
17#include <asm/bcache.h>
18#include <asm/irq.h>
19#include <asm/reboot.h>
20#include <asm/gdb-stub.h>
21#include <asm/time.h>
22#include <asm/debug.h>
23#include <asm/traps.h>
24
25#include <asm/ddb5xxx/ddb5xxx.h>
26
27// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
28
29#ifdef USE_CPU_COUNTER_TIMER
30
31#define CPU_COUNTER_FREQUENCY 83000000
32#else
33/* otherwise we use general purpose timer */
34#define TIMER_FREQUENCY 83000000
35#define TIMER_BASE DDB_T2CTRL
36#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
37#endif
38
39static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
40
41static void ddb_machine_restart(char *command)
42{
43 u32 t;
44
45 /* PCI cold reset */
46 t = ddb_in32(DDB_PCICTRL + 4);
47 t |= 0x40000000;
48 ddb_out32(DDB_PCICTRL + 4, t);
49 /* CPU cold reset */
50 t = ddb_in32(DDB_CPUSTAT);
51 t |= 1;
52 ddb_out32(DDB_CPUSTAT, t);
53 /* Call the PROM */
54 back_to_prom();
55}
56
57static void ddb_machine_halt(void)
58{
59 printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
60 while (1);
61}
62
63static void ddb_machine_power_off(void)
64{
65 printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
66 while (1);
67}
68
69extern void rtc_ds1386_init(unsigned long base);
70
71static void __init ddb_time_init(void)
72{
73#if defined(USE_CPU_COUNTER_TIMER)
74 mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
75#endif
76
77 /* we have ds1396 RTC chip */
78 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
79}
80
81
82extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
83static void __init ddb_timer_setup(struct irqaction *irq)
84{
85#if defined(USE_CPU_COUNTER_TIMER)
86
87 unsigned int count;
88
89 /* we are using the cpu counter for timer interrupts */
90 setup_irq(CPU_IRQ_BASE + 7, irq);
91
92 /* to generate the first timer interrupt */
93 count = read_c0_count();
94 write_c0_compare(count + 1000);
95
96#else
97
98 ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
99 ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
100 setup_irq(TIMER_IRQ, irq);
101#endif
102}
103
104static struct {
105 struct resource dma1;
106 struct resource timer;
107 struct resource rtc;
108 struct resource dma_page_reg;
109 struct resource dma2;
110} ddb5476_ioport = {
111 {
112 .start = 0x00,
113 .end = 0x1f,
114 .name = "dma1",
115 .flags = IORESOURCE_BUSY
116 }, {
117 .start = 0x40,
118 .end = 0x5f,
119 .name = "timer",
120 .flags = IORESOURCE_BUSY
121 }, {
122 .start = 0x70,
123 .end = 0x7f,
124 .name = "rtc",
125 .flags = IORESOURCE_BUSY
126 }, {
127 .start = 0x80,
128 .end = 0x8f,
129 .name = "dma page reg",
130 .flags = IORESOURCE_BUSY
131 }, {
132 .start = 0xc0,
133 .end = 0xdf,
134 .name = "dma2",
135 .flags = IORESOURCE_BUSY
136 }
137};
138
139static struct {
140 struct resource nile4;
141} ddb5476_iomem = {
142 {
143 .start = DDB_BASE,
144 .end = DDB_BASE + DDB_SIZE - 1,
145 .name = "Nile 4",
146 .flags = IORESOURCE_BUSY
147 }
148};
149
150
151static void ddb5476_board_init(void);
152
153void __init plat_mem_setup(void)
154{
155 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
156
157 board_time_init = ddb_time_init;
158 board_timer_setup = ddb_timer_setup;
159
160 _machine_restart = ddb_machine_restart;
161 _machine_halt = ddb_machine_halt;
162 pm_power_off = ddb_machine_power_off;
163
164 /* request io port/mem resources */
165 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
166 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
167 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
168 request_resource(&ioport_resource,
169 &ddb5476_ioport.dma_page_reg)
170 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
171 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
172 printk
173 ("ddb_setup - requesting oo port resources failed.\n");
174 for (;;);
175 }
176
177 /* Reboot on panic */
178 panic_timeout = 180;
179
180 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
181 /* *(long*)0xbfa00218 = 0x8; */
182
183 /* board initialization stuff */
184 ddb5476_board_init();
185}
186
187/*
188 * We don't trust bios. We essentially does hardware re-initialization
189 * as complete as possible, as far as we know we can safely do.
190 */
191static void ddb5476_board_init(void)
192{
193 /* ----------- setup PDARs ------------ */
194 /* check SDRAM0, whether we are on MEM bus does not matter */
195 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
196 ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
197
198 /* SDRAM1 should be turned off. What is this for anyway ? */
199 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
200
201 /* flash 1&2, DDB status, DDB control */
202 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
203 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
204 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
205 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
206
207 /* shut off other pdar so they don't accidentally get into the way */
208 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
209 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
210 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
211
212 /* verify VRC5477 base addr */
213 /* don't care about some details */
214 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
215 ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
216
217 /* verify BOOT ROM addr */
218 /* don't care about some details */
219 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
220 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
221
222 /* setup PCI windows - window1 for MEM/config, window0 for IO */
223 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
224 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
225
226 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
227 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
228
229 /* ----------- setup PDARs ------------ */
230 /* this is problematic - it will reset Aladin which cause we loose
231 * serial port, and we don't know how to set up Aladin chip again.
232 */
233 // ddb_pci_reset_bus();
234
235 ddb_out32(DDB_BAR0, 0x00000008);
236
237 ddb_out32(DDB_BARC, 0xffffffff);
238 ddb_out32(DDB_BARB, 0xffffffff);
239 ddb_out32(DDB_BAR1, 0xffffffff);
240 ddb_out32(DDB_BAR2, 0xffffffff);
241 ddb_out32(DDB_BAR3, 0xffffffff);
242 ddb_out32(DDB_BAR4, 0xffffffff);
243 ddb_out32(DDB_BAR5, 0xffffffff);
244 ddb_out32(DDB_BAR6, 0xffffffff);
245 ddb_out32(DDB_BAR7, 0xffffffff);
246 ddb_out32(DDB_BAR8, 0xffffffff);
247
248 /* ----------- switch PCI1 to PCI CONFIG space ------------ */
249 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
250 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
251
252 /* ----- M1543 PCI setup ------ */
253
254 /* we know M1543 PCI-ISA controller is at addr:18 */
255 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
256 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
257 *(volatile unsigned char *) 0xa8040072 |= 0xa;
258
259 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
260 * no IOCHRDY signal, (bit 7 - 1)
261 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
262 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
263 */
264 *(unsigned char *) 0xa8040074 = 0xd1;
265
266 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
267 * SCI routing to IRQ 13 disabled (bit 7 - 1)
268 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
269 */
270 *(unsigned char *) 0xa8040076 = 0x83;
271
272 /* setup IDE controller
273 * enable IDE controller (bit 6 - 1)
274 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
275 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
276 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
277 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
278 */
279 // *(unsigned char*)0xa8040058 = 0x71;
280 // *(unsigned char*)0xa8040058 = 0x79;
281 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
282 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
283
284#if 0
285 /* this is not necessary if M5229 does not use SIRQ */
286 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
287 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
288#endif
289
290 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
291 /* M5229 IDSEL is addr:24; see above setting */
292 *(unsigned char *) 0xa9000050 |= 0x1;
293
294 /* enable bus master (bit 2) and IO decoding (bit 0) */
295 *(unsigned char *) 0xa9000004 |= 0x5;
296
297 /* enable native, copied from arch/ppc/k2boot/head.S */
298 /* TODO - need volatile, need to be portable */
299 *(unsigned char *) 0xa9000009 = 0xff;
300
301 /* ----- end of M1543 PCI setup ------ */
302
303 /* ----- reset on-board ether chip ------ */
304 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
305 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
306
307 /* send reset command */
308 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
309
310 /* disable ether chip */
311 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
312
313 /* put it into sleep */
314 *((volatile u32 *) 0xa8020040) = 0x80000000;
315
316 /* ----- end of reset on-board ether chip ------ */
317
318 /* ----------- switch PCI1 back to PCI MEM space ------------ */
319 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
320 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
321}
diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
deleted file mode 100644
index a3c5e7b18018..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * The irq controller for vrc5476.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18
19#include <asm/system.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23static int irq_base;
24
25static void vrc5476_irq_enable(uint irq)
26{
27 nile4_enable_irq(irq - irq_base);
28}
29
30static void vrc5476_irq_disable(uint irq)
31{
32 nile4_disable_irq(irq - irq_base);
33}
34
35static unsigned int vrc5476_irq_startup(uint irq)
36{
37 nile4_enable_irq(irq - irq_base);
38 return 0;
39}
40
41#define vrc5476_irq_shutdown vrc5476_irq_disable
42
43static void vrc5476_irq_ack(uint irq)
44{
45 nile4_clear_irq(irq - irq_base);
46 nile4_disable_irq(irq - irq_base);
47}
48
49static void vrc5476_irq_end(uint irq)
50{
51 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
52 vrc5476_irq_enable(irq);
53}
54
55static hw_irq_controller vrc5476_irq_controller = {
56 .typename = "vrc5476",
57 .startup = vrc5476_irq_startup,
58 .shutdown = vrc5476_irq_shutdown,
59 .enable = vrc5476_irq_enable,
60 .disable = vrc5476_irq_disable,
61 .ack = vrc5476_irq_ack,
62 .end = vrc5476_irq_end
63};
64
65void __init
66vrc5476_irq_init(u32 base)
67{
68 u32 i;
69
70 irq_base = base;
71 for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
72 irq_desc[i].status = IRQ_DISABLED;
73 irq_desc[i].action = NULL;
74 irq_desc[i].depth = 1;
75 irq_desc[i].handler = &vrc5476_irq_controller;
76 }
77}
78
79
80void
81vrc5476_irq_dispatch(struct pt_regs *regs)
82{
83 u32 mask;
84 int nile4_irq;
85
86 mask = nile4_get_irq_stat(0);
87
88 /* quick check for possible time interrupt */
89 if (mask & (1 << VRC5476_IRQ_GPT)) {
90 do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
91 return;
92 }
93
94 /* check for i8259 interrupts */
95 if (mask & (1 << VRC5476_I8259_CASCADE)) {
96 int i8259_irq = nile4_i8259_iack();
97 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
98 return;
99 }
100
101 /* regular nile4 interrupts (we should not really have any */
102 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
103 if (mask & 1) {
104 do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
105 return;
106 }
107 }
108 spurious_interrupt(regs);
109}
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index f7b0beb5752f..f72ba3f1b7f5 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -41,7 +41,6 @@ CONFIG_MIPS=y
41# CONFIG_MIPS_XXS1500 is not set 41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set 42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set 43# CONFIG_PNX8550_JBS is not set
44# CONFIG_DDB5476 is not set
45# CONFIG_DDB5477 is not set 44# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 45# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 46# CONFIG_PMC_YOSEMITE is not set
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index d028197d8326..c5f5516f4695 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
22# 22#
23# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
24# 24#
25obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o
26obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o 25obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
27obj-$(CONFIG_LASAT) += pci-lasat.o 26obj-$(CONFIG_LASAT) += pci-lasat.o
28obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 27obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
diff --git a/arch/mips/pci/ops-ddb5476.c b/arch/mips/pci/ops-ddb5476.c
deleted file mode 100644
index 12da58e75ec7..000000000000
--- a/arch/mips/pci/ops-ddb5476.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5476/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20
21#include <asm/addrspace.h>
22#include <asm/debug.h>
23
24#include <asm/ddb5xxx/ddb5xxx.h>
25
26/*
27 * config_swap structure records what set of pdar/pmr are used
28 * to access pci config space. It also provides a place hold the
29 * original values for future restoring.
30 */
31struct pci_config_swap {
32 u32 pdar;
33 u32 pmr;
34 u32 config_base;
35 u32 config_size;
36 u32 pdar_backup;
37 u32 pmr_backup;
38};
39
40/*
41 * On DDB5476, we have one set of swap registers
42 */
43struct pci_config_swap ext_pci_swap = {
44 DDB_PCIW0,
45 DDB_PCIINIT0,
46 DDB_PCI_CONFIG_BASE,
47 DDB_PCI_CONFIG_SIZE
48};
49
50static int pci_config_workaround = 1;
51
52/*
53 * access config space
54 */
55static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
56 u32 slot_num)
57{
58 u32 pci_addr = 0;
59 u32 pciinit_offset = 0;
60 u32 virt_addr = swap->config_base;
61 u32 option;
62
63 if (pci_config_workaround) {
64 /* [jsun] work around Vrc5476 controller itself, returnning
65 * slot 0 essentially makes vrc5476 invisible
66 */
67 if (slot_num == 12)
68 slot_num = 0;
69
70#if 0
71 /* BUG : skip P2P bridge for now */
72 if (slot_num == 5)
73 slot_num = 0;
74#endif
75
76 } else {
77 /* now we have to be hornest, returning the true
78 * PCI config headers for vrc5476
79 */
80 if (slot_num == 12) {
81 swap->pdar_backup = ddb_in32(swap->pdar);
82 swap->pmr_backup = ddb_in32(swap->pmr);
83 return DDB_BASE + DDB_PCI_BASE;
84 }
85 }
86
87 /* minimum pdar (window) size is 2MB */
88 db_assert(swap->config_size >= (2 << 20));
89
90 db_assert(slot_num < (1 << 5));
91 db_assert(bus < (1 << 8));
92
93 /* backup registers */
94 swap->pdar_backup = ddb_in32(swap->pdar);
95 swap->pmr_backup = ddb_in32(swap->pmr);
96
97 /* set the pdar (pci window) register */
98 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
99 0, /* not on local memory bus */
100 0); /* not visible from PCI bus (N/A) */
101
102 /*
103 * calcuate the absolute pci config addr;
104 * according to the spec, we start scanning from adr:11 (0x800)
105 */
106 if (bus == 0) {
107 /* type 0 config */
108 pci_addr = 0x800 << slot_num;
109 } else {
110 /* type 1 config */
111 pci_addr = (bus << 16) | (slot_num << 11);
112 /* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
113 }
114
115 /*
116 * if pci_addr is less than pci config window size, we set
117 * pciinit_offset to 0 and adjust the virt_address.
118 * Otherwise we will try to adjust pciinit_offset.
119 */
120 if (pci_addr < swap->config_size) {
121 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
122 pciinit_offset = 0;
123 } else {
124 db_assert((pci_addr & (swap->config_size - 1)) == 0);
125 virt_addr = KSEG1ADDR(swap->config_base);
126 pciinit_offset = pci_addr;
127 }
128
129 /* set the pmr register */
130 option = DDB_PCI_ACCESS_32;
131 if (bus != 0)
132 option |= DDB_PCI_CFGTYPE1;
133 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
134
135 return virt_addr;
136}
137
138static inline void ddb_close_config_base(struct pci_config_swap *swap)
139{
140 ddb_out32(swap->pdar, swap->pdar_backup);
141 ddb_out32(swap->pmr, swap->pmr_backup);
142}
143
144static int read_config_dword(struct pci_config_swap *swap,
145 struct pci_dev *dev, u32 where, u32 * val)
146{
147 u32 bus, slot_num, func_num;
148 u32 base;
149
150 db_assert((where & 3) == 0);
151 db_assert(where < (1 << 8));
152
153 /* check if the bus is top-level */
154 if (dev->bus->parent != NULL) {
155 bus = dev->bus->number;
156 db_assert(bus != 0);
157 } else {
158 bus = 0;
159 }
160
161 slot_num = PCI_SLOT(dev->devfn);
162 func_num = PCI_FUNC(dev->devfn);
163 base = ddb_access_config_base(swap, bus, slot_num);
164 *val = *(volatile u32 *) (base + (func_num << 8) + where);
165 ddb_close_config_base(swap);
166 return PCIBIOS_SUCCESSFUL;
167}
168
169static int read_config_word(struct pci_config_swap *swap,
170 struct pci_dev *dev, u32 where, u16 * val)
171{
172 int status;
173 u32 result;
174
175 db_assert((where & 1) == 0);
176
177 status = read_config_dword(swap, dev, where & ~3, &result);
178 if (where & 2)
179 result >>= 16;
180 *val = result & 0xffff;
181 return status;
182}
183
184static int read_config_byte(struct pci_config_swap *swap,
185 struct pci_dev *dev, u32 where, u8 * val)
186{
187 int status;
188 u32 result;
189
190 status = read_config_dword(swap, dev, where & ~3, &result);
191 if (where & 1)
192 result >>= 8;
193 if (where & 2)
194 result >>= 16;
195 *val = result & 0xff;
196 return status;
197}
198
199static int write_config_dword(struct pci_config_swap *swap,
200 struct pci_dev *dev, u32 where, u32 val)
201{
202 u32 bus, slot_num, func_num;
203 u32 base;
204
205 db_assert((where & 3) == 0);
206 db_assert(where < (1 << 8));
207
208 /* check if the bus is top-level */
209 if (dev->bus->parent != NULL) {
210 bus = dev->bus->number;
211 db_assert(bus != 0);
212 } else {
213 bus = 0;
214 }
215
216 slot_num = PCI_SLOT(dev->devfn);
217 func_num = PCI_FUNC(dev->devfn);
218 base = ddb_access_config_base(swap, bus, slot_num);
219 *(volatile u32 *) (base + (func_num << 8) + where) = val;
220 ddb_close_config_base(swap);
221 return PCIBIOS_SUCCESSFUL;
222}
223
224static int write_config_word(struct pci_config_swap *swap,
225 struct pci_dev *dev, u32 where, u16 val)
226{
227 int status, shift = 0;
228 u32 result;
229
230 db_assert((where & 1) == 0);
231
232 status = read_config_dword(swap, dev, where & ~3, &result);
233 if (status != PCIBIOS_SUCCESSFUL)
234 return status;
235
236 if (where & 2)
237 shift += 16;
238 result &= ~(0xffff << shift);
239 result |= val << shift;
240 return write_config_dword(swap, dev, where & ~3, result);
241}
242
243static int write_config_byte(struct pci_config_swap *swap,
244 struct pci_dev *dev, u32 where, u8 val)
245{
246 int status, shift = 0;
247 u32 result;
248
249 status = read_config_dword(swap, dev, where & ~3, &result);
250 if (status != PCIBIOS_SUCCESSFUL)
251 return status;
252
253 if (where & 2)
254 shift += 16;
255 if (where & 1)
256 shift += 8;
257 result &= ~(0xff << shift);
258 result |= val << shift;
259 return write_config_dword(swap, dev, where & ~3, result);
260}
261
262#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
263static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
264{ \
265 return rw##_config_##unitname(pciswap, \
266 dev, \
267 where, \
268 val); \
269}
270
271MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
272 MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
273 MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
274
275 MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
276 MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
277 MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
278
279struct pci_ops ddb5476_ext_pci_ops = {
280 extpci_read_config_byte,
281 extpci_read_config_word,
282 extpci_read_config_dword,
283 extpci_write_config_byte,
284 extpci_write_config_word,
285 extpci_write_config_dword
286};
diff --git a/arch/mips/pci/pci-ddb5476.c b/arch/mips/pci/pci-ddb5476.c
deleted file mode 100644
index 2f44c0b783d9..000000000000
--- a/arch/mips/pci/pci-ddb5476.c
+++ /dev/null
@@ -1,93 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/types.h>
4#include <linux/pci.h>
5
6#include <asm/debug.h>
7
8#include <asm/ddb5xxx/ddb5xxx.h>
9
10static struct resource extpci_io_resource = {
11 .start = 0x1000, /* leave some room for ISA bus */
12 .end = DDB_PCI_IO_SIZE - 1,
13 .name = "pci IO space",
14 .flags = IORESOURCE_IO
15};
16
17static struct resource extpci_mem_resource = {
18 .start = DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
19 .end = DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
20 .name = "pci memory space",
21 .flags = IORESOURCE_MEM
22};
23
24extern struct pci_ops ddb5476_ext_pci_ops;
25
26struct pci_controller ddb5476_controller = {
27 .pci_ops = &ddb5476_ext_pci_ops,
28 .io_resource = &extpci_io_resource,
29 .mem_resource = &extpci_mem_resource
30};
31
32
33/*
34 * we fix up irqs based on the slot number.
35 * The first entry is at AD:11.
36 *
37 * This does not work for devices on sub-buses yet.
38 */
39
40/*
41 * temporary
42 */
43
44#define PCI_EXT_INTA 8
45#define PCI_EXT_INTB 9
46#define PCI_EXT_INTC 10
47#define PCI_EXT_INTD 11
48#define PCI_EXT_INTE 12
49
50/*
51 * based on ddb5477 manual page 11
52 */
53#define MAX_SLOT_NUM 21
54static unsigned char irq_map[MAX_SLOT_NUM] = {
55 [ 2] = 9, /* AD:13 USB */
56 [ 3] = 10, /* AD:14 PMU */
57 [ 5] = 0, /* AD:16 P2P bridge */
58 [ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */
59 [ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */
60 [ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */
61 [ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */
62 [13] = 14, /* AD:24 HD controller, M5229 */
63};
64
65int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
66{
67 return irq_map[slot];
68}
69
70/* Do platform specific device initialization at pci_enable_device() time */
71int pcibios_plat_dev_init(struct pci_dev *dev)
72{
73 return 0;
74}
75
76void __init ddb_pci_reset_bus(void)
77{
78 u32 temp;
79
80 /*
81 * I am not sure about the "official" procedure, the following
82 * steps work as far as I know:
83 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
84 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
85 * The same is true for both PCI channels.
86 */
87 temp = ddb_in32(DDB_PCICTRL + 4);
88 temp |= 0x80000000;
89 ddb_out32(DDB_PCICTRL + 4, temp);
90 temp &= ~0xc0000000;
91 ddb_out32(DDB_PCICTRL + 4, temp);
92
93}
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index c67c91251d04..351a45d8e4ab 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1483,14 +1483,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
1483 sa_offset = 2; /* Grrr, damn Matrox boards. */ 1483 sa_offset = 2; /* Grrr, damn Matrox boards. */
1484 multiport_cnt = 4; 1484 multiport_cnt = 4;
1485 } 1485 }
1486#ifdef CONFIG_DDB5476
1487 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
1488 /* DDB5476 MAC address in first EEPROM locations. */
1489 sa_offset = 0;
1490 /* No media table either */
1491 tp->flags &= ~HAS_MEDIA_TABLE;
1492 }
1493#endif
1494#ifdef CONFIG_DDB5477 1486#ifdef CONFIG_DDB5477
1495 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) { 1487 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1496 /* DDB5477 MAC address in first EEPROM locations. */ 1488 /* DDB5477 MAC address in first EEPROM locations. */
diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h
deleted file mode 100644
index 4c23390d9354..000000000000
--- a/include/asm-mips/ddb5xxx/ddb5476.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * header file specific for ddb5476
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/*
15 * Memory map (physical address)
16 *
17 * Note most of the following address must be properly aligned by the
18 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
19 * PCI_IO_BASE must be aligned along 16MB boundary.
20 */
21#define DDB_SDRAM_BASE 0x00000000
22#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
23
24#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
25#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
26
27#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
28#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
29
30#define DDB_PCI_IO_BASE 0x06000000
31#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
32
33#define DDB_PCI_MEM_BASE 0x08000000
34#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
35
36#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
37#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
38
39#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
40#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
41
42#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
43#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
44
45#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
46#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
47
48
49/* aliases */
50#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
51#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
52
53/* PCI intr ack share PCIW0 with PCI IO */
54#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
55
56/*
57 * Interrupt mapping
58 *
59 * We have three interrupt controllers:
60 *
61 * . CPU itself - 8 sources
62 * . i8259 - 16 sources
63 * . vrc5476 - 16 sources
64 *
65 * They connected as follows:
66 * all vrc5476 interrupts are routed to cpu IP2 (by software setting)
67 * all i2869 are routed to INTC in vrc5476 (by hardware connection)
68 *
69 * All VRC5476 PCI interrupts are level-triggered (no ack needed).
70 * All PCI irq but INTC are active low.
71 */
72
73/*
74 * irq number block assignment
75 */
76
77#define NUM_CPU_IRQ 8
78#define NUM_I8259_IRQ 16
79#define NUM_VRC5476_IRQ 16
80
81#define DDB_IRQ_BASE 0
82
83#define I8259_IRQ_BASE DDB_IRQ_BASE
84#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
85#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
86
87/*
88 * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
89 */
90
91#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
92#define VRC5476_IRQ_CNTD 1 /* cpu no target */
93#define VRC5476_IRQ_MCE 2 /* memory check error */
94#define VRC5476_IRQ_DMA 3 /* DMA */
95#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
96#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
97#define VRC5476_IRQ_GPT 6 /* general purpose timer */
98#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
99#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
100#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
101#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
102#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
103#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
104#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
105#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
106#define VRC5476_IRQ_PCI 15 /* PCI internal error */
107
108/*
109 * i2859 irq assignment
110 */
111#define I8259_IRQ_RESERVED_0 0
112#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
113#define I8259_IRQ_CASCADE 2
114#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
115#define I8259_IRQ_UART_A 4 /* M1543 default */
116#define I8259_IRQ_PARALLEL 5 /* M1543 default */
117#define I8259_IRQ_RESERVED_6 6
118#define I8259_IRQ_RESERVED_7 7
119#define I8259_IRQ_RTC 8 /* who set this? */
120#define I8259_IRQ_USB 9 /* ddb_setup */
121#define I8259_IRQ_PMU 10 /* ddb_setup */
122#define I8259_IRQ_RESERVED_11 11
123#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
124#define I8259_IRQ_RESERVED_13 13
125#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
126#define I8259_IRQ_HDC2 15 /* default */
127
128
129/*
130 * misc
131 */
132#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
133#define CPU_VRC5476_CASCADE 2
134
135#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
136#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
137#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
138
139/*
140 * low-level irq functions
141 */
142#ifndef __ASSEMBLY__
143extern void nile4_map_irq(int nile4_irq, int cpu_irq);
144extern void nile4_map_irq_all(int cpu_irq);
145extern void nile4_enable_irq(int nile4_irq);
146extern void nile4_disable_irq(int nile4_irq);
147extern void nile4_disable_irq_all(void);
148extern u16 nile4_get_irq_stat(int cpu_irq);
149extern void nile4_enable_irq_output(int cpu_irq);
150extern void nile4_disable_irq_output(int cpu_irq);
151extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
152extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
153extern void nile4_clear_irq(int nile4_irq);
154extern void nile4_clear_irq_mask(u32 mask);
155extern u8 nile4_i8259_iack(void);
156extern void nile4_dump_irq_status(void); /* Debug */
157#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
index 2c8c93430c1c..2f1b191c6fff 100644
--- a/include/asm-mips/ddb5xxx/ddb5xxx.h
+++ b/include/asm-mips/ddb5xxx/ddb5xxx.h
@@ -255,9 +255,7 @@ extern void ddb_pci_reset_bus(void);
255/* 255/*
256 * include the board dependent part 256 * include the board dependent part
257 */ 257 */
258#if defined(CONFIG_DDB5476) 258#if defined(CONFIG_DDB5477)
259#include <asm/ddb5xxx/ddb5476.h>
260#elif defined(CONFIG_DDB5477)
261#include <asm/ddb5xxx/ddb5477.h> 259#include <asm/ddb5xxx/ddb5477.h>
262#else 260#else
263#error "Unknown DDB board!" 261#error "Unknown DDB board!"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 21:18:14 -0500