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-rw-r--r--arch/powerpc/platforms/86xx/gef_pic.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
index 0110a8736d33..7ad9c0df7707 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -49,7 +49,7 @@
49#define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 49#define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
50 50
51 51
52static DEFINE_SPINLOCK(gef_pic_lock); 52static DEFINE_RAW_SPINLOCK(gef_pic_lock);
53 53
54static void __iomem *gef_pic_irq_reg_base; 54static void __iomem *gef_pic_irq_reg_base;
55static struct irq_host *gef_pic_irq_host; 55static struct irq_host *gef_pic_irq_host;
@@ -118,11 +118,11 @@ static void gef_pic_mask(unsigned int virq)
118 118
119 hwirq = gef_irq_to_hw(virq); 119 hwirq = gef_irq_to_hw(virq);
120 120
121 spin_lock_irqsave(&gef_pic_lock, flags); 121 raw_spin_lock_irqsave(&gef_pic_lock, flags);
122 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); 122 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
123 mask &= ~(1 << hwirq); 123 mask &= ~(1 << hwirq);
124 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); 124 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
125 spin_unlock_irqrestore(&gef_pic_lock, flags); 125 raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
126} 126}
127 127
128static void gef_pic_mask_ack(unsigned int virq) 128static void gef_pic_mask_ack(unsigned int virq)
@@ -141,11 +141,11 @@ static void gef_pic_unmask(unsigned int virq)
141 141
142 hwirq = gef_irq_to_hw(virq); 142 hwirq = gef_irq_to_hw(virq);
143 143
144 spin_lock_irqsave(&gef_pic_lock, flags); 144 raw_spin_lock_irqsave(&gef_pic_lock, flags);
145 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); 145 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
146 mask |= (1 << hwirq); 146 mask |= (1 << hwirq);
147 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); 147 out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
148 spin_unlock_irqrestore(&gef_pic_lock, flags); 148 raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
149} 149}
150 150
151static struct irq_chip gef_pic_chip = { 151static struct irq_chip gef_pic_chip = {
@@ -199,7 +199,7 @@ void __init gef_pic_init(struct device_node *np)
199 /* Map the devices registers into memory */ 199 /* Map the devices registers into memory */
200 gef_pic_irq_reg_base = of_iomap(np, 0); 200 gef_pic_irq_reg_base = of_iomap(np, 0);
201 201
202 spin_lock_irqsave(&gef_pic_lock, flags); 202 raw_spin_lock_irqsave(&gef_pic_lock, flags);
203 203
204 /* Initialise everything as masked. */ 204 /* Initialise everything as masked. */
205 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0); 205 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
@@ -208,7 +208,7 @@ void __init gef_pic_init(struct device_node *np)
208 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0); 208 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
209 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0); 209 out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
210 210
211 spin_unlock_irqrestore(&gef_pic_lock, flags); 211 raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
212 212
213 /* Map controller */ 213 /* Map controller */
214 gef_pic_cascade_irq = irq_of_parse_and_map(np, 0); 214 gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);