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-rw-r--r--arch/blackfin/kernel/bfin_gpio.c10
-rw-r--r--arch/blackfin/kernel/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/setup.c20
-rw-r--r--arch/blackfin/lib/memcmp.S2
-rw-r--r--arch/blackfin/lib/memcpy.S2
-rw-r--r--arch/blackfin/lib/memmove.S4
-rw-r--r--arch/blackfin/mach-bf533/head.S10
-rw-r--r--arch/blackfin/mach-bf537/head.S18
-rw-r--r--arch/blackfin/mach-bf548/head.S2
-rw-r--r--arch/blackfin/mach-bf561/head.S11
-rw-r--r--arch/blackfin/mach-common/cacheinit.S2
-rw-r--r--arch/blackfin/mach-common/cplbmgr.S2
-rw-r--r--arch/blackfin/mach-common/entry.S10
-rw-r--r--arch/blackfin/mach-common/interrupt.S6
-rw-r--r--include/asm-blackfin/blackfin.h118
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h437
-rw-r--r--include/asm-blackfin/mach-bf533/bf533.h2
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h216
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h2
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h94
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h378
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h2
-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h4
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h132
-rw-r--r--include/asm-blackfin/system.h93
25 files changed, 875 insertions, 706 deletions
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 5d488ef965ce..b818a8da1215 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -330,7 +330,7 @@ EXPORT_SYMBOL(set_gpio_ ## name);
330SET_GPIO_SC(maska) 330SET_GPIO_SC(maska)
331SET_GPIO_SC(maskb) 331SET_GPIO_SC(maskb)
332 332
333#if defined(ANOMALY_05000311) 333#if ANOMALY_05000311
334void set_gpio_data(unsigned short gpio, unsigned short arg) 334void set_gpio_data(unsigned short gpio, unsigned short arg)
335{ 335{
336 unsigned long flags; 336 unsigned long flags;
@@ -349,7 +349,7 @@ SET_GPIO_SC(data)
349#endif 349#endif
350 350
351 351
352#if defined(ANOMALY_05000311) 352#if ANOMALY_05000311
353void set_gpio_toggle(unsigned short gpio) 353void set_gpio_toggle(unsigned short gpio)
354{ 354{
355 unsigned long flags; 355 unsigned long flags;
@@ -387,7 +387,7 @@ SET_GPIO_P(maska)
387SET_GPIO_P(maskb) 387SET_GPIO_P(maskb)
388 388
389 389
390#if defined(ANOMALY_05000311) 390#if ANOMALY_05000311
391void set_gpiop_data(unsigned short gpio, unsigned short arg) 391void set_gpiop_data(unsigned short gpio, unsigned short arg)
392{ 392{
393 unsigned long flags; 393 unsigned long flags;
@@ -421,7 +421,7 @@ GET_GPIO(maska)
421GET_GPIO(maskb) 421GET_GPIO(maskb)
422 422
423 423
424#if defined(ANOMALY_05000311) 424#if ANOMALY_05000311
425unsigned short get_gpio_data(unsigned short gpio) 425unsigned short get_gpio_data(unsigned short gpio)
426{ 426{
427 unsigned long flags; 427 unsigned long flags;
@@ -455,7 +455,7 @@ GET_GPIO_P(both)
455GET_GPIO_P(maska) 455GET_GPIO_P(maska)
456GET_GPIO_P(maskb) 456GET_GPIO_P(maskb)
457 457
458#if defined(ANOMALY_05000311) 458#if ANOMALY_05000311
459unsigned short get_gpiop_data(unsigned short gpio) 459unsigned short get_gpiop_data(unsigned short gpio)
460{ 460{
461 unsigned long flags; 461 unsigned long flags;
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
index bbdb403fcb55..3b1c87c9fd51 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -230,8 +230,8 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en
230 cplb_data[i].psize, 230 cplb_data[i].psize,
231 cplb_data[i].i_conf); 231 cplb_data[i].i_conf);
232 } else { 232 } else {
233#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) 233#if defined(CONFIG_BLKFIN_CACHE)
234 if (i == SDRAM_KERN) { 234 if (ANOMALY_05000263 && i == SDRAM_KERN) {
235 fill_cplbtab(t, 235 fill_cplbtab(t,
236 cplb_data[i].start, 236 cplb_data[i].start,
237 cplb_data[i].end, 237 cplb_data[i].end,
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 88f221b89b33..02c15272f8ef 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -179,14 +179,16 @@ void __init setup_arch(char **cmdline_p)
179 cclk = get_cclk(); 179 cclk = get_cclk();
180 sclk = get_sclk(); 180 sclk = get_sclk();
181 181
182#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273) 182#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
183 if (cclk == sclk) 183 if (ANOMALY_05000273 && cclk == sclk)
184 panic("ANOMALY 05000273, SCLK can not be same as CCLK"); 184 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
185#endif 185#endif
186 186
187#if defined(ANOMALY_05000266) 187#ifdef BF561_FAMILY
188 bfin_read_IMDMA_D0_IRQ_STATUS(); 188 if (ANOMALY_05000266) {
189 bfin_read_IMDMA_D1_IRQ_STATUS(); 189 bfin_read_IMDMA_D0_IRQ_STATUS();
190 bfin_read_IMDMA_D1_IRQ_STATUS();
191 }
190#endif 192#endif
191 193
192#ifdef DEBUG_SERIAL_EARLY_INIT 194#ifdef DEBUG_SERIAL_EARLY_INIT
@@ -260,7 +262,7 @@ void __init setup_arch(char **cmdline_p)
260 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) 262 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
261 mtd_size = 263 mtd_size =
262 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); 264 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
263# if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) 265# if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263)
264 /* Due to a Hardware Anomaly we need to limit the size of usable 266 /* Due to a Hardware Anomaly we need to limit the size of usable
265 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on 267 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
266 * 05000263 - Hardware loop corrupted when taking an ICPLB exception 268 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -289,7 +291,7 @@ void __init setup_arch(char **cmdline_p)
289 _ebss = memory_mtd_start; /* define _ebss for compatible */ 291 _ebss = memory_mtd_start; /* define _ebss for compatible */
290#endif /* CONFIG_MTD_UCLINUX */ 292#endif /* CONFIG_MTD_UCLINUX */
291 293
292#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) 294#if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263)
293 /* Due to a Hardware Anomaly we need to limit the size of usable 295 /* Due to a Hardware Anomaly we need to limit the size of usable
294 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on 296 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
295 * 05000263 - Hardware loop corrupted when taking an ICPLB exception 297 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -337,10 +339,8 @@ void __init setup_arch(char **cmdline_p)
337 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n", 339 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
338 cclk / 1000000, sclk / 1000000); 340 cclk / 1000000, sclk / 1000000);
339 341
340#if defined(ANOMALY_05000273) 342 if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
341 if ((cclk >> 1) <= sclk)
342 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); 343 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
343#endif
344 344
345 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); 345 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
346 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); 346 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
index b88c5d2d1ebe..219fa2877c62 100644
--- a/arch/blackfin/lib/memcmp.S
+++ b/arch/blackfin/lib/memcmp.S
@@ -61,7 +61,7 @@ ENTRY(_memcmp)
61 61
62 LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1; 62 LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
63.Lquad_loop_s: 63.Lquad_loop_s:
64#ifdef ANOMALY_05000202 64#if ANOMALY_05000202
65 R0 = [P0++]; 65 R0 = [P0++];
66 R1 = [I0++]; 66 R1 = [I0++];
67#else 67#else
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index 14a5585bbd02..2e6336492b4b 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -98,7 +98,7 @@ ENTRY(_memcpy)
98 R0 = R1; 98 R0 = R1;
99 I1 = P1; 99 I1 = P1;
100 R3 = [I1++]; 100 R3 = [I1++];
101#ifdef ANOMALY_05000202 101#if ANOMALY_05000202
102.Lword_loops: 102.Lword_loops:
103 [P0++] = R3; 103 [P0++] = R3;
104.Lword_loope: 104.Lword_loope:
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
index 6ee6e206e77c..33f8653145b7 100644
--- a/arch/blackfin/lib/memmove.S
+++ b/arch/blackfin/lib/memmove.S
@@ -70,7 +70,7 @@ ENTRY(_memmove)
70 R1 = [I0++]; 70 R1 = [I0++];
71 71
72 LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1; 72 LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
73#ifdef ANOMALY_05000202 73#if ANOMALY_05000202
74.Lquad_loops: 74.Lquad_loops:
75 [P0++] = R1; 75 [P0++] = R1;
76.Lquad_loope: 76.Lquad_loope:
@@ -102,7 +102,7 @@ ENTRY(_memmove)
102 R1 = B[P3--] (Z); 102 R1 = B[P3--] (Z);
103 CC = P2 == 0; 103 CC = P2 == 0;
104 IF CC JUMP .Lno_loop; 104 IF CC JUMP .Lno_loop;
105#ifdef ANOMALY_05000245 105#if ANOMALY_05000245
106 NOP; 106 NOP;
107 NOP; 107 NOP;
108#endif 108#endif
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7dd0e9c3a936..5aeffd06fe71 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -151,13 +151,13 @@ ENTRY(__start)
151 R0 = R0 & R1; 151 R0 = R0 & R1;
152 152
153 /* Anomaly 05000125 */ 153 /* Anomaly 05000125 */
154#ifdef ANOMALY_05000125 154#if ANOMALY_05000125
155 CLI R2; 155 CLI R2;
156 SSYNC; 156 SSYNC;
157#endif 157#endif
158 [p0] = R0; 158 [p0] = R0;
159 SSYNC; 159 SSYNC;
160#ifdef ANOMALY_05000125 160#if ANOMALY_05000125
161 STI R2; 161 STI R2;
162#endif 162#endif
163 163
@@ -169,13 +169,13 @@ ENTRY(__start)
169 R0 = R0 & R1; 169 R0 = R0 & R1;
170 170
171 /* Anomaly 05000125 */ 171 /* Anomaly 05000125 */
172#ifdef ANOMALY_05000125 172#if ANOMALY_05000125
173 CLI R2; 173 CLI R2;
174 SSYNC; 174 SSYNC;
175#endif 175#endif
176 [p0] = R0; 176 [p0] = R0;
177 SSYNC; 177 SSYNC;
178#ifdef ANOMALY_05000125 178#if ANOMALY_05000125
179 STI R2; 179 STI R2;
180#endif 180#endif
181 181
@@ -264,7 +264,7 @@ ENTRY(__start)
264 p0.l = .LWAIT_HERE; 264 p0.l = .LWAIT_HERE;
265 p0.h = .LWAIT_HERE; 265 p0.h = .LWAIT_HERE;
266 reti = p0; 266 reti = p0;
267#if defined(ANOMALY_05000281) 267#if ANOMALY_05000281
268 nop; nop; nop; 268 nop; nop; nop;
269#endif 269#endif
270 rti; 270 rti;
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 429c8a1019da..d9b411adf6a7 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -107,13 +107,13 @@ ENTRY(__start)
107 R0 = R0 & R1; 107 R0 = R0 & R1;
108 108
109 /* Anomaly 05000125 */ 109 /* Anomaly 05000125 */
110#ifdef ANOMALY_05000125 110#if ANOMALY_05000125
111 CLI R2; 111 CLI R2;
112 SSYNC; 112 SSYNC;
113#endif 113#endif
114 [p0] = R0; 114 [p0] = R0;
115 SSYNC; 115 SSYNC;
116#ifdef ANOMALY_05000125 116#if ANOMALY_05000125
117 STI R2; 117 STI R2;
118#endif 118#endif
119 119
@@ -125,13 +125,13 @@ ENTRY(__start)
125 R0 = R0 & R1; 125 R0 = R0 & R1;
126 126
127 /* Anomaly 05000125 */ 127 /* Anomaly 05000125 */
128#ifdef ANOMALY_05000125 128#if ANOMALY_05000125
129 CLI R2; 129 CLI R2;
130 SSYNC; 130 SSYNC;
131#endif 131#endif
132 [p0] = R0; 132 [p0] = R0;
133 SSYNC; 133 SSYNC;
134#ifdef ANOMALY_05000125 134#if ANOMALY_05000125
135 STI R2; 135 STI R2;
136#endif 136#endif
137 137
@@ -141,12 +141,12 @@ ENTRY(__start)
141 */ 141 */
142 p0.h = hi(BFIN_PORT_MUX); 142 p0.h = hi(BFIN_PORT_MUX);
143 p0.l = lo(BFIN_PORT_MUX); 143 p0.l = lo(BFIN_PORT_MUX);
144#ifdef ANOMALY_05000212 144#if ANOMALY_05000212
145 R0.L = W[P0]; /* Read */ 145 R0.L = W[P0]; /* Read */
146 SSYNC; 146 SSYNC;
147#endif 147#endif
148 R0 = (PGDE_UART | PFTE_UART)(Z); 148 R0 = (PGDE_UART | PFTE_UART)(Z);
149#ifdef ANOMALY_05000212 149#if ANOMALY_05000212
150 W[P0] = R0.L; /* Write */ 150 W[P0] = R0.L; /* Write */
151 SSYNC; 151 SSYNC;
152#endif 152#endif
@@ -155,12 +155,12 @@ ENTRY(__start)
155 155
156 p0.h = hi(PORTF_FER); 156 p0.h = hi(PORTF_FER);
157 p0.l = lo(PORTF_FER); 157 p0.l = lo(PORTF_FER);
158#ifdef ANOMALY_05000212 158#if ANOMALY_05000212
159 R0.L = W[P0]; /* Read */ 159 R0.L = W[P0]; /* Read */
160 SSYNC; 160 SSYNC;
161#endif 161#endif
162 R0 = 0x000F(Z); 162 R0 = 0x000F(Z);
163#ifdef ANOMALY_05000212 163#if ANOMALY_05000212
164 W[P0] = R0.L; /* Write */ 164 W[P0] = R0.L; /* Write */
165 SSYNC; 165 SSYNC;
166#endif 166#endif
@@ -274,7 +274,7 @@ ENTRY(__start)
274 p0.l = .LWAIT_HERE; 274 p0.l = .LWAIT_HERE;
275 p0.h = .LWAIT_HERE; 275 p0.h = .LWAIT_HERE;
276 reti = p0; 276 reti = p0;
277#if defined(ANOMALY_05000281) 277#if ANOMALY_05000281
278 nop; nop; nop; 278 nop; nop; nop;
279#endif 279#endif
280 rti; 280 rti;
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 06751ae8b857..e5e56df3bf46 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -172,7 +172,7 @@ ENTRY(__stext)
172 p0.l = .LWAIT_HERE; 172 p0.l = .LWAIT_HERE;
173 p0.h = .LWAIT_HERE; 173 p0.h = .LWAIT_HERE;
174 reti = p0; 174 reti = p0;
175#if defined (ANOMALY_05000281) 175#if ANOMALY_05000281
176 nop; 176 nop;
177 nop; 177 nop;
178 nop; 178 nop;
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 38650a628980..b1d0e54a97a9 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -106,14 +106,13 @@ ENTRY(__start)
106 R0 = ~ENICPLB; 106 R0 = ~ENICPLB;
107 R0 = R0 & R1; 107 R0 = R0 & R1;
108 108
109 /* Anomaly 05000125 */ 109#if ANOMALY_05000125
110#ifdef ANOMALY_05000125
111 CLI R2; 110 CLI R2;
112 SSYNC; 111 SSYNC;
113#endif 112#endif
114 [p0] = R0; 113 [p0] = R0;
115 SSYNC; 114 SSYNC;
116#ifdef ANOMALY_05000125 115#if ANOMALY_05000125
117 STI R2; 116 STI R2;
118#endif 117#endif
119 118
@@ -125,13 +124,13 @@ ENTRY(__start)
125 R0 = R0 & R1; 124 R0 = R0 & R1;
126 125
127 /* Anomaly 05000125 */ 126 /* Anomaly 05000125 */
128#ifdef ANOMALY_05000125 127#if ANOMALY_05000125
129 CLI R2; 128 CLI R2;
130 SSYNC; 129 SSYNC;
131#endif 130#endif
132 [p0] = R0; 131 [p0] = R0;
133 SSYNC; 132 SSYNC;
134#ifdef ANOMALY_05000125 133#if ANOMALY_05000125
135 STI R2; 134 STI R2;
136#endif 135#endif
137 136
@@ -220,7 +219,7 @@ ENTRY(__start)
220 p0.l = .LWAIT_HERE; 219 p0.l = .LWAIT_HERE;
221 p0.h = .LWAIT_HERE; 220 p0.h = .LWAIT_HERE;
222 reti = p0; 221 reti = p0;
223#if defined(ANOMALY_05000281) 222#if ANOMALY_05000281
224 nop; nop; nop; 223 nop; nop; nop;
225#endif 224#endif
226 rti; 225 rti;
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 5be6b975ae4a..05c0c77510b2 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,7 +38,7 @@
38 38
39.text 39.text
40 40
41#ifdef ANOMALY_05000125 41#if ANOMALY_05000125
42#if defined(CONFIG_BLKFIN_CACHE) 42#if defined(CONFIG_BLKFIN_CACHE)
43ENTRY(_bfin_write_IMEM_CONTROL) 43ENTRY(_bfin_write_IMEM_CONTROL)
44 44
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S
index e4b47e09cf13..6c256baf087d 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/mach-common/cplbmgr.S
@@ -405,7 +405,7 @@ ENTRY(_cplb_mgr)
405 P3.L = _page_size_table; /* retrieve end address */ 405 P3.L = _page_size_table; /* retrieve end address */
406 P3.H = _page_size_table; /* retrieve end address */ 406 P3.H = _page_size_table; /* retrieve end address */
407 R3 = 0x1002; /* 16th - position, 2 bits -length */ 407 R3 = 0x1002; /* 16th - position, 2 bits -length */
408#ifdef ANOMALY_05000209 408#if ANOMALY_05000209
409 nop; /* Anomaly 05000209 */ 409 nop; /* Anomaly 05000209 */
410#endif 410#endif
411 R7 = EXTRACT(R1,R3.l); 411 R7 = EXTRACT(R1,R3.l);
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 960458808344..207e69786b40 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -69,7 +69,7 @@
69 * patch up CPLB misses on the kernel stack. 69 * patch up CPLB misses on the kernel stack.
70 */ 70 */
71ENTRY(_ex_dcplb) 71ENTRY(_ex_dcplb)
72#if defined(ANOMALY_05000261) 72#if ANOMALY_05000261
73 /* 73 /*
74 * Work around an anomaly: if we see a new DCPLB fault, return 74 * Work around an anomaly: if we see a new DCPLB fault, return
75 * without doing anything. Then, if we get the same fault again, 75 * without doing anything. Then, if we get the same fault again,
@@ -137,7 +137,7 @@ ENTRY(_ex_single_step)
137 137
138_return_from_exception: 138_return_from_exception:
139 DEBUG_START_HWTRACE(p5, r7) 139 DEBUG_START_HWTRACE(p5, r7)
140#ifdef ANOMALY_05000257 140#if ANOMALY_05000257
141 R7=LC0; 141 R7=LC0;
142 LC0=R7; 142 LC0=R7;
143 R7=LC1; 143 R7=LC1;
@@ -634,7 +634,7 @@ ENTRY(_return_from_int)
634 p1.h = _schedule_and_signal_from_int; 634 p1.h = _schedule_and_signal_from_int;
635 [p0] = p1; 635 [p0] = p1;
636 csync; 636 csync;
637#if defined(ANOMALY_05000281) 637#if ANOMALY_05000281
638 r0.l = lo(CONFIG_BOOT_LOAD); 638 r0.l = lo(CONFIG_BOOT_LOAD);
639 r0.h = hi(CONFIG_BOOT_LOAD); 639 r0.h = hi(CONFIG_BOOT_LOAD);
640 reti = r0; 640 reti = r0;
@@ -648,7 +648,7 @@ ENTRY(_return_from_int)
648ENDPROC(_return_from_int) 648ENDPROC(_return_from_int)
649 649
650ENTRY(_lower_to_irq14) 650ENTRY(_lower_to_irq14)
651#if defined(ANOMALY_05000281) 651#if ANOMALY_05000281
652 r0.l = lo(CONFIG_BOOT_LOAD); 652 r0.l = lo(CONFIG_BOOT_LOAD);
653 r0.h = hi(CONFIG_BOOT_LOAD); 653 r0.h = hi(CONFIG_BOOT_LOAD);
654 reti = r0; 654 reti = r0;
@@ -1184,7 +1184,7 @@ _exception_stack:
1184 .endr 1184 .endr
1185_exception_stack_top: 1185_exception_stack_top:
1186 1186
1187#if defined(ANOMALY_05000261) 1187#if ANOMALY_05000261
1188/* Used by the assembly entry point to work around an anomaly. */ 1188/* Used by the assembly entry point to work around an anomaly. */
1189_last_cplb_fault_retx: 1189_last_cplb_fault_retx:
1190 .long 0; 1190 .long 0;
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 203e20709163..14ef800a564d 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -140,7 +140,7 @@ __common_int_entry:
140 fp = 0; 140 fp = 0;
141#endif 141#endif
142 142
143#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315) 143#if ANOMALY_05000283 || ANOMALY_05000315
144 cc = r7 == r7; 144 cc = r7 == r7;
145 p5.h = 0xffc0; 145 p5.h = 0xffc0;
146 p5.l = 0x0014; 146 p5.l = 0x0014;
@@ -163,7 +163,7 @@ ENTRY(_evt_ivhw)
163#ifdef CONFIG_FRAME_POINTER 163#ifdef CONFIG_FRAME_POINTER
164 fp = 0; 164 fp = 0;
165#endif 165#endif
166#ifdef ANOMALY_05000283 166#if ANOMALY_05000283
167 cc = r7 == r7; 167 cc = r7 == r7;
168 p5.h = 0xffc0; 168 p5.h = 0xffc0;
169 p5.l = 0x0014; 169 p5.l = 0x0014;
@@ -207,7 +207,7 @@ ENTRY(_evt_evt2)
207#ifdef CONFIG_FRAME_POINTER 207#ifdef CONFIG_FRAME_POINTER
208 fp = 0; 208 fp = 0;
209#endif 209#endif
210#ifdef ANOMALY_05000283 210#if ANOMALY_05000283
211 cc = r7 == r7; 211 cc = r7 == r7;
212 p5.h = 0xffc0; 212 p5.h = 0xffc0;
213 p5.l = 0x0014; 213 p5.l = 0x0014;
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index 25b934b7f829..1b2dd5a3fe7a 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -17,72 +17,66 @@
17#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
18 18
19/* SSYNC implementation for C file */ 19/* SSYNC implementation for C file */
20#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) 20static inline void SSYNC(void)
21static inline void SSYNC (void)
22{ 21{
23 int _tmp; 22 int _tmp;
24 __asm__ __volatile__ ("cli %0;\n\t" 23 if (ANOMALY_05000312 && ANOMALY_05000244)
25 "nop;nop;\n\t" 24 __asm__ __volatile__(
26 "ssync;\n\t" 25 "cli %0;"
27 "sti %0;\n\t" 26 "nop;"
28 :"=d"(_tmp):); 27 "nop;"
28 "ssync;"
29 "sti %0;"
30 : "=d" (_tmp)
31 );
32 else if (ANOMALY_05000312 && !ANOMALY_05000244)
33 __asm__ __volatile__(
34 "cli %0;"
35 "ssync;"
36 "sti %0;"
37 : "=d" (_tmp)
38 );
39 else if (!ANOMALY_05000312 && ANOMALY_05000244)
40 __asm__ __volatile__(
41 "nop;"
42 "nop;"
43 "nop;"
44 "ssync;"
45 );
46 else
47 __asm__ __volatile__("ssync;");
29} 48}
30#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
31static inline void SSYNC (void)
32{
33 int _tmp;
34 __asm__ __volatile__ ("cli %0;\n\t"
35 "ssync;\n\t"
36 "sti %0;\n\t"
37 :"=d"(_tmp):);
38}
39#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
40static inline void SSYNC (void)
41{
42 __asm__ __volatile__ ("nop; nop; nop;\n\t"
43 "ssync;\n\t"
44 ::);
45}
46#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
47static inline void SSYNC (void)
48{
49 __asm__ __volatile__ ("ssync;\n\t");
50}
51#endif
52 49
53/* CSYNC implementation for C file */ 50/* CSYNC implementation for C file */
54#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) 51static inline void CSYNC(void)
55static inline void CSYNC (void)
56{ 52{
57 int _tmp; 53 int _tmp;
58 __asm__ __volatile__ ("cli %0;\n\t" 54 if (ANOMALY_05000312 && ANOMALY_05000244)
59 "nop;nop;\n\t" 55 __asm__ __volatile__(
60 "csync;\n\t" 56 "cli %0;"
61 "sti %0;\n\t" 57 "nop;"
62 :"=d"(_tmp):); 58 "nop;"
63} 59 "csync;"
64#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) 60 "sti %0;"
65static inline void CSYNC (void) 61 : "=d" (_tmp)
66{ 62 );
67 int _tmp; 63 else if (ANOMALY_05000312 && !ANOMALY_05000244)
68 __asm__ __volatile__ ("cli %0;\n\t" 64 __asm__ __volatile__(
69 "csync;\n\t" 65 "cli %0;"
70 "sti %0;\n\t" 66 "csync;"
71 :"=d"(_tmp):); 67 "sti %0;"
72} 68 : "=d" (_tmp)
73#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) 69 );
74static inline void CSYNC (void) 70 else if (!ANOMALY_05000312 && ANOMALY_05000244)
75{ 71 __asm__ __volatile__(
76 __asm__ __volatile__ ("nop; nop; nop;\n\t" 72 "nop;"
77 "ssync;\n\t" 73 "nop;"
78 ::); 74 "nop;"
79} 75 "ssync;"
80#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) 76 );
81static inline void CSYNC (void) 77 else
82{ 78 __asm__ __volatile__("csync;");
83 __asm__ __volatile__ ("csync;\n\t");
84} 79}
85#endif
86 80
87#else /* __ASSEMBLY__ */ 81#else /* __ASSEMBLY__ */
88 82
@@ -91,19 +85,19 @@ static inline void CSYNC (void)
91#define ssync(x) SSYNC(x) 85#define ssync(x) SSYNC(x)
92#define csync(x) CSYNC(x) 86#define csync(x) CSYNC(x)
93 87
94#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) 88#if ANOMALY_05000312 && ANOMALY_05000244
95#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; 89#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
96#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; 90#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
97 91
98#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) 92#elif ANOMALY_05000312 && !ANOMALY_05000244
99#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; 93#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
100#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; 94#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
101 95
102#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) 96#elif !ANOMALY_05000312 && ANOMALY_05000244
103#define SSYNC(scratch) nop; nop; nop; SSYNC; 97#define SSYNC(scratch) nop; nop; nop; SSYNC;
104#define CSYNC(scratch) nop; nop; nop; CSYNC; 98#define CSYNC(scratch) nop; nop; nop; CSYNC;
105 99
106#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) 100#elif !ANOMALY_05000312 && !ANOMALY_05000244
107#define SSYNC(scratch) SSYNC; 101#define SSYNC(scratch) SSYNC;
108#define CSYNC(scratch) CSYNC; 102#define CSYNC(scratch) CSYNC;
109 103
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 2a63ffc250a1..caea0b0f8326 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,219 +7,252 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List 10 * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List
11 * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List 11 * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
12 * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List 12 * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
13 */ 13 */
14 14
15#ifndef _MACH_ANOMALY_H_ 15#ifndef _MACH_ANOMALY_H_
16#define _MACH_ANOMALY_H_ 16#define _MACH_ANOMALY_H_
17 17
18/* We do not support 0.1 or 0.2 silicon - sorry */ 18/* We do not support 0.1 or 0.2 silicon - sorry */
19#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) 19#if __SILICON_REVISION__ < 3
20#error Kernel will not work on BF533 Version 0.1 or 0.2 20# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2
21#endif 21#endif
22 22
23/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ 23#if defined(__ADSPBF531__)
24#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ 24# define ANOMALY_BF531 1
25 || defined(CONFIG_BF_REV_0_3)) 25#else
26#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 26# define ANOMALY_BF531 0
27 * slot1 and store of a P register in slot 2 is not 27#endif
28 * supported */ 28#if defined(__ADSPBF532__)
29#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on 29# define ANOMALY_BF532 1
30 * every corresponding match */ 30#else
31#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive 31# define ANOMALY_BF532 0
32 * Channel DMA stops */ 32#endif
33#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR 33#if defined(__ADSPBF533__)
34 * registers. */ 34# define ANOMALY_BF533 1
35#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out 35#else
36 * upper bits*/ 36# define ANOMALY_BF533 0
37#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ 37#endif
38#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
39 * syncs */
40#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
41 * functional */
42#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
43 * state */
44#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
45#define ANOMALY_05000272 /* Certain data cache write through modes fail for
46 * VDDint <=0.9V */
47#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
48#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
49 * an edge is detected may clear interrupt */
50#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
51 * DMA system instability */
52#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
53 * not restored */
54#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
55 * control */
56#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
57 * killed in a particular stage*/
58#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
59 * sequences */
60#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
61 * registers are interrupted */
62#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
63#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
64 * Next System MMR Access */
65#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
66 * and 1.15V Not Allowed for LQFP Packages */
67#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
68 38
69/* These issues only occur on 0.3 or 0.4 BF533 */ 39/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
70#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) 40#define ANOMALY_05000074 (1)
71#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not 41/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
72 * updated at the same time. */ 42#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
73#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data 43/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
74 * Cache Fill can be corrupted after or during 44#define ANOMALY_05000105 (1)
75 * Instruction DMA if certain core stalls exist */ 45/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
76#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General 46#define ANOMALY_05000119 (1)
77 * Purpose TX or RX modes */ 47/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
78#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by 48#define ANOMALY_05000122 (1)
79 * preceding memory read */ 49/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
80#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during 50#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
81 * inactive channels in certain conditions */ 51/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag 52#define ANOMALY_05000166 (1)
83 * situation */ 53/* Turning Serial Ports on with External Frame Syncs */
84#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ 54#define ANOMALY_05000167 (1)
85#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ 55/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
86#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect 56#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
87 * data*/ 57/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
88#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate 58#define ANOMALY_05000180 (1)
89 * Differences in certain Conditions */ 59/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
90#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ 60#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
91#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to 61/* False Protection Exceptions */
92 * hardware reset */ 62#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
93#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 63/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
94 * IDLE around a Change of Control causes 64#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
95 * unpredictable results */ 65/* Restarting SPORT in Specific Modes May Cause Data Corruption */
96#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the 66#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
97 * shadow of a conditional branch */ 67/* Failing MMR Accesses When Stalled by Preceding Memory Read */
98#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware 68#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
99 * errors */ 69/* Current DMA Address Shows Wrong Value During Carry Fix */
100#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ 70#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
101#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event 71/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
102 * interrupt not functional */ 72#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
103#define ANOMALY_05000257 /* An interrupt or exception during short Hardware 73/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
104 * loops may cause the instruction fetch unit to 74#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
105 * malfunction */ 75/* Possible Infinite Stall with Specific Dual-DAG Situation */
106#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of 76#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
107 * the ICPLB Data registers differ */ 77/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
108#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ 78#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
109#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ 79/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
110#define ANOMALY_05000262 /* Stores to data cache may be lost */ 80#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
111#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ 81/* Recovery from "Brown-Out" Condition */
112#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE 82#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
113 * instruction will cause an infinite stall in the 83/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
114 * second to last instruction in a hardware loop */ 84#define ANOMALY_05000208 (1)
115#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 85/* Speed Path in Computational Unit Affects Certain Instructions */
116 * SPORT external receive and transmit clocks. */ 86#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
117#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the 87/* UART TX Interrupt Masked Erroneously */
118 * internal voltage regulator (VDDint) to increase. */ 88#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
119#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the 89/* NMI Event at Boot Time Results in Unpredictable State */
120 * internal voltage regulator (VDDint) to decrease */ 90#define ANOMALY_05000219 (1)
121#endif /* issues only occur on 0.3 or 0.4 BF533 */ 91/* Incorrect Pulse-Width of UART Start Bit */
92#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
93/* Scratchpad Memory Bank Reads May Return Incorrect Data */
94#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
95/* SPI Slave Boot Mode Modifies Registers from Reset Value */
96#define ANOMALY_05000229 (1)
97/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
98#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
99/* UART STB Bit Incorrectly Affects Receiver Setting */
100#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
101/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
102#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
103/* Incorrect Revision Number in DSPID Register */
104#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
105/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
106#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
107/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
108#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
109/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
110#define ANOMALY_05000245 (1)
111/* Data CPLBs Should Prevent Spurious Hardware Errors */
112#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
113/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
114#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
115/* Maximum External Clock Speed for Timers */
116#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
117/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
118#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
119/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
120#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
121/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
122#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
123/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
124#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
125/* ICPLB_STATUS MMR Register May Be Corrupted */
126#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
127/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
128#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
129/* Stores To Data Cache May Be Lost */
130#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
131/* Hardware Loop Corrupted When Taking an ICPLB Exception */
132#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
133/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
134#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
135/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
136#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
138#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
139/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
140#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
141/* Spontaneous Reset of Internal Voltage Regulator */
142#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
143/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
144#define ANOMALY_05000272 (1)
145/* Writes to Synchronous SDRAM Memory May Be Lost */
146#define ANOMALY_05000273 (1)
147/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
148#define ANOMALY_05000276 (1)
149/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
150#define ANOMALY_05000277 (1)
151/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
152#define ANOMALY_05000278 (1)
153/* False Hardware Error Exception When ISR Context Is Not Restored */
154#define ANOMALY_05000281 (1)
155/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
156#define ANOMALY_05000282 (1)
157/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
158#define ANOMALY_05000283 (1)
159/* SPORTs May Receive Bad Data If FIFOs Fill Up */
160#define ANOMALY_05000288 (1)
161/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
162#define ANOMALY_05000301 (1)
163/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
164#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
166#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
167/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
168#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
169/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
170#define ANOMALY_05000310 (1)
171/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
172#define ANOMALY_05000311 (1)
173/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
174#define ANOMALY_05000312 (1)
175/* PPI Is Level-Sensitive on First Transfer */
176#define ANOMALY_05000313 (1)
177/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
178#define ANOMALY_05000315 (1)
179/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
180#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
122 181
123/* These issues are only on 0.4 silicon */ 182/* These anomalies have been "phased" out of analog.com anomaly sheets and are
124#if (defined(CONFIG_BF_REV_0_4)) 183 * here to show running on older silicon just isn't feasible.
125#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ 184 */
126#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
127 * (TDM) */
128#endif /* issues are only on 0.4 silicon */
129 185
130/* These issues are only on 0.3 silicon */ 186/* Watchpoints (Hardware Breakpoints) are not supported */
131#if defined(CONFIG_BF_REV_0_3) 187#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
132#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with 188/* Reserved bits in SYSCFG register not set at power on */
133 * External Frame Syncs */ 189#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
134#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative 190/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
135 * Instruction or Data Fetches, or by Fetches at the 191#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
136 * boundary of reserved memory space */ 192/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
137#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs 193#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
138 * when polarity setting is changed */ 194/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
139#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data 195#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
140 * corruption */ 196/* Erroneous exception when enabling cache */
141#define ANOMALY_05000199 /* DMA current address shows wrong value during carry 197#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
142 * fix */ 198/* SPI clock polarity and phase bits incorrect during booting */
143#define ANOMALY_05000201 /* Receive frame sync not ignored during active 199#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
144 * frames in sport MCM */ 200/* DMEM_CONTROL is not set on Reset */
145#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA 201#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
146 * stopping */ 202/* SPI boot will not complete if there is a zero fill block in the loader file */
147#if defined(CONFIG_BF533) 203#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
148#define ANOMALY_05000204 /* Incorrect data read with write-through cache and 204/* Allowing the SPORT RX FIFO to fill will cause an overflow */
149 * allocate cache lines on reads only mode */ 205#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
150#endif /* CONFIG_BF533 */ 206/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
151#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ 207#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
152#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain 208/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
153 * instructions */ 209#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
154#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame 210/* A read from external memory may return a wrong value with data cache enabled */
155 * Sync Transmit Mode */ 211#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
156#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ 212/* DMA and TESTSET conflict when both are accessing external memory */
157#endif /* only on 0.3 silicon */ 213#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
214/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
215#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
216/* MDMA may lose the first few words of a descriptor chain */
217#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
218/* The source MDMA descriptor may stop with a DMA Error */
219#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
220/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
221#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
222/* Frame Delay in SPORT Multichannel Mode */
223#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
224/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
225#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
226/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
227#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
228/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
229#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
230/* SPORT transmit data is not gated by external frame sync in certain conditions */
231#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
232/* SDRAM auto-refresh and subsequent Power Ups */
233#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
234/* DATA CPLB page miss can result in lost write-through cache data writes */
235#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
236/* DMA vs Core accesses to external memory */
237#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
238/* Cache Fill Buffer Data lost */
239#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
240/* Overlapping Sequencer and Memory Stalls */
241#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
242/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
243#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
244/* Disabling the PPI resets the PPI configuration registers */
245#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
246/* PPI TX Mode with 2 External Frame Syncs */
247#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
248/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
249#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
250/* In PPI Transmit Modes with External Frame Syncs POLC */
251#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
252/* Internal Voltage Regulator may not start up */
253#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
158 254
159#if defined(CONFIG_BF_REV_0_2) 255/* Anomalies that don't exist on this proc */
160#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not 256#define ANOMALY_05000266 (0)
161 * supported */
162#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
163 * power on */
164#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
165 * emulation mode and/or exception, NMI, reset
166 * handlers */
167#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
168 * incorrect if data cache or DMA is active */
169#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
170 * or 1:1 */
171#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
172#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
173 * during booting */
174#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
175#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
176 * block in the loader file */
177#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
178 * overflow */
179#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
180 * of consecutive dual dag events */
181#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
182 * flag is configured to be edge sensitive */
183#define ANOMALY_05000143 /* A read from external memory may return a wrong
184 * value with data cache enabled */
185#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
186 * external memory */
187#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
188 * generate a waveform from PPI_CLK */
189#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
190 * chain */
191#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
192 * Error */
193#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
194 * device, the upper 8-bits of each word must be
195 * 0x00 */
196#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
197#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
198 * outside of valid channels */
199#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
200 * certain PPI mode is in use */
201#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
202 * the next system MMR access thinking it should be
203 * 32-bit. */
204#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
205 * sync in certain conditions */
206#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
207#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
208 * write-through cache data writes */
209#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
210#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
211#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
212#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
213 * accumulator saturation */
214#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
215 * registers */
216#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
217#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
218 * Transmit Modes */
219#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
220 * POLC */
221#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
222 257
223#endif 258#endif
224
225#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
index 185fc1284858..41e4e834e2d3 100644
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -226,7 +226,7 @@
226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly 226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
227#endif 227#endif
228 228
229#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) 229#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK 230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
231#endif 231#endif
232 232
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 5c5e33dec5f1..dc736c61980f 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,109 +7,137 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
11 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List 11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
12 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List 12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
13 */ 13 */
14 14
15#ifndef _MACH_ANOMALY_H_ 15#ifndef _MACH_ANOMALY_H_
16#define _MACH_ANOMALY_H_ 16#define _MACH_ANOMALY_H_
17 17
18/* We do not support 0.1 silicon - sorry */ 18/* We do not support 0.1 silicon - sorry */
19#if (defined(CONFIG_BF_REV_0_1)) 19#if __SILICON_REVISION__ < 2
20#error Kernel will not work on BF537/6/4 Version 0.1 20# error Kernel will not work on BF537 silicon version 0.0 or 0.1
21#endif 21#endif
22 22
23#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) 23#if defined(__ADSPBF534__)
24#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 24# define ANOMALY_BF534 1
25 * slot1 and store of a P register in slot 2 is not 25#else
26 * supported */ 26# define ANOMALY_BF534 0
27#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
28 * Channel DMA stops */
29#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
30 * registers. */
31#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
32 * upper bits*/
33#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
34 * syncs */
35#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
36#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
37 * Changed */
38#endif 27#endif
39#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 28#if defined(__ADSPBF536__)
40 * SPORT external receive and transmit clocks. */ 29# define ANOMALY_BF536 1
41#define ANOMALY_05000272 /* Certain data cache write through modes fail for 30#else
42 * VDDint <=0.9V */ 31# define ANOMALY_BF536 0
43#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
44#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
45 * an edge is detected may clear interrupt */
46#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
47 * not restored */
48#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
49 * control */
50#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
51 * killed in a particular stage*/
52#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
53 * boundary of reserved memory */
54#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
55 * registers are interrupted */
56#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
57#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
58 * received properly */
59#endif 32#endif
60 33#if defined(__ADSPBF537__)
61#if defined(CONFIG_BF_REV_0_2) 34# define ANOMALY_BF537 1
62#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 35#else
63 * IDLE around a Change of Control causes 36# define ANOMALY_BF537 0
64 * unpredictable results */
65#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
66 * (TDM) */
67#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
68#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
69#endif
70#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
71#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
72 * interrupt not functional */
73#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
74#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
75#endif 37#endif
76#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
77 * loops may cause the instruction fetch unit to
78 * malfunction */
79#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
80 * the ICPLB Data registers differ */
81#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
82#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
83#define ANOMALY_05000262 /* Stores to data cache may be lost */
84#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
85#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
86 * instruction will cause an infinite stall in the
87 * second to last instruction in a hardware loop */
88#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
89 * and non-zero DEB_TRAFFIC_PERIOD value */
90#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
91 * internal voltage regulator (VDDint) to decrease */
92#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
93 * an edge is detected may clear interrupt */
94#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
95 * DMA system instability */
96#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
97 * Atmel Dataflash devices */
98#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
99 * is not restored */
100#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
101 * control */
102#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
103 * Killed in a Particular Stage */
104#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
105 * (Not Available On Older Silicon) */
106#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
107#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
108 * On Next System MMR Access */
109#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
110 * mode */
111#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
112 * status No Carrier */
113#endif /* CONFIG_BF_REV_0_2 */
114 38
115#endif /* _MACH_ANOMALY_H_ */ 39/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
40#define ANOMALY_05000074 (1)
41/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
42#define ANOMALY_05000119 (1)
43/* Rx.H cannot be used to access 16-bit System MMR registers */
44#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
47/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/
48#define ANOMALY_05000166 (1) /* XXX: deleted from BF537 sheet ? */
49/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
50#define ANOMALY_05000180 (1)
51/* Instruction Cache Is Not Functional */
52#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
53/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
54#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
55/* Spurious Hardware Error from an access in the shadow of a conditional branch */
56#define ANOMALY_05000245 (1)
57/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
58#define ANOMALY_05000247 (1)
59/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
60#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
61/* EMAC Tx DMA error after an early frame abort */
62#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
63/* Maximum external clock speed for Timers */
64#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
65/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
66#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
67/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
68#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
69/* EMAC MDIO input latched on wrong MDC edge */
70#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
71/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
72#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
73/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
74#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
75/* ICPLB_STATUS MMR register may be corrupted */
76#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
77/* DCPLB_FAULT_ADDR MMR register may be corrupted */
78#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
79/* Stores to data cache may be lost */
80#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
81/* Hardware loop corrupted when taking an ICPLB exception */
82#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
83/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
84#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
85/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
86#define ANOMALY_05000265 (1)
87/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
88#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
89/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
90#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
91/* Certain data cache write through modes fail for VDDint <=0.9V */
92#define ANOMALY_05000272 (1)
93/* Writes to Synchronous SDRAM memory may be lost */
94#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
95/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
96#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
97/* Disabling Peripherals with DMA running may cause DMA system instability */
98#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
99/* SPI Master boot mode does not work well with Atmel Data flash devices */
100#define ANOMALY_05000280 (1)
101/* False Hardware Error Exception when ISR context is not restored */
102#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
103/* Memory DMA corruption with 32-bit data and traffic control */
104#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
105/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
106#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
107/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
108#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
109/* SPORTs may receive bad data if FIFOs fill up */
110#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
111/* Memory to memory DMA source/destination descriptors must be in same memory space */
112#define ANOMALY_05000301 (1)
113/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
114#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
115/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
116#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
117/* SCKELOW Bit Does Not Maintain State Through Hibernate */
118#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
119/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
120#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
121/* False hardware errors caused by fetches at the boundary of reserved memory */
122#define ANOMALY_05000310 (1)
123/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
124#define ANOMALY_05000312 (1)
125/* PPI is level sensitive on first transfer */
126#define ANOMALY_05000313 (1)
127/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
128#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: collisions occur in Full Duplex mode */
130#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
132#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
133/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
134#define ANOMALY_05000322 (1)
135
136/* Anomalies that don't exist on this proc */
137#define ANOMALY_05000125 (0)
138#define ANOMALY_05000183 (0)
139#define ANOMALY_05000198 (0)
140#define ANOMALY_05000266 (0)
141#define ANOMALY_05000311 (0)
142
143#endif
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index b8924cd7730c..04b08164e292 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -206,7 +206,7 @@
206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly 206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207#endif 207#endif
208 208
209#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) 209#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK 210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
211#endif 211#endif
212 212
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 964a1c0ea637..952f03e140f2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -6,46 +6,62 @@
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with:
10 * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List
11 */
12
9#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
10#define _MACH_ANOMALY_H_ 14#define _MACH_ANOMALY_H_
11 15
12#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
13 * slot1 and store of a P register in slot 2 is not 17#define ANOMALY_05000074 (1)
14 * supported */ 18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
15#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive 19#define ANOMALY_05000119 (1)
16 * Channel DMA stops */ 20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
17#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR 21#define ANOMALY_05000122 (1)
18 * registers. */ 22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
19#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the 23#define ANOMALY_05000245 (1)
20 * Shadow of a Conditional Branch */ 24/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
21#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event 25#define ANOMALY_05000255 (1)
22 * interrupt not functional */ 26/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 27#define ANOMALY_05000265 (1)
24 * SPORT external receive and transmit clocks. */ 28/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
25#define ANOMALY_05000272 /* Certain data cache write through modes fail for 29#define ANOMALY_05000272 (1)
26 * VDDint <=0.9V */ 30/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
27#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is 31#define ANOMALY_05000310 (1)
28 * not restored */ 32/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the 33#define ANOMALY_05000312 (1)
30 * Boundary of Reserved Memory */ 34/* TWI Slave Boot Mode Is Not Functional */
31#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and 35#define ANOMALY_05000324 (1)
32 * LC Registers Are Interrupted */ 36/* External FIFO Boot Mode Is Not Functional */
33#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ 37#define ANOMALY_05000325 (1)
34#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ 38/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
35#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to 39#define ANOMALY_05000327 (1)
36 * the USB FIFO Simultaneously */ 40/* Incorrect Access of OTP_STATUS During otp_write() Function */
37#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() 41#define ANOMALY_05000328 (1)
38 * function */ 42/* Synchronous Burst Flash Boot Mode Is Not Functional */
39#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional 43#define ANOMALY_05000329 (1)
40 * */ 44/* Host DMA Boot Mode Is Not Functional */
41#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ 45#define ANOMALY_05000330 (1)
42#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM 46/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
43 * Skew */ 47#define ANOMALY_05000334 (1)
44#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ 48/* Inadequate Rotary Debounce Logic Duration */
45#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration 49#define ANOMALY_05000335 (1)
46 * of Host DMA Port */ 50/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
47#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent 51#define ANOMALY_05000336 (1)
48 * Allowed Configuration on Host DMA Port */ 52/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
49#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 53#define ANOMALY_05000337 (1)
54/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
55#define ANOMALY_05000338 (1)
56
57/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0)
59#define ANOMALY_05000183 (0)
60#define ANOMALY_05000198 (0)
61#define ANOMALY_05000244 (0)
62#define ANOMALY_05000263 (0)
63#define ANOMALY_05000266 (0)
64#define ANOMALY_05000273 (0)
65#define ANOMALY_05000311 (0)
50 66
51#endif /* _MACH_ANOMALY_H_ */ 67#endif
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 5a7986a83bee..4cb3337d45ee 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,155 +7,249 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision L, Aug 10, 2006; ADSP-BF561 Silicon Anomaly List 10 * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_ 14#define _MACH_ANOMALY_H_
15 15
16/* We do not support 0.1 or 0.4 silicon - sorry */ 16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) 17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 18# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Issues that are common to 0.5 and 0.3 silicon */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
22#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) 22#define ANOMALY_05000074 (1)
23#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24 * slot1 and store of a P register in slot 2 is not 24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25 * supported */ 25/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
26#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not 26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27 * updated at the same time. */ 27/* Testset instructions restricted to 32-bit aligned memory locations */
28#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned 28#define ANOMALY_05000120 (1)
29 * memory locations */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR 30#define ANOMALY_05000122 (1)
31 * registers */ 31/* Erroneous exception when enabling cache */
32#define ANOMALY_05000127 /* Signbits instruction not functional under certain 32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33 * conditions */ 33/* Signbits instruction not functional under certain conditions */
34#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ 34#define ANOMALY_05000127 (1)
35#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out 35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36 * upper bits */ 36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
37#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ 37/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
38#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame 38#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
39 * syncs */ 39/* Stall in multi-unit DMA operations */
40#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz 40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41 * and higher devices */ 41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ 42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ 43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not 44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45 * functional */ 45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the 46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
47 * shadow of a conditional branch */ 47/* DMA and TESTSET conflict when both are accessing external memory */
48#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop 48#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
49 * may cause bad instruction fetches */ 49/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
50#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 50#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
51 * external SPORT TX and RX clocks */ 51/* MDMA may lose the first few words of a descriptor chain */
52#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ 52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal 53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54 * voltage regulator (VDDint) to increase */ 54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal 55/* IMDMA S1/D1 channel may stall */
56 * voltage regulator (VDDint) to decrease */ 56#define ANOMALY_05000149 (1)
57#define ANOMALY_05000272 /* Certain data cache write through modes fail for 57/* DMA engine may lose data due to incorrect handshaking */
58 * VDDint <=0.9V */ 58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
59#define ANOMALY_05000274 /* Data cache write back to external synchronous memory 59/* DMA stalls when all three controllers read data from the same source */
60 * may be lost */ 60#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
61#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ 61/* Execution stall when executing in L2 and doing external accesses */
62#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC 62#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
63 * registers are interrupted */ 63/* Frame Delay in SPORT Multichannel Mode */
64#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73/* A read from external memory may return a wrong value with data cache enabled */
74#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1)
83/* Turning Serial Ports on with External Frame Syncs */
84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93/* DMA vs Core accesses to external memory */
94#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95/* Cache Fill Buffer Data lost */
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */
108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */
122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144#define ANOMALY_05000208 (1)
145/* Speed Path in Computational Unit Affects Certain Instructions */
146#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147/* UART TX Interrupt Masked Erroneously */
148#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149/* NMI Event at Boot Time Results in Unpredictable State */
150#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153/* Incorrect Pulse-Width of UART Start Bit */
154#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155/* Scratchpad Memory Bank Reads May Return Incorrect Data */
156#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173/* Exception Not Generated for MMR Accesses in Reserved Region */
174#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175/* Maximum External Clock Speed for Timers */
176#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183/* ICPLB_STATUS MMR Register May Be Corrupted */
184#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187/* Stores To Data Cache May Be Lost */
188#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189/* Hardware Loop Corrupted When Taking an ICPLB Exception */
190#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */
198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1)
201/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */
206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
212#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
213/* False Hardware Error Exception When ISR Context Is Not Restored */
214#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
215/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
216#define ANOMALY_05000283 (1)
217/* A read will receive incorrect data under certain conditions */
218#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
219/* SPORTs May Receive Bad Data If FIFOs Fill Up */
220#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
221/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
222#define ANOMALY_05000301 (1)
223/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
224#define ANOMALY_05000302 (1)
225/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
226#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
227/* SCKELOW Bit Does Not Maintain State Through Hibernate */
228#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
229/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
230#define ANOMALY_05000310 (1)
231/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
232#define ANOMALY_05000312 (1)
233/* PPI Is Level-Sensitive on First Transfer */
234#define ANOMALY_05000313 (1)
235/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
236#define ANOMALY_05000315 (1)
237/* PF2 Output Remains Asserted After SPI Master Boot */
238#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
239/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
240#define ANOMALY_05000323 (1)
241/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
242#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
243/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
244#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
245/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
246#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
247/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
64 249
65#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ 250/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000183 (0)
252#define ANOMALY_05000273 (0)
253#define ANOMALY_05000311 (0)
66 254
67#if (defined(CONFIG_BF_REV_0_5))
68#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
69 * mode with external clock */
70#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
71 * using IMDMA */
72#endif 255#endif
73
74#if (defined(CONFIG_BF_REV_0_3))
75#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
76 * Mode with 0 Frame Syncs */
77#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
78#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
79 * cache data writes */
80#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
81#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
82#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
83#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
84 * accumulator saturation */
85#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
86 * Purpose TX or RX modes */
87#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
88 * registers */
89#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
90 * External Frame Syncs */
91#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
92#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
93 * (not a meaningful mode) */
94#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
95 * Placement in Memory */
96#define ANOMALY_05000189 /* False Protection Exception */
97#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
98 * when polarity setting is changed */
99#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
100 * corruption */
101#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
102 * memory read */
103#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
104 * fix */
105#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
106 * inactive channels in certain conditions */
107#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
108 * situation */
109#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
110 * allocate cache lines on reads only mode */
111#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
112 * stopping */
113#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
114#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
115 * instructions */
116#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
117#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
118 * state */
119#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
120 * Non-Cached On-Chip L2 Memory */
121#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
122#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
123 * data */
124#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
125 * Differences in certain Conditions */
126#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
127#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
128 * multichannel mode */
129#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
130 * hardware reset */
131#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
132 * Control causes failures */
133#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
134#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
135 * (TDM) mode in certain conditions */
136#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
137 * reserved region */
138#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
139#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
140 * of the ICPLB Data registers differ */
141#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
142#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
143#define ANOMALY_05000262 /* Stores to data cache may be lost */
144#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
145 * exception */
146#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
147 * to last instruction in hardware loop */
148#define ANOMALY_05000276 /* Timing requirements change for External Frame
149 * Sync PPI Modes with non-zero PPI_DELAY */
150#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
151 * DMA system instability */
152#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
153 * not restored */
154#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
155 * in a particular stage */
156#define ANOMALY_05000287 /* A read will receive incorrect data under certain
157 * conditions */
158#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
159#endif
160
161#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 96a5d3a47e45..8cc2e0033e0a 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -311,7 +311,7 @@
311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly 311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
312#endif 312#endif
313 313
314#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) 314#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK 315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
316#endif 316#endif
317 317
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 94ed381e5606..ede210eca4ec 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,7 +39,7 @@
39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) 39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) 40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) 41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#ifdef ANOMALY_05000125 42#if ANOMALY_05000125
43extern void bfin_write_DMEM_CONTROL(unsigned int val); 43extern void bfin_write_DMEM_CONTROL(unsigned int val);
44#else 44#else
45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) 45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
@@ -129,7 +129,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
129#define DTEST_DATA3 0xFFE0040C 129#define DTEST_DATA3 0xFFE0040C
130*/ 130*/
131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) 131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
132#ifdef ANOMALY_05000125 132#if ANOMALY_05000125
133extern void bfin_write_IMEM_CONTROL(unsigned int val); 133extern void bfin_write_IMEM_CONTROL(unsigned int val);
134#else 134#else
135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) 135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index be1ece8c0c27..260515d15280 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -33,81 +33,77 @@
33 33
34#include <asm/mach/anomaly.h> 34#include <asm/mach/anomaly.h>
35 35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x) 36#define MK_BMSK_(x) (1<<x)
42 37
43#if defined(ANOMALY_05000198) 38#ifndef __ASSEMBLY__
44
45#define bfin_read8(addr) ({ unsigned char __v; \
46 __asm__ __volatile__ ("NOP;\n\t" \
47 "%0 = b[%1] (z);\n\t" \
48 : "=d"(__v) : "a"(addr)); \
49 __v; })
50
51#define bfin_read16(addr) ({ unsigned __v; \
52 __asm__ __volatile__ ("NOP;\n\t"\
53 "%0 = w[%1] (z);\n\t"\
54 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
55
56#define bfin_read32(addr) ({ unsigned __v; \
57 __asm__ __volatile__ ("NOP;\n\t"\
58 "%0 = [%1];\n\t"\
59 : "=d"(__v) : "a"(addr)); __v; })
60 39
61#define bfin_write8(addr, val) ({ \ 40#include <linux/types.h>
62 __asm__ __volatile__ ("NOP;\n\t" \
63 "b[%0] = %1;\n\t" \
64 : : "a"(addr), "d"(val) : "memory");})
65
66#define bfin_write16(addr,val) ({\
67 __asm__ __volatile__ ("NOP;\n\t"\
68 "w[%0] = %1;\n\t"\
69 : : "a"(addr) , "d"(val) : "memory");})
70
71#define bfin_write32(addr,val) ({\
72 __asm__ __volatile__ ("NOP;\n\t"\
73 "[%0] = %1;\n\t"\
74 : : "a"(addr) , "d"(val) : "memory");})
75 41
42#if ANOMALY_05000198
43# define NOP_PAD_ANOMALY_05000198 "nop;"
76#else 44#else
77 45# define NOP_PAD_ANOMALY_05000198
78#define bfin_read8(addr) ({ unsigned char __v; \
79 __asm__ __volatile__ ( \
80 "%0 = b[%1] (z);\n\t" \
81 :"=d"(__v) : "a"(addr)); \
82 __v; })
83
84#define bfin_read16(addr) ({ unsigned __v; \
85 __asm__ __volatile__ (\
86 "%0 = w[%1] (z);\n\t"\
87 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
88
89#define bfin_read32(addr) ({ unsigned __v; \
90 __asm__ __volatile__ (\
91 "%0 = [%1];\n\t"\
92 : "=d"(__v) : "a"(addr)); __v; })
93
94#define bfin_write8(addr, val) ({ \
95 __asm__ __volatile__ ( \
96 "b[%0] = %1; \n\t" \
97 ::"a"(addr), "d"(val) : "memory");})
98
99#define bfin_write16(addr,val) ({\
100 __asm__ __volatile__ (\
101 "w[%0] = %1;\n\t"\
102 : : "a"(addr) , "d"(val) : "memory");})
103
104#define bfin_write32(addr,val) ({\
105 __asm__ __volatile__ (\
106 "[%0] = %1;\n\t"\
107 : : "a"(addr) , "d"(val) : "memory");})
108
109#endif 46#endif
110 47
48#define bfin_read8(addr) ({ \
49 uint8_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58#define bfin_read16(addr) ({ \
59 uint16_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68#define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78#define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" (val) \
84 : "memory" \
85 )
86
87#define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" (val) \
93 : "memory" \
94 )
95
96#define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105#endif /* __ASSEMBLY__ */
106
111/************************************************** 107/**************************************************
112 * System Register Bits 108 * System Register Bits
113 **************************************************/ 109 **************************************************/
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
index 5e5f1a0566c0..b03cf7d5b9a3 100644
--- a/include/asm-blackfin/system.h
+++ b/include/asm-blackfin/system.h
@@ -36,6 +36,7 @@
36 36
37#include <linux/linkage.h> 37#include <linux/linkage.h>
38#include <linux/compiler.h> 38#include <linux/compiler.h>
39#include <asm/mach/anomaly.h>
39 40
40/* 41/*
41 * Interrupt configuring macros. 42 * Interrupt configuring macros.
@@ -43,53 +44,60 @@
43 44
44extern unsigned long irq_flags; 45extern unsigned long irq_flags;
45 46
46#define local_irq_enable() do { \ 47#define local_irq_enable() \
47 __asm__ __volatile__ ( \ 48 __asm__ __volatile__( \
48 "sti %0;" \ 49 "sti %0;" \
49 ::"d"(irq_flags)); \ 50 : \
50} while (0) 51 : "d" (irq_flags) \
52 )
51 53
52#define local_irq_disable() do { \ 54#define local_irq_disable() \
53 int _tmp_dummy; \ 55 do { \
54 __asm__ __volatile__ ( \ 56 int __tmp_dummy; \
55 "cli %0;" \ 57 __asm__ __volatile__( \
56 :"=d" (_tmp_dummy):); \ 58 "cli %0;" \
57} while (0) 59 : "=d" (__tmp_dummy) \
60 ); \
61 } while (0)
58 62
59#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE) 63#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE)
60#define idle_with_irq_disabled() do { \ 64# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
61 __asm__ __volatile__ ( \
62 "nop; nop;\n" \
63 ".align 8;\n" \
64 "sti %0; idle;\n" \
65 ::"d" (irq_flags)); \
66} while (0)
67#else 65#else
68#define idle_with_irq_disabled() do { \ 66# define NOP_PAD_ANOMALY_05000244
69 __asm__ __volatile__ ( \
70 ".align 8;\n" \
71 "sti %0; idle;\n" \
72 ::"d" (irq_flags)); \
73} while (0)
74#endif 67#endif
75 68
69#define idle_with_irq_disabled() \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000244 \
72 ".align 8;" \
73 "sti %0;" \
74 "idle;" \
75 : \
76 : "d" (irq_flags) \
77 )
78
76#ifdef CONFIG_DEBUG_HWERR 79#ifdef CONFIG_DEBUG_HWERR
77#define __save_and_cli(x) do { \ 80# define __save_and_cli(x) \
78 __asm__ __volatile__ ( \ 81 __asm__ __volatile__( \
79 "cli %0;\n\tsti %1;" \ 82 "cli %0;" \
80 :"=&d"(x): "d" (0x3F)); \ 83 "sti %1;" \
81} while (0) 84 : "=&d" (x) \
85 : "d" (0x3F) \
86 )
82#else 87#else
83#define __save_and_cli(x) do { \ 88# define __save_and_cli(x) \
84 __asm__ __volatile__ ( \ 89 __asm__ __volatile__( \
85 "cli %0;" \ 90 "cli %0;" \
86 :"=&d"(x):); \ 91 : "=&d" (x) \
87} while (0) 92 )
88#endif 93#endif
89 94
90#define local_save_flags(x) asm volatile ("cli %0;" \ 95#define local_save_flags(x) \
91 "sti %0;" \ 96 __asm__ __volatile__( \
92 :"=d"(x):); 97 "cli %0;" \
98 "sti %0;" \
99 : "=d" (x) \
100 )
93 101
94#ifdef CONFIG_DEBUG_HWERR 102#ifdef CONFIG_DEBUG_HWERR
95#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0) 103#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
@@ -97,10 +105,11 @@ extern unsigned long irq_flags;
97#define irqs_enabled_from_flags(x) ((x) != 0x1f) 105#define irqs_enabled_from_flags(x) ((x) != 0x1f)
98#endif 106#endif
99 107
100#define local_irq_restore(x) do { \ 108#define local_irq_restore(x) \
101 if (irqs_enabled_from_flags(x)) \ 109 do { \
102 local_irq_enable (); \ 110 if (irqs_enabled_from_flags(x)) \
103} while (0) 111 local_irq_enable(); \
112 } while (0)
104 113
105/* For spinlocks etc */ 114/* For spinlocks etc */
106#define local_irq_save(x) __save_and_cli(x) 115#define local_irq_save(x) __save_and_cli(x)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 02:00:02 -0500