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-rw-r--r--arch/arm/mach-ep93xx/core.c44
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h15
2 files changed, 38 insertions, 21 deletions
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1905676b08b2..90fb591cbffa 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -84,13 +84,40 @@ void __init ep93xx_map_io(void)
84 * to use this timer for something else. We also use timer 4 for keeping 84 * to use this timer for something else. We also use timer 4 for keeping
85 * track of lost jiffies. 85 * track of lost jiffies.
86 */ 86 */
87static unsigned int last_jiffy_time; 87#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
88 88#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
89#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
90#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
91#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
92#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
93#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
94#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
95#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
96#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
97#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
98#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
99#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
100#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
101#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
102#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
103#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
104#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
105#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
106
107#define EP93XX_TIMER123_CLOCK 508469
108#define EP93XX_TIMER4_CLOCK 983040
109
110#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
89#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) 111#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
90 112
113static unsigned int last_jiffy_time;
114
91static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 115static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
92{ 116{
117 /* Writing any value clears the timer interrupt */
93 __raw_writel(1, EP93XX_TIMER1_CLEAR); 118 __raw_writel(1, EP93XX_TIMER1_CLEAR);
119
120 /* Recover lost jiffies */
94 while ((signed long) 121 while ((signed long)
95 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) 122 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
96 >= TIMER4_TICKS_PER_JIFFY) { 123 >= TIMER4_TICKS_PER_JIFFY) {
@@ -109,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = {
109 136
110static void __init ep93xx_timer_init(void) 137static void __init ep93xx_timer_init(void)
111{ 138{
139 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
140 EP93XX_TIMER123_CONTROL_CLKSEL;
141
112 /* Enable periodic HZ timer. */ 142 /* Enable periodic HZ timer. */
113 __raw_writel(0x48, EP93XX_TIMER1_CONTROL); 143 __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
114 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD); 144 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
115 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL); 145 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
146 EP93XX_TIMER1_CONTROL);
116 147
117 /* Enable lost jiffy timer. */ 148 /* Enable lost jiffy timer. */
118 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH); 149 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
150 EP93XX_TIMER4_VALUE_HIGH);
119 151
120 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); 152 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
121} 153}
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index cd359120c1f5..93e2ecc79ceb 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -92,21 +92,6 @@
92 92
93/* APB peripherals */ 93/* APB peripherals */
94#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) 94#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
95#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
96#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
97#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
98#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
99#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
100#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
101#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
102#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
103#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
104#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
105#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
106#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
107#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
108#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
109#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
110 95
111#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) 96#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
112 97