diff options
| -rw-r--r-- | Documentation/powerpc/dts-bindings/fsl/ssi.txt | 68 |
1 files changed, 39 insertions, 29 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/ssi.txt b/Documentation/powerpc/dts-bindings/fsl/ssi.txt index 731332288931..5ff76c9c57d2 100644 --- a/Documentation/powerpc/dts-bindings/fsl/ssi.txt +++ b/Documentation/powerpc/dts-bindings/fsl/ssi.txt | |||
| @@ -4,46 +4,56 @@ The SSI is a serial device that communicates with audio codecs. It can | |||
| 4 | be programmed in AC97, I2S, left-justified, or right-justified modes. | 4 | be programmed in AC97, I2S, left-justified, or right-justified modes. |
| 5 | 5 | ||
| 6 | Required properties: | 6 | Required properties: |
| 7 | - compatible : compatible list, containing "fsl,ssi" | 7 | - compatible: Compatible list, contains "fsl,ssi". |
| 8 | - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on | 8 | - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. |
| 9 | - reg : offset and length of the register set for the device | 9 | - reg: Offset and length of the register set for the device. |
| 10 | - interrupts : <a b> where a is the interrupt number and b is a | 10 | - interrupts: <a b> where a is the interrupt number and b is a |
| 11 | field that represents an encoding of the sense and | 11 | field that represents an encoding of the sense and |
| 12 | level information for the interrupt. This should be | 12 | level information for the interrupt. This should be |
| 13 | encoded based on the information in section 2) | 13 | encoded based on the information in section 2) |
| 14 | depending on the type of interrupt controller you | 14 | depending on the type of interrupt controller you |
| 15 | have. | 15 | have. |
| 16 | - interrupt-parent : the phandle for the interrupt controller that | 16 | - interrupt-parent: The phandle for the interrupt controller that |
| 17 | services interrupts for this device. | 17 | services interrupts for this device. |
| 18 | - fsl,mode : the operating mode for the SSI interface | 18 | - fsl,mode: The operating mode for the SSI interface. |
| 19 | "i2s-slave" - I2S mode, SSI is clock slave | 19 | "i2s-slave" - I2S mode, SSI is clock slave |
| 20 | "i2s-master" - I2S mode, SSI is clock master | 20 | "i2s-master" - I2S mode, SSI is clock master |
| 21 | "lj-slave" - left-justified mode, SSI is clock slave | 21 | "lj-slave" - left-justified mode, SSI is clock slave |
| 22 | "lj-master" - l.j. mode, SSI is clock master | 22 | "lj-master" - l.j. mode, SSI is clock master |
| 23 | "rj-slave" - right-justified mode, SSI is clock slave | 23 | "rj-slave" - right-justified mode, SSI is clock slave |
| 24 | "rj-master" - r.j., SSI is clock master | 24 | "rj-master" - r.j., SSI is clock master |
| 25 | "ac97-slave" - AC97 mode, SSI is clock slave | 25 | "ac97-slave" - AC97 mode, SSI is clock slave |
| 26 | "ac97-master" - AC97 mode, SSI is clock master | 26 | "ac97-master" - AC97 mode, SSI is clock master |
| 27 | - fsl,playback-dma: phandle to a node for the DMA channel to use for | 27 | - fsl,playback-dma: Phandle to a node for the DMA channel to use for |
| 28 | playback of audio. This is typically dictated by SOC | 28 | playback of audio. This is typically dictated by SOC |
| 29 | design. See the notes below. | 29 | design. See the notes below. |
| 30 | - fsl,capture-dma: phandle to a node for the DMA channel to use for | 30 | - fsl,capture-dma: Phandle to a node for the DMA channel to use for |
| 31 | capture (recording) of audio. This is typically dictated | 31 | capture (recording) of audio. This is typically dictated |
| 32 | by SOC design. See the notes below. | 32 | by SOC design. See the notes below. |
| 33 | - fsl,fifo-depth: the number of elements in the transmit and receive FIFOs. | 33 | - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. |
| 34 | This number is the maximum allowed value for SFCSR[TFWM0]. | 34 | This number is the maximum allowed value for SFCSR[TFWM0]. |
| 35 | - fsl,ssi-asynchronous: | ||
| 36 | If specified, the SSI is to be programmed in asynchronous | ||
| 37 | mode. In this mode, pins SRCK, STCK, SRFS, and STFS must | ||
| 38 | all be connected to valid signals. In synchronous mode, | ||
| 39 | SRCK and SRFS are ignored. Asynchronous mode allows | ||
| 40 | playback and capture to use different sample sizes and | ||
| 41 | sample rates. Some drivers may require that SRCK and STCK | ||
| 42 | be connected together, and SRFS and STFS be connected | ||
| 43 | together. This would still allow different sample sizes, | ||
| 44 | but not different sample rates. | ||
| 35 | 45 | ||
| 36 | Optional properties: | 46 | Optional properties: |
| 37 | - codec-handle : phandle to a 'codec' node that defines an audio | 47 | - codec-handle: Phandle to a 'codec' node that defines an audio |
| 38 | codec connected to this SSI. This node is typically | 48 | codec connected to this SSI. This node is typically |
| 39 | a child of an I2C or other control node. | 49 | a child of an I2C or other control node. |
| 40 | 50 | ||
| 41 | Child 'codec' node required properties: | 51 | Child 'codec' node required properties: |
| 42 | - compatible : compatible list, contains the name of the codec | 52 | - compatible: Compatible list, contains the name of the codec |
| 43 | 53 | ||
| 44 | Child 'codec' node optional properties: | 54 | Child 'codec' node optional properties: |
| 45 | - clock-frequency : The frequency of the input clock, which typically | 55 | - clock-frequency: The frequency of the input clock, which typically comes |
| 46 | comes from an on-board dedicated oscillator. | 56 | from an on-board dedicated oscillator. |
| 47 | 57 | ||
| 48 | Notes on fsl,playback-dma and fsl,capture-dma: | 58 | Notes on fsl,playback-dma and fsl,capture-dma: |
| 49 | 59 | ||