diff options
-rw-r--r-- | drivers/i2c/busses/i2c-mpc.c | 262 |
1 files changed, 242 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 9b38c9236464..4af5c09f0e8f 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c | |||
@@ -26,6 +26,9 @@ | |||
26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
28 | 28 | ||
29 | #include <asm/mpc52xx.h> | ||
30 | #include <sysdev/fsl_soc.h> | ||
31 | |||
29 | #define DRV_NAME "mpc-i2c" | 32 | #define DRV_NAME "mpc-i2c" |
30 | 33 | ||
31 | #define MPC_I2C_FDR 0x04 | 34 | #define MPC_I2C_FDR 0x04 |
@@ -56,7 +59,18 @@ struct mpc_i2c { | |||
56 | wait_queue_head_t queue; | 59 | wait_queue_head_t queue; |
57 | struct i2c_adapter adap; | 60 | struct i2c_adapter adap; |
58 | int irq; | 61 | int irq; |
59 | u32 flags; | 62 | }; |
63 | |||
64 | struct mpc_i2c_divider { | ||
65 | u16 divider; | ||
66 | u16 fdr; /* including dfsrr */ | ||
67 | }; | ||
68 | |||
69 | struct mpc_i2c_match_data { | ||
70 | void (*setclock)(struct device_node *node, | ||
71 | struct mpc_i2c *i2c, | ||
72 | u32 clock, u32 prescaler); | ||
73 | u32 prescaler; | ||
60 | }; | 74 | }; |
61 | 75 | ||
62 | static inline void writeccr(struct mpc_i2c *i2c, u32 x) | 76 | static inline void writeccr(struct mpc_i2c *i2c, u32 x) |
@@ -150,17 +164,180 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) | |||
150 | return 0; | 164 | return 0; |
151 | } | 165 | } |
152 | 166 | ||
153 | static void mpc_i2c_setclock(struct mpc_i2c *i2c) | 167 | #ifdef CONFIG_PPC_52xx |
168 | static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { | ||
169 | {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, | ||
170 | {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, | ||
171 | {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, | ||
172 | {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, | ||
173 | {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, | ||
174 | {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, | ||
175 | {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, | ||
176 | {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, | ||
177 | {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, | ||
178 | {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, | ||
179 | {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, | ||
180 | {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, | ||
181 | {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, | ||
182 | {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, | ||
183 | {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, | ||
184 | {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, | ||
185 | {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, | ||
186 | {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} | ||
187 | }; | ||
188 | |||
189 | int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) | ||
190 | { | ||
191 | const struct mpc52xx_i2c_divider *div = NULL; | ||
192 | unsigned int pvr = mfspr(SPRN_PVR); | ||
193 | u32 divider; | ||
194 | int i; | ||
195 | |||
196 | if (!clock) | ||
197 | return -EINVAL; | ||
198 | |||
199 | /* Determine divider value */ | ||
200 | divider = mpc52xx_find_ipb_freq(node) / clock; | ||
201 | |||
202 | /* | ||
203 | * We want to choose an FDR/DFSR that generates an I2C bus speed that | ||
204 | * is equal to or lower than the requested speed. | ||
205 | */ | ||
206 | for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) { | ||
207 | div = &mpc_i2c_dividers_52xx[i]; | ||
208 | /* Old MPC5200 rev A CPUs do not support the high bits */ | ||
209 | if (div->fdr & 0xc0 && pvr == 0x80822011) | ||
210 | continue; | ||
211 | if (div->divider >= divider) | ||
212 | break; | ||
213 | } | ||
214 | |||
215 | return div ? (int)div->fdr : -EINVAL; | ||
216 | } | ||
217 | |||
218 | static void mpc_i2c_setclock_52xx(struct device_node *node, | ||
219 | struct mpc_i2c *i2c, | ||
220 | u32 clock, u32 prescaler) | ||
221 | { | ||
222 | int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler); | ||
223 | |||
224 | if (fdr < 0) | ||
225 | fdr = 0x3f; /* backward compatibility */ | ||
226 | writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); | ||
227 | dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); | ||
228 | } | ||
229 | #else /* !CONFIG_PPC_52xx */ | ||
230 | static void mpc_i2c_setclock_52xx(struct device_node *node, | ||
231 | struct mpc_i2c *i2c, | ||
232 | u32 clock, u32 prescaler) | ||
233 | { | ||
234 | } | ||
235 | #endif /* CONFIG_PPC_52xx*/ | ||
236 | |||
237 | #ifdef CONFIG_FSL_SOC | ||
238 | static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { | ||
239 | {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, | ||
240 | {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, | ||
241 | {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, | ||
242 | {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, | ||
243 | {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, | ||
244 | {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, | ||
245 | {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, | ||
246 | {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, | ||
247 | {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, | ||
248 | {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, | ||
249 | {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, | ||
250 | {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, | ||
251 | {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, | ||
252 | {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, | ||
253 | {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, | ||
254 | {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, | ||
255 | {49152, 0x011e}, {61440, 0x011f} | ||
256 | }; | ||
257 | |||
258 | u32 mpc_i2c_get_sec_cfg_8xxx(void) | ||
259 | { | ||
260 | struct device_node *node = NULL; | ||
261 | u32 __iomem *reg; | ||
262 | u32 val = 0; | ||
263 | |||
264 | node = of_find_node_by_name(NULL, "global-utilities"); | ||
265 | if (node) { | ||
266 | const u32 *prop = of_get_property(node, "reg", NULL); | ||
267 | if (prop) { | ||
268 | /* | ||
269 | * Map and check POR Device Status Register 2 | ||
270 | * (PORDEVSR2) at 0xE0014 | ||
271 | */ | ||
272 | reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); | ||
273 | if (!reg) | ||
274 | printk(KERN_ERR | ||
275 | "Error: couldn't map PORDEVSR2\n"); | ||
276 | else | ||
277 | val = in_be32(reg) & 0x00000080; /* sec-cfg */ | ||
278 | iounmap(reg); | ||
279 | } | ||
280 | } | ||
281 | if (node) | ||
282 | of_node_put(node); | ||
283 | |||
284 | return val; | ||
285 | } | ||
286 | |||
287 | int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) | ||
288 | { | ||
289 | const struct mpc_i2c_divider *div = NULL; | ||
290 | u32 divider; | ||
291 | int i; | ||
292 | |||
293 | if (!clock) | ||
294 | return -EINVAL; | ||
295 | |||
296 | /* Determine proper divider value */ | ||
297 | if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) | ||
298 | prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; | ||
299 | if (!prescaler) | ||
300 | prescaler = 1; | ||
301 | |||
302 | divider = fsl_get_sys_freq() / clock / prescaler; | ||
303 | |||
304 | pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", | ||
305 | fsl_get_sys_freq(), clock, divider); | ||
306 | |||
307 | /* | ||
308 | * We want to choose an FDR/DFSR that generates an I2C bus speed that | ||
309 | * is equal to or lower than the requested speed. | ||
310 | */ | ||
311 | for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { | ||
312 | div = &mpc_i2c_dividers_8xxx[i]; | ||
313 | if (div->divider >= divider) | ||
314 | break; | ||
315 | } | ||
316 | |||
317 | return div ? (int)div->fdr : -EINVAL; | ||
318 | } | ||
319 | |||
320 | static void mpc_i2c_setclock_8xxx(struct device_node *node, | ||
321 | struct mpc_i2c *i2c, | ||
322 | u32 clock, u32 prescaler) | ||
323 | { | ||
324 | int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); | ||
325 | |||
326 | if (fdr < 0) | ||
327 | fdr = 0x1031; /* backward compatibility */ | ||
328 | writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); | ||
329 | writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); | ||
330 | dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", | ||
331 | clock, fdr >> 8, fdr & 0xff); | ||
332 | } | ||
333 | |||
334 | #else /* !CONFIG_FSL_SOC */ | ||
335 | static void mpc_i2c_setclock_8xxx(struct device_node *node, | ||
336 | struct mpc_i2c *i2c, | ||
337 | u32 clock, u32 prescaler) | ||
154 | { | 338 | { |
155 | /* Set clock and filters */ | ||
156 | if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) { | ||
157 | writeb(0x31, i2c->base + MPC_I2C_FDR); | ||
158 | writeb(0x10, i2c->base + MPC_I2C_DFSRR); | ||
159 | } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200) | ||
160 | writeb(0x3f, i2c->base + MPC_I2C_FDR); | ||
161 | else | ||
162 | writel(0x1031, i2c->base + MPC_I2C_FDR); | ||
163 | } | 339 | } |
340 | #endif /* CONFIG_FSL_SOC */ | ||
164 | 341 | ||
165 | static void mpc_i2c_start(struct mpc_i2c *i2c) | 342 | static void mpc_i2c_start(struct mpc_i2c *i2c) |
166 | { | 343 | { |
@@ -315,8 +492,11 @@ static struct i2c_adapter mpc_ops = { | |||
315 | static int __devinit fsl_i2c_probe(struct of_device *op, | 492 | static int __devinit fsl_i2c_probe(struct of_device *op, |
316 | const struct of_device_id *match) | 493 | const struct of_device_id *match) |
317 | { | 494 | { |
318 | int result = 0; | ||
319 | struct mpc_i2c *i2c; | 495 | struct mpc_i2c *i2c; |
496 | const u32 *prop; | ||
497 | u32 clock = 0; | ||
498 | int result = 0; | ||
499 | int plen; | ||
320 | 500 | ||
321 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); | 501 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); |
322 | if (!i2c) | 502 | if (!i2c) |
@@ -324,13 +504,6 @@ static int __devinit fsl_i2c_probe(struct of_device *op, | |||
324 | 504 | ||
325 | i2c->dev = &op->dev; /* for debug and error output */ | 505 | i2c->dev = &op->dev; /* for debug and error output */ |
326 | 506 | ||
327 | if (of_get_property(op->node, "dfsrr", NULL)) | ||
328 | i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR; | ||
329 | |||
330 | if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") || | ||
331 | of_device_is_compatible(op->node, "mpc5200-i2c")) | ||
332 | i2c->flags |= FSL_I2C_DEV_CLOCK_5200; | ||
333 | |||
334 | init_waitqueue_head(&i2c->queue); | 507 | init_waitqueue_head(&i2c->queue); |
335 | 508 | ||
336 | i2c->base = of_iomap(op->node, 0); | 509 | i2c->base = of_iomap(op->node, 0); |
@@ -350,7 +523,22 @@ static int __devinit fsl_i2c_probe(struct of_device *op, | |||
350 | } | 523 | } |
351 | } | 524 | } |
352 | 525 | ||
353 | mpc_i2c_setclock(i2c); | 526 | if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) { |
527 | prop = of_get_property(op->node, "clock-frequency", &plen); | ||
528 | if (prop && plen == sizeof(u32)) | ||
529 | clock = *prop; | ||
530 | |||
531 | if (match->data) { | ||
532 | struct mpc_i2c_match_data *data = | ||
533 | (struct mpc_i2c_match_data *)match->data; | ||
534 | data->setclock(op->node, i2c, clock, data->prescaler); | ||
535 | } else { | ||
536 | /* Backwards compatibility */ | ||
537 | if (of_get_property(op->node, "dfsrr", NULL)) | ||
538 | mpc_i2c_setclock_8xxx(op->node, i2c, | ||
539 | clock, 0); | ||
540 | } | ||
541 | } | ||
354 | 542 | ||
355 | dev_set_drvdata(&op->dev, i2c); | 543 | dev_set_drvdata(&op->dev, i2c); |
356 | 544 | ||
@@ -395,9 +583,43 @@ static int __devexit fsl_i2c_remove(struct of_device *op) | |||
395 | }; | 583 | }; |
396 | 584 | ||
397 | static const struct of_device_id mpc_i2c_of_match[] = { | 585 | static const struct of_device_id mpc_i2c_of_match[] = { |
398 | {.compatible = "fsl-i2c",}, | 586 | {.compatible = "mpc5200-i2c", |
587 | .data = &(struct mpc_i2c_match_data) { | ||
588 | .setclock = mpc_i2c_setclock_52xx, | ||
589 | }, | ||
590 | }, | ||
591 | {.compatible = "fsl,mpc5200b-i2c", | ||
592 | .data = &(struct mpc_i2c_match_data) { | ||
593 | .setclock = mpc_i2c_setclock_52xx, | ||
594 | }, | ||
595 | }, | ||
596 | {.compatible = "fsl,mpc5200-i2c", | ||
597 | .data = &(struct mpc_i2c_match_data) { | ||
598 | .setclock = mpc_i2c_setclock_52xx, | ||
599 | }, | ||
600 | }, | ||
601 | {.compatible = "fsl,mpc8313-i2c", | ||
602 | .data = &(struct mpc_i2c_match_data) { | ||
603 | .setclock = mpc_i2c_setclock_8xxx, | ||
604 | }, | ||
605 | }, | ||
606 | {.compatible = "fsl,mpc8543-i2c", | ||
607 | .data = &(struct mpc_i2c_match_data) { | ||
608 | .setclock = mpc_i2c_setclock_8xxx, | ||
609 | .prescaler = 2, | ||
610 | }, | ||
611 | }, | ||
612 | {.compatible = "fsl,mpc8544-i2c", | ||
613 | .data = &(struct mpc_i2c_match_data) { | ||
614 | .setclock = mpc_i2c_setclock_8xxx, | ||
615 | .prescaler = 3, | ||
616 | }, | ||
617 | /* Backward compatibility */ | ||
618 | }, | ||
619 | {.compatible = "fsl-i2c", }, | ||
399 | {}, | 620 | {}, |
400 | }; | 621 | }; |
622 | |||
401 | MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); | 623 | MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); |
402 | 624 | ||
403 | 625 | ||