diff options
-rw-r--r-- | arch/arm/mach-omap2/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap2/gpmc.c | 209 | ||||
-rw-r--r-- | arch/arm/mach-omap2/io.c | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-omap/gpmc.h | 91 |
4 files changed, 304 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 111eaa64258f..7a8edd6cd198 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -3,7 +3,8 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o | 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ |
7 | serial.o gpmc.o | ||
7 | 8 | ||
8 | obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o | 9 | obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o |
9 | 10 | ||
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c new file mode 100644 index 000000000000..4aeaa4e79585 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -0,0 +1,209 @@ | |||
1 | /* | ||
2 | * GPMC support functions | ||
3 | * | ||
4 | * Copyright (C) 2005-2006 Nokia Corporation | ||
5 | * | ||
6 | * Author: Juha Yrjola | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/err.h> | ||
15 | #include <linux/clk.h> | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/arch/gpmc.h> | ||
19 | |||
20 | #undef DEBUG | ||
21 | |||
22 | #define GPMC_BASE 0x6800a000 | ||
23 | #define GPMC_REVISION 0x00 | ||
24 | #define GPMC_SYSCONFIG 0x10 | ||
25 | #define GPMC_SYSSTATUS 0x14 | ||
26 | #define GPMC_IRQSTATUS 0x18 | ||
27 | #define GPMC_IRQENABLE 0x1c | ||
28 | #define GPMC_TIMEOUT_CONTROL 0x40 | ||
29 | #define GPMC_ERR_ADDRESS 0x44 | ||
30 | #define GPMC_ERR_TYPE 0x48 | ||
31 | #define GPMC_CONFIG 0x50 | ||
32 | #define GPMC_STATUS 0x54 | ||
33 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | ||
34 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | ||
35 | #define GPMC_PREFETCH_CONTROL 0x1e8 | ||
36 | #define GPMC_PREFETCH_STATUS 0x1f0 | ||
37 | #define GPMC_ECC_CONFIG 0x1f4 | ||
38 | #define GPMC_ECC_CONTROL 0x1f8 | ||
39 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | ||
40 | |||
41 | #define GPMC_CS0 0x60 | ||
42 | #define GPMC_CS_SIZE 0x30 | ||
43 | |||
44 | static void __iomem *gpmc_base = | ||
45 | (void __iomem *) IO_ADDRESS(GPMC_BASE); | ||
46 | static void __iomem *gpmc_cs_base = | ||
47 | (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; | ||
48 | |||
49 | static struct clk *gpmc_l3_clk; | ||
50 | |||
51 | static void gpmc_write_reg(int idx, u32 val) | ||
52 | { | ||
53 | __raw_writel(val, gpmc_base + idx); | ||
54 | } | ||
55 | |||
56 | static u32 gpmc_read_reg(int idx) | ||
57 | { | ||
58 | return __raw_readl(gpmc_base + idx); | ||
59 | } | ||
60 | |||
61 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | ||
62 | { | ||
63 | void __iomem *reg_addr; | ||
64 | |||
65 | reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx; | ||
66 | __raw_writel(val, reg_addr); | ||
67 | } | ||
68 | |||
69 | u32 gpmc_cs_read_reg(int cs, int idx) | ||
70 | { | ||
71 | return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); | ||
72 | } | ||
73 | |||
74 | /* TODO: Add support for gpmc_fck to clock framework and use it */ | ||
75 | static unsigned long gpmc_get_fclk_period(void) | ||
76 | { | ||
77 | /* In picoseconds */ | ||
78 | return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); | ||
79 | } | ||
80 | |||
81 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | ||
82 | { | ||
83 | unsigned long tick_ps; | ||
84 | |||
85 | /* Calculate in picosecs to yield more exact results */ | ||
86 | tick_ps = gpmc_get_fclk_period(); | ||
87 | |||
88 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | ||
89 | } | ||
90 | |||
91 | #ifdef DEBUG | ||
92 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | ||
93 | int time, int div, const char *name) | ||
94 | #else | ||
95 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | ||
96 | int time) | ||
97 | #endif | ||
98 | { | ||
99 | u32 l; | ||
100 | int ticks, mask, nr_bits; | ||
101 | |||
102 | if (time == 0) | ||
103 | ticks = 0; | ||
104 | else | ||
105 | ticks = gpmc_ns_to_ticks(time); | ||
106 | nr_bits = end_bit - st_bit + 1; | ||
107 | if (ticks >= 1 << nr_bits) | ||
108 | return -1; | ||
109 | |||
110 | mask = (1 << nr_bits) - 1; | ||
111 | l = gpmc_cs_read_reg(cs, reg); | ||
112 | #ifdef DEBUG | ||
113 | printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n", | ||
114 | cs, name, ticks, gpmc_get_clk_period(div) * ticks / 1000, | ||
115 | (l >> st_bit) & mask); | ||
116 | #endif | ||
117 | l &= ~(mask << st_bit); | ||
118 | l |= ticks << st_bit; | ||
119 | gpmc_cs_write_reg(cs, reg, l); | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | #ifdef DEBUG | ||
125 | #define GPMC_SET_ONE(reg, st, end, field) \ | ||
126 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | ||
127 | t->field, #field) < 0) \ | ||
128 | return -1 | ||
129 | #else | ||
130 | #define GPMC_SET_ONE(reg, st, end, field) \ | ||
131 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | ||
132 | return -1 | ||
133 | #endif | ||
134 | |||
135 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | ||
136 | { | ||
137 | int div; | ||
138 | u32 l; | ||
139 | |||
140 | l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); | ||
141 | div = l / gpmc_get_fclk_period(); | ||
142 | if (div > 4) | ||
143 | return -1; | ||
144 | if (div < 0) | ||
145 | div = 1; | ||
146 | |||
147 | return div; | ||
148 | } | ||
149 | |||
150 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | ||
151 | { | ||
152 | int div; | ||
153 | u32 l; | ||
154 | |||
155 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | ||
156 | if (div < 0) | ||
157 | return -1; | ||
158 | |||
159 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | ||
160 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | ||
161 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | ||
162 | |||
163 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | ||
164 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | ||
165 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | ||
166 | |||
167 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | ||
168 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | ||
169 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | ||
170 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | ||
171 | |||
172 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | ||
173 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | ||
174 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | ||
175 | |||
176 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | ||
177 | |||
178 | #ifdef DEBUG | ||
179 | printk(KERN_INFO "GPMC CLK period is %d (div %d)\n", | ||
180 | cs, get_gpmc_clk_period(div), div); | ||
181 | #endif | ||
182 | |||
183 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
184 | l &= ~0x03; | ||
185 | l |= (div - 1); | ||
186 | |||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | unsigned long gpmc_cs_get_base_addr(int cs) | ||
191 | { | ||
192 | return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24; | ||
193 | } | ||
194 | |||
195 | void __init gpmc_init(void) | ||
196 | { | ||
197 | u32 l; | ||
198 | |||
199 | gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); | ||
200 | BUG_ON(IS_ERR(gpmc_l3_clk)); | ||
201 | |||
202 | l = gpmc_read_reg(GPMC_REVISION); | ||
203 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | ||
204 | /* Set smart idle mode and automatic L3 clock gating */ | ||
205 | l = gpmc_read_reg(GPMC_SYSCONFIG); | ||
206 | l &= 0x03 << 3; | ||
207 | l |= (0x02 << 3) | (1 << 0); | ||
208 | gpmc_write_reg(GPMC_SYSCONFIG, l); | ||
209 | } | ||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 7d5711611f2f..68456b79a0a8 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -27,6 +27,7 @@ | |||
27 | extern void omap_sram_init(void); | 27 | extern void omap_sram_init(void); |
28 | extern int omap2_clk_init(void); | 28 | extern int omap2_clk_init(void); |
29 | extern void omap2_check_revision(void); | 29 | extern void omap2_check_revision(void); |
30 | extern void gpmc_init(void); | ||
30 | 31 | ||
31 | /* | 32 | /* |
32 | * The machine specific code may provide the extra mapping besides the | 33 | * The machine specific code may provide the extra mapping besides the |
@@ -67,4 +68,5 @@ void __init omap2_init_common_hw(void) | |||
67 | { | 68 | { |
68 | omap2_mux_init(); | 69 | omap2_mux_init(); |
69 | omap2_clk_init(); | 70 | omap2_clk_init(); |
71 | gpmc_init(); | ||
70 | } | 72 | } |
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h new file mode 100644 index 000000000000..1a0a5207822d --- /dev/null +++ b/include/asm-arm/arch-omap/gpmc.h | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * General-Purpose Memory Controller for OMAP2 | ||
3 | * | ||
4 | * Copyright (C) 2005-2006 Nokia Corporation | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __OMAP2_GPMC_H | ||
12 | #define __OMAP2_GPMC_H | ||
13 | |||
14 | #define GPMC_CS_CONFIG1 0x00 | ||
15 | #define GPMC_CS_CONFIG2 0x04 | ||
16 | #define GPMC_CS_CONFIG3 0x08 | ||
17 | #define GPMC_CS_CONFIG4 0x0c | ||
18 | #define GPMC_CS_CONFIG5 0x10 | ||
19 | #define GPMC_CS_CONFIG6 0x14 | ||
20 | #define GPMC_CS_CONFIG7 0x18 | ||
21 | #define GPMC_CS_NAND_COMMAND 0x1c | ||
22 | #define GPMC_CS_NAND_ADDRESS 0x20 | ||
23 | #define GPMC_CS_NAND_DATA 0x24 | ||
24 | |||
25 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | ||
26 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20) | ||
27 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | ||
28 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | ||
29 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | ||
30 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | ||
31 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | ||
32 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | ||
33 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | ||
34 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | ||
35 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | ||
36 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | ||
37 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | ||
38 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | ||
39 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | ||
40 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | ||
41 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) | ||
42 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | ||
43 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | ||
44 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | ||
45 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | ||
46 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | ||
47 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | ||
48 | |||
49 | /* | ||
50 | * Note that all values in this struct are in nanoseconds, while | ||
51 | * the register values are in gpmc_fck cycles. | ||
52 | */ | ||
53 | struct gpmc_timings { | ||
54 | /* Minimum clock period for synchronous mode */ | ||
55 | u16 sync_clk; | ||
56 | |||
57 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | ||
58 | u16 cs_on; /* Assertion time */ | ||
59 | u16 cs_rd_off; /* Read deassertion time */ | ||
60 | u16 cs_wr_off; /* Write deassertion time */ | ||
61 | |||
62 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | ||
63 | u16 adv_on; /* Assertion time */ | ||
64 | u16 adv_rd_off; /* Read deassertion time */ | ||
65 | u16 adv_wr_off; /* Write deassertion time */ | ||
66 | |||
67 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | ||
68 | u16 we_on; /* WE assertion time */ | ||
69 | u16 we_off; /* WE deassertion time */ | ||
70 | |||
71 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | ||
72 | u16 oe_on; /* OE assertion time */ | ||
73 | u16 oe_off; /* OE deassertion time */ | ||
74 | |||
75 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | ||
76 | u16 page_burst_access; /* Multiple access word delay */ | ||
77 | u16 access; /* Start-cycle to first data valid delay */ | ||
78 | u16 rd_cycle; /* Total read cycle time */ | ||
79 | u16 wr_cycle; /* Total write cycle time */ | ||
80 | }; | ||
81 | |||
82 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | ||
83 | |||
84 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | ||
85 | extern u32 gpmc_cs_read_reg(int cs, int idx); | ||
86 | extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); | ||
87 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | ||
88 | extern unsigned long gpmc_cs_get_base_addr(int cs); | ||
89 | |||
90 | |||
91 | #endif | ||