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-rw-r--r--arch/arm/mach-imx/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-imx/irq.c32
-rw-r--r--arch/arm/mach-mx2/devices.h15
-rw-r--r--arch/arm/mach-mx2/mx27ads.c12
-rw-r--r--arch/arm/mach-mx2/pcm038.c8
-rw-r--r--arch/arm/mach-mx2/serial.c51
-rw-r--r--arch/arm/mach-mx3/devices.c43
-rw-r--r--arch/arm/mach-mx3/devices.h6
-rw-r--r--arch/arm/mach-mx3/iomux.c6
-rw-r--r--arch/arm/mach-mx3/mx31ads.c114
-rw-r--r--arch/arm/mach-mx3/pcm037.c6
-rw-r--r--arch/arm/plat-mxc/Kconfig11
-rw-r--r--arch/arm/plat-mxc/Makefile4
-rw-r--r--arch/arm/plat-mxc/devices.c36
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c840
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h89
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S12
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h24
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h20
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h6
-rw-r--r--arch/arm/plat-mxc/irq.c34
27 files changed, 1270 insertions, 115 deletions
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
index eb8d5bd05d56..67812c5ac1f9 100644
--- a/arch/arm/mach-imx/include/mach/irqs.h
+++ b/arch/arm/mach-imx/include/mach/irqs.h
@@ -111,6 +111,11 @@
111/* decode irq number to use with IMR(x), ISR(x) and friends */ 111/* decode irq number to use with IMR(x), ISR(x) and friends */
112#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) 112#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
113 113
114/* all normal IRQs can be FIQs */
115#define FIQ_START 0
116/* switch betwean IRQ and FIQ */
117extern int imx_set_irq_fiq(unsigned int irq, unsigned int type);
118
114#define NR_IRQS (IRQ_GPIOD(32) + 1) 119#define NR_IRQS (IRQ_GPIOD(32) + 1)
115#define IRQ_GPIO(x) 120#define IRQ_GPIO(x)
116#endif 121#endif
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 232e3b9f880d..531b95deadc0 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -36,10 +36,7 @@
36/* 36/*
37 * 37 *
38 * We simply use the ENABLE DISABLE registers inside of the IMX 38 * We simply use the ENABLE DISABLE registers inside of the IMX
39 * to turn on/off specific interrupts. FIXME- We should 39 * to turn on/off specific interrupts.
40 * also add support for the accelerated interrupt controller
41 * by putting offets to irq jump code in the appropriate
42 * places.
43 * 40 *
44 */ 41 */
45 42
@@ -102,6 +99,28 @@ imx_unmask_irq(unsigned int irq)
102 __raw_writel(irq, IMX_AITC_INTENNUM); 99 __raw_writel(irq, IMX_AITC_INTENNUM);
103} 100}
104 101
102#ifdef CONFIG_FIQ
103int imx_set_irq_fiq(unsigned int irq, unsigned int type)
104{
105 unsigned int irqt;
106
107 if (irq >= IMX_IRQS)
108 return -EINVAL;
109
110 if (irq < IMX_IRQS / 2) {
111 irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
112 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
113 } else {
114 irq -= IMX_IRQS / 2;
115 irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
116 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
117 }
118
119 return 0;
120}
121EXPORT_SYMBOL(imx_set_irq_fiq);
122#endif /* CONFIG_FIQ */
123
105static int 124static int
106imx_gpio_irq_type(unsigned int _irq, unsigned int type) 125imx_gpio_irq_type(unsigned int _irq, unsigned int type)
107{ 126{
@@ -284,4 +303,9 @@ imx_init_irq(void)
284 303
285 /* Release masking of interrupts according to priority */ 304 /* Release masking of interrupts according to priority */
286 __raw_writel(-1, IMX_AITC_NIMASK); 305 __raw_writel(-1, IMX_AITC_NIMASK);
306
307#ifdef CONFIG_FIQ
308 /* Initialize FIQ */
309 init_FIQ();
310#endif
287} 311}
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
new file mode 100644
index 000000000000..c77a4b8f73b4
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.h
@@ -0,0 +1,15 @@
1
2extern struct platform_device mxc_gpt1;
3extern struct platform_device mxc_gpt2;
4extern struct platform_device mxc_gpt3;
5extern struct platform_device mxc_gpt4;
6extern struct platform_device mxc_gpt5;
7extern struct platform_device mxc_wdt;
8extern struct platform_device mxc_irda_device;
9extern struct platform_device mxc_uart_device0;
10extern struct platform_device mxc_uart_device1;
11extern struct platform_device mxc_uart_device2;
12extern struct platform_device mxc_uart_device3;
13extern struct platform_device mxc_uart_device4;
14extern struct platform_device mxc_uart_device5;
15
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 4ce56ef4d8d3..56e22d3ca075 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -34,6 +34,8 @@
34#include <mach/iomux-mx1-mx2.h> 34#include <mach/iomux-mx1-mx2.h>
35#include <mach/board-mx27ads.h> 35#include <mach/board-mx27ads.h>
36 36
37#include "devices.h"
38
37/* ADS's NOR flash */ 39/* ADS's NOR flash */
38static struct physmap_flash_data mx27ads_flash_data = { 40static struct physmap_flash_data mx27ads_flash_data = {
39 .width = 2, 41 .width = 2,
@@ -251,12 +253,14 @@ static struct imxuart_platform_data uart_pdata[] = {
251 253
252static void __init mx27ads_board_init(void) 254static void __init mx27ads_board_init(void)
253{ 255{
254 int i;
255
256 gpio_fec_active(); 256 gpio_fec_active();
257 257
258 for (i = 0; i < 6; i++) 258 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
259 imx_init_uart(i, &uart_pdata[i]); 259 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
260 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
261 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
262 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
263 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
260 264
261 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 265 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
262} 266}
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index 1028f453cfc8..7f55746e2591 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -28,6 +28,8 @@
28#include <mach/imx-uart.h> 28#include <mach/imx-uart.h>
29#include <mach/board-pcm038.h> 29#include <mach/board-pcm038.h>
30 30
31#include "devices.h"
32
31/* 33/*
32 * Phytec's phyCORE-i.MX27 comes with 32MiB flash, 34 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
33 * 16 bit width 35 * 16 bit width
@@ -170,11 +172,11 @@ static struct platform_device *platform_devices[] __initdata = {
170 172
171static void __init pcm038_init(void) 173static void __init pcm038_init(void)
172{ 174{
173 int i;
174 gpio_fec_active(); 175 gpio_fec_active();
175 176
176 for (i = 0; i < 3; i++) 177 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
177 imx_init_uart(i, &uart_pdata[i]); 178 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
179 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
178 180
179 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 181 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
180 182
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index e31fd44f7941..16debc296dad 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -35,7 +35,7 @@ static struct resource uart0[] = {
35 }, 35 },
36}; 36};
37 37
38static struct platform_device mxc_uart_device0 = { 38struct platform_device mxc_uart_device0 = {
39 .name = "imx-uart", 39 .name = "imx-uart",
40 .id = 0, 40 .id = 0,
41 .resource = uart0, 41 .resource = uart0,
@@ -54,7 +54,7 @@ static struct resource uart1[] = {
54 }, 54 },
55}; 55};
56 56
57static struct platform_device mxc_uart_device1 = { 57struct platform_device mxc_uart_device1 = {
58 .name = "imx-uart", 58 .name = "imx-uart",
59 .id = 1, 59 .id = 1,
60 .resource = uart1, 60 .resource = uart1,
@@ -73,7 +73,7 @@ static struct resource uart2[] = {
73 }, 73 },
74}; 74};
75 75
76static struct platform_device mxc_uart_device2 = { 76struct platform_device mxc_uart_device2 = {
77 .name = "imx-uart", 77 .name = "imx-uart",
78 .id = 2, 78 .id = 2,
79 .resource = uart2, 79 .resource = uart2,
@@ -92,7 +92,7 @@ static struct resource uart3[] = {
92 }, 92 },
93}; 93};
94 94
95static struct platform_device mxc_uart_device3 = { 95struct platform_device mxc_uart_device3 = {
96 .name = "imx-uart", 96 .name = "imx-uart",
97 .id = 3, 97 .id = 3,
98 .resource = uart3, 98 .resource = uart3,
@@ -111,7 +111,7 @@ static struct resource uart4[] = {
111 }, 111 },
112}; 112};
113 113
114static struct platform_device mxc_uart_device4 = { 114struct platform_device mxc_uart_device4 = {
115 .name = "imx-uart", 115 .name = "imx-uart",
116 .id = 4, 116 .id = 4,
117 .resource = uart4, 117 .resource = uart4,
@@ -130,48 +130,9 @@ static struct resource uart5[] = {
130 }, 130 },
131}; 131};
132 132
133static struct platform_device mxc_uart_device5 = { 133struct platform_device mxc_uart_device5 = {
134 .name = "imx-uart", 134 .name = "imx-uart",
135 .id = 5, 135 .id = 5,
136 .resource = uart5, 136 .resource = uart5,
137 .num_resources = ARRAY_SIZE(uart5), 137 .num_resources = ARRAY_SIZE(uart5),
138}; 138};
139
140/*
141 * Register only those UARTs that physically exists
142 */
143int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
144{
145 switch (uart_no) {
146 case 0:
147 mxc_uart_device0.dev.platform_data = pdata;
148 platform_device_register(&mxc_uart_device0);
149 break;
150 case 1:
151 mxc_uart_device1.dev.platform_data = pdata;
152 platform_device_register(&mxc_uart_device1);
153 break;
154#ifndef CONFIG_MXC_IRDA
155 case 2:
156 mxc_uart_device2.dev.platform_data = pdata;
157 platform_device_register(&mxc_uart_device2);
158 break;
159#endif
160 case 3:
161 mxc_uart_device3.dev.platform_data = pdata;
162 platform_device_register(&mxc_uart_device3);
163 break;
164 case 4:
165 mxc_uart_device4.dev.platform_data = pdata;
166 platform_device_register(&mxc_uart_device4);
167 break;
168 case 5:
169 mxc_uart_device5.dev.platform_data = pdata;
170 platform_device_register(&mxc_uart_device5);
171 break;
172 default:
173 return -ENODEV;
174 }
175
176 return 0;
177}
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index e08c6a8ac56b..a6bdcc07f3c9 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -36,7 +36,7 @@ static struct resource uart0[] = {
36 }, 36 },
37}; 37};
38 38
39static struct platform_device mxc_uart_device0 = { 39struct platform_device mxc_uart_device0 = {
40 .name = "imx-uart", 40 .name = "imx-uart",
41 .id = 0, 41 .id = 0,
42 .resource = uart0, 42 .resource = uart0,
@@ -55,7 +55,7 @@ static struct resource uart1[] = {
55 }, 55 },
56}; 56};
57 57
58static struct platform_device mxc_uart_device1 = { 58struct platform_device mxc_uart_device1 = {
59 .name = "imx-uart", 59 .name = "imx-uart",
60 .id = 1, 60 .id = 1,
61 .resource = uart1, 61 .resource = uart1,
@@ -74,7 +74,7 @@ static struct resource uart2[] = {
74 }, 74 },
75}; 75};
76 76
77static struct platform_device mxc_uart_device2 = { 77struct platform_device mxc_uart_device2 = {
78 .name = "imx-uart", 78 .name = "imx-uart",
79 .id = 2, 79 .id = 2,
80 .resource = uart2, 80 .resource = uart2,
@@ -93,7 +93,7 @@ static struct resource uart3[] = {
93 }, 93 },
94}; 94};
95 95
96static struct platform_device mxc_uart_device3 = { 96struct platform_device mxc_uart_device3 = {
97 .name = "imx-uart", 97 .name = "imx-uart",
98 .id = 3, 98 .id = 3,
99 .resource = uart3, 99 .resource = uart3,
@@ -112,46 +112,13 @@ static struct resource uart4[] = {
112 }, 112 },
113}; 113};
114 114
115static struct platform_device mxc_uart_device4 = { 115struct platform_device mxc_uart_device4 = {
116 .name = "imx-uart", 116 .name = "imx-uart",
117 .id = 4, 117 .id = 4,
118 .resource = uart4, 118 .resource = uart4,
119 .num_resources = ARRAY_SIZE(uart4), 119 .num_resources = ARRAY_SIZE(uart4),
120}; 120};
121 121
122/*
123 * Register only those UARTs that physically exist
124 */
125int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
126{
127 switch (uart_no) {
128 case 0:
129 mxc_uart_device0.dev.platform_data = pdata;
130 platform_device_register(&mxc_uart_device0);
131 break;
132 case 1:
133 mxc_uart_device1.dev.platform_data = pdata;
134 platform_device_register(&mxc_uart_device1);
135 break;
136 case 2:
137 mxc_uart_device2.dev.platform_data = pdata;
138 platform_device_register(&mxc_uart_device2);
139 break;
140 case 3:
141 mxc_uart_device3.dev.platform_data = pdata;
142 platform_device_register(&mxc_uart_device3);
143 break;
144 case 4:
145 mxc_uart_device4.dev.platform_data = pdata;
146 platform_device_register(&mxc_uart_device4);
147 break;
148 default:
149 return -ENODEV;
150 }
151
152 return 0;
153}
154
155/* GPIO port description */ 122/* GPIO port description */
156static struct mxc_gpio_port imx_gpio_ports[] = { 123static struct mxc_gpio_port imx_gpio_ports[] = {
157 [0] = { 124 [0] = {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
new file mode 100644
index 000000000000..4dc03f9e6001
--- /dev/null
+++ b/arch/arm/mach-mx3/devices.h
@@ -0,0 +1,6 @@
1
2extern struct platform_device mxc_uart_device0;
3extern struct platform_device mxc_uart_device1;
4extern struct platform_device mxc_uart_device2;
5extern struct platform_device mxc_uart_device3;
6extern struct platform_device mxc_uart_device4;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 3dda1fe23cbf..6e664be8cc13 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -43,7 +43,8 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
43 */ 43 */
44int mxc_iomux_mode(unsigned int pin_mode) 44int mxc_iomux_mode(unsigned int pin_mode)
45{ 45{
46 u32 reg, field, l, mode, ret = 0; 46 u32 field, l, mode, ret = 0;
47 void __iomem *reg;
47 48
48 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); 49 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
49 field = pin_mode & 0x3; 50 field = pin_mode & 0x3;
@@ -70,7 +71,8 @@ EXPORT_SYMBOL(mxc_iomux_mode);
70 */ 71 */
71void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) 72void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
72{ 73{
73 u32 reg, field, l; 74 u32 field, l;
75 void __iomem *reg;
74 76
75 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3; 77 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
76 field = (pin + 2) % 3; 78 field = (pin + 2) % 3;
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 0cd90a9667c8..1be4a390c63f 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -22,6 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25#include <linux/irq.h>
25 26
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
@@ -31,6 +32,8 @@
31#include <asm/mach/map.h> 32#include <asm/mach/map.h>
32#include <mach/common.h> 33#include <mach/common.h>
33#include <mach/board-mx31ads.h> 34#include <mach/board-mx31ads.h>
35#include <mach/imx-uart.h>
36#include <mach/iomux-mx3.h>
34 37
35/*! 38/*!
36 * @file mx31ads.c 39 * @file mx31ads.c
@@ -84,6 +87,108 @@ static inline int mxc_init_extuart(void)
84} 87}
85#endif 88#endif
86 89
90#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
91static struct imxuart_platform_data uart_pdata = {
92 .flags = IMXUART_HAVE_RTSCTS,
93};
94
95static inline void mxc_init_imx_uart(void)
96{
97 mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
98 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
99 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
100 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
101
102 mxc_register_device(&mxc_uart_device0, &uart_pdata);
103}
104#else /* !SERIAL_IMX */
105static inline void mxc_init_imx_uart(void)
106{
107}
108#endif /* !SERIAL_IMX */
109
110static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
111{
112 u32 imr_val;
113 u32 int_valid;
114 u32 expio_irq;
115
116 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
117 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
118
119 expio_irq = MXC_EXP_IO_BASE;
120 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
121 if ((int_valid & 1) == 0)
122 continue;
123
124 generic_handle_irq(expio_irq);
125 }
126}
127
128/*
129 * Disable an expio pin's interrupt by setting the bit in the imr.
130 * @param irq an expio virtual irq number
131 */
132static void expio_mask_irq(u32 irq)
133{
134 u32 expio = MXC_IRQ_TO_EXPIO(irq);
135 /* mask the interrupt */
136 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
137 __raw_readw(PBC_INTMASK_CLEAR_REG);
138}
139
140/*
141 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
142 * @param irq an expanded io virtual irq number
143 */
144static void expio_ack_irq(u32 irq)
145{
146 u32 expio = MXC_IRQ_TO_EXPIO(irq);
147 /* clear the interrupt status */
148 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
149}
150
151/*
152 * Enable a expio pin's interrupt by clearing the bit in the imr.
153 * @param irq a expio virtual irq number
154 */
155static void expio_unmask_irq(u32 irq)
156{
157 u32 expio = MXC_IRQ_TO_EXPIO(irq);
158 /* unmask the interrupt */
159 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
160}
161
162static struct irq_chip expio_irq_chip = {
163 .ack = expio_ack_irq,
164 .mask = expio_mask_irq,
165 .unmask = expio_unmask_irq,
166};
167
168static void __init mx31ads_init_expio(void)
169{
170 int i;
171
172 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
173
174 /*
175 * Configure INT line as GPIO input
176 */
177 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO));
178
179 /* disable the interrupt and clear the status */
180 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
181 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
182 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
183 i++) {
184 set_irq_chip(i, &expio_irq_chip);
185 set_irq_handler(i, handle_level_irq);
186 set_irq_flags(i, IRQF_VALID);
187 }
188 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
189 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
190}
191
87/*! 192/*!
88 * This structure defines static mappings for the i.MX31ADS board. 193 * This structure defines static mappings for the i.MX31ADS board.
89 */ 194 */
@@ -120,12 +225,19 @@ void __init mx31ads_map_io(void)
120 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); 225 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
121} 226}
122 227
228void __init mx31ads_init_irq(void)
229{
230 mxc_init_irq();
231 mx31ads_init_expio();
232}
233
123/*! 234/*!
124 * Board specific initialization. 235 * Board specific initialization.
125 */ 236 */
126static void __init mxc_board_init(void) 237static void __init mxc_board_init(void)
127{ 238{
128 mxc_init_extuart(); 239 mxc_init_extuart();
240 mxc_init_imx_uart();
129} 241}
130 242
131static void __init mx31ads_timer_init(void) 243static void __init mx31ads_timer_init(void)
@@ -148,7 +260,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
148 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 260 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
149 .boot_params = PHYS_OFFSET + 0x100, 261 .boot_params = PHYS_OFFSET + 0x100,
150 .map_io = mx31ads_map_io, 262 .map_io = mx31ads_map_io,
151 .init_irq = mxc_init_irq, 263 .init_irq = mx31ads_init_irq,
152 .init_machine = mxc_board_init, 264 .init_machine = mxc_board_init,
153 .timer = &mx31ads_timer, 265 .timer = &mx31ads_timer,
154MACHINE_END 266MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 0a152ed15a85..03374f9e0000 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -33,6 +33,8 @@
33#include <mach/iomux-mx3.h> 33#include <mach/iomux-mx3.h>
34#include <mach/board-pcm037.h> 34#include <mach/board-pcm037.h>
35 35
36#include "devices.h"
37
36static struct physmap_flash_data pcm037_flash_data = { 38static struct physmap_flash_data pcm037_flash_data = {
37 .width = 2, 39 .width = 2,
38}; 40};
@@ -73,12 +75,12 @@ static void __init mxc_board_init(void)
73 mxc_iomux_mode(MX31_PIN_TXD1__TXD1); 75 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
74 mxc_iomux_mode(MX31_PIN_RXD1__RXD1); 76 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
75 77
76 imx_init_uart(0, &uart_pdata); 78 mxc_register_device(&mxc_uart_device0, &uart_pdata);
77 79
78 mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3); 80 mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
79 mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3); 81 mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
80 82
81 imx_init_uart(2, &uart_pdata); 83 mxc_register_device(&mxc_uart_device2, &uart_pdata);
82} 84}
83 85
84/* 86/*
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index e14eaad11dd5..b2a7e3fad117 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -23,4 +23,15 @@ source "arch/arm/mach-mx3/Kconfig"
23 23
24endmenu 24endmenu
25 25
26config MXC_IRQ_PRIOR
27 bool "Use IRQ priority"
28 depends on ARCH_MXC
29 help
30 Select this if you want to use prioritized IRQ handling.
31 This feature prevents higher priority ISR to be interrupted
32 by lower priority IRQ even IRQF_DISABLED flag is not set.
33 This may be useful in embedded applications, where are strong
34 requirements for timing.
35 Say N here, unless you have a specialized requirement.
36
26endif 37endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db66e9ae8414..067556f7c91f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o 6obj-y := irq.o clock.o gpio.o time.o devices.o
7 7
8obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o 8obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
new file mode 100644
index 000000000000..c66748267c45
--- /dev/null
+++ b/arch/arm/plat-mxc/devices.c
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
16 * Boston, MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22
23int __init mxc_register_device(struct platform_device *pdev, void *data)
24{
25 int ret;
26
27 pdev->dev.platform_data = data;
28
29 ret = platform_device_register(pdev);
30 if (ret)
31 pr_debug("Unable to register platform device '%s': %d\n",
32 pdev->name, ret);
33
34 return ret;
35}
36
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
new file mode 100644
index 000000000000..b296f19fd89a
--- /dev/null
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -0,0 +1,840 @@
1/*
2 * linux/arch/arm/plat-mxc/dma-mx1-mx2.c
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/interrupt.h>
29#include <linux/errno.h>
30#include <linux/clk.h>
31#include <linux/scatterlist.h>
32#include <linux/io.h>
33
34#include <asm/system.h>
35#include <asm/irq.h>
36#include <mach/hardware.h>
37#include <asm/dma.h>
38#include <mach/dma-mx1-mx2.h>
39
40#define DMA_DCR 0x00 /* Control Register */
41#define DMA_DISR 0x04 /* Interrupt status Register */
42#define DMA_DIMR 0x08 /* Interrupt mask Register */
43#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
44#define DMA_DRTOSR 0x10 /* Request timeout Register */
45#define DMA_DSESR 0x14 /* Transfer Error Status Register */
46#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
47#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
48#define DMA_WSRA 0x40 /* W-Size Register A */
49#define DMA_XSRA 0x44 /* X-Size Register A */
50#define DMA_YSRA 0x48 /* Y-Size Register A */
51#define DMA_WSRB 0x4c /* W-Size Register B */
52#define DMA_XSRB 0x50 /* X-Size Register B */
53#define DMA_YSRB 0x54 /* Y-Size Register B */
54#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
55#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
56#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
57#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
58#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
59#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
60#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
61#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
62#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
63
64#define DCR_DRST (1<<1)
65#define DCR_DEN (1<<0)
66#define DBTOCR_EN (1<<15)
67#define DBTOCR_CNT(x) ((x) & 0x7fff)
68#define CNTR_CNT(x) ((x) & 0xffffff)
69#define CCR_ACRPT (1<<14)
70#define CCR_DMOD_LINEAR (0x0 << 12)
71#define CCR_DMOD_2D (0x1 << 12)
72#define CCR_DMOD_FIFO (0x2 << 12)
73#define CCR_DMOD_EOBFIFO (0x3 << 12)
74#define CCR_SMOD_LINEAR (0x0 << 10)
75#define CCR_SMOD_2D (0x1 << 10)
76#define CCR_SMOD_FIFO (0x2 << 10)
77#define CCR_SMOD_EOBFIFO (0x3 << 10)
78#define CCR_MDIR_DEC (1<<9)
79#define CCR_MSEL_B (1<<8)
80#define CCR_DSIZ_32 (0x0 << 6)
81#define CCR_DSIZ_8 (0x1 << 6)
82#define CCR_DSIZ_16 (0x2 << 6)
83#define CCR_SSIZ_32 (0x0 << 4)
84#define CCR_SSIZ_8 (0x1 << 4)
85#define CCR_SSIZ_16 (0x2 << 4)
86#define CCR_REN (1<<3)
87#define CCR_RPT (1<<2)
88#define CCR_FRC (1<<1)
89#define CCR_CEN (1<<0)
90#define RTOR_EN (1<<15)
91#define RTOR_CLK (1<<14)
92#define RTOR_PSC (1<<13)
93
94/*
95 * struct imx_dma_channel - i.MX specific DMA extension
96 * @name: name specified by DMA client
97 * @irq_handler: client callback for end of transfer
98 * @err_handler: client callback for error condition
99 * @data: clients context data for callbacks
100 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
101 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
102 * @resbytes: total residual number of bytes to transfer
103 * (it can be lower or same as sum of SG mapped chunk sizes)
104 * @sgcount: number of chunks to be read/written
105 *
106 * Structure is used for IMX DMA processing. It would be probably good
107 * @struct dma_struct in the future for external interfacing and use
108 * @struct imx_dma_channel only as extension to it.
109 */
110
111struct imx_dma_channel {
112 const char *name;
113 void (*irq_handler) (int, void *);
114 void (*err_handler) (int, void *, int errcode);
115 void (*prog_handler) (int, void *, struct scatterlist *);
116 void *data;
117 dmamode_t dma_mode;
118 struct scatterlist *sg;
119 unsigned int resbytes;
120 int dma_num;
121
122 int in_use;
123
124 u32 ccr_from_device;
125 u32 ccr_to_device;
126
127 struct timer_list watchdog;
128
129 int hw_chaining;
130};
131
132static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
133
134static struct clk *dma_clk;
135
136static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
137{
138 if (cpu_is_mx27())
139 return imxdma->hw_chaining;
140 else
141 return 0;
142}
143
144
145/*
146 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
147 */
148static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
149{
150 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
151 unsigned long now;
152
153 if (!imxdma->name) {
154 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
155 __func__, channel);
156 return 0;
157 }
158
159 now = min(imxdma->resbytes, sg->length);
160 imxdma->resbytes -= now;
161
162 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
163 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
164 else
165 __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel));
166
167 __raw_writel(now, DMA_BASE + DMA_CNTR(channel));
168
169 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
170 "size 0x%08x\n", channel,
171 __raw_readl(DMA_BASE + DMA_DAR(channel)),
172 __raw_readl(DMA_BASE + DMA_SAR(channel)),
173 __raw_readl(DMA_BASE + DMA_CNTR(channel)));
174
175 return now;
176}
177
178/**
179 * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
180 * device transfer
181 *
182 * @channel: i.MX DMA channel number
183 * @dma_address: the DMA/physical memory address of the linear data block
184 * to transfer
185 * @dma_length: length of the data block in bytes
186 * @dev_addr: physical device port address
187 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
188 * or %DMA_MODE_WRITE from memory to the device
189 *
190 * Return value: if incorrect parameters are provided -%EINVAL.
191 * Zero indicates success.
192 */
193int
194imx_dma_setup_single(int channel, dma_addr_t dma_address,
195 unsigned int dma_length, unsigned int dev_addr,
196 dmamode_t dmamode)
197{
198 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
199
200 imxdma->sg = NULL;
201 imxdma->dma_mode = dmamode;
202
203 if (!dma_address) {
204 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
205 channel);
206 return -EINVAL;
207 }
208
209 if (!dma_length) {
210 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
211 channel);
212 return -EINVAL;
213 }
214
215 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
216 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
217 "dev_addr=0x%08x for read\n",
218 channel, __func__, (unsigned int)dma_address,
219 dma_length, dev_addr);
220
221 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
222 __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel));
223 __raw_writel(imxdma->ccr_from_device,
224 DMA_BASE + DMA_CCR(channel));
225 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
226 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
227 "dev_addr=0x%08x for write\n",
228 channel, __func__, (unsigned int)dma_address,
229 dma_length, dev_addr);
230
231 __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel));
232 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
233 __raw_writel(imxdma->ccr_to_device,
234 DMA_BASE + DMA_CCR(channel));
235 } else {
236 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
237 channel);
238 return -EINVAL;
239 }
240
241 __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel));
242
243 return 0;
244}
245EXPORT_SYMBOL(imx_dma_setup_single);
246
247/**
248 * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
249 * @channel: i.MX DMA channel number
250 * @sg: pointer to the scatter-gather list/vector
251 * @sgcount: scatter-gather list hungs count
252 * @dma_length: total length of the transfer request in bytes
253 * @dev_addr: physical device port address
254 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
255 * or %DMA_MODE_WRITE from memory to the device
256 *
257 * The function sets up DMA channel state and registers to be ready for
258 * transfer specified by provided parameters. The scatter-gather emulation
259 * is set up according to the parameters.
260 *
261 * The full preparation of the transfer requires setup of more register
262 * by the caller before imx_dma_enable() can be called.
263 *
264 * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
265 *
266 * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
267 *
268 * %CCR(channel) has to specify transfer parameters, the next settings is
269 * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
270 * specified
271 *
272 * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
273 *
274 * The typical setup for %DMA_MODE_WRITE is specified by next options
275 * combination
276 *
277 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
278 *
279 * Be careful here and do not mistakenly mix source and target device
280 * port sizes constants, they are really different:
281 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
282 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
283 *
284 * Return value: if incorrect parameters are provided -%EINVAL.
285 * Zero indicates success.
286 */
287int
288imx_dma_setup_sg(int channel,
289 struct scatterlist *sg, unsigned int sgcount,
290 unsigned int dma_length, unsigned int dev_addr,
291 dmamode_t dmamode)
292{
293 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
294
295 if (imxdma->in_use)
296 return -EBUSY;
297
298 imxdma->sg = sg;
299 imxdma->dma_mode = dmamode;
300 imxdma->resbytes = dma_length;
301
302 if (!sg || !sgcount) {
303 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
304 channel);
305 return -EINVAL;
306 }
307
308 if (!sg->length) {
309 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
310 channel);
311 return -EINVAL;
312 }
313
314 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
315 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
316 "dev_addr=0x%08x for read\n",
317 channel, __func__, sg, sgcount, dma_length, dev_addr);
318
319 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
320 __raw_writel(imxdma->ccr_from_device,
321 DMA_BASE + DMA_CCR(channel));
322 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
323 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
324 "dev_addr=0x%08x for write\n",
325 channel, __func__, sg, sgcount, dma_length, dev_addr);
326
327 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
328 __raw_writel(imxdma->ccr_to_device,
329 DMA_BASE + DMA_CCR(channel));
330 } else {
331 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
332 channel);
333 return -EINVAL;
334 }
335
336 imx_dma_sg_next(channel, sg);
337
338 return 0;
339}
340EXPORT_SYMBOL(imx_dma_setup_sg);
341
342int
343imx_dma_config_channel(int channel, unsigned int config_port,
344 unsigned int config_mem, unsigned int dmareq, int hw_chaining)
345{
346 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
347 u32 dreq = 0;
348
349 imxdma->hw_chaining = 0;
350
351 if (hw_chaining) {
352 imxdma->hw_chaining = 1;
353 if (!imx_dma_hw_chain(imxdma))
354 return -EINVAL;
355 }
356
357 if (dmareq)
358 dreq = CCR_REN;
359
360 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
361 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
362
363 __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel));
364
365 return 0;
366}
367EXPORT_SYMBOL(imx_dma_config_channel);
368
369void imx_dma_config_burstlen(int channel, unsigned int burstlen)
370{
371 __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel));
372}
373EXPORT_SYMBOL(imx_dma_config_burstlen);
374
375/**
376 * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
377 * handlers
378 * @channel: i.MX DMA channel number
379 * @irq_handler: the pointer to the function called if the transfer
380 * ends successfully
381 * @err_handler: the pointer to the function called if the premature
382 * end caused by error occurs
383 * @data: user specified value to be passed to the handlers
384 */
385int
386imx_dma_setup_handlers(int channel,
387 void (*irq_handler) (int, void *),
388 void (*err_handler) (int, void *, int),
389 void *data)
390{
391 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
392 unsigned long flags;
393
394 if (!imxdma->name) {
395 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
396 __func__, channel);
397 return -ENODEV;
398 }
399
400 local_irq_save(flags);
401 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
402 imxdma->irq_handler = irq_handler;
403 imxdma->err_handler = err_handler;
404 imxdma->data = data;
405 local_irq_restore(flags);
406 return 0;
407}
408EXPORT_SYMBOL(imx_dma_setup_handlers);
409
410/**
411 * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
412 * handlers
413 * @channel: i.MX DMA channel number
414 * @prog_handler: the pointer to the function called if the transfer progresses
415 */
416int
417imx_dma_setup_progression_handler(int channel,
418 void (*prog_handler) (int, void*, struct scatterlist*))
419{
420 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
421 unsigned long flags;
422
423 if (!imxdma->name) {
424 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
425 __func__, channel);
426 return -ENODEV;
427 }
428
429 local_irq_save(flags);
430 imxdma->prog_handler = prog_handler;
431 local_irq_restore(flags);
432 return 0;
433}
434EXPORT_SYMBOL(imx_dma_setup_progression_handler);
435
436/**
437 * imx_dma_enable - function to start i.MX DMA channel operation
438 * @channel: i.MX DMA channel number
439 *
440 * The channel has to be allocated by driver through imx_dma_request()
441 * or imx_dma_request_by_prio() function.
442 * The transfer parameters has to be set to the channel registers through
443 * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
444 * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
445 * be set prior this function call by the channel user.
446 */
447void imx_dma_enable(int channel)
448{
449 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
450 unsigned long flags;
451
452 pr_debug("imxdma%d: imx_dma_enable\n", channel);
453
454 if (!imxdma->name) {
455 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
456 __func__, channel);
457 return;
458 }
459
460 if (imxdma->in_use)
461 return;
462
463 local_irq_save(flags);
464
465 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
466 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel),
467 DMA_BASE + DMA_DIMR);
468 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN |
469 CCR_ACRPT,
470 DMA_BASE + DMA_CCR(channel));
471
472#ifdef CONFIG_ARCH_MX2
473 if (imxdma->sg && imx_dma_hw_chain(imxdma)) {
474 imxdma->sg = sg_next(imxdma->sg);
475 if (imxdma->sg) {
476 u32 tmp;
477 imx_dma_sg_next(channel, imxdma->sg);
478 tmp = __raw_readl(DMA_BASE + DMA_CCR(channel));
479 __raw_writel(tmp | CCR_RPT | CCR_ACRPT,
480 DMA_BASE + DMA_CCR(channel));
481 }
482 }
483#endif
484 imxdma->in_use = 1;
485
486 local_irq_restore(flags);
487}
488EXPORT_SYMBOL(imx_dma_enable);
489
490/**
491 * imx_dma_disable - stop, finish i.MX DMA channel operatin
492 * @channel: i.MX DMA channel number
493 */
494void imx_dma_disable(int channel)
495{
496 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
497 unsigned long flags;
498
499 pr_debug("imxdma%d: imx_dma_disable\n", channel);
500
501 if (imx_dma_hw_chain(imxdma))
502 del_timer(&imxdma->watchdog);
503
504 local_irq_save(flags);
505 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
506 DMA_BASE + DMA_DIMR);
507 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
508 DMA_BASE + DMA_CCR(channel));
509 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
510 imxdma->in_use = 0;
511 local_irq_restore(flags);
512}
513EXPORT_SYMBOL(imx_dma_disable);
514
515static void imx_dma_watchdog(unsigned long chno)
516{
517 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
518
519 __raw_writel(0, DMA_BASE + DMA_CCR(chno));
520 imxdma->in_use = 0;
521 imxdma->sg = NULL;
522
523 if (imxdma->err_handler)
524 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
525}
526
527static irqreturn_t dma_err_handler(int irq, void *dev_id)
528{
529 int i, disr;
530 struct imx_dma_channel *imxdma;
531 unsigned int err_mask;
532 int errcode;
533
534 disr = __raw_readl(DMA_BASE + DMA_DISR);
535
536 err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) |
537 __raw_readl(DMA_BASE + DMA_DRTOSR) |
538 __raw_readl(DMA_BASE + DMA_DSESR) |
539 __raw_readl(DMA_BASE + DMA_DBOSR);
540
541 if (!err_mask)
542 return IRQ_HANDLED;
543
544 __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR);
545
546 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
547 if (!(err_mask & (1 << i)))
548 continue;
549 imxdma = &imx_dma_channels[i];
550 errcode = 0;
551
552 if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) {
553 __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR);
554 errcode |= IMX_DMA_ERR_BURST;
555 }
556 if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) {
557 __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR);
558 errcode |= IMX_DMA_ERR_REQUEST;
559 }
560 if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) {
561 __raw_writel(1 << i, DMA_BASE + DMA_DSESR);
562 errcode |= IMX_DMA_ERR_TRANSFER;
563 }
564 if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) {
565 __raw_writel(1 << i, DMA_BASE + DMA_DBOSR);
566 errcode |= IMX_DMA_ERR_BUFFER;
567 }
568 if (imxdma->name && imxdma->err_handler) {
569 imxdma->err_handler(i, imxdma->data, errcode);
570 continue;
571 }
572
573 imx_dma_channels[i].sg = NULL;
574
575 printk(KERN_WARNING
576 "DMA timeout on channel %d (%s) -%s%s%s%s\n",
577 i, imxdma->name,
578 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
579 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
580 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
581 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
582 }
583 return IRQ_HANDLED;
584}
585
586static void dma_irq_handle_channel(int chno)
587{
588 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
589
590 if (!imxdma->name) {
591 /*
592 * IRQ for an unregistered DMA channel:
593 * let's clear the interrupts and disable it.
594 */
595 printk(KERN_WARNING
596 "spurious IRQ for DMA channel %d\n", chno);
597 return;
598 }
599
600 if (imxdma->sg) {
601 u32 tmp;
602 struct scatterlist *current_sg = imxdma->sg;
603 imxdma->sg = sg_next(imxdma->sg);
604
605 if (imxdma->sg) {
606 imx_dma_sg_next(chno, imxdma->sg);
607
608 tmp = __raw_readl(DMA_BASE + DMA_CCR(chno));
609
610 if (imx_dma_hw_chain(imxdma)) {
611 /* FIXME: The timeout should probably be
612 * configurable
613 */
614 mod_timer(&imxdma->watchdog,
615 jiffies + msecs_to_jiffies(500));
616
617 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
618 __raw_writel(tmp, DMA_BASE +
619 DMA_CCR(chno));
620 } else {
621 __raw_writel(tmp & ~CCR_CEN, DMA_BASE +
622 DMA_CCR(chno));
623 tmp |= CCR_CEN;
624 }
625
626 __raw_writel(tmp, DMA_BASE + DMA_CCR(chno));
627
628 if (imxdma->prog_handler)
629 imxdma->prog_handler(chno, imxdma->data,
630 current_sg);
631
632 return;
633 }
634
635 if (imx_dma_hw_chain(imxdma)) {
636 del_timer(&imxdma->watchdog);
637 return;
638 }
639 }
640
641 __raw_writel(0, DMA_BASE + DMA_CCR(chno));
642 imxdma->in_use = 0;
643 if (imxdma->irq_handler)
644 imxdma->irq_handler(chno, imxdma->data);
645}
646
647static irqreturn_t dma_irq_handler(int irq, void *dev_id)
648{
649 int i, disr;
650
651#ifdef CONFIG_ARCH_MX2
652 dma_err_handler(irq, dev_id);
653#endif
654
655 disr = __raw_readl(DMA_BASE + DMA_DISR);
656
657 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
658 disr);
659
660 __raw_writel(disr, DMA_BASE + DMA_DISR);
661 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
662 if (disr & (1 << i))
663 dma_irq_handle_channel(i);
664 }
665
666 return IRQ_HANDLED;
667}
668
669/**
670 * imx_dma_request - request/allocate specified channel number
671 * @channel: i.MX DMA channel number
672 * @name: the driver/caller own non-%NULL identification
673 */
674int imx_dma_request(int channel, const char *name)
675{
676 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
677 unsigned long flags;
678 int ret;
679
680 /* basic sanity checks */
681 if (!name)
682 return -EINVAL;
683
684 if (channel >= IMX_DMA_CHANNELS) {
685 printk(KERN_CRIT "%s: called for non-existed channel %d\n",
686 __func__, channel);
687 return -EINVAL;
688 }
689
690 local_irq_save(flags);
691 if (imxdma->name) {
692 local_irq_restore(flags);
693 return -EBUSY;
694 }
695
696#ifdef CONFIG_ARCH_MX2
697 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
698 NULL);
699 if (ret) {
700 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
701 MXC_INT_DMACH0 + channel, channel);
702 return ret;
703 }
704 init_timer(&imxdma->watchdog);
705 imxdma->watchdog.function = &imx_dma_watchdog;
706 imxdma->watchdog.data = channel;
707#endif
708
709 imxdma->name = name;
710 imxdma->irq_handler = NULL;
711 imxdma->err_handler = NULL;
712 imxdma->data = NULL;
713 imxdma->sg = NULL;
714
715 local_irq_restore(flags);
716 return 0;
717}
718EXPORT_SYMBOL(imx_dma_request);
719
720/**
721 * imx_dma_free - release previously acquired channel
722 * @channel: i.MX DMA channel number
723 */
724void imx_dma_free(int channel)
725{
726 unsigned long flags;
727 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
728
729 if (!imxdma->name) {
730 printk(KERN_CRIT
731 "%s: trying to free free channel %d\n",
732 __func__, channel);
733 return;
734 }
735
736 local_irq_save(flags);
737 /* Disable interrupts */
738 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
739 DMA_BASE + DMA_DIMR);
740 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
741 DMA_BASE + DMA_CCR(channel));
742 imxdma->name = NULL;
743
744#ifdef CONFIG_ARCH_MX2
745 free_irq(MXC_INT_DMACH0 + channel, NULL);
746#endif
747
748 local_irq_restore(flags);
749}
750EXPORT_SYMBOL(imx_dma_free);
751
752/**
753 * imx_dma_request_by_prio - find and request some of free channels best
754 * suiting requested priority
755 * @channel: i.MX DMA channel number
756 * @name: the driver/caller own non-%NULL identification
757 *
758 * This function tries to find a free channel in the specified priority group
759 * This function tries to find a free channel in the specified priority group
760 * if the priority cannot be achieved it tries to look for free channel
761 * in the higher and then even lower priority groups.
762 *
763 * Return value: If there is no free channel to allocate, -%ENODEV is returned.
764 * On successful allocation channel is returned.
765 */
766int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
767{
768 int i;
769 int best;
770
771 switch (prio) {
772 case (DMA_PRIO_HIGH):
773 best = 8;
774 break;
775 case (DMA_PRIO_MEDIUM):
776 best = 4;
777 break;
778 case (DMA_PRIO_LOW):
779 default:
780 best = 0;
781 break;
782 }
783
784 for (i = best; i < IMX_DMA_CHANNELS; i++)
785 if (!imx_dma_request(i, name))
786 return i;
787
788 for (i = best - 1; i >= 0; i--)
789 if (!imx_dma_request(i, name))
790 return i;
791
792 printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
793
794 return -ENODEV;
795}
796EXPORT_SYMBOL(imx_dma_request_by_prio);
797
798static int __init imx_dma_init(void)
799{
800 int ret = 0;
801 int i;
802
803 dma_clk = clk_get(NULL, "dma_clk");
804 clk_enable(dma_clk);
805
806 /* reset DMA module */
807 __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR);
808
809#ifdef CONFIG_ARCH_MX1
810 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
811 if (ret) {
812 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
813 return ret;
814 }
815
816 ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
817 if (ret) {
818 printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n");
819 free_irq(DMA_INT, NULL);
820 return ret;
821 }
822#endif
823 /* enable DMA module */
824 __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR);
825
826 /* clear all interrupts */
827 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR);
828
829 /* disable interrupts */
830 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR);
831
832 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
833 imx_dma_channels[i].sg = NULL;
834 imx_dma_channels[i].dma_num = i;
835 }
836
837 return ret;
838}
839
840arch_initcall(imx_dma_init);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 1bc6fb0f9a83..745b48864f93 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -90,6 +90,9 @@
90#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) 90#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
91#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) 91#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
92 92
93#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
94#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
95
93#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) 96#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
94#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) 97#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
95#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) 98#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 24caa2b7c91d..d21f78e78819 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -39,7 +39,7 @@ struct clk {
39 /* Register bit position for clock's enable/disable control. */ 39 /* Register bit position for clock's enable/disable control. */
40 u8 enable_shift; 40 u8 enable_shift;
41 /* Register address for clock's enable/disable control. */ 41 /* Register address for clock's enable/disable control. */
42 u32 enable_reg; 42 void __iomem *enable_reg;
43 u32 flags; 43 u32 flags;
44 /* get the current clock rate (always a fresh value) */ 44 /* get the current clock rate (always a fresh value) */
45 unsigned long (*get_rate) (struct clk *); 45 unsigned long (*get_rate) (struct clk *);
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a6d2e24aab15..6350287a59b9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -11,10 +11,13 @@
11#ifndef __ASM_ARCH_MXC_COMMON_H__ 11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct platform_device;
15
14extern void mxc_map_io(void); 16extern void mxc_map_io(void);
15extern void mxc_init_irq(void); 17extern void mxc_init_irq(void);
16extern void mxc_timer_init(const char *clk_timer); 18extern void mxc_timer_init(const char *clk_timer);
17extern int mxc_clocks_init(unsigned long fref); 19extern int mxc_clocks_init(unsigned long fref);
18extern int mxc_register_gpios(void); 20extern int mxc_register_gpios(void);
21extern int mxc_register_device(struct platform_device *pdev, void *data);
19 22
20#endif 23#endif
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..e85fd946116c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,89 @@
1/*
2 * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#include <asm/dma.h>
26
27#ifndef __ASM_ARCH_MXC_DMA_H
28#define __ASM_ARCH_MXC_DMA_H
29
30#define IMX_DMA_CHANNELS 16
31
32#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
33
34#define IMX_DMA_MEMSIZE_32 (0 << 4)
35#define IMX_DMA_MEMSIZE_8 (1 << 4)
36#define IMX_DMA_MEMSIZE_16 (2 << 4)
37#define IMX_DMA_TYPE_LINEAR (0 << 10)
38#define IMX_DMA_TYPE_2D (1 << 10)
39#define IMX_DMA_TYPE_FIFO (2 << 10)
40
41#define IMX_DMA_ERR_BURST (1 << 0)
42#define IMX_DMA_ERR_REQUEST (1 << 1)
43#define IMX_DMA_ERR_TRANSFER (1 << 2)
44#define IMX_DMA_ERR_BUFFER (1 << 3)
45#define IMX_DMA_ERR_TIMEOUT (1 << 4)
46
47int
48imx_dma_config_channel(int channel, unsigned int config_port,
49 unsigned int config_mem, unsigned int dmareq, int hw_chaining);
50
51void
52imx_dma_config_burstlen(int channel, unsigned int burstlen);
53
54int
55imx_dma_setup_single(int channel, dma_addr_t dma_address,
56 unsigned int dma_length, unsigned int dev_addr,
57 dmamode_t dmamode);
58
59int
60imx_dma_setup_sg(int channel, struct scatterlist *sg,
61 unsigned int sgcount, unsigned int dma_length,
62 unsigned int dev_addr, dmamode_t dmamode);
63
64int
65imx_dma_setup_handlers(int channel,
66 void (*irq_handler) (int, void *),
67 void (*err_handler) (int, void *, int), void *data);
68
69int
70imx_dma_setup_progression_handler(int channel,
71 void (*prog_handler) (int, void*, struct scatterlist*));
72
73void imx_dma_enable(int channel);
74
75void imx_dma_disable(int channel);
76
77int imx_dma_request(int channel, const char *name);
78
79void imx_dma_free(int channel);
80
81enum imx_dma_prio {
82 DMA_PRIO_HIGH = 0,
83 DMA_PRIO_MEDIUM = 1,
84 DMA_PRIO_LOW = 2
85};
86
87int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
88
89#endif /* _ASM_ARCH_MXC_DMA_H */
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index b542433afb1b..11632028f7d1 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,11 +9,17 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#define AVIC_NIMASK 0x04
13
12 @ this macro disables fast irq (not implemented) 14 @ this macro disables fast irq (not implemented)
13 .macro disable_fiq 15 .macro disable_fiq
14 .endm 16 .endm
15 17
16 .macro get_irqnr_preamble, base, tmp 18 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
20#ifdef CONFIG_MXC_IRQ_PRIOR
21 ldr r4, [\base, #AVIC_NIMASK]
22#endif
17 .endm 23 .endm
18 24
19 .macro arch_ret_to_user, tmp1, tmp2 25 .macro arch_ret_to_user, tmp1, tmp2
@@ -23,7 +29,6 @@
23 @ and returns its number in irqnr 29 @ and returns its number in irqnr
24 @ and returns if an interrupt occured in irqstat 30 @ and returns if an interrupt occured in irqstat
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26 ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
27 @ Load offset & priority of the highest priority 32 @ Load offset & priority of the highest priority
28 @ interrupt pending from AVIC_NIVECSR 33 @ interrupt pending from AVIC_NIVECSR
29 ldr \irqstat, [\base, #0x40] 34 ldr \irqstat, [\base, #0x40]
@@ -32,6 +37,11 @@
32 mov \irqnr, \irqstat, asr #16 37 mov \irqnr, \irqstat, asr #16
33 @ set zero flag if IRQ + 1 == 0 38 @ set zero flag if IRQ + 1 == 0
34 adds \tmp, \irqnr, #1 39 adds \tmp, \irqnr, #1
40#ifdef CONFIG_MXC_IRQ_PRIOR
41 bicne \tmp, \irqstat, #0xFFFFFFE0
42 strne \tmp, [\base, #AVIC_NIMASK]
43 streq r4, [\base, #AVIC_NIMASK]
44#endif
35 .endm 45 .endm
36 46
37 @ irq priority table (not used) 47 @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
index 076d37b38eb2..3d09bfd6c53d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
@@ -247,6 +247,11 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
247#endif 247#endif
248 248
249#ifdef CONFIG_ARCH_MX2 249#ifdef CONFIG_ARCH_MX2
250#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
251#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
252#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
253#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
254#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5) 255#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6) 256#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7) 257#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
@@ -294,6 +299,16 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
294#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20) 299#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
295#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21) 300#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
296#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21) 301#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
302#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
303#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
304#define PB24_PF_USB_OC_B (GPIO_PORTB | GPIO_PF | 24)
305#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
306#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
307#define PB27_PF_USBH1_OE_B (GPIO_PORTB | GPIO_PF | 27)
308#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
309#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
310#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
311#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
297#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26) 312#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
298#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28) 313#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
299#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29) 314#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
@@ -335,8 +350,15 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
335#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) 350#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
336#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) 351#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
337#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) 352#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
353#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
354#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
355#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
356#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
357#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
358#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
338#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) 359#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
339#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) 360#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
361#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
340#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) 362#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
341#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) 363#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
342#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) 364#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
@@ -355,6 +377,8 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
355#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) 377#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
356#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) 378#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
357#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) 379#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
380#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
381#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
358#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) 382#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
359#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) 383#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
360#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) 384#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 7509e7692f08..c9f39c2fb8c6 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -491,6 +491,26 @@ enum iomux_pins {
491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) 491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) 492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) 493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
494#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
495#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
496#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
497#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
498#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
499#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
500#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
501#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
502#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
503#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
504#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
505#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
506#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
507#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
508#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
509#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
510#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
511#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
512/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
513 * cspi1_ss1*/
494 514
495/* 515/*
496 * This function configures the pad value for a IOMUX pin. 516 * This function configures the pad value for a IOMUX pin.
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 228c4f68ccdf..b55bba35e18a 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,5 +12,6 @@
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
15 16
16#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 17#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 212ecc246626..a86db64744a1 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,6 +128,7 @@
128 * it returns 0xDEADBEEF 128 * it returns 0xDEADBEEF
129 */ 129 */
130#define IO_ADDRESS(x) \ 130#define IO_ADDRESS(x) \
131 (void __iomem *) \
131 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ 132 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
132 AIPI_IO_ADDRESS(x) : \ 133 AIPI_IO_ADDRESS(x) : \
133 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ 134 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index a7373e4a56cb..0536f8917bc0 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -198,6 +198,7 @@
198 * it returns 0xDEADBEEF 198 * it returns 0xDEADBEEF
199 */ 199 */
200#define IO_ADDRESS(x) \ 200#define IO_ADDRESS(x) \
201 (void __iomem *) \
201 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ 202 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
202 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ 203 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
203 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ 204 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 332eda4dbd3b..f6caab062131 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -33,4 +33,10 @@
33# define cpu_is_mx27() (0) 33# define cpu_is_mx27() (0)
34#endif 34#endif
35 35
36#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
37#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
38#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
39#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
40#endif
41
36#endif /* __ASM_ARCH_MXC_H__ */ 42#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index c6b837893d87..d862c9e5f8db 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -30,14 +30,7 @@
30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ 30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ 31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ 32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
33#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ 33#define AVIC_NIPRIORITY(x) (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
34#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
35#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
36#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
37#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
38#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
39#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
40#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
41#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ 34#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
42#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ 35#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
43#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ 36#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
@@ -54,6 +47,24 @@
54#define IIM_PROD_REV_SH 3 47#define IIM_PROD_REV_SH 3
55#define IIM_PROD_REV_LEN 5 48#define IIM_PROD_REV_LEN 5
56 49
50#ifdef CONFIG_MXC_IRQ_PRIOR
51void imx_irq_set_priority(unsigned char irq, unsigned char prio)
52{
53 unsigned int temp;
54 unsigned int mask = 0x0F << irq % 8 * 4;
55
56 if (irq > 63)
57 return;
58
59 temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
60 temp &= ~mask;
61 temp |= prio & mask;
62
63 __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
64}
65EXPORT_SYMBOL(imx_irq_set_priority);
66#endif
67
57/* Disable interrupt number "irq" in the AVIC */ 68/* Disable interrupt number "irq" in the AVIC */
58static void mxc_mask_irq(unsigned int irq) 69static void mxc_mask_irq(unsigned int irq)
59{ 70{
@@ -101,10 +112,9 @@ void __init mxc_init_irq(void)
101 set_irq_flags(i, IRQF_VALID); 112 set_irq_flags(i, IRQF_VALID);
102 } 113 }
103 114
104 /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ 115 /* Set default priority value (0) for all IRQ's */
105 reg = __raw_readl(AVIC_NIPRIORITY6); 116 for (i = 0; i < 8; i++)
106 reg |= (0xF << 28); 117 __raw_writel(0, AVIC_NIPRIORITY(i));
107 __raw_writel(reg, AVIC_NIPRIORITY6);
108 118
109 /* init architectures chained interrupt handler */ 119 /* init architectures chained interrupt handler */
110 mxc_register_gpios(); 120 mxc_register_gpios();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 03:12:29 -0500