diff options
-rw-r--r-- | drivers/net/mv643xx_eth.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h index 7754d1974b9e..4262c1da6d4a 100644 --- a/drivers/net/mv643xx_eth.h +++ b/drivers/net/mv643xx_eth.h | |||
@@ -42,13 +42,23 @@ | |||
42 | #define MAX_DESCS_PER_SKB 1 | 42 | #define MAX_DESCS_PER_SKB 1 |
43 | #endif | 43 | #endif |
44 | 44 | ||
45 | /* | ||
46 | * The MV643XX HW requires 8-byte alignment. However, when I/O | ||
47 | * is non-cache-coherent, we need to ensure that the I/O buffers | ||
48 | * we use don't share cache lines with other data. | ||
49 | */ | ||
50 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_NOT_COHERENT_CACHE) | ||
51 | #define ETH_DMA_ALIGN L1_CACHE_BYTES | ||
52 | #else | ||
53 | #define ETH_DMA_ALIGN 8 | ||
54 | #endif | ||
55 | |||
45 | #define ETH_VLAN_HLEN 4 | 56 | #define ETH_VLAN_HLEN 4 |
46 | #define ETH_FCS_LEN 4 | 57 | #define ETH_FCS_LEN 4 |
47 | #define ETH_DMA_ALIGN 8 /* hw requires 8-byte alignment */ | 58 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ |
48 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | ||
49 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | 59 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ |
50 | ETH_VLAN_HLEN + ETH_FCS_LEN) | 60 | ETH_VLAN_HLEN + ETH_FCS_LEN) |
51 | #define ETH_RX_SKB_SIZE ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7) | 61 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + ETH_DMA_ALIGN) |
52 | 62 | ||
53 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ | 63 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ |
54 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ | 64 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ |