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-rw-r--r--drivers/net/bnx2x_main.c92
-rw-r--r--drivers/net/bnx2x_reg.h162
2 files changed, 130 insertions, 124 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index a4177e964c56..b2886db57048 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -685,7 +685,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp)
685static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, 685static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
686 u8 storm, u16 index, u8 op, u8 update) 686 u8 storm, u16 index, u8 op, u8 update)
687{ 687{
688 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 688 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
689 COMMAND_REG_INT_ACK);
689 struct igu_ack_register igu_ack; 690 struct igu_ack_register igu_ack;
690 691
691 igu_ack.status_block_index = index; 692 igu_ack.status_block_index = index;
@@ -695,9 +696,9 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
695 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 696 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
696 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 697 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
697 698
698 DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n", 699 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
699 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); 700 (*(u32 *)&igu_ack), hc_addr);
700 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack)); 701 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
701} 702}
702 703
703static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 704static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
@@ -719,19 +720,13 @@ static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
719 720
720static u16 bnx2x_ack_int(struct bnx2x *bp) 721static u16 bnx2x_ack_int(struct bnx2x *bp)
721{ 722{
722 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 723 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
723 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr); 724 COMMAND_REG_SIMD_MASK);
725 u32 result = REG_RD(bp, hc_addr);
724 726
725 DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n", 727 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
726 result, BAR_IGU_INTMEM + igu_addr); 728 result, hc_addr);
727 729
728#ifdef IGU_DEBUG
729#warning IGU_DEBUG active
730 if (result == 0) {
731 BNX2X_ERR("read %x from IGU\n", result);
732 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
733 }
734#endif
735 return result; 730 return result;
736} 731}
737 732
@@ -2444,8 +2439,8 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2444static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 2439static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2445{ 2440{
2446 int port = BP_PORT(bp); 2441 int port = BP_PORT(bp);
2447 int func = BP_FUNC(bp); 2442 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2448 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8; 2443 COMMAND_REG_ATTN_BITS_SET);
2449 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2444 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2450 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2445 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2451 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 2446 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
@@ -2523,9 +2518,9 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2523 2518
2524 } /* if hardwired */ 2519 } /* if hardwired */
2525 2520
2526 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n", 2521 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2527 asserted, BAR_IGU_INTMEM + igu_addr); 2522 asserted, hc_addr);
2528 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted); 2523 REG_WR(bp, hc_addr, asserted);
2529 2524
2530 /* now set back the mask */ 2525 /* now set back the mask */
2531 if (asserted & ATTN_NIG_FOR_FUNC) 2526 if (asserted & ATTN_NIG_FOR_FUNC)
@@ -2764,12 +2759,12 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2764 2759
2765 bnx2x_release_alr(bp); 2760 bnx2x_release_alr(bp);
2766 2761
2767 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 2762 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2768 2763
2769 val = ~deasserted; 2764 val = ~deasserted;
2770 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", 2765 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2771 val, reg_addr); 2766 val, reg_addr);
2772 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); 2767 REG_WR(bp, reg_addr, val);
2773 2768
2774 if (~bp->attn_state & deasserted) 2769 if (~bp->attn_state & deasserted)
2775 BNX2X_ERR("IGU ERROR\n"); 2770 BNX2X_ERR("IGU ERROR\n");
@@ -3998,8 +3993,8 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3998 sizeof(struct cstorm_def_status_block)/4); 3993 sizeof(struct cstorm_def_status_block)/4);
3999} 3994}
4000 3995
4001static void bnx2x_init_sb(struct bnx2x *bp, int sb_id, 3996static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4002 struct host_status_block *sb, dma_addr_t mapping) 3997 dma_addr_t mapping, int sb_id)
4003{ 3998{
4004 int port = BP_PORT(bp); 3999 int port = BP_PORT(bp);
4005 int func = BP_FUNC(bp); 4000 int func = BP_FUNC(bp);
@@ -4075,7 +4070,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4075 atten_status_block); 4070 atten_status_block);
4076 def_sb->atten_status_block.status_block_id = sb_id; 4071 def_sb->atten_status_block.status_block_id = sb_id;
4077 4072
4078 bp->def_att_idx = 0;
4079 bp->attn_state = 0; 4073 bp->attn_state = 0;
4080 4074
4081 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4075 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
@@ -4109,17 +4103,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4109 u_def_status_block); 4103 u_def_status_block);
4110 def_sb->u_def_status_block.status_block_id = sb_id; 4104 def_sb->u_def_status_block.status_block_id = sb_id;
4111 4105
4112 bp->def_u_idx = 0;
4113
4114 REG_WR(bp, BAR_USTRORM_INTMEM + 4106 REG_WR(bp, BAR_USTRORM_INTMEM +
4115 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4107 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4116 REG_WR(bp, BAR_USTRORM_INTMEM + 4108 REG_WR(bp, BAR_USTRORM_INTMEM +
4117 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4109 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4118 U64_HI(section)); 4110 U64_HI(section));
4119 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + 4111 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4120 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4112 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4121 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
4122 BNX2X_BTR);
4123 4113
4124 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) 4114 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4125 REG_WR16(bp, BAR_USTRORM_INTMEM + 4115 REG_WR16(bp, BAR_USTRORM_INTMEM +
@@ -4130,17 +4120,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4130 c_def_status_block); 4120 c_def_status_block);
4131 def_sb->c_def_status_block.status_block_id = sb_id; 4121 def_sb->c_def_status_block.status_block_id = sb_id;
4132 4122
4133 bp->def_c_idx = 0;
4134
4135 REG_WR(bp, BAR_CSTRORM_INTMEM + 4123 REG_WR(bp, BAR_CSTRORM_INTMEM +
4136 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4124 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4137 REG_WR(bp, BAR_CSTRORM_INTMEM + 4125 REG_WR(bp, BAR_CSTRORM_INTMEM +
4138 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4126 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4139 U64_HI(section)); 4127 U64_HI(section));
4140 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + 4128 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4141 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4129 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4142 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
4143 BNX2X_BTR);
4144 4130
4145 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) 4131 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4146 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4132 REG_WR16(bp, BAR_CSTRORM_INTMEM +
@@ -4151,17 +4137,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4151 t_def_status_block); 4137 t_def_status_block);
4152 def_sb->t_def_status_block.status_block_id = sb_id; 4138 def_sb->t_def_status_block.status_block_id = sb_id;
4153 4139
4154 bp->def_t_idx = 0;
4155
4156 REG_WR(bp, BAR_TSTRORM_INTMEM + 4140 REG_WR(bp, BAR_TSTRORM_INTMEM +
4157 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4141 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4158 REG_WR(bp, BAR_TSTRORM_INTMEM + 4142 REG_WR(bp, BAR_TSTRORM_INTMEM +
4159 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4143 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4160 U64_HI(section)); 4144 U64_HI(section));
4161 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF + 4145 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4162 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4146 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4163 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
4164 BNX2X_BTR);
4165 4147
4166 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++) 4148 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4167 REG_WR16(bp, BAR_TSTRORM_INTMEM + 4149 REG_WR16(bp, BAR_TSTRORM_INTMEM +
@@ -4172,17 +4154,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
4172 x_def_status_block); 4154 x_def_status_block);
4173 def_sb->x_def_status_block.status_block_id = sb_id; 4155 def_sb->x_def_status_block.status_block_id = sb_id;
4174 4156
4175 bp->def_x_idx = 0;
4176
4177 REG_WR(bp, BAR_XSTRORM_INTMEM + 4157 REG_WR(bp, BAR_XSTRORM_INTMEM +
4178 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); 4158 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4179 REG_WR(bp, BAR_XSTRORM_INTMEM + 4159 REG_WR(bp, BAR_XSTRORM_INTMEM +
4180 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), 4160 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4181 U64_HI(section)); 4161 U64_HI(section));
4182 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF + 4162 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4183 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); 4163 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4184 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
4185 BNX2X_BTR);
4186 4164
4187 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++) 4165 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4188 REG_WR16(bp, BAR_XSTRORM_INTMEM + 4166 REG_WR16(bp, BAR_XSTRORM_INTMEM +
@@ -4205,21 +4183,25 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
4205 /* HC_INDEX_U_ETH_RX_CQ_CONS */ 4183 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4206 REG_WR8(bp, BAR_USTRORM_INTMEM + 4184 REG_WR8(bp, BAR_USTRORM_INTMEM +
4207 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4185 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4208 HC_INDEX_U_ETH_RX_CQ_CONS), 4186 U_SB_ETH_RX_CQ_INDEX),
4209 bp->rx_ticks/12); 4187 bp->rx_ticks/12);
4210 REG_WR16(bp, BAR_USTRORM_INTMEM + 4188 REG_WR16(bp, BAR_USTRORM_INTMEM +
4211 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4189 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4212 HC_INDEX_U_ETH_RX_CQ_CONS), 4190 U_SB_ETH_RX_CQ_INDEX),
4191 bp->rx_ticks ? 0 : 1);
4192 REG_WR16(bp, BAR_USTRORM_INTMEM +
4193 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4194 U_SB_ETH_RX_BD_INDEX),
4213 bp->rx_ticks ? 0 : 1); 4195 bp->rx_ticks ? 0 : 1);
4214 4196
4215 /* HC_INDEX_C_ETH_TX_CQ_CONS */ 4197 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4216 REG_WR8(bp, BAR_CSTRORM_INTMEM + 4198 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4217 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, 4199 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4218 HC_INDEX_C_ETH_TX_CQ_CONS), 4200 C_SB_ETH_TX_CQ_INDEX),
4219 bp->tx_ticks/12); 4201 bp->tx_ticks/12);
4220 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4202 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4221 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, 4203 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4222 HC_INDEX_C_ETH_TX_CQ_CONS), 4204 C_SB_ETH_TX_CQ_INDEX),
4223 bp->tx_ticks ? 0 : 1); 4205 bp->tx_ticks ? 0 : 1);
4224 } 4206 }
4225} 4207}
@@ -4494,7 +4476,7 @@ static void bnx2x_init_context(struct bnx2x *bp)
4494 } 4476 }
4495 4477
4496 context->cstorm_st_context.sb_index_number = 4478 context->cstorm_st_context.sb_index_number =
4497 HC_INDEX_C_ETH_TX_CQ_CONS; 4479 C_SB_ETH_TX_CQ_INDEX;
4498 context->cstorm_st_context.status_block_id = sb_id; 4480 context->cstorm_st_context.status_block_id = sb_id;
4499 4481
4500 context->xstorm_ag_context.cdu_reserved = 4482 context->xstorm_ag_context.cdu_reserved =
@@ -4773,12 +4755,14 @@ static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4773 DP(NETIF_MSG_IFUP, 4755 DP(NETIF_MSG_IFUP,
4774 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", 4756 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4775 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp)); 4757 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4776 bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk, 4758 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4777 fp->status_blk_mapping); 4759 FP_SB_ID(fp));
4760 bnx2x_update_fpsb_idx(fp);
4778 } 4761 }
4779 4762
4780 bnx2x_init_def_sb(bp, bp->def_status_blk, 4763 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4781 bp->def_status_blk_mapping, DEF_SB_ID); 4764 DEF_SB_ID);
4765 bnx2x_update_dsb_idx(bp);
4782 bnx2x_update_coalesce(bp); 4766 bnx2x_update_coalesce(bp);
4783 bnx2x_init_rx_rings(bp); 4767 bnx2x_init_rx_rings(bp);
4784 bnx2x_init_tx_ring(bp); 4768 bnx2x_init_tx_ring(bp);
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index f72ffd29e379..a85ff2073681 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -740,6 +740,7 @@
740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 740#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
741#define HC_REG_ATTN_NUM_P0 0x108038 741#define HC_REG_ATTN_NUM_P0 0x108038
742#define HC_REG_ATTN_NUM_P1 0x10803c 742#define HC_REG_ATTN_NUM_P1 0x10803c
743#define HC_REG_COMMAND_REG 0x108180
743#define HC_REG_CONFIG_0 0x108000 744#define HC_REG_CONFIG_0 0x108000
744#define HC_REG_CONFIG_1 0x108004 745#define HC_REG_CONFIG_1 0x108004
745#define HC_REG_FUNC_NUM_P0 0x1080ac 746#define HC_REG_FUNC_NUM_P0 0x1080ac
@@ -5168,59 +5169,73 @@
5168#define GRCBASE_MISC_AEU GRCBASE_MISC 5169#define GRCBASE_MISC_AEU GRCBASE_MISC
5169 5170
5170 5171
5171/*the offset of the configuration space in the pci core register*/ 5172/* offset of configuration space in the pci core register */
5172#define PCICFG_OFFSET 0x2000 5173#define PCICFG_OFFSET 0x2000
5173#define PCICFG_VENDOR_ID_OFFSET 0x00 5174#define PCICFG_VENDOR_ID_OFFSET 0x00
5174#define PCICFG_DEVICE_ID_OFFSET 0x02 5175#define PCICFG_DEVICE_ID_OFFSET 0x02
5175#define PCICFG_COMMAND_OFFSET 0x04 5176#define PCICFG_COMMAND_OFFSET 0x04
5177#define PCICFG_COMMAND_IO_SPACE (1<<0)
5178#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5179#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5180#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5181#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5182#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5183#define PCICFG_COMMAND_PERR_ENA (1<<6)
5184#define PCICFG_COMMAND_STEPPING (1<<7)
5185#define PCICFG_COMMAND_SERR_ENA (1<<8)
5186#define PCICFG_COMMAND_FAST_B2B (1<<9)
5187#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5188#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5176#define PCICFG_STATUS_OFFSET 0x06 5189#define PCICFG_STATUS_OFFSET 0x06
5177#define PCICFG_REVESION_ID 0x08 5190#define PCICFG_REVESION_ID 0x08
5178#define PCICFG_CACHE_LINE_SIZE 0x0c 5191#define PCICFG_CACHE_LINE_SIZE 0x0c
5179#define PCICFG_LATENCY_TIMER 0x0d 5192#define PCICFG_LATENCY_TIMER 0x0d
5180#define PCICFG_BAR_1_LOW 0x10 5193#define PCICFG_BAR_1_LOW 0x10
5181#define PCICFG_BAR_1_HIGH 0x14 5194#define PCICFG_BAR_1_HIGH 0x14
5182#define PCICFG_BAR_2_LOW 0x18 5195#define PCICFG_BAR_2_LOW 0x18
5183#define PCICFG_BAR_2_HIGH 0x1c 5196#define PCICFG_BAR_2_HIGH 0x1c
5184#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5197#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5185#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5198#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5186#define PCICFG_INT_LINE 0x3c 5199#define PCICFG_INT_LINE 0x3c
5187#define PCICFG_INT_PIN 0x3d 5200#define PCICFG_INT_PIN 0x3d
5188#define PCICFG_PM_CSR_OFFSET 0x4c 5201#define PCICFG_PM_CAPABILITY 0x48
5189#define PCICFG_GRC_ADDRESS 0x78 5202#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5190#define PCICFG_GRC_DATA 0x80 5203#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5204#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5205#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5206#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5207#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5208#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5209#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5210#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5211#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5212#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5213#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5214#define PCICFG_PM_CSR_OFFSET 0x4c
5215#define PCICFG_PM_CSR_STATE (0x3<<0)
5216#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5217#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5218#define PCICFG_GRC_ADDRESS 0x78
5219#define PCICFG_GRC_DATA 0x80
5191#define PCICFG_DEVICE_CONTROL 0xb4 5220#define PCICFG_DEVICE_CONTROL 0xb4
5192#define PCICFG_LINK_CONTROL 0xbc 5221#define PCICFG_LINK_CONTROL 0xbc
5193 5222
5194#define PCICFG_COMMAND_IO_SPACE (1<<0)
5195#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5196#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5197#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5198#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5199#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5200#define PCICFG_COMMAND_PERR_ENA (1<<6)
5201#define PCICFG_COMMAND_STEPPING (1<<7)
5202#define PCICFG_COMMAND_SERR_ENA (1<<8)
5203#define PCICFG_COMMAND_FAST_B2B (1<<9)
5204#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5205#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5206
5207#define PCICFG_PM_CSR_STATE (0x3<<0)
5208#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5209 5223
5210#define BAR_USTRORM_INTMEM 0x400000 5224#define BAR_USTRORM_INTMEM 0x400000
5211#define BAR_CSTRORM_INTMEM 0x410000 5225#define BAR_CSTRORM_INTMEM 0x410000
5212#define BAR_XSTRORM_INTMEM 0x420000 5226#define BAR_XSTRORM_INTMEM 0x420000
5213#define BAR_TSTRORM_INTMEM 0x430000 5227#define BAR_TSTRORM_INTMEM 0x430000
5214 5228
5229/* for accessing the IGU in case of status block ACK */
5215#define BAR_IGU_INTMEM 0x440000 5230#define BAR_IGU_INTMEM 0x440000
5216 5231
5217#define BAR_DOORBELL_OFFSET 0x800000 5232#define BAR_DOORBELL_OFFSET 0x800000
5218 5233
5219#define BAR_ME_REGISTER 0x450000 5234#define BAR_ME_REGISTER 0x450000
5220 5235
5221 5236/* config_2 offset */
5222#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */ 5237#define GRC_CONFIG_2_SIZE_REG 0x408
5223#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 5238#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5224#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 5239#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5225#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 5240#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5226#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 5241#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
@@ -5237,11 +5252,11 @@
5237#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 5252#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5238#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 5253#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5239#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 5254#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5240#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 5255#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5241#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 5256#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5242#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 5257#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5243#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 5258#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5244#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 5259#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5245#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 5260#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5246#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 5261#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5247#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 5262#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
@@ -5258,46 +5273,44 @@
5258#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 5273#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5259#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 5274#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5260#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 5275#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5261#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 5276#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5262#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 5277#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5263 5278
5264/* config_3 offset */ 5279/* config_3 offset */
5265#define GRC_CONFIG_3_SIZE_REG (0x40c) 5280#define GRC_CONFIG_3_SIZE_REG 0x40c
5266#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 5281#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5267#define PCI_CONFIG_3_FORCE_PME (1L<<24) 5282#define PCI_CONFIG_3_FORCE_PME (1L<<24)
5268#define PCI_CONFIG_3_PME_STATUS (1L<<25) 5283#define PCI_CONFIG_3_PME_STATUS (1L<<25)
5269#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 5284#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5270#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 5285#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5271#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 5286#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5272#define PCI_CONFIG_3_PCI_POWER (1L<<31) 5287#define PCI_CONFIG_3_PCI_POWER (1L<<31)
5273
5274/* config_2 offset */
5275#define GRC_CONFIG_2_SIZE_REG 0x408
5276 5288
5277#define GRC_BAR2_CONFIG 0x4e0 5289#define GRC_BAR2_CONFIG 0x4e0
5278#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 5290#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5279#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 5291#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5280#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 5292#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5281#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 5293#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5282#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 5294#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5283#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 5295#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5284#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 5296#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5285#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 5297#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5286#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 5298#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5287#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 5299#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5288#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 5300#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5289#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 5301#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5290#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 5302#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5291#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 5303#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5292#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 5304#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5293#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 5305#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5294#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 5306#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5295#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 5307#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5308
5309#define PCI_PM_DATA_A 0x410
5310#define PCI_PM_DATA_B 0x414
5311#define PCI_ID_VAL1 0x434
5312#define PCI_ID_VAL2 0x438
5296 5313
5297#define PCI_PM_DATA_A (0x410)
5298#define PCI_PM_DATA_B (0x414)
5299#define PCI_ID_VAL1 (0x434)
5300#define PCI_ID_VAL2 (0x438)
5301 5314
5302#define MDIO_REG_BANK_CL73_IEEEB0 0x0 5315#define MDIO_REG_BANK_CL73_IEEEB0 0x0
5303#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 5316#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
@@ -5624,4 +5637,13 @@ Theotherbitsarereservedandshouldbezero*/
5624#define IGU_INT_NOP 2 5637#define IGU_INT_NOP 2
5625#define IGU_INT_NOP2 3 5638#define IGU_INT_NOP2 3
5626 5639
5640#define COMMAND_REG_INT_ACK 0x0
5641#define COMMAND_REG_PROD_UPD 0x4
5642#define COMMAND_REG_ATTN_BITS_UPD 0x8
5643#define COMMAND_REG_ATTN_BITS_SET 0xc
5644#define COMMAND_REG_ATTN_BITS_CLR 0x10
5645#define COMMAND_REG_COALESCE_NOW 0x14
5646#define COMMAND_REG_SIMD_MASK 0x18
5647#define COMMAND_REG_SIMD_NOMASK 0x1c
5648
5627 5649
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 13:34:03 -0500