diff options
-rw-r--r-- | drivers/scsi/a100u2w.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/scsi/a100u2w.c b/drivers/scsi/a100u2w.c index ced3eebe252c..1dd0fcfe1d70 100644 --- a/drivers/scsi/a100u2w.c +++ b/drivers/scsi/a100u2w.c | |||
@@ -389,7 +389,7 @@ static u8 orc_load_firmware(struct orc_host * host) | |||
389 | 389 | ||
390 | outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ | 390 | outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ |
391 | data32_ptr = (u8 *) & data32; | 391 | data32_ptr = (u8 *) & data32; |
392 | data32 = 0; /* Initial FW address to 0 */ | 392 | data32 = cpu_to_le32(0); /* Initial FW address to 0 */ |
393 | outw(0x0010, host->base + ORC_EBIOSADR0); | 393 | outw(0x0010, host->base + ORC_EBIOSADR0); |
394 | *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ | 394 | *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ |
395 | outw(0x0011, host->base + ORC_EBIOSADR0); | 395 | outw(0x0011, host->base + ORC_EBIOSADR0); |
@@ -397,18 +397,18 @@ static u8 orc_load_firmware(struct orc_host * host) | |||
397 | outw(0x0012, host->base + ORC_EBIOSADR0); | 397 | outw(0x0012, host->base + ORC_EBIOSADR0); |
398 | *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ | 398 | *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ |
399 | outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); | 399 | outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); |
400 | outl(data32, host->base + ORC_FWBASEADR); /* Write FW address */ | 400 | outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR); /* Write FW address */ |
401 | 401 | ||
402 | /* Copy the code from the BIOS to the SRAM */ | 402 | /* Copy the code from the BIOS to the SRAM */ |
403 | 403 | ||
404 | bios_addr = (u16) data32; /* FW code locate at BIOS address + ? */ | 404 | bios_addr = (u16) le32_to_cpu(data32); /* FW code locate at BIOS address + ? */ |
405 | for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */ | 405 | for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */ |
406 | i < 0x1000; /* Firmware code size = 4K */ | 406 | i < 0x1000; /* Firmware code size = 4K */ |
407 | i++, bios_addr++) { | 407 | i++, bios_addr++) { |
408 | outw(bios_addr, host->base + ORC_EBIOSADR0); | 408 | outw(bios_addr, host->base + ORC_EBIOSADR0); |
409 | *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ | 409 | *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ |
410 | if ((i % 4) == 3) { | 410 | if ((i % 4) == 3) { |
411 | outl(data32, host->base + ORC_RISCRAM); /* Write every 4 bytes */ | 411 | outl(le32_to_cpu(data32), host->base + ORC_RISCRAM); /* Write every 4 bytes */ |
412 | data32_ptr = (u8 *) & data32; | 412 | data32_ptr = (u8 *) & data32; |
413 | } | 413 | } |
414 | } | 414 | } |
@@ -423,7 +423,7 @@ static u8 orc_load_firmware(struct orc_host * host) | |||
423 | outw(bios_addr, host->base + ORC_EBIOSADR0); | 423 | outw(bios_addr, host->base + ORC_EBIOSADR0); |
424 | *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ | 424 | *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ |
425 | if ((i % 4) == 3) { | 425 | if ((i % 4) == 3) { |
426 | if (inl(host->base + ORC_RISCRAM) != data32) { | 426 | if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) { |
427 | outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ | 427 | outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ |
428 | outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ | 428 | outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ |
429 | return 0; | 429 | return 0; |
@@ -459,8 +459,8 @@ static void setup_SCBs(struct orc_host * host) | |||
459 | 459 | ||
460 | for (i = 0; i < ORC_MAXQUEUE; i++) { | 460 | for (i = 0; i < ORC_MAXQUEUE; i++) { |
461 | escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i)); | 461 | escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i)); |
462 | scb->sg_addr = (u32) escb_phys; | 462 | scb->sg_addr = cpu_to_le32((u32) escb_phys); |
463 | scb->sense_addr = (u32) escb_phys; | 463 | scb->sense_addr = cpu_to_le32((u32) escb_phys); |
464 | scb->escb = escb; | 464 | scb->escb = escb; |
465 | scb->scbidx = i; | 465 | scb->scbidx = i; |
466 | scb++; | 466 | scb++; |
@@ -642,8 +642,8 @@ static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsig | |||
642 | scb->link = 0xFF; | 642 | scb->link = 0xFF; |
643 | scb->reserved0 = 0; | 643 | scb->reserved0 = 0; |
644 | scb->reserved1 = 0; | 644 | scb->reserved1 = 0; |
645 | scb->xferlen = 0; | 645 | scb->xferlen = cpu_to_le32(0); |
646 | scb->sg_len = 0; | 646 | scb->sg_len = cpu_to_le32(0); |
647 | 647 | ||
648 | escb->srb = NULL; | 648 | escb->srb = NULL; |
649 | escb->srb = cmd; | 649 | escb->srb = cmd; |
@@ -858,9 +858,9 @@ static void inia100_build_scb(struct orc_host * host, struct orc_scb * scb, stru | |||
858 | scb->lun = cmd->device->lun; | 858 | scb->lun = cmd->device->lun; |
859 | scb->reserved0 = 0; | 859 | scb->reserved0 = 0; |
860 | scb->reserved1 = 0; | 860 | scb->reserved1 = 0; |
861 | scb->sg_len = 0; | 861 | scb->sg_len = cpu_to_le32(0); |
862 | 862 | ||
863 | scb->xferlen = (u32) scsi_bufflen(cmd); | 863 | scb->xferlen = cpu_to_le32((u32) scsi_bufflen(cmd)); |
864 | sgent = (struct orc_sgent *) & escb->sglist[0]; | 864 | sgent = (struct orc_sgent *) & escb->sglist[0]; |
865 | 865 | ||
866 | count_sg = scsi_dma_map(cmd); | 866 | count_sg = scsi_dma_map(cmd); |
@@ -868,18 +868,18 @@ static void inia100_build_scb(struct orc_host * host, struct orc_scb * scb, stru | |||
868 | 868 | ||
869 | /* Build the scatter gather lists */ | 869 | /* Build the scatter gather lists */ |
870 | if (count_sg) { | 870 | if (count_sg) { |
871 | scb->sg_len = (u32) (count_sg * 8); | 871 | scb->sg_len = cpu_to_le32((u32) (count_sg * 8)); |
872 | scsi_for_each_sg(cmd, sg, count_sg, i) { | 872 | scsi_for_each_sg(cmd, sg, count_sg, i) { |
873 | sgent->base = (u32) sg_dma_address(sg); | 873 | sgent->base = cpu_to_le32((u32) sg_dma_address(sg)); |
874 | sgent->length = (u32) sg_dma_len(sg); | 874 | sgent->length = cpu_to_le32((u32) sg_dma_len(sg)); |
875 | sgent++; | 875 | sgent++; |
876 | } | 876 | } |
877 | } else { | 877 | } else { |
878 | scb->sg_len = 0; | 878 | scb->sg_len = cpu_to_le32(0); |
879 | sgent->base = 0; | 879 | sgent->base = cpu_to_le32(0); |
880 | sgent->length = 0; | 880 | sgent->length = cpu_to_le32(0); |
881 | } | 881 | } |
882 | scb->sg_addr = (u32) scb->sense_addr; | 882 | scb->sg_addr = (u32) scb->sense_addr; /* sense_addr is already little endian */ |
883 | scb->hastat = 0; | 883 | scb->hastat = 0; |
884 | scb->tastat = 0; | 884 | scb->tastat = 0; |
885 | scb->link = 0xFF; | 885 | scb->link = 0xFF; |