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-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.c17
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.h54
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c472
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.h127
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c193
5 files changed, 644 insertions, 219 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index 2a60c89ab346..a1562287342f 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -31,6 +31,7 @@
31#include "ixgbe_type.h" 31#include "ixgbe_type.h"
32#include "ixgbe_dcb.h" 32#include "ixgbe_dcb.h"
33#include "ixgbe_dcb_82598.h" 33#include "ixgbe_dcb_82598.h"
34#include "ixgbe_dcb_82599.h"
34 35
35/** 36/**
36 * ixgbe_dcb_config - Struct containing DCB settings. 37 * ixgbe_dcb_config - Struct containing DCB settings.
@@ -215,6 +216,8 @@ s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
215 s32 ret = 0; 216 s32 ret = 0;
216 if (hw->mac.type == ixgbe_mac_82598EB) 217 if (hw->mac.type == ixgbe_mac_82598EB)
217 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); 218 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
219 else if (hw->mac.type == ixgbe_mac_82599EB)
220 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
218 return ret; 221 return ret;
219} 222}
220 223
@@ -232,6 +235,8 @@ s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
232 s32 ret = 0; 235 s32 ret = 0;
233 if (hw->mac.type == ixgbe_mac_82598EB) 236 if (hw->mac.type == ixgbe_mac_82598EB)
234 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); 237 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
238 else if (hw->mac.type == ixgbe_mac_82599EB)
239 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
235 return ret; 240 return ret;
236} 241}
237 242
@@ -248,6 +253,8 @@ s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw,
248 s32 ret = 0; 253 s32 ret = 0;
249 if (hw->mac.type == ixgbe_mac_82598EB) 254 if (hw->mac.type == ixgbe_mac_82598EB)
250 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); 255 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
256 else if (hw->mac.type == ixgbe_mac_82599EB)
257 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config);
251 return ret; 258 return ret;
252} 259}
253 260
@@ -264,6 +271,8 @@ s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw,
264 s32 ret = 0; 271 s32 ret = 0;
265 if (hw->mac.type == ixgbe_mac_82598EB) 272 if (hw->mac.type == ixgbe_mac_82598EB)
266 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config); 273 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
274 else if (hw->mac.type == ixgbe_mac_82599EB)
275 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config);
267 return ret; 276 return ret;
268} 277}
269 278
@@ -280,6 +289,8 @@ s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw,
280 s32 ret = 0; 289 s32 ret = 0;
281 if (hw->mac.type == ixgbe_mac_82598EB) 290 if (hw->mac.type == ixgbe_mac_82598EB)
282 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config); 291 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
292 else if (hw->mac.type == ixgbe_mac_82599EB)
293 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config);
283 return ret; 294 return ret;
284} 295}
285 296
@@ -296,6 +307,8 @@ s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw,
296 s32 ret = 0; 307 s32 ret = 0;
297 if (hw->mac.type == ixgbe_mac_82598EB) 308 if (hw->mac.type == ixgbe_mac_82598EB)
298 ret = ixgbe_dcb_config_pfc_82598(hw, dcb_config); 309 ret = ixgbe_dcb_config_pfc_82598(hw, dcb_config);
310 else if (hw->mac.type == ixgbe_mac_82599EB)
311 ret = ixgbe_dcb_config_pfc_82599(hw, dcb_config);
299 return ret; 312 return ret;
300} 313}
301 314
@@ -311,6 +324,8 @@ s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
311 s32 ret = 0; 324 s32 ret = 0;
312 if (hw->mac.type == ixgbe_mac_82598EB) 325 if (hw->mac.type == ixgbe_mac_82598EB)
313 ret = ixgbe_dcb_config_tc_stats_82598(hw); 326 ret = ixgbe_dcb_config_tc_stats_82598(hw);
327 else if (hw->mac.type == ixgbe_mac_82599EB)
328 ret = ixgbe_dcb_config_tc_stats_82599(hw);
314 return ret; 329 return ret;
315} 330}
316 331
@@ -327,6 +342,8 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
327 s32 ret = 0; 342 s32 ret = 0;
328 if (hw->mac.type == ixgbe_mac_82598EB) 343 if (hw->mac.type == ixgbe_mac_82598EB)
329 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config); 344 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config);
345 else if (hw->mac.type == ixgbe_mac_82599EB)
346 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config);
330 return ret; 347 return ret;
331} 348}
332 349
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h
index 0da5c6d5bcaf..64a9fa15c059 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ixgbe/ixgbe_dcb.h
@@ -75,6 +75,26 @@ enum strict_prio_type {
75 prio_link 75 prio_link
76}; 76};
77 77
78/* DCB capability definitions */
79#define IXGBE_DCB_PG_SUPPORT 0x00000001
80#define IXGBE_DCB_PFC_SUPPORT 0x00000002
81#define IXGBE_DCB_BCN_SUPPORT 0x00000004
82#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
83#define IXGBE_DCB_GSP_SUPPORT 0x00000010
84
85#define IXGBE_DCB_8_TC_SUPPORT 0x80
86
87struct dcb_support {
88 /* DCB capabilities */
89 u32 capabilities;
90
91 /* Each bit represents a number of TCs configurable in the hw.
92 * If 8 traffic classes can be configured, the value is 0x80.
93 */
94 u8 traffic_classes;
95 u8 pfc_traffic_classes;
96};
97
78/* Traffic class bandwidth allocation per direction */ 98/* Traffic class bandwidth allocation per direction */
79struct tc_bw_alloc { 99struct tc_bw_alloc {
80 u8 bwg_id; /* Bandwidth Group (BWG) ID */ 100 u8 bwg_id; /* Bandwidth Group (BWG) ID */
@@ -108,38 +128,18 @@ enum dcb_rx_pba_cfg {
108 pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 128 pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
109}; 129};
110 130
111/* 131struct dcb_num_tcs {
112 * This structure contains many values encoded as fixed-point 132 u8 pg_tcs;
113 * numbers, meaning that some of bits are dedicated to the 133 u8 pfc_tcs;
114 * magnitude and others to the fraction part. In the comments
115 * this is shown as f=n, where n is the number of fraction bits.
116 * These fraction bits are always the low-order bits. The size
117 * of the magnitude is not specified.
118 */
119struct bcn_config {
120 u32 rp_admin_mode[MAX_TRAFFIC_CLASS]; /* BCN enabled, per TC */
121 u32 bcna_option[2]; /* BCNA Port + MAC Addr */
122 u32 rp_w; /* Derivative Weight, f=3 */
123 u32 rp_gi; /* Increase Gain, f=12 */
124 u32 rp_gd; /* Decrease Gain, f=12 */
125 u32 rp_ru; /* Rate Unit */
126 u32 rp_alpha; /* Max Decrease Factor, f=12 */
127 u32 rp_beta; /* Max Increase Factor, f=12 */
128 u32 rp_ri; /* Initial Rate */
129 u32 rp_td; /* Drift Interval Timer */
130 u32 rp_rd; /* Drift Increase */
131 u32 rp_tmax; /* Severe Congestion Backoff Timer Range */
132 u32 rp_rmin; /* Severe Congestion Restart Rate */
133 u32 rp_wrtt; /* RTT Moving Average Weight */
134}; 134};
135 135
136struct ixgbe_dcb_config { 136struct ixgbe_dcb_config {
137 struct bcn_config bcn; 137 struct dcb_support support;
138 138 struct dcb_num_tcs num_tcs;
139 struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; 139 struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
140 u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ 140 u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
141 141 bool pfc_mode_enable;
142 bool round_robin_enable; 142 bool round_robin_enable;
143 143
144 enum dcb_rx_pba_cfg rx_pba_cfg; 144 enum dcb_rx_pba_cfg rx_pba_cfg;
145 145
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
new file mode 100644
index 000000000000..1467d56435a0
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -0,0 +1,472 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "ixgbe.h"
29#include "ixgbe_type.h"
30#include "ixgbe_dcb.h"
31#include "ixgbe_dcb_82599.h"
32
33/**
34 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
35 * @hw: pointer to hardware structure
36 * @stats: pointer to statistics structure
37 * @tc_count: Number of elements in bwg_array.
38 *
39 * This function returns the status data for each of the Traffic Classes in use.
40 */
41s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
42 struct ixgbe_hw_stats *stats,
43 u8 tc_count)
44{
45 int tc;
46
47 if (tc_count > MAX_TRAFFIC_CLASS)
48 return DCB_ERR_PARAM;
49 /* Statistics pertaining to each traffic class */
50 for (tc = 0; tc < tc_count; tc++) {
51 /* Transmitted Packets */
52 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
53 /* Transmitted Bytes */
54 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
55 /* Received Packets */
56 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
57 /* Received Bytes */
58 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
59 }
60
61 return 0;
62}
63
64/**
65 * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
66 * @hw: pointer to hardware structure
67 * @stats: pointer to statistics structure
68 * @tc_count: Number of elements in bwg_array.
69 *
70 * This function returns the CBFC status data for each of the Traffic Classes.
71 */
72s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
73 struct ixgbe_hw_stats *stats,
74 u8 tc_count)
75{
76 int tc;
77
78 if (tc_count > MAX_TRAFFIC_CLASS)
79 return DCB_ERR_PARAM;
80 for (tc = 0; tc < tc_count; tc++) {
81 /* Priority XOFF Transmitted */
82 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
83 /* Priority XOFF Received */
84 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
85 }
86
87 return 0;
88}
89
90/**
91 * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
92 * @hw: pointer to hardware structure
93 * @dcb_config: pointer to ixgbe_dcb_config structure
94 *
95 * Configure packet buffers for DCB mode.
96 */
97s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw,
98 struct ixgbe_dcb_config *dcb_config)
99{
100 s32 ret_val = 0;
101 u32 value = IXGBE_RXPBSIZE_64KB;
102 u8 i = 0;
103
104 /* Setup Rx packet buffer sizes */
105 switch (dcb_config->rx_pba_cfg) {
106 case pba_80_48:
107 /* Setup the first four at 80KB */
108 value = IXGBE_RXPBSIZE_80KB;
109 for (; i < 4; i++)
110 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
111 /* Setup the last four at 48KB...don't re-init i */
112 value = IXGBE_RXPBSIZE_48KB;
113 /* Fall Through */
114 case pba_equal:
115 default:
116 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
117 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
118
119 /* Setup Tx packet buffer sizes */
120 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
121 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
122 IXGBE_TXPBSIZE_20KB);
123 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i),
124 IXGBE_TXPBTHRESH_DCB);
125 }
126 break;
127 }
128
129 return ret_val;
130}
131
132/**
133 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
134 * @hw: pointer to hardware structure
135 * @dcb_config: pointer to ixgbe_dcb_config structure
136 *
137 * Configure Rx Packet Arbiter and credits for each traffic class.
138 */
139s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
140 struct ixgbe_dcb_config *dcb_config)
141{
142 struct tc_bw_alloc *p;
143 u32 reg = 0;
144 u32 credit_refill = 0;
145 u32 credit_max = 0;
146 u8 i = 0;
147
148 /* Disable the arbiter before changing parameters */
149 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RTRPCS_ARBDIS);
150
151 /* Map all traffic classes to their UP, 1 to 1 */
152 reg = 0;
153 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
154 reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT));
155 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
156
157 /* Configure traffic class credits and priority */
158 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
159 p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
160
161 credit_refill = p->data_credits_refill;
162 credit_max = p->data_credits_max;
163 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
164
165 reg |= (u32)(p->bwg_id) << IXGBE_RTRPT4C_BWG_SHIFT;
166
167 if (p->prio_type == prio_link)
168 reg |= IXGBE_RTRPT4C_LSP;
169
170 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
171 }
172
173 /*
174 * Configure Rx packet plane (recycle mode; WSP) and
175 * enable arbiter
176 */
177 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
178 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
179
180 return 0;
181}
182
183/**
184 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
185 * @hw: pointer to hardware structure
186 * @dcb_config: pointer to ixgbe_dcb_config structure
187 *
188 * Configure Tx Descriptor Arbiter and credits for each traffic class.
189 */
190s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
191 struct ixgbe_dcb_config *dcb_config)
192{
193 struct tc_bw_alloc *p;
194 u32 reg, max_credits;
195 u8 i;
196
197 /* Disable the arbiter before changing parameters */
198 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, IXGBE_RTTDCS_ARBDIS);
199
200 /* Clear the per-Tx queue credits; we use per-TC instead */
201 for (i = 0; i < 128; i++) {
202 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
203 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
204 }
205
206 /* Configure traffic class credits and priority */
207 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
208 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
209 max_credits = dcb_config->tc_config[i].desc_credits_max;
210 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
211 reg |= p->data_credits_refill;
212 reg |= (u32)(p->bwg_id) << IXGBE_RTTDT2C_BWG_SHIFT;
213
214 if (p->prio_type == prio_group)
215 reg |= IXGBE_RTTDT2C_GSP;
216
217 if (p->prio_type == prio_link)
218 reg |= IXGBE_RTTDT2C_LSP;
219
220 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
221 }
222
223 /*
224 * Configure Tx descriptor plane (recycle mode; WSP) and
225 * enable arbiter
226 */
227 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
228 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
229
230 return 0;
231}
232
233/**
234 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
235 * @hw: pointer to hardware structure
236 * @dcb_config: pointer to ixgbe_dcb_config structure
237 *
238 * Configure Tx Packet Arbiter and credits for each traffic class.
239 */
240s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
241 struct ixgbe_dcb_config *dcb_config)
242{
243 struct tc_bw_alloc *p;
244 u32 reg;
245 u8 i;
246
247 /* Disable the arbiter before changing parameters */
248 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, IXGBE_RTTPCS_ARBDIS);
249
250 /* Map all traffic classes to their UP, 1 to 1 */
251 reg = 0;
252 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
253 reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT));
254 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
255
256 /* Configure traffic class credits and priority */
257 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
258 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
259 reg = p->data_credits_refill;
260 reg |= (u32)(p->data_credits_max) << IXGBE_RTTPT2C_MCL_SHIFT;
261 reg |= (u32)(p->bwg_id) << IXGBE_RTTPT2C_BWG_SHIFT;
262
263 if (p->prio_type == prio_group)
264 reg |= IXGBE_RTTPT2C_GSP;
265
266 if (p->prio_type == prio_link)
267 reg |= IXGBE_RTTPT2C_LSP;
268
269 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
270 }
271
272 /*
273 * Configure Tx packet plane (recycle mode; SP; arb delay) and
274 * enable arbiter
275 */
276 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
277 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
278 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
279
280 return 0;
281}
282
283/**
284 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
285 * @hw: pointer to hardware structure
286 * @dcb_config: pointer to ixgbe_dcb_config structure
287 *
288 * Configure Priority Flow Control (PFC) for each traffic class.
289 */
290s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
291 struct ixgbe_dcb_config *dcb_config)
292{
293 u32 i, reg;
294
295 /* If PFC is disabled globally then fall back to LFC. */
296 if (!dcb_config->pfc_mode_enable) {
297 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
298 hw->mac.ops.setup_fc(hw, i);
299 goto out;
300 }
301
302 /* PFC is mutually exclusive with link flow control */
303 hw->fc.current_mode = ixgbe_fc_none;
304
305 /* Configure PFC Tx thresholds per TC */
306 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
307 /* Config and remember Tx */
308 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
309 dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) {
310 reg = hw->fc.high_water | IXGBE_FCRTH_FCEN;
311 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
312 reg = hw->fc.low_water | IXGBE_FCRTL_XONE;
313 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
314 } else {
315 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
316 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
317 }
318 }
319
320 /* Configure pause time (2 TCs per register) */
321 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
322 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
323 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
324
325 /* Configure flow control refresh threshold value */
326 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
327
328 /* Enable Transmit PFC */
329 reg = IXGBE_FCCFG_TFCE_PRIORITY;
330 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
331
332 /*
333 * Enable Receive PFC
334 * We will always honor XOFF frames we receive when
335 * we are in PFC mode.
336 */
337 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
338 reg &= ~IXGBE_MFLCN_RFCE;
339 reg |= IXGBE_MFLCN_RPFCE;
340 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
341out:
342 return 0;
343}
344
345/**
346 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
347 * @hw: pointer to hardware structure
348 *
349 * Configure queue statistics registers, all queues belonging to same traffic
350 * class uses a single set of queue statistics counters.
351 */
352s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
353{
354 u32 reg = 0;
355 u8 i = 0;
356
357 /*
358 * Receive Queues stats setting
359 * 32 RQSMR registers, each configuring 4 queues.
360 * Set all 16 queues of each TC to the same stat
361 * with TC 'n' going to stat 'n'.
362 */
363 for (i = 0; i < 32; i++) {
364 reg = 0x01010101 * (i / 4);
365 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
366 }
367 /*
368 * Transmit Queues stats setting
369 * 32 TQSM registers, each controlling 4 queues.
370 * Set all queues of each TC to the same stat
371 * with TC 'n' going to stat 'n'.
372 * Tx queues are allocated non-uniformly to TCs:
373 * 32, 32, 16, 16, 8, 8, 8, 8.
374 */
375 for (i = 0; i < 32; i++) {
376 if (i < 8)
377 reg = 0x00000000;
378 else if (i < 16)
379 reg = 0x01010101;
380 else if (i < 20)
381 reg = 0x02020202;
382 else if (i < 24)
383 reg = 0x03030303;
384 else if (i < 26)
385 reg = 0x04040404;
386 else if (i < 28)
387 reg = 0x05050505;
388 else if (i < 30)
389 reg = 0x06060606;
390 else
391 reg = 0x07070707;
392 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
393 }
394
395 return 0;
396}
397
398/**
399 * ixgbe_dcb_config_82599 - Configure general DCB parameters
400 * @hw: pointer to hardware structure
401 * @dcb_config: pointer to ixgbe_dcb_config structure
402 *
403 * Configure general DCB parameters.
404 */
405s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
406{
407 u32 reg;
408 u32 q;
409
410 /* Disable the Tx desc arbiter so that MTQC can be changed */
411 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
412 reg |= IXGBE_RTTDCS_ARBDIS;
413 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
414
415 /* Enable DCB for Rx with 8 TCs */
416 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
417 switch (reg & IXGBE_MRQC_MRQE_MASK) {
418 case 0:
419 case IXGBE_MRQC_RT4TCEN:
420 /* RSS disabled cases */
421 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN;
422 break;
423 case IXGBE_MRQC_RSSEN:
424 case IXGBE_MRQC_RTRSS4TCEN:
425 /* RSS enabled cases */
426 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RTRSS8TCEN;
427 break;
428 default:
429 /* Unsupported value, assume stale data, overwrite no RSS */
430 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | IXGBE_MRQC_RT8TCEN;
431 }
432 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
433
434 /* Enable DCB for Tx with 8 TCs */
435 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
436 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
437
438 /* Disable drop for all queues */
439 for (q = 0; q < 128; q++)
440 IXGBE_WRITE_REG(hw, IXGBE_QDE, q << IXGBE_QDE_IDX_SHIFT);
441
442 /* Enable the Tx desc arbiter */
443 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
444 reg &= ~IXGBE_RTTDCS_ARBDIS;
445 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
446
447 return 0;
448}
449
450/**
451 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
452 * @hw: pointer to hardware structure
453 * @dcb_config: pointer to ixgbe_dcb_config structure
454 *
455 * Configure dcb settings and enable dcb mode.
456 */
457s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
458 struct ixgbe_dcb_config *dcb_config)
459{
460 u32 pap = 0;
461
462 ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config);
463 ixgbe_dcb_config_82599(hw);
464 ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config);
465 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config);
466 ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config);
467 ixgbe_dcb_config_pfc_82599(hw, dcb_config);
468 ixgbe_dcb_config_tc_stats_82599(hw);
469
470 return 0;
471}
472
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ixgbe/ixgbe_dcb_82599.h
new file mode 100644
index 000000000000..9e5e2827e4af
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -0,0 +1,127 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _DCB_82599_CONFIG_H_
29#define _DCB_82599_CONFIG_H_
30
31/* DCB register definitions */
32#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
33 * 1 WSP - Weighted Strict Priority
34 */
35#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
36 * 1 WRR - Weighted Round Robin
37 */
38#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
39#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
40#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
41#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
42 * clear!
43 */
44#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
45
46/* Receive UP2TC mapping */
47#define IXGBE_RTRUP2TC_UP_SHIFT 3
48/* Transmit UP2TC mapping */
49#define IXGBE_RTTUP2TC_UP_SHIFT 3
50
51#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
52#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */
53#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
54#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
55
56#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
57 * buffers enable
58 */
59#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
60 * (RSS) enable
61 */
62
63/* RTRPCS Bit Masks */
64#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
65/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
66#define IXGBE_RTRPCS_RAC 0x00000004
67#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */
68
69/* RTTDT2C Bit Masks */
70#define IXGBE_RTTDT2C_MCL_SHIFT 12
71#define IXGBE_RTTDT2C_BWG_SHIFT 9
72#define IXGBE_RTTDT2C_GSP 0x40000000
73#define IXGBE_RTTDT2C_LSP 0x80000000
74
75#define IXGBE_RTTPT2C_MCL_SHIFT 12
76#define IXGBE_RTTPT2C_BWG_SHIFT 9
77#define IXGBE_RTTPT2C_GSP 0x40000000
78#define IXGBE_RTTPT2C_LSP 0x80000000
79
80/* RTTPCS Bit Masks */
81#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,
82 * 1 SP - Strict Priority
83 */
84#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */
85#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
86#define IXGBE_RTTPCS_ARBD_SHIFT 22
87#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
88
89#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
90#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
91#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
92#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
93#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
94#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
95
96#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
97
98
99/* DCB hardware-specific driver APIs */
100
101/* DCB PFC functions */
102s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
103 struct ixgbe_dcb_config *dcb_config);
104s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
105 struct ixgbe_hw_stats *stats,
106 u8 tc_count);
107
108/* DCB traffic class stats */
109s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw);
110s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
111 struct ixgbe_hw_stats *stats,
112 u8 tc_count);
113
114/* DCB config arbiters */
115s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
116 struct ixgbe_dcb_config *dcb_config);
117s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
118 struct ixgbe_dcb_config *dcb_config);
119s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
120 struct ixgbe_dcb_config *dcb_config);
121
122
123/* DCB hw initialization */
124s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
125 struct ixgbe_dcb_config *config);
126
127#endif /* _DCB_82599_CONFIG_H */
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index dd9d1d63a59c..087cf886f2af 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -35,6 +35,7 @@
35#define BIT_PG_RX 0x04 35#define BIT_PG_RX 0x04
36#define BIT_PG_TX 0x08 36#define BIT_PG_TX 0x08
37#define BIT_BCN 0x10 37#define BIT_BCN 0x10
38#define BIT_LINKSPEED 0x80
38 39
39int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, 40int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
40 struct ixgbe_dcb_config *dst_dcb_cfg, int tc_max) 41 struct ixgbe_dcb_config *dst_dcb_cfg, int tc_max)
@@ -89,25 +90,6 @@ int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
89 src_dcb_cfg->tc_config[i - DCB_PFC_UP_ATTR_0].dcb_pfc; 90 src_dcb_cfg->tc_config[i - DCB_PFC_UP_ATTR_0].dcb_pfc;
90 } 91 }
91 92
92 for (i = DCB_BCN_ATTR_RP_0; i < DCB_BCN_ATTR_RP_ALL; i++) {
93 dst_dcb_cfg->bcn.rp_admin_mode[i - DCB_BCN_ATTR_RP_0] =
94 src_dcb_cfg->bcn.rp_admin_mode[i - DCB_BCN_ATTR_RP_0];
95 }
96 dst_dcb_cfg->bcn.bcna_option[0] = src_dcb_cfg->bcn.bcna_option[0];
97 dst_dcb_cfg->bcn.bcna_option[1] = src_dcb_cfg->bcn.bcna_option[1];
98 dst_dcb_cfg->bcn.rp_alpha = src_dcb_cfg->bcn.rp_alpha;
99 dst_dcb_cfg->bcn.rp_beta = src_dcb_cfg->bcn.rp_beta;
100 dst_dcb_cfg->bcn.rp_gd = src_dcb_cfg->bcn.rp_gd;
101 dst_dcb_cfg->bcn.rp_gi = src_dcb_cfg->bcn.rp_gi;
102 dst_dcb_cfg->bcn.rp_tmax = src_dcb_cfg->bcn.rp_tmax;
103 dst_dcb_cfg->bcn.rp_td = src_dcb_cfg->bcn.rp_td;
104 dst_dcb_cfg->bcn.rp_rmin = src_dcb_cfg->bcn.rp_rmin;
105 dst_dcb_cfg->bcn.rp_w = src_dcb_cfg->bcn.rp_w;
106 dst_dcb_cfg->bcn.rp_rd = src_dcb_cfg->bcn.rp_rd;
107 dst_dcb_cfg->bcn.rp_ru = src_dcb_cfg->bcn.rp_ru;
108 dst_dcb_cfg->bcn.rp_wrtt = src_dcb_cfg->bcn.rp_wrtt;
109 dst_dcb_cfg->bcn.rp_ri = src_dcb_cfg->bcn.rp_ri;
110
111 return 0; 93 return 0;
112} 94}
113 95
@@ -444,175 +426,6 @@ static void ixgbe_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
444 return; 426 return;
445} 427}
446 428
447static void ixgbe_dcbnl_getbcnrp(struct net_device *netdev, int priority,
448 u8 *setting)
449{
450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451
452 *setting = adapter->dcb_cfg.bcn.rp_admin_mode[priority];
453}
454
455
456static void ixgbe_dcbnl_getbcncfg(struct net_device *netdev, int enum_index,
457 u32 *setting)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460
461 switch (enum_index) {
462 case DCB_BCN_ATTR_BCNA_0:
463 *setting = adapter->dcb_cfg.bcn.bcna_option[0];
464 break;
465 case DCB_BCN_ATTR_BCNA_1:
466 *setting = adapter->dcb_cfg.bcn.bcna_option[1];
467 break;
468 case DCB_BCN_ATTR_ALPHA:
469 *setting = adapter->dcb_cfg.bcn.rp_alpha;
470 break;
471 case DCB_BCN_ATTR_BETA:
472 *setting = adapter->dcb_cfg.bcn.rp_beta;
473 break;
474 case DCB_BCN_ATTR_GD:
475 *setting = adapter->dcb_cfg.bcn.rp_gd;
476 break;
477 case DCB_BCN_ATTR_GI:
478 *setting = adapter->dcb_cfg.bcn.rp_gi;
479 break;
480 case DCB_BCN_ATTR_TMAX:
481 *setting = adapter->dcb_cfg.bcn.rp_tmax;
482 break;
483 case DCB_BCN_ATTR_TD:
484 *setting = adapter->dcb_cfg.bcn.rp_td;
485 break;
486 case DCB_BCN_ATTR_RMIN:
487 *setting = adapter->dcb_cfg.bcn.rp_rmin;
488 break;
489 case DCB_BCN_ATTR_W:
490 *setting = adapter->dcb_cfg.bcn.rp_w;
491 break;
492 case DCB_BCN_ATTR_RD:
493 *setting = adapter->dcb_cfg.bcn.rp_rd;
494 break;
495 case DCB_BCN_ATTR_RU:
496 *setting = adapter->dcb_cfg.bcn.rp_ru;
497 break;
498 case DCB_BCN_ATTR_WRTT:
499 *setting = adapter->dcb_cfg.bcn.rp_wrtt;
500 break;
501 case DCB_BCN_ATTR_RI:
502 *setting = adapter->dcb_cfg.bcn.rp_ri;
503 break;
504 default:
505 *setting = -1;
506 }
507}
508
509static void ixgbe_dcbnl_setbcnrp(struct net_device *netdev, int priority,
510 u8 setting)
511{
512 struct ixgbe_adapter *adapter = netdev_priv(netdev);
513
514 adapter->temp_dcb_cfg.bcn.rp_admin_mode[priority] = setting;
515
516 if (adapter->temp_dcb_cfg.bcn.rp_admin_mode[priority] !=
517 adapter->dcb_cfg.bcn.rp_admin_mode[priority])
518 adapter->dcb_set_bitmap |= BIT_BCN;
519}
520
521static void ixgbe_dcbnl_setbcncfg(struct net_device *netdev, int enum_index,
522 u32 setting)
523{
524 struct ixgbe_adapter *adapter = netdev_priv(netdev);
525
526 switch (enum_index) {
527 case DCB_BCN_ATTR_BCNA_0:
528 adapter->temp_dcb_cfg.bcn.bcna_option[0] = setting;
529 if (adapter->temp_dcb_cfg.bcn.bcna_option[0] !=
530 adapter->dcb_cfg.bcn.bcna_option[0])
531 adapter->dcb_set_bitmap |= BIT_BCN;
532 break;
533 case DCB_BCN_ATTR_BCNA_1:
534 adapter->temp_dcb_cfg.bcn.bcna_option[1] = setting;
535 if (adapter->temp_dcb_cfg.bcn.bcna_option[1] !=
536 adapter->dcb_cfg.bcn.bcna_option[1])
537 adapter->dcb_set_bitmap |= BIT_BCN;
538 break;
539 case DCB_BCN_ATTR_ALPHA:
540 adapter->temp_dcb_cfg.bcn.rp_alpha = setting;
541 if (adapter->temp_dcb_cfg.bcn.rp_alpha !=
542 adapter->dcb_cfg.bcn.rp_alpha)
543 adapter->dcb_set_bitmap |= BIT_BCN;
544 break;
545 case DCB_BCN_ATTR_BETA:
546 adapter->temp_dcb_cfg.bcn.rp_beta = setting;
547 if (adapter->temp_dcb_cfg.bcn.rp_beta !=
548 adapter->dcb_cfg.bcn.rp_beta)
549 adapter->dcb_set_bitmap |= BIT_BCN;
550 break;
551 case DCB_BCN_ATTR_GD:
552 adapter->temp_dcb_cfg.bcn.rp_gd = setting;
553 if (adapter->temp_dcb_cfg.bcn.rp_gd !=
554 adapter->dcb_cfg.bcn.rp_gd)
555 adapter->dcb_set_bitmap |= BIT_BCN;
556 break;
557 case DCB_BCN_ATTR_GI:
558 adapter->temp_dcb_cfg.bcn.rp_gi = setting;
559 if (adapter->temp_dcb_cfg.bcn.rp_gi !=
560 adapter->dcb_cfg.bcn.rp_gi)
561 adapter->dcb_set_bitmap |= BIT_BCN;
562 break;
563 case DCB_BCN_ATTR_TMAX:
564 adapter->temp_dcb_cfg.bcn.rp_tmax = setting;
565 if (adapter->temp_dcb_cfg.bcn.rp_tmax !=
566 adapter->dcb_cfg.bcn.rp_tmax)
567 adapter->dcb_set_bitmap |= BIT_BCN;
568 break;
569 case DCB_BCN_ATTR_TD:
570 adapter->temp_dcb_cfg.bcn.rp_td = setting;
571 if (adapter->temp_dcb_cfg.bcn.rp_td !=
572 adapter->dcb_cfg.bcn.rp_td)
573 adapter->dcb_set_bitmap |= BIT_BCN;
574 break;
575 case DCB_BCN_ATTR_RMIN:
576 adapter->temp_dcb_cfg.bcn.rp_rmin = setting;
577 if (adapter->temp_dcb_cfg.bcn.rp_rmin !=
578 adapter->dcb_cfg.bcn.rp_rmin)
579 adapter->dcb_set_bitmap |= BIT_BCN;
580 break;
581 case DCB_BCN_ATTR_W:
582 adapter->temp_dcb_cfg.bcn.rp_w = setting;
583 if (adapter->temp_dcb_cfg.bcn.rp_w !=
584 adapter->dcb_cfg.bcn.rp_w)
585 adapter->dcb_set_bitmap |= BIT_BCN;
586 break;
587 case DCB_BCN_ATTR_RD:
588 adapter->temp_dcb_cfg.bcn.rp_rd = setting;
589 if (adapter->temp_dcb_cfg.bcn.rp_rd !=
590 adapter->dcb_cfg.bcn.rp_rd)
591 adapter->dcb_set_bitmap |= BIT_BCN;
592 break;
593 case DCB_BCN_ATTR_RU:
594 adapter->temp_dcb_cfg.bcn.rp_ru = setting;
595 if (adapter->temp_dcb_cfg.bcn.rp_ru !=
596 adapter->dcb_cfg.bcn.rp_ru)
597 adapter->dcb_set_bitmap |= BIT_BCN;
598 break;
599 case DCB_BCN_ATTR_WRTT:
600 adapter->temp_dcb_cfg.bcn.rp_wrtt = setting;
601 if (adapter->temp_dcb_cfg.bcn.rp_wrtt !=
602 adapter->dcb_cfg.bcn.rp_wrtt)
603 adapter->dcb_set_bitmap |= BIT_BCN;
604 break;
605 case DCB_BCN_ATTR_RI:
606 adapter->temp_dcb_cfg.bcn.rp_ri = setting;
607 if (adapter->temp_dcb_cfg.bcn.rp_ri !=
608 adapter->dcb_cfg.bcn.rp_ri)
609 adapter->dcb_set_bitmap |= BIT_BCN;
610 break;
611 default:
612 break;
613 }
614}
615
616struct dcbnl_rtnl_ops dcbnl_ops = { 429struct dcbnl_rtnl_ops dcbnl_ops = {
617 .getstate = ixgbe_dcbnl_get_state, 430 .getstate = ixgbe_dcbnl_get_state,
618 .setstate = ixgbe_dcbnl_set_state, 431 .setstate = ixgbe_dcbnl_set_state,
@@ -633,9 +446,5 @@ struct dcbnl_rtnl_ops dcbnl_ops = {
633 .setnumtcs = ixgbe_dcbnl_setnumtcs, 446 .setnumtcs = ixgbe_dcbnl_setnumtcs,
634 .getpfcstate = ixgbe_dcbnl_getpfcstate, 447 .getpfcstate = ixgbe_dcbnl_getpfcstate,
635 .setpfcstate = ixgbe_dcbnl_setpfcstate, 448 .setpfcstate = ixgbe_dcbnl_setpfcstate,
636 .getbcncfg = ixgbe_dcbnl_getbcncfg,
637 .getbcnrp = ixgbe_dcbnl_getbcnrp,
638 .setbcncfg = ixgbe_dcbnl_setbcncfg,
639 .setbcnrp = ixgbe_dcbnl_setbcnrp
640}; 449};
641 450
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 03:25:57 -0500