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-rw-r--r--arch/arm/boot/compressed/head.S6
-rw-r--r--arch/arm/common/locomo.c1
-rw-r--r--arch/arm/configs/h5000_defconfig996
-rw-r--r--arch/arm/mach-pxa/Kconfig14
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/clock.c1
-rw-r--r--arch/arm/mach-pxa/cm-x300.c5
-rw-r--r--arch/arm/mach-pxa/corgi.c32
-rw-r--r--arch/arm/mach-pxa/cpufreq-pxa2xx.c57
-rw-r--r--arch/arm/mach-pxa/devices.c95
-rw-r--r--arch/arm/mach-pxa/devices.h1
-rw-r--r--arch/arm/mach-pxa/ezx.c4
-rw-r--r--arch/arm/mach-pxa/gpio.c59
-rw-r--r--arch/arm/mach-pxa/h5000.c200
-rw-r--r--arch/arm/mach-pxa/include/mach/h5000.h113
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h48
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h31
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/mioa701.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h507
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h12
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ac97.h99
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-uart.h143
-rw-r--r--arch/arm/mach-pxa/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-pxa/littleton.c2
-rw-r--r--arch/arm/mach-pxa/magician.c4
-rw-r--r--arch/arm/mach-pxa/mainstone.c4
-rw-r--r--arch/arm/mach-pxa/mfp-pxa2xx.c62
-rw-r--r--arch/arm/mach-pxa/mioa701.c203
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c4
-rw-r--r--arch/arm/mach-pxa/poodle.c32
-rw-r--r--arch/arm/mach-pxa/pxa25x.c18
-rw-r--r--arch/arm/mach-pxa/pxa27x.c26
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c24
-rw-r--r--arch/arm/mach-pxa/spitz.c36
-rw-r--r--arch/arm/mach-pxa/tosa.c74
-rw-r--r--arch/arm/mach-pxa/zylonite.c2
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa320.c2
-rw-r--r--arch/arm/mm/proc-xsc3.S25
-rw-r--r--drivers/input/touchscreen/mainstone-wm97xx.c2
-rw-r--r--drivers/media/video/pxa_camera.c2
-rw-r--r--drivers/media/video/pxa_camera.h95
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c2
-rw-r--r--drivers/net/irda/pxaficp_ir.c43
-rw-r--r--drivers/net/smc911x.h3
-rw-r--r--drivers/serial/pxa.c1
-rw-r--r--drivers/video/pxafb.c18
-rw-r--r--drivers/video/pxafb.h3
-rw-r--r--sound/arm/pxa2xx-ac97-lib.c2
-rw-r--r--sound/arm/pxa2xx-ac97.c1
-rw-r--r--sound/arm/pxa2xx-pcm.h2
-rw-r--r--sound/soc/pxa/pxa2xx-ac97.c1
53 files changed, 2361 insertions, 779 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 7b1f31295a0a..77d614232d81 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -624,6 +624,12 @@ proc_types:
624 b __armv4_mmu_cache_off 624 b __armv4_mmu_cache_off
625 b __armv4_mmu_cache_flush 625 b __armv4_mmu_cache_flush
626 626
627 .word 0x56056930
628 .word 0xff0ffff0 @ PXA935
629 b __armv4_mmu_cache_on
630 b __armv4_mmu_cache_off
631 b __armv4_mmu_cache_flush
632
627 .word 0x56050000 @ Feroceon 633 .word 0x56050000 @ Feroceon
628 .word 0xff0f0000 634 .word 0xff0f0000
629 b __armv4_mmu_cache_on 635 b __armv4_mmu_cache_on
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 7c6b4b99a2df..2293f0ce061e 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -1108,6 +1108,7 @@ void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf)
1108 locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); 1108 locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
1109 spin_unlock_irqrestore(&lchip->lock, flags); 1109 spin_unlock_irqrestore(&lchip->lock, flags);
1110} 1110}
1111EXPORT_SYMBOL(locomo_frontlight_set);
1111 1112
1112/* 1113/*
1113 * LoCoMo "Register Access Bus." 1114 * LoCoMo "Register Access Bus."
diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
new file mode 100644
index 000000000000..649baa370495
--- /dev/null
+++ b/arch/arm/configs/h5000_defconfig
@@ -0,0 +1,996 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc6
4# Tue Sep 16 16:13:48 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_ARCH_MTD_XIP=y
28CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
29CONFIG_VECTORS_BASE=0xffff0000
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_INIT_ENV_ARG_LIMIT=32
38CONFIG_LOCALVERSION=""
39CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_POSIX_MQUEUE is not set
44# CONFIG_BSD_PROCESS_ACCT is not set
45# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set
47CONFIG_IKCONFIG=y
48CONFIG_IKCONFIG_PROC=y
49CONFIG_LOG_BUF_SHIFT=16
50# CONFIG_CGROUPS is not set
51CONFIG_GROUP_SCHED=y
52CONFIG_FAIR_GROUP_SCHED=y
53# CONFIG_RT_GROUP_SCHED is not set
54CONFIG_USER_SCHED=y
55# CONFIG_CGROUP_SCHED is not set
56# CONFIG_SYSFS_DEPRECATED_V2 is not set
57# CONFIG_RELAY is not set
58# CONFIG_NAMESPACES is not set
59# CONFIG_BLK_DEV_INITRD is not set
60# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
61CONFIG_SYSCTL=y
62CONFIG_EMBEDDED=y
63# CONFIG_UID16 is not set
64CONFIG_SYSCTL_SYSCALL=y
65CONFIG_KALLSYMS=y
66# CONFIG_KALLSYMS_ALL is not set
67# CONFIG_KALLSYMS_EXTRA_PASS is not set
68CONFIG_HOTPLUG=y
69CONFIG_PRINTK=y
70CONFIG_BUG=y
71CONFIG_ELF_CORE=y
72CONFIG_COMPAT_BRK=y
73CONFIG_BASE_FULL=y
74CONFIG_FUTEX=y
75CONFIG_ANON_INODES=y
76CONFIG_EPOLL=y
77CONFIG_SIGNALFD=y
78CONFIG_TIMERFD=y
79CONFIG_EVENTFD=y
80CONFIG_SHMEM=y
81CONFIG_VM_EVENT_COUNTERS=y
82CONFIG_SLAB=y
83# CONFIG_SLUB is not set
84# CONFIG_SLOB is not set
85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
87CONFIG_HAVE_OPROFILE=y
88# CONFIG_KPROBES is not set
89# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
90# CONFIG_HAVE_IOREMAP_PROT is not set
91CONFIG_HAVE_KPROBES=y
92CONFIG_HAVE_KRETPROBES=y
93# CONFIG_HAVE_ARCH_TRACEHOOK is not set
94# CONFIG_HAVE_DMA_ATTRS is not set
95# CONFIG_USE_GENERIC_SMP_HELPERS is not set
96CONFIG_HAVE_CLK=y
97# CONFIG_PROC_PAGE_MONITOR is not set
98CONFIG_HAVE_GENERIC_DMA_COHERENT=y
99CONFIG_SLABINFO=y
100CONFIG_RT_MUTEXES=y
101# CONFIG_TINY_SHMEM is not set
102CONFIG_BASE_SMALL=0
103CONFIG_MODULES=y
104# CONFIG_MODULE_FORCE_LOAD is not set
105CONFIG_MODULE_UNLOAD=y
106CONFIG_MODULE_FORCE_UNLOAD=y
107# CONFIG_MODVERSIONS is not set
108# CONFIG_MODULE_SRCVERSION_ALL is not set
109CONFIG_KMOD=y
110CONFIG_BLOCK=y
111# CONFIG_LBD is not set
112# CONFIG_BLK_DEV_IO_TRACE is not set
113# CONFIG_LSF is not set
114# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set
116
117#
118# IO Schedulers
119#
120CONFIG_IOSCHED_NOOP=y
121CONFIG_IOSCHED_AS=y
122CONFIG_IOSCHED_DEADLINE=y
123# CONFIG_IOSCHED_CFQ is not set
124CONFIG_DEFAULT_AS=y
125# CONFIG_DEFAULT_DEADLINE is not set
126# CONFIG_DEFAULT_CFQ is not set
127# CONFIG_DEFAULT_NOOP is not set
128CONFIG_DEFAULT_IOSCHED="anticipatory"
129CONFIG_CLASSIC_RCU=y
130
131#
132# System Type
133#
134# CONFIG_ARCH_AAEC2000 is not set
135# CONFIG_ARCH_INTEGRATOR is not set
136# CONFIG_ARCH_REALVIEW is not set
137# CONFIG_ARCH_VERSATILE is not set
138# CONFIG_ARCH_AT91 is not set
139# CONFIG_ARCH_CLPS7500 is not set
140# CONFIG_ARCH_CLPS711X is not set
141# CONFIG_ARCH_EBSA110 is not set
142# CONFIG_ARCH_EP93XX is not set
143# CONFIG_ARCH_FOOTBRIDGE is not set
144# CONFIG_ARCH_NETX is not set
145# CONFIG_ARCH_H720X is not set
146# CONFIG_ARCH_IMX is not set
147# CONFIG_ARCH_IOP13XX is not set
148# CONFIG_ARCH_IOP32X is not set
149# CONFIG_ARCH_IOP33X is not set
150# CONFIG_ARCH_IXP23XX is not set
151# CONFIG_ARCH_IXP2000 is not set
152# CONFIG_ARCH_IXP4XX is not set
153# CONFIG_ARCH_L7200 is not set
154# CONFIG_ARCH_KIRKWOOD is not set
155# CONFIG_ARCH_KS8695 is not set
156# CONFIG_ARCH_NS9XXX is not set
157# CONFIG_ARCH_LOKI is not set
158# CONFIG_ARCH_MV78XX0 is not set
159# CONFIG_ARCH_MXC is not set
160# CONFIG_ARCH_ORION5X is not set
161# CONFIG_ARCH_PNX4008 is not set
162CONFIG_ARCH_PXA=y
163# CONFIG_ARCH_RPC is not set
164# CONFIG_ARCH_SA1100 is not set
165# CONFIG_ARCH_S3C2410 is not set
166# CONFIG_ARCH_SHARK is not set
167# CONFIG_ARCH_LH7A40X is not set
168# CONFIG_ARCH_DAVINCI is not set
169# CONFIG_ARCH_OMAP is not set
170# CONFIG_ARCH_MSM7X00A is not set
171
172#
173# Intel PXA2xx/PXA3xx Implementations
174#
175# CONFIG_ARCH_GUMSTIX is not set
176# CONFIG_ARCH_LUBBOCK is not set
177# CONFIG_MACH_LOGICPD_PXA270 is not set
178# CONFIG_MACH_MAINSTONE is not set
179# CONFIG_ARCH_PXA_IDP is not set
180# CONFIG_PXA_SHARPSL is not set
181# CONFIG_ARCH_PXA_ESERIES is not set
182CONFIG_MACH_H5000=y
183# CONFIG_MACH_TRIZEPS4 is not set
184# CONFIG_MACH_EM_X270 is not set
185# CONFIG_MACH_COLIBRI is not set
186# CONFIG_MACH_ZYLONITE is not set
187# CONFIG_MACH_LITTLETON is not set
188# CONFIG_MACH_TAVOREVB is not set
189# CONFIG_MACH_SAAR is not set
190# CONFIG_MACH_ARMCORE is not set
191# CONFIG_MACH_MAGICIAN is not set
192# CONFIG_MACH_PCM027 is not set
193# CONFIG_ARCH_PXA_PALM is not set
194# CONFIG_PXA_EZX is not set
195CONFIG_PXA25x=y
196# CONFIG_PXA_PWM is not set
197
198#
199# Boot options
200#
201
202#
203# Power management
204#
205
206#
207# Processor Type
208#
209CONFIG_CPU_32=y
210CONFIG_CPU_XSCALE=y
211CONFIG_CPU_32v5=y
212CONFIG_CPU_ABRT_EV5T=y
213CONFIG_CPU_PABRT_NOIFAR=y
214CONFIG_CPU_CACHE_VIVT=y
215CONFIG_CPU_TLB_V4WBI=y
216CONFIG_CPU_CP15=y
217CONFIG_CPU_CP15_MMU=y
218
219#
220# Processor Features
221#
222CONFIG_ARM_THUMB=y
223# CONFIG_CPU_DCACHE_DISABLE is not set
224# CONFIG_OUTER_CACHE is not set
225# CONFIG_IWMMXT is not set
226CONFIG_XSCALE_PMU=y
227
228#
229# Bus support
230#
231# CONFIG_PCI_SYSCALL is not set
232# CONFIG_ARCH_SUPPORTS_MSI is not set
233# CONFIG_PCCARD is not set
234
235#
236# Kernel Features
237#
238CONFIG_TICK_ONESHOT=y
239# CONFIG_NO_HZ is not set
240# CONFIG_HIGH_RES_TIMERS is not set
241CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
242# CONFIG_PREEMPT is not set
243CONFIG_HZ=100
244CONFIG_AEABI=y
245CONFIG_OABI_COMPAT=y
246CONFIG_ARCH_FLATMEM_HAS_HOLES=y
247# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
248CONFIG_SELECT_MEMORY_MODEL=y
249CONFIG_FLATMEM_MANUAL=y
250# CONFIG_DISCONTIGMEM_MANUAL is not set
251# CONFIG_SPARSEMEM_MANUAL is not set
252CONFIG_FLATMEM=y
253CONFIG_FLAT_NODE_MEM_MAP=y
254# CONFIG_SPARSEMEM_STATIC is not set
255# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
256CONFIG_PAGEFLAGS_EXTENDED=y
257CONFIG_SPLIT_PTLOCK_CPUS=4096
258# CONFIG_RESOURCES_64BIT is not set
259CONFIG_ZONE_DMA_FLAG=1
260CONFIG_BOUNCE=y
261CONFIG_VIRT_TO_BUS=y
262CONFIG_ALIGNMENT_TRAP=y
263
264#
265# Boot options
266#
267CONFIG_ZBOOT_ROM_TEXT=0x0
268CONFIG_ZBOOT_ROM_BSS=0x0
269CONFIG_CMDLINE="keepinitrd"
270# CONFIG_XIP_KERNEL is not set
271CONFIG_KEXEC=y
272CONFIG_ATAGS_PROC=y
273
274#
275# CPU Frequency scaling
276#
277# CONFIG_CPU_FREQ is not set
278
279#
280# Floating point emulation
281#
282
283#
284# At least one emulation must be selected
285#
286CONFIG_FPE_NWFPE=y
287# CONFIG_FPE_NWFPE_XP is not set
288# CONFIG_FPE_FASTFPE is not set
289
290#
291# Userspace binary formats
292#
293CONFIG_BINFMT_ELF=y
294# CONFIG_BINFMT_AOUT is not set
295# CONFIG_BINFMT_MISC is not set
296
297#
298# Power management options
299#
300CONFIG_PM=y
301# CONFIG_PM_DEBUG is not set
302CONFIG_PM_SLEEP=y
303CONFIG_SUSPEND=y
304CONFIG_SUSPEND_FREEZER=y
305CONFIG_APM_EMULATION=y
306CONFIG_ARCH_SUSPEND_POSSIBLE=y
307CONFIG_NET=y
308
309#
310# Networking options
311#
312CONFIG_PACKET=y
313CONFIG_PACKET_MMAP=y
314CONFIG_UNIX=y
315# CONFIG_NET_KEY is not set
316CONFIG_INET=y
317CONFIG_IP_MULTICAST=y
318# CONFIG_IP_ADVANCED_ROUTER is not set
319CONFIG_IP_FIB_HASH=y
320CONFIG_IP_PNP=y
321# CONFIG_IP_PNP_DHCP is not set
322# CONFIG_IP_PNP_BOOTP is not set
323# CONFIG_IP_PNP_RARP is not set
324# CONFIG_NET_IPIP is not set
325# CONFIG_NET_IPGRE is not set
326# CONFIG_IP_MROUTE is not set
327# CONFIG_ARPD is not set
328# CONFIG_SYN_COOKIES is not set
329# CONFIG_INET_AH is not set
330# CONFIG_INET_ESP is not set
331# CONFIG_INET_IPCOMP is not set
332# CONFIG_INET_XFRM_TUNNEL is not set
333# CONFIG_INET_TUNNEL is not set
334# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
335# CONFIG_INET_XFRM_MODE_TUNNEL is not set
336# CONFIG_INET_XFRM_MODE_BEET is not set
337# CONFIG_INET_LRO is not set
338# CONFIG_INET_DIAG is not set
339# CONFIG_TCP_CONG_ADVANCED is not set
340CONFIG_TCP_CONG_CUBIC=y
341CONFIG_DEFAULT_TCP_CONG="cubic"
342# CONFIG_TCP_MD5SIG is not set
343# CONFIG_IPV6 is not set
344# CONFIG_NETWORK_SECMARK is not set
345# CONFIG_NETFILTER is not set
346# CONFIG_IP_DCCP is not set
347# CONFIG_IP_SCTP is not set
348# CONFIG_TIPC is not set
349# CONFIG_ATM is not set
350# CONFIG_BRIDGE is not set
351# CONFIG_VLAN_8021Q is not set
352# CONFIG_DECNET is not set
353# CONFIG_LLC2 is not set
354# CONFIG_IPX is not set
355# CONFIG_ATALK is not set
356# CONFIG_X25 is not set
357# CONFIG_LAPB is not set
358# CONFIG_ECONET is not set
359# CONFIG_WAN_ROUTER is not set
360# CONFIG_NET_SCHED is not set
361
362#
363# Network testing
364#
365# CONFIG_NET_PKTGEN is not set
366# CONFIG_HAMRADIO is not set
367# CONFIG_CAN is not set
368# CONFIG_IRDA is not set
369# CONFIG_BT is not set
370# CONFIG_AF_RXRPC is not set
371
372#
373# Wireless
374#
375# CONFIG_CFG80211 is not set
376# CONFIG_WIRELESS_EXT is not set
377# CONFIG_MAC80211 is not set
378# CONFIG_IEEE80211 is not set
379# CONFIG_RFKILL is not set
380# CONFIG_NET_9P is not set
381
382#
383# Device Drivers
384#
385
386#
387# Generic Driver Options
388#
389CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
390CONFIG_STANDALONE=y
391CONFIG_PREVENT_FIRMWARE_BUILD=y
392CONFIG_FW_LOADER=y
393CONFIG_FIRMWARE_IN_KERNEL=y
394CONFIG_EXTRA_FIRMWARE=""
395# CONFIG_DEBUG_DRIVER is not set
396# CONFIG_DEBUG_DEVRES is not set
397# CONFIG_SYS_HYPERVISOR is not set
398# CONFIG_CONNECTOR is not set
399CONFIG_MTD=y
400# CONFIG_MTD_DEBUG is not set
401# CONFIG_MTD_CONCAT is not set
402CONFIG_MTD_PARTITIONS=y
403# CONFIG_MTD_REDBOOT_PARTS is not set
404# CONFIG_MTD_CMDLINE_PARTS is not set
405# CONFIG_MTD_AFS_PARTS is not set
406# CONFIG_MTD_AR7_PARTS is not set
407
408#
409# User Modules And Translation Layers
410#
411# CONFIG_MTD_CHAR is not set
412CONFIG_MTD_BLKDEVS=y
413CONFIG_MTD_BLOCK=y
414# CONFIG_FTL is not set
415# CONFIG_NFTL is not set
416# CONFIG_INFTL is not set
417# CONFIG_RFD_FTL is not set
418# CONFIG_SSFDC is not set
419# CONFIG_MTD_OOPS is not set
420
421#
422# RAM/ROM/Flash chip drivers
423#
424CONFIG_MTD_CFI=y
425# CONFIG_MTD_JEDECPROBE is not set
426CONFIG_MTD_GEN_PROBE=y
427CONFIG_MTD_CFI_ADV_OPTIONS=y
428CONFIG_MTD_CFI_NOSWAP=y
429# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
430# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
431CONFIG_MTD_CFI_GEOMETRY=y
432CONFIG_MTD_MAP_BANK_WIDTH_1=y
433CONFIG_MTD_MAP_BANK_WIDTH_2=y
434CONFIG_MTD_MAP_BANK_WIDTH_4=y
435# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
436# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
437# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
438CONFIG_MTD_CFI_I1=y
439CONFIG_MTD_CFI_I2=y
440# CONFIG_MTD_CFI_I4 is not set
441# CONFIG_MTD_CFI_I8 is not set
442# CONFIG_MTD_OTP is not set
443CONFIG_MTD_CFI_INTELEXT=y
444# CONFIG_MTD_CFI_AMDSTD is not set
445# CONFIG_MTD_CFI_STAA is not set
446CONFIG_MTD_CFI_UTIL=y
447# CONFIG_MTD_RAM is not set
448# CONFIG_MTD_ROM is not set
449# CONFIG_MTD_ABSENT is not set
450# CONFIG_MTD_XIP is not set
451
452#
453# Mapping drivers for chip access
454#
455# CONFIG_MTD_COMPLEX_MAPPINGS is not set
456CONFIG_MTD_PHYSMAP=y
457CONFIG_MTD_PHYSMAP_START=0x8000000
458CONFIG_MTD_PHYSMAP_LEN=0x0
459CONFIG_MTD_PHYSMAP_BANKWIDTH=2
460# CONFIG_MTD_PXA2XX is not set
461# CONFIG_MTD_ARM_INTEGRATOR is not set
462# CONFIG_MTD_SHARP_SL is not set
463# CONFIG_MTD_PLATRAM is not set
464
465#
466# Self-contained MTD device drivers
467#
468# CONFIG_MTD_SLRAM is not set
469# CONFIG_MTD_PHRAM is not set
470# CONFIG_MTD_MTDRAM is not set
471# CONFIG_MTD_BLOCK2MTD is not set
472
473#
474# Disk-On-Chip Device Drivers
475#
476# CONFIG_MTD_DOC2000 is not set
477# CONFIG_MTD_DOC2001 is not set
478# CONFIG_MTD_DOC2001PLUS is not set
479# CONFIG_MTD_NAND is not set
480# CONFIG_MTD_ONENAND is not set
481
482#
483# UBI - Unsorted block images
484#
485# CONFIG_MTD_UBI is not set
486# CONFIG_PARPORT is not set
487CONFIG_BLK_DEV=y
488# CONFIG_BLK_DEV_COW_COMMON is not set
489# CONFIG_BLK_DEV_LOOP is not set
490# CONFIG_BLK_DEV_NBD is not set
491# CONFIG_BLK_DEV_RAM is not set
492# CONFIG_CDROM_PKTCDVD is not set
493# CONFIG_ATA_OVER_ETH is not set
494CONFIG_MISC_DEVICES=y
495# CONFIG_EEPROM_93CX6 is not set
496# CONFIG_ENCLOSURE_SERVICES is not set
497CONFIG_HAVE_IDE=y
498# CONFIG_IDE is not set
499
500#
501# SCSI device support
502#
503# CONFIG_RAID_ATTRS is not set
504# CONFIG_SCSI is not set
505# CONFIG_SCSI_DMA is not set
506# CONFIG_SCSI_NETLINK is not set
507# CONFIG_ATA is not set
508# CONFIG_MD is not set
509# CONFIG_NETDEVICES is not set
510# CONFIG_ISDN is not set
511
512#
513# Input device support
514#
515CONFIG_INPUT=y
516# CONFIG_INPUT_FF_MEMLESS is not set
517# CONFIG_INPUT_POLLDEV is not set
518
519#
520# Userland interfaces
521#
522# CONFIG_INPUT_MOUSEDEV is not set
523# CONFIG_INPUT_JOYDEV is not set
524# CONFIG_INPUT_EVDEV is not set
525# CONFIG_INPUT_EVBUG is not set
526# CONFIG_INPUT_APMPOWER is not set
527
528#
529# Input Device Drivers
530#
531# CONFIG_INPUT_KEYBOARD is not set
532# CONFIG_INPUT_MOUSE is not set
533# CONFIG_INPUT_JOYSTICK is not set
534# CONFIG_INPUT_TABLET is not set
535# CONFIG_INPUT_TOUCHSCREEN is not set
536# CONFIG_INPUT_MISC is not set
537
538#
539# Hardware I/O ports
540#
541# CONFIG_SERIO is not set
542# CONFIG_GAMEPORT is not set
543
544#
545# Character devices
546#
547CONFIG_VT=y
548CONFIG_CONSOLE_TRANSLATIONS=y
549CONFIG_VT_CONSOLE=y
550CONFIG_HW_CONSOLE=y
551# CONFIG_VT_HW_CONSOLE_BINDING is not set
552CONFIG_DEVKMEM=y
553# CONFIG_SERIAL_NONSTANDARD is not set
554
555#
556# Serial drivers
557#
558# CONFIG_SERIAL_8250 is not set
559
560#
561# Non-8250 serial port support
562#
563CONFIG_SERIAL_PXA=y
564CONFIG_SERIAL_PXA_CONSOLE=y
565CONFIG_SERIAL_CORE=y
566CONFIG_SERIAL_CORE_CONSOLE=y
567CONFIG_UNIX98_PTYS=y
568CONFIG_LEGACY_PTYS=y
569CONFIG_LEGACY_PTY_COUNT=32
570# CONFIG_IPMI_HANDLER is not set
571# CONFIG_HW_RANDOM is not set
572# CONFIG_NVRAM is not set
573# CONFIG_R3964 is not set
574# CONFIG_RAW_DRIVER is not set
575# CONFIG_TCG_TPM is not set
576# CONFIG_I2C is not set
577# CONFIG_SPI is not set
578CONFIG_ARCH_REQUIRE_GPIOLIB=y
579CONFIG_GPIOLIB=y
580# CONFIG_DEBUG_GPIO is not set
581# CONFIG_GPIO_SYSFS is not set
582
583#
584# I2C GPIO expanders:
585#
586
587#
588# PCI GPIO expanders:
589#
590
591#
592# SPI GPIO expanders:
593#
594# CONFIG_W1 is not set
595# CONFIG_POWER_SUPPLY is not set
596# CONFIG_HWMON is not set
597# CONFIG_WATCHDOG is not set
598
599#
600# Sonics Silicon Backplane
601#
602CONFIG_SSB_POSSIBLE=y
603# CONFIG_SSB is not set
604
605#
606# Multifunction device drivers
607#
608# CONFIG_MFD_CORE is not set
609# CONFIG_MFD_SM501 is not set
610# CONFIG_HTC_EGPIO is not set
611# CONFIG_HTC_PASIC3 is not set
612# CONFIG_MFD_TMIO is not set
613# CONFIG_MFD_T7L66XB is not set
614# CONFIG_MFD_TC6387XB is not set
615# CONFIG_MFD_TC6393XB is not set
616
617#
618# Multimedia devices
619#
620
621#
622# Multimedia core support
623#
624# CONFIG_VIDEO_DEV is not set
625# CONFIG_DVB_CORE is not set
626# CONFIG_VIDEO_MEDIA is not set
627
628#
629# Multimedia drivers
630#
631# CONFIG_DAB is not set
632
633#
634# Graphics support
635#
636# CONFIG_VGASTATE is not set
637# CONFIG_VIDEO_OUTPUT_CONTROL is not set
638# CONFIG_FB is not set
639# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
640
641#
642# Display device support
643#
644# CONFIG_DISPLAY_SUPPORT is not set
645
646#
647# Console display driver support
648#
649# CONFIG_VGA_CONSOLE is not set
650CONFIG_DUMMY_CONSOLE=y
651# CONFIG_SOUND is not set
652# CONFIG_HID_SUPPORT is not set
653CONFIG_USB_SUPPORT=y
654CONFIG_USB_ARCH_HAS_HCD=y
655# CONFIG_USB_ARCH_HAS_OHCI is not set
656# CONFIG_USB_ARCH_HAS_EHCI is not set
657# CONFIG_USB is not set
658# CONFIG_USB_OTG_WHITELIST is not set
659# CONFIG_USB_OTG_BLACKLIST_HUB is not set
660# CONFIG_USB_MUSB_HDRC is not set
661# CONFIG_USB_GADGET_MUSB_HDRC is not set
662
663#
664# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
665#
666CONFIG_USB_GADGET=y
667# CONFIG_USB_GADGET_DEBUG is not set
668# CONFIG_USB_GADGET_DEBUG_FILES is not set
669CONFIG_USB_GADGET_SELECTED=y
670# CONFIG_USB_GADGET_AMD5536UDC is not set
671# CONFIG_USB_GADGET_ATMEL_USBA is not set
672# CONFIG_USB_GADGET_FSL_USB2 is not set
673# CONFIG_USB_GADGET_NET2280 is not set
674CONFIG_USB_GADGET_PXA25X=y
675CONFIG_USB_PXA25X=y
676CONFIG_USB_PXA25X_SMALL=y
677# CONFIG_USB_GADGET_M66592 is not set
678# CONFIG_USB_GADGET_PXA27X is not set
679# CONFIG_USB_GADGET_GOKU is not set
680# CONFIG_USB_GADGET_LH7A40X is not set
681# CONFIG_USB_GADGET_OMAP is not set
682# CONFIG_USB_GADGET_S3C2410 is not set
683# CONFIG_USB_GADGET_AT91 is not set
684# CONFIG_USB_GADGET_DUMMY_HCD is not set
685# CONFIG_USB_GADGET_DUALSPEED is not set
686# CONFIG_USB_ZERO is not set
687CONFIG_USB_ETH=y
688# CONFIG_USB_ETH_RNDIS is not set
689# CONFIG_USB_GADGETFS is not set
690# CONFIG_USB_FILE_STORAGE is not set
691# CONFIG_USB_G_SERIAL is not set
692# CONFIG_USB_MIDI_GADGET is not set
693# CONFIG_USB_G_PRINTER is not set
694# CONFIG_USB_CDC_COMPOSITE is not set
695# CONFIG_MMC is not set
696# CONFIG_NEW_LEDS is not set
697CONFIG_RTC_LIB=y
698CONFIG_RTC_CLASS=y
699CONFIG_RTC_HCTOSYS=y
700CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
701# CONFIG_RTC_DEBUG is not set
702
703#
704# RTC interfaces
705#
706CONFIG_RTC_INTF_SYSFS=y
707CONFIG_RTC_INTF_PROC=y
708CONFIG_RTC_INTF_DEV=y
709# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
710# CONFIG_RTC_DRV_TEST is not set
711
712#
713# SPI RTC drivers
714#
715
716#
717# Platform RTC drivers
718#
719# CONFIG_RTC_DRV_CMOS is not set
720# CONFIG_RTC_DRV_DS1511 is not set
721# CONFIG_RTC_DRV_DS1553 is not set
722# CONFIG_RTC_DRV_DS1742 is not set
723# CONFIG_RTC_DRV_STK17TA8 is not set
724# CONFIG_RTC_DRV_M48T86 is not set
725# CONFIG_RTC_DRV_M48T59 is not set
726# CONFIG_RTC_DRV_V3020 is not set
727
728#
729# on-CPU RTC drivers
730#
731CONFIG_RTC_DRV_SA1100=y
732# CONFIG_DMADEVICES is not set
733
734#
735# Voltage and Current regulators
736#
737# CONFIG_REGULATOR is not set
738# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
739# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
740# CONFIG_REGULATOR_BQ24022 is not set
741# CONFIG_UIO is not set
742
743#
744# File systems
745#
746CONFIG_EXT2_FS=y
747# CONFIG_EXT2_FS_XATTR is not set
748# CONFIG_EXT2_FS_XIP is not set
749# CONFIG_EXT3_FS is not set
750# CONFIG_EXT4DEV_FS is not set
751# CONFIG_REISERFS_FS is not set
752# CONFIG_JFS_FS is not set
753# CONFIG_FS_POSIX_ACL is not set
754# CONFIG_XFS_FS is not set
755# CONFIG_OCFS2_FS is not set
756CONFIG_DNOTIFY=y
757CONFIG_INOTIFY=y
758CONFIG_INOTIFY_USER=y
759# CONFIG_QUOTA is not set
760# CONFIG_AUTOFS_FS is not set
761# CONFIG_AUTOFS4_FS is not set
762# CONFIG_FUSE_FS is not set
763
764#
765# CD-ROM/DVD Filesystems
766#
767# CONFIG_ISO9660_FS is not set
768# CONFIG_UDF_FS is not set
769
770#
771# DOS/FAT/NT Filesystems
772#
773# CONFIG_MSDOS_FS is not set
774# CONFIG_VFAT_FS is not set
775# CONFIG_NTFS_FS is not set
776
777#
778# Pseudo filesystems
779#
780CONFIG_PROC_FS=y
781CONFIG_PROC_SYSCTL=y
782CONFIG_SYSFS=y
783CONFIG_TMPFS=y
784# CONFIG_TMPFS_POSIX_ACL is not set
785# CONFIG_HUGETLB_PAGE is not set
786# CONFIG_CONFIGFS_FS is not set
787
788#
789# Miscellaneous filesystems
790#
791# CONFIG_ADFS_FS is not set
792# CONFIG_AFFS_FS is not set
793# CONFIG_HFS_FS is not set
794# CONFIG_HFSPLUS_FS is not set
795# CONFIG_BEFS_FS is not set
796# CONFIG_BFS_FS is not set
797# CONFIG_EFS_FS is not set
798CONFIG_JFFS2_FS=y
799CONFIG_JFFS2_FS_DEBUG=0
800CONFIG_JFFS2_FS_WRITEBUFFER=y
801# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
802# CONFIG_JFFS2_SUMMARY is not set
803# CONFIG_JFFS2_FS_XATTR is not set
804CONFIG_JFFS2_COMPRESSION_OPTIONS=y
805CONFIG_JFFS2_ZLIB=y
806# CONFIG_JFFS2_LZO is not set
807CONFIG_JFFS2_RTIME=y
808# CONFIG_JFFS2_RUBIN is not set
809# CONFIG_JFFS2_CMODE_NONE is not set
810CONFIG_JFFS2_CMODE_PRIORITY=y
811# CONFIG_JFFS2_CMODE_SIZE is not set
812# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
813# CONFIG_CRAMFS is not set
814# CONFIG_VXFS_FS is not set
815# CONFIG_MINIX_FS is not set
816# CONFIG_OMFS_FS is not set
817# CONFIG_HPFS_FS is not set
818# CONFIG_QNX4FS_FS is not set
819# CONFIG_ROMFS_FS is not set
820# CONFIG_SYSV_FS is not set
821# CONFIG_UFS_FS is not set
822# CONFIG_NETWORK_FILESYSTEMS is not set
823
824#
825# Partition Types
826#
827# CONFIG_PARTITION_ADVANCED is not set
828CONFIG_MSDOS_PARTITION=y
829# CONFIG_NLS is not set
830# CONFIG_DLM is not set
831
832#
833# Kernel hacking
834#
835CONFIG_PRINTK_TIME=y
836CONFIG_ENABLE_WARN_DEPRECATED=y
837CONFIG_ENABLE_MUST_CHECK=y
838CONFIG_FRAME_WARN=1024
839# CONFIG_MAGIC_SYSRQ is not set
840# CONFIG_UNUSED_SYMBOLS is not set
841# CONFIG_DEBUG_FS is not set
842# CONFIG_HEADERS_CHECK is not set
843CONFIG_DEBUG_KERNEL=y
844# CONFIG_DEBUG_SHIRQ is not set
845CONFIG_DETECT_SOFTLOCKUP=y
846# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
847CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
848# CONFIG_SCHED_DEBUG is not set
849# CONFIG_SCHEDSTATS is not set
850# CONFIG_TIMER_STATS is not set
851# CONFIG_DEBUG_OBJECTS is not set
852# CONFIG_DEBUG_SLAB is not set
853# CONFIG_DEBUG_RT_MUTEXES is not set
854# CONFIG_RT_MUTEX_TESTER is not set
855# CONFIG_DEBUG_SPINLOCK is not set
856# CONFIG_DEBUG_MUTEXES is not set
857# CONFIG_DEBUG_LOCK_ALLOC is not set
858# CONFIG_PROVE_LOCKING is not set
859# CONFIG_LOCK_STAT is not set
860# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
861# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
862# CONFIG_DEBUG_KOBJECT is not set
863# CONFIG_DEBUG_BUGVERBOSE is not set
864# CONFIG_DEBUG_INFO is not set
865# CONFIG_DEBUG_VM is not set
866# CONFIG_DEBUG_WRITECOUNT is not set
867# CONFIG_DEBUG_MEMORY_INIT is not set
868# CONFIG_DEBUG_LIST is not set
869# CONFIG_DEBUG_SG is not set
870CONFIG_FRAME_POINTER=y
871# CONFIG_BOOT_PRINTK_DELAY is not set
872# CONFIG_RCU_TORTURE_TEST is not set
873# CONFIG_BACKTRACE_SELF_TEST is not set
874# CONFIG_FAULT_INJECTION is not set
875# CONFIG_LATENCYTOP is not set
876CONFIG_SYSCTL_SYSCALL_CHECK=y
877CONFIG_HAVE_FTRACE=y
878CONFIG_HAVE_DYNAMIC_FTRACE=y
879# CONFIG_FTRACE is not set
880# CONFIG_IRQSOFF_TRACER is not set
881# CONFIG_SCHED_TRACER is not set
882# CONFIG_CONTEXT_SWITCH_TRACER is not set
883# CONFIG_SAMPLES is not set
884CONFIG_HAVE_ARCH_KGDB=y
885# CONFIG_KGDB is not set
886# CONFIG_DEBUG_USER is not set
887# CONFIG_DEBUG_ERRORS is not set
888# CONFIG_DEBUG_STACK_USAGE is not set
889# CONFIG_DEBUG_LL is not set
890
891#
892# Security options
893#
894# CONFIG_KEYS is not set
895# CONFIG_SECURITY is not set
896# CONFIG_SECURITY_FILE_CAPABILITIES is not set
897CONFIG_CRYPTO=y
898
899#
900# Crypto core or helper
901#
902CONFIG_CRYPTO_ALGAPI=y
903CONFIG_CRYPTO_HASH=y
904CONFIG_CRYPTO_MANAGER=y
905# CONFIG_CRYPTO_GF128MUL is not set
906# CONFIG_CRYPTO_NULL is not set
907# CONFIG_CRYPTO_CRYPTD is not set
908# CONFIG_CRYPTO_AUTHENC is not set
909# CONFIG_CRYPTO_TEST is not set
910
911#
912# Authenticated Encryption with Associated Data
913#
914# CONFIG_CRYPTO_CCM is not set
915# CONFIG_CRYPTO_GCM is not set
916# CONFIG_CRYPTO_SEQIV is not set
917
918#
919# Block modes
920#
921# CONFIG_CRYPTO_CBC is not set
922# CONFIG_CRYPTO_CTR is not set
923# CONFIG_CRYPTO_CTS is not set
924# CONFIG_CRYPTO_ECB is not set
925# CONFIG_CRYPTO_LRW is not set
926# CONFIG_CRYPTO_PCBC is not set
927# CONFIG_CRYPTO_XTS is not set
928
929#
930# Hash modes
931#
932CONFIG_CRYPTO_HMAC=y
933# CONFIG_CRYPTO_XCBC is not set
934
935#
936# Digest
937#
938# CONFIG_CRYPTO_CRC32C is not set
939# CONFIG_CRYPTO_MD4 is not set
940CONFIG_CRYPTO_MD5=y
941# CONFIG_CRYPTO_MICHAEL_MIC is not set
942# CONFIG_CRYPTO_RMD128 is not set
943# CONFIG_CRYPTO_RMD160 is not set
944# CONFIG_CRYPTO_RMD256 is not set
945# CONFIG_CRYPTO_RMD320 is not set
946CONFIG_CRYPTO_SHA1=y
947# CONFIG_CRYPTO_SHA256 is not set
948# CONFIG_CRYPTO_SHA512 is not set
949# CONFIG_CRYPTO_TGR192 is not set
950# CONFIG_CRYPTO_WP512 is not set
951
952#
953# Ciphers
954#
955# CONFIG_CRYPTO_AES is not set
956# CONFIG_CRYPTO_ANUBIS is not set
957# CONFIG_CRYPTO_ARC4 is not set
958# CONFIG_CRYPTO_BLOWFISH is not set
959# CONFIG_CRYPTO_CAMELLIA is not set
960# CONFIG_CRYPTO_CAST5 is not set
961# CONFIG_CRYPTO_CAST6 is not set
962CONFIG_CRYPTO_DES=y
963# CONFIG_CRYPTO_FCRYPT is not set
964# CONFIG_CRYPTO_KHAZAD is not set
965# CONFIG_CRYPTO_SALSA20 is not set
966# CONFIG_CRYPTO_SEED is not set
967# CONFIG_CRYPTO_SERPENT is not set
968# CONFIG_CRYPTO_TEA is not set
969# CONFIG_CRYPTO_TWOFISH is not set
970
971#
972# Compression
973#
974CONFIG_CRYPTO_DEFLATE=y
975# CONFIG_CRYPTO_LZO is not set
976# CONFIG_CRYPTO_HW is not set
977
978#
979# Library routines
980#
981CONFIG_BITREVERSE=y
982# CONFIG_GENERIC_FIND_FIRST_BIT is not set
983# CONFIG_GENERIC_FIND_NEXT_BIT is not set
984CONFIG_CRC_CCITT=y
985# CONFIG_CRC16 is not set
986# CONFIG_CRC_T10DIF is not set
987# CONFIG_CRC_ITU_T is not set
988CONFIG_CRC32=y
989# CONFIG_CRC7 is not set
990# CONFIG_LIBCRC32C is not set
991CONFIG_ZLIB_INFLATE=y
992CONFIG_ZLIB_DEFLATE=y
993CONFIG_PLIST=y
994CONFIG_HAS_IOMEM=y
995CONFIG_HAS_IOPORT=y
996CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 740f0a382bac..6755c7d6bb31 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -19,6 +19,9 @@ config CPU_PXA320
19config CPU_PXA930 19config CPU_PXA930
20 bool "PXA930 (codename Tavor-P)" 20 bool "PXA930 (codename Tavor-P)"
21 21
22config CPU_PXA935
23 bool "PXA935 (codename Tavor-P65)"
24
22endmenu 25endmenu
23 26
24endif 27endif
@@ -199,6 +202,10 @@ config MACH_E800
199config TRIZEPS_PXA 202config TRIZEPS_PXA
200 bool "PXA based Keith und Koep Trizeps DIMM-Modules" 203 bool "PXA based Keith und Koep Trizeps DIMM-Modules"
201 204
205config MACH_H5000
206 bool "HP iPAQ h5000"
207 select PXA25x
208
202config MACH_TRIZEPS4 209config MACH_TRIZEPS4
203 bool "Keith und Koep Trizeps4 DIMM-Module" 210 bool "Keith und Koep Trizeps4 DIMM-Module"
204 depends on TRIZEPS_PXA 211 depends on TRIZEPS_PXA
@@ -283,7 +290,6 @@ config MACH_MIOA701
283 bool "Mitac Mio A701 Support" 290 bool "Mitac Mio A701 Support"
284 select PXA27x 291 select PXA27x
285 select IWMMXT 292 select IWMMXT
286 select LEDS_GPIO
287 select HAVE_PWM 293 select HAVE_PWM
288 select GPIO_SYSFS 294 select GPIO_SYSFS
289 help 295 help
@@ -396,6 +402,12 @@ config PXA27x
396 help 402 help
397 Select code specific to PXA27x variants 403 Select code specific to PXA27x variants
398 404
405config CPU_PXA26x
406 bool
407 select PXA25x
408 help
409 Select code specific to PXA26x (codename Dalhart)
410
399config PXA3xx 411config PXA3xx
400 bool 412 bool
401 select CPU_XSC3 413 select CPU_XSC3
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index d64c68b232e3..dc184eae5109 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_MP900C) += mp900.o
35obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 35obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
36obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o 36obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
37obj-$(CONFIG_MACH_COLIBRI) += colibri.o 37obj-$(CONFIG_MACH_COLIBRI) += colibri.o
38obj-$(CONFIG_MACH_H5000) += h5000.o
38obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o 39obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
39obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o 40obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
40obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o 41obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index a3e0e1989a6b..40b774084514 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -14,7 +14,6 @@
14 14
15#include <asm/clkdev.h> 15#include <asm/clkdev.h>
16#include <mach/pxa2xx-regs.h> 16#include <mach/pxa2xx-regs.h>
17#include <mach/pxa2xx-gpio.h>
18#include <mach/hardware.h> 17#include <mach/hardware.h>
19 18
20#include "devices.h" 19#include "devices.h"
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index deb46cd144bf..ff0c577cd1ac 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -31,7 +31,6 @@
31#include <mach/mfp-pxa300.h> 31#include <mach/mfp-pxa300.h>
32 32
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/gpio.h>
35#include <mach/pxafb.h> 34#include <mach/pxafb.h>
36#include <mach/mmc.h> 35#include <mach/mmc.h>
37#include <mach/ohci.h> 36#include <mach/ohci.h>
@@ -137,6 +136,10 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
137 GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ 136 GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */
138 GPIO85_GPIO, /* MMC WP */ 137 GPIO85_GPIO, /* MMC WP */
139 GPIO99_GPIO, /* Ethernet IRQ */ 138 GPIO99_GPIO, /* Ethernet IRQ */
139
140 /* Standard I2C */
141 GPIO21_I2C_SCL,
142 GPIO22_I2C_SDA,
140}; 143};
141 144
142#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) 145#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 65558d6aa220..c5e28a46b292 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -19,6 +19,7 @@
19#include <linux/fs.h> 19#include <linux/fs.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/mmc/host.h> 21#include <linux/mmc/host.h>
22#include <linux/mtd/physmap.h>
22#include <linux/pm.h> 23#include <linux/pm.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <linux/backlight.h> 25#include <linux/backlight.h>
@@ -541,11 +542,42 @@ err_free_1:
541static inline void corgi_init_spi(void) {} 542static inline void corgi_init_spi(void) {}
542#endif 543#endif
543 544
545static struct mtd_partition sharpsl_rom_parts[] = {
546 {
547 .name ="Boot PROM Filesystem",
548 .offset = 0x00120000,
549 .size = MTDPART_SIZ_FULL,
550 },
551};
552
553static struct physmap_flash_data sharpsl_rom_data = {
554 .width = 2,
555 .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
556 .parts = sharpsl_rom_parts,
557};
558
559static struct resource sharpsl_rom_resources[] = {
560 {
561 .start = 0x00000000,
562 .end = 0x007fffff,
563 .flags = IORESOURCE_MEM,
564 },
565};
566
567static struct platform_device sharpsl_rom_device = {
568 .name = "physmap-flash",
569 .id = -1,
570 .resource = sharpsl_rom_resources,
571 .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
572 .dev.platform_data = &sharpsl_rom_data,
573};
574
544static struct platform_device *devices[] __initdata = { 575static struct platform_device *devices[] __initdata = {
545 &corgiscoop_device, 576 &corgiscoop_device,
546 &corgifb_device, 577 &corgifb_device,
547 &corgikbd_device, 578 &corgikbd_device,
548 &corgiled_device, 579 &corgiled_device,
580 &sharpsl_rom_device,
549}; 581};
550 582
551static void corgi_poweroff(void) 583static void corgi_poweroff(void)
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 1f272ea83f36..771dd4eac935 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -64,7 +64,7 @@ typedef struct {
64 64
65/* Define the refresh period in mSec for the SDRAM and the number of rows */ 65/* Define the refresh period in mSec for the SDRAM and the number of rows */
66#define SDRAM_TREF 64 /* standard 64ms SDRAM */ 66#define SDRAM_TREF 64 /* standard 64ms SDRAM */
67#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ 67static unsigned int sdram_rows;
68 68
69#define CCLKCFG_TURBO 0x1 69#define CCLKCFG_TURBO 0x1
70#define CCLKCFG_FCS 0x2 70#define CCLKCFG_FCS 0x2
@@ -73,6 +73,9 @@ typedef struct {
73#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) 73#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
74#define MDREFR_DRI_MASK 0xFFF 74#define MDREFR_DRI_MASK 0xFFF
75 75
76#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
77#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
78
76/* 79/*
77 * PXA255 definitions 80 * PXA255 definitions
78 */ 81 */
@@ -109,6 +112,10 @@ static struct cpufreq_frequency_table
109static struct cpufreq_frequency_table 112static struct cpufreq_frequency_table
110 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; 113 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
111 114
115static unsigned int pxa255_turbo_table;
116module_param(pxa255_turbo_table, uint, 0);
117MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
118
112/* 119/*
113 * PXA270 definitions 120 * PXA270 definitions
114 * 121 *
@@ -158,22 +165,16 @@ static struct cpufreq_frequency_table
158 165
159extern unsigned get_clk_frequency_khz(int info); 166extern unsigned get_clk_frequency_khz(int info);
160 167
161static void find_freq_tables(struct cpufreq_policy *policy, 168static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
162 struct cpufreq_frequency_table **freq_table,
163 pxa_freqs_t **pxa_freqs) 169 pxa_freqs_t **pxa_freqs)
164{ 170{
165 if (cpu_is_pxa25x()) { 171 if (cpu_is_pxa25x()) {
166 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 172 if (!pxa255_turbo_table) {
167 *pxa_freqs = pxa255_run_freqs; 173 *pxa_freqs = pxa255_run_freqs;
168 *freq_table = pxa255_run_freq_table; 174 *freq_table = pxa255_run_freq_table;
169 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { 175 } else {
170 *pxa_freqs = pxa255_turbo_freqs; 176 *pxa_freqs = pxa255_turbo_freqs;
171 *freq_table = pxa255_turbo_freq_table; 177 *freq_table = pxa255_turbo_freq_table;
172 } else {
173 printk("CPU PXA: Unknown policy found. "
174 "Using CPUFREQ_POLICY_PERFORMANCE\n");
175 *pxa_freqs = pxa255_run_freqs;
176 *freq_table = pxa255_run_freq_table;
177 } 178 }
178 } 179 }
179 if (cpu_is_pxa27x()) { 180 if (cpu_is_pxa27x()) {
@@ -194,14 +195,28 @@ static void pxa27x_guess_max_freq(void)
194 } 195 }
195} 196}
196 197
198static void init_sdram_rows(void)
199{
200 uint32_t mdcnfg = MDCNFG;
201 unsigned int drac2 = 0, drac0 = 0;
202
203 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
204 drac2 = MDCNFG_DRAC2(mdcnfg);
205
206 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
207 drac0 = MDCNFG_DRAC0(mdcnfg);
208
209 sdram_rows = 1 << (11 + max(drac0, drac2));
210}
211
197static u32 mdrefr_dri(unsigned int freq) 212static u32 mdrefr_dri(unsigned int freq)
198{ 213{
199 u32 dri = 0; 214 u32 dri = 0;
200 215
201 if (cpu_is_pxa25x()) 216 if (cpu_is_pxa25x())
202 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32)); 217 dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
203 if (cpu_is_pxa27x()) 218 if (cpu_is_pxa27x())
204 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32; 219 dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
205 return dri; 220 return dri;
206} 221}
207 222
@@ -212,7 +227,7 @@ static int pxa_verify_policy(struct cpufreq_policy *policy)
212 pxa_freqs_t *pxa_freqs; 227 pxa_freqs_t *pxa_freqs;
213 int ret; 228 int ret;
214 229
215 find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs); 230 find_freq_tables(&pxa_freqs_table, &pxa_freqs);
216 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); 231 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
217 232
218 if (freq_debug) 233 if (freq_debug)
@@ -240,7 +255,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
240 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; 255 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
241 256
242 /* Get the current policy */ 257 /* Get the current policy */
243 find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings); 258 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
244 259
245 /* Lookup the next frequency */ 260 /* Lookup the next frequency */
246 if (cpufreq_frequency_table_target(policy, pxa_freqs_table, 261 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
@@ -329,11 +344,15 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
329{ 344{
330 int i; 345 int i;
331 unsigned int freq; 346 unsigned int freq;
347 struct cpufreq_frequency_table *pxa255_freq_table;
348 pxa_freqs_t *pxa255_freqs;
332 349
333 /* try to guess pxa27x cpu */ 350 /* try to guess pxa27x cpu */
334 if (cpu_is_pxa27x()) 351 if (cpu_is_pxa27x())
335 pxa27x_guess_max_freq(); 352 pxa27x_guess_max_freq();
336 353
354 init_sdram_rows();
355
337 /* set default policy and cpuinfo */ 356 /* set default policy and cpuinfo */
338 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 357 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
339 policy->cur = get_clk_frequency_khz(0); /* current freq */ 358 policy->cur = get_clk_frequency_khz(0); /* current freq */
@@ -354,6 +373,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
354 } 373 }
355 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; 374 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
356 375
376 pxa255_turbo_table = !!pxa255_turbo_table;
377
357 /* Generate the pxa27x cpufreq_frequency_table struct */ 378 /* Generate the pxa27x cpufreq_frequency_table struct */
358 for (i = 0; i < NUM_PXA27x_FREQS; i++) { 379 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
359 freq = pxa27x_freqs[i].khz; 380 freq = pxa27x_freqs[i].khz;
@@ -368,8 +389,12 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
368 * Set the policy's minimum and maximum frequencies from the tables 389 * Set the policy's minimum and maximum frequencies from the tables
369 * just constructed. This sets cpuinfo.mxx_freq, min and max. 390 * just constructed. This sets cpuinfo.mxx_freq, min and max.
370 */ 391 */
371 if (cpu_is_pxa25x()) 392 if (cpu_is_pxa25x()) {
372 cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table); 393 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
394 pr_info("PXA255 cpufreq using %s frequency table\n",
395 pxa255_turbo_table ? "turbo" : "run");
396 cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
397 }
373 else if (cpu_is_pxa27x()) 398 else if (cpu_is_pxa27x())
374 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); 399 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
375 400
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 35736fc08634..e16f8e3d58d3 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,13 +4,12 @@
4#include <linux/platform_device.h> 4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h> 5#include <linux/dma-mapping.h>
6 6
7#include <mach/gpio.h> 7#include <mach/pxa-regs.h>
8#include <mach/udc.h> 8#include <mach/udc.h>
9#include <mach/pxafb.h> 9#include <mach/pxafb.h>
10#include <mach/mmc.h> 10#include <mach/mmc.h>
11#include <mach/irda.h> 11#include <mach/irda.h>
12#include <mach/i2c.h> 12#include <mach/i2c.h>
13#include <mach/mfp-pxa27x.h>
14#include <mach/ohci.h> 13#include <mach/ohci.h>
15#include <mach/pxa27x_keypad.h> 14#include <mach/pxa27x_keypad.h>
16#include <mach/pxa2xx_spi.h> 15#include <mach/pxa2xx_spi.h>
@@ -156,8 +155,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev)
156 155
157static struct resource pxa_resource_ffuart[] = { 156static struct resource pxa_resource_ffuart[] = {
158 { 157 {
159 .start = __PREG(FFUART), 158 .start = 0x40100000,
160 .end = __PREG(FFUART) + 35, 159 .end = 0x40100023,
161 .flags = IORESOURCE_MEM, 160 .flags = IORESOURCE_MEM,
162 }, { 161 }, {
163 .start = IRQ_FFUART, 162 .start = IRQ_FFUART,
@@ -175,8 +174,8 @@ struct platform_device pxa_device_ffuart= {
175 174
176static struct resource pxa_resource_btuart[] = { 175static struct resource pxa_resource_btuart[] = {
177 { 176 {
178 .start = __PREG(BTUART), 177 .start = 0x40200000,
179 .end = __PREG(BTUART) + 35, 178 .end = 0x40200023,
180 .flags = IORESOURCE_MEM, 179 .flags = IORESOURCE_MEM,
181 }, { 180 }, {
182 .start = IRQ_BTUART, 181 .start = IRQ_BTUART,
@@ -194,8 +193,8 @@ struct platform_device pxa_device_btuart = {
194 193
195static struct resource pxa_resource_stuart[] = { 194static struct resource pxa_resource_stuart[] = {
196 { 195 {
197 .start = __PREG(STUART), 196 .start = 0x40700000,
198 .end = __PREG(STUART) + 35, 197 .end = 0x40700023,
199 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
200 }, { 199 }, {
201 .start = IRQ_STUART, 200 .start = IRQ_STUART,
@@ -213,8 +212,8 @@ struct platform_device pxa_device_stuart = {
213 212
214static struct resource pxa_resource_hwuart[] = { 213static struct resource pxa_resource_hwuart[] = {
215 { 214 {
216 .start = __PREG(HWUART), 215 .start = 0x41600000,
217 .end = __PREG(HWUART) + 47, 216 .end = 0x4160002F,
218 .flags = IORESOURCE_MEM, 217 .flags = IORESOURCE_MEM,
219 }, { 218 }, {
220 .start = IRQ_HWUART, 219 .start = IRQ_HWUART,
@@ -249,18 +248,53 @@ struct platform_device pxa_device_i2c = {
249 .num_resources = ARRAY_SIZE(pxai2c_resources), 248 .num_resources = ARRAY_SIZE(pxai2c_resources),
250}; 249};
251 250
252static unsigned long pxa27x_i2c_mfp_cfg[] = {
253 GPIO117_I2C_SCL,
254 GPIO118_I2C_SDA,
255};
256
257void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) 251void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
258{ 252{
259 if (cpu_is_pxa27x())
260 pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
261 pxa_register_device(&pxa_device_i2c, info); 253 pxa_register_device(&pxa_device_i2c, info);
262} 254}
263 255
256#ifdef CONFIG_PXA27x
257static struct resource pxa27x_resources_i2c_power[] = {
258 {
259 .start = 0x40f00180,
260 .end = 0x40f001a3,
261 .flags = IORESOURCE_MEM,
262 }, {
263 .start = IRQ_PWRI2C,
264 .end = IRQ_PWRI2C,
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269struct platform_device pxa27x_device_i2c_power = {
270 .name = "pxa2xx-i2c",
271 .id = 1,
272 .resource = pxa27x_resources_i2c_power,
273 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
274};
275#endif
276
277#ifdef CONFIG_PXA3xx
278static struct resource pxa3xx_resources_i2c_power[] = {
279 {
280 .start = 0x40f500c0,
281 .end = 0x40f500d3,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = IRQ_PWRI2C,
285 .end = IRQ_PWRI2C,
286 .flags = IORESOURCE_IRQ,
287 },
288};
289
290struct platform_device pxa3xx_device_i2c_power = {
291 .name = "pxa2xx-i2c",
292 .id = 1,
293 .resource = pxa3xx_resources_i2c_power,
294 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
295};
296#endif
297
264static struct resource pxai2s_resources[] = { 298static struct resource pxai2s_resources[] = {
265 { 299 {
266 .start = 0x40400000, 300 .start = 0x40400000,
@@ -296,11 +330,36 @@ void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
296 pxa_register_device(&pxa_device_ficp, info); 330 pxa_register_device(&pxa_device_ficp, info);
297} 331}
298 332
299struct platform_device pxa_device_rtc = { 333static struct resource pxa_rtc_resources[] = {
334 [0] = {
335 .start = 0x40900000,
336 .end = 0x40900000 + 0x3b,
337 .flags = IORESOURCE_MEM,
338 },
339 [1] = {
340 .start = IRQ_RTC1Hz,
341 .end = IRQ_RTC1Hz,
342 .flags = IORESOURCE_IRQ,
343 },
344 [2] = {
345 .start = IRQ_RTCAlrm,
346 .end = IRQ_RTCAlrm,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351struct platform_device sa1100_device_rtc = {
300 .name = "sa1100-rtc", 352 .name = "sa1100-rtc",
301 .id = -1, 353 .id = -1,
302}; 354};
303 355
356struct platform_device pxa_device_rtc = {
357 .name = "pxa-rtc",
358 .id = -1,
359 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
360 .resource = pxa_rtc_resources,
361};
362
304static struct resource pxa_ac97_resources[] = { 363static struct resource pxa_ac97_resources[] = {
305 [0] = { 364 [0] = {
306 .start = 0x40500000, 365 .start = 0x40500000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index bb04af4b0aa3..ecc24a4dca6d 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -11,6 +11,7 @@ extern struct platform_device pxa_device_hwuart;
11extern struct platform_device pxa_device_i2c; 11extern struct platform_device pxa_device_i2c;
12extern struct platform_device pxa_device_i2s; 12extern struct platform_device pxa_device_i2s;
13extern struct platform_device pxa_device_ficp; 13extern struct platform_device pxa_device_ficp;
14extern struct platform_device sa1100_device_rtc;
14extern struct platform_device pxa_device_rtc; 15extern struct platform_device pxa_device_rtc;
15extern struct platform_device pxa_device_ac97; 16extern struct platform_device pxa_device_ac97;
16 17
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 83c56d3abacb..3e6aa33a2c7c 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -113,6 +113,10 @@ static unsigned long ezx_pin_config[] __initdata = {
113 GPIO91_USB_P3_1, /* ICL_XRXD */ 113 GPIO91_USB_P3_1, /* ICL_XRXD */
114 GPIO56_USB_P3_4, /* ICL_VMOUT */ 114 GPIO56_USB_P3_4, /* ICL_VMOUT */
115 GPIO113_USB_P3_3, /* /ICL_VMIN */ 115 GPIO113_USB_P3_3, /* /ICL_VMIN */
116
117 /* I2C */
118 GPIO117_I2C_SCL,
119 GPIO118_I2C_SDA,
116}; 120};
117 121
118static void __init ezx_init(void) 122static void __init ezx_init(void)
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 14930cf8be7b..5fec1e479cb3 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -25,6 +25,18 @@
25 25
26#include "generic.h" 26#include "generic.h"
27 27
28#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
29#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
30#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
31#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
32
33#define GPLR_OFFSET 0x00
34#define GPDR_OFFSET 0x0C
35#define GPSR_OFFSET 0x18
36#define GPCR_OFFSET 0x24
37#define GRER_OFFSET 0x30
38#define GFER_OFFSET 0x3C
39#define GEDR_OFFSET 0x48
28 40
29struct pxa_gpio_chip { 41struct pxa_gpio_chip {
30 struct gpio_chip chip; 42 struct gpio_chip chip;
@@ -33,6 +45,18 @@ struct pxa_gpio_chip {
33 45
34int pxa_last_gpio; 46int pxa_last_gpio;
35 47
48#ifdef CONFIG_CPU_PXA26x
49/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
50 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
51 */
52static int __gpio_is_inverted(unsigned gpio)
53{
54 return cpu_is_pxa25x() && gpio > 85;
55}
56#else
57#define __gpio_is_inverted(gpio) (0)
58#endif
59
36/* 60/*
37 * Configure pins for GPIO or other functions 61 * Configure pins for GPIO or other functions
38 */ 62 */
@@ -75,7 +99,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
75 gpdr = pxa->regbase + GPDR_OFFSET; 99 gpdr = pxa->regbase + GPDR_OFFSET;
76 local_irq_save(flags); 100 local_irq_save(flags);
77 value = __raw_readl(gpdr); 101 value = __raw_readl(gpdr);
78 value &= ~mask; 102 if (__gpio_is_inverted(chip->base + offset))
103 value |= mask;
104 else
105 value &= ~mask;
79 __raw_writel(value, gpdr); 106 __raw_writel(value, gpdr);
80 local_irq_restore(flags); 107 local_irq_restore(flags);
81 108
@@ -97,7 +124,10 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
97 gpdr = pxa->regbase + GPDR_OFFSET; 124 gpdr = pxa->regbase + GPDR_OFFSET;
98 local_irq_save(flags); 125 local_irq_save(flags);
99 tmp = __raw_readl(gpdr); 126 tmp = __raw_readl(gpdr);
100 tmp |= mask; 127 if (__gpio_is_inverted(chip->base + offset))
128 tmp &= ~mask;
129 else
130 tmp |= mask;
101 __raw_writel(tmp, gpdr); 131 __raw_writel(tmp, gpdr);
102 local_irq_restore(flags); 132 local_irq_restore(flags);
103 133
@@ -173,10 +203,17 @@ static unsigned long GPIO_IRQ_mask[4];
173 */ 203 */
174static int __gpio_is_occupied(unsigned gpio) 204static int __gpio_is_occupied(unsigned gpio)
175{ 205{
176 if (cpu_is_pxa25x() || cpu_is_pxa27x()) 206 if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
177 return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2)); 207 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
178 else 208 int dir = GPDR(gpio) & GPIO_bit(gpio);
179 return 0; 209
210 if (__gpio_is_inverted(gpio))
211 return af != 1 || dir == 0;
212 else
213 return af != 0 || dir != 0;
214 }
215
216 return 0;
180} 217}
181 218
182static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 219static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
@@ -190,9 +227,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
190 /* Don't mess with enabled GPIOs using preconfigured edges or 227 /* Don't mess with enabled GPIOs using preconfigured edges or
191 * GPIOs set to alternate function or to output during probe 228 * GPIOs set to alternate function or to output during probe
192 */ 229 */
193 if ((GPIO_IRQ_rising_edge[idx] | 230 if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
194 GPIO_IRQ_falling_edge[idx] | 231 (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
195 GPDR(gpio)) & GPIO_bit(gpio))
196 return 0; 232 return 0;
197 233
198 if (__gpio_is_occupied(gpio)) 234 if (__gpio_is_occupied(gpio))
@@ -201,7 +237,10 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
201 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 237 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
202 } 238 }
203 239
204 GPDR(gpio) &= ~GPIO_bit(gpio); 240 if (__gpio_is_inverted(gpio))
241 GPDR(gpio) |= GPIO_bit(gpio);
242 else
243 GPDR(gpio) &= ~GPIO_bit(gpio);
205 244
206 if (type & IRQ_TYPE_EDGE_RISING) 245 if (type & IRQ_TYPE_EDGE_RISING)
207 __set_bit(gpio, GPIO_IRQ_rising_edge); 246 __set_bit(gpio, GPIO_IRQ_rising_edge);
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
new file mode 100644
index 000000000000..da6e4422c0f3
--- /dev/null
+++ b/arch/arm/mach-pxa/h5000.c
@@ -0,0 +1,200 @@
1/*
2 * Hardware definitions for HP iPAQ h5xxx Handheld Computers
3 *
4 * Copyright 2000-2003 Hewlett-Packard Company.
5 * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com>
6 * Copyright 2004-2005 Phil Blundell <pb@handhelds.org>
7 * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
15 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
16 * FITNESS FOR ANY PARTICULAR PURPOSE.
17 *
18 * Author: Jamey Hicks.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/mtd/physmap.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <mach/h5000.h>
31#include <mach/pxa-regs.h>
32#include <mach/pxa2xx-regs.h>
33#include <mach/mfp-pxa25x.h>
34#include <mach/udc.h>
35#include "generic.h"
36
37/*
38 * Flash
39 */
40
41static struct mtd_partition h5000_flash0_partitions[] = {
42 {
43 .name = "bootldr",
44 .size = 0x00040000,
45 .offset = 0,
46 .mask_flags = MTD_WRITEABLE,
47 },
48 {
49 .name = "root",
50 .size = MTDPART_SIZ_FULL,
51 .offset = MTDPART_OFS_APPEND,
52 },
53};
54
55static struct mtd_partition h5000_flash1_partitions[] = {
56 {
57 .name = "second root",
58 .size = SZ_16M - 0x00040000,
59 .offset = 0,
60 },
61 {
62 .name = "asset",
63 .size = MTDPART_SIZ_FULL,
64 .offset = MTDPART_OFS_APPEND,
65 .mask_flags = MTD_WRITEABLE,
66 },
67};
68
69static struct physmap_flash_data h5000_flash0_data = {
70 .width = 4,
71 .parts = h5000_flash0_partitions,
72 .nr_parts = ARRAY_SIZE(h5000_flash0_partitions),
73};
74
75static struct physmap_flash_data h5000_flash1_data = {
76 .width = 4,
77 .parts = h5000_flash1_partitions,
78 .nr_parts = ARRAY_SIZE(h5000_flash1_partitions),
79};
80
81static struct resource h5000_flash0_resources = {
82 .start = PXA_CS0_PHYS,
83 .end = PXA_CS0_PHYS + SZ_32M - 1,
84 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
85};
86
87static struct resource h5000_flash1_resources = {
88 .start = PXA_CS0_PHYS + SZ_32M,
89 .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1,
90 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
91};
92
93static struct platform_device h5000_flash[] = {
94 {
95 .name = "physmap-flash",
96 .id = 0,
97 .resource = &h5000_flash0_resources,
98 .num_resources = 1,
99 .dev = {
100 .platform_data = &h5000_flash0_data,
101 },
102 },
103 {
104 .name = "physmap-flash",
105 .id = 1,
106 .resource = &h5000_flash1_resources,
107 .num_resources = 1,
108 .dev = {
109 .platform_data = &h5000_flash1_data,
110 },
111 },
112};
113
114/*
115 * USB Device Controller
116 */
117
118static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = {
119 .gpio_pullup = H5000_GPIO_USB_PULLUP,
120};
121
122/*
123 * GPIO setup
124 */
125
126static unsigned long h5000_pin_config[] __initdata = {
127 /* Crystal and Clock Signals */
128 GPIO12_32KHz,
129
130 /* SDRAM and Static Memory I/O Signals */
131 GPIO15_nCS_1,
132 GPIO78_nCS_2,
133 GPIO79_nCS_3,
134 GPIO80_nCS_4,
135
136 /* FFUART */
137 GPIO34_FFUART_RXD,
138 GPIO35_FFUART_CTS,
139 GPIO36_FFUART_DCD,
140 GPIO37_FFUART_DSR,
141 GPIO38_FFUART_RI,
142 GPIO39_FFUART_TXD,
143 GPIO40_FFUART_DTR,
144 GPIO41_FFUART_RTS,
145
146 /* BTUART */
147 GPIO42_BTUART_RXD,
148 GPIO43_BTUART_TXD,
149 GPIO44_BTUART_CTS,
150 GPIO45_BTUART_RTS,
151
152 /* SSP1 */
153 GPIO23_SSP1_SCLK,
154 GPIO25_SSP1_TXD,
155 GPIO26_SSP1_RXD,
156};
157
158/*
159 * Localbus setup:
160 * CS0: Flash;
161 * CS1: MediaQ chip, select 16-bit bus and vlio;
162 * CS5: SAMCOP.
163 */
164
165static void fix_msc(void)
166{
167 MSC0 = 0x129c24f2;
168 MSC1 = 0x7ff424fa;
169 MSC2 = 0x7ff47ff4;
170
171 MDREFR |= 0x02080000;
172}
173
174/*
175 * Platform devices
176 */
177
178static struct platform_device *devices[] __initdata = {
179 &h5000_flash[0],
180 &h5000_flash[1],
181};
182
183static void __init h5000_init(void)
184{
185 fix_msc();
186
187 pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
188 pxa_set_udc_info(&h5000_udc_mach_info);
189 platform_add_devices(ARRAY_AND_SIZE(devices));
190}
191
192MACHINE_START(H5400, "HP iPAQ H5000")
193 .phys_io = 0x40000000,
194 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
195 .boot_params = 0xa0000100,
196 .map_io = pxa_map_io,
197 .init_irq = pxa25x_init_irq,
198 .timer = &pxa_timer,
199 .init_machine = h5000_init,
200MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h
new file mode 100644
index 000000000000..2a5ae3802787
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/h5000.h
@@ -0,0 +1,113 @@
1/*
2 * Hardware definitions for HP iPAQ h5xxx Handheld Computers
3 *
4 * Copyright(20)02 Hewlett-Packard Company.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
12 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
13 * FITNESS FOR ANY PARTICULAR PURPOSE.
14 *
15 * Author: Jamey Hicks
16 */
17
18#ifndef __ASM_ARCH_H5000_H
19#define __ASM_ARCH_H5000_H
20
21#include <mach/mfp-pxa25x.h>
22
23/*
24 * CPU GPIOs
25 */
26
27#define H5000_GPIO_POWER_BUTTON (0)
28#define H5000_GPIO_RESET_BUTTON_N (1)
29#define H5000_GPIO_OPT_INT (2)
30#define H5000_GPIO_BACKUP_POWER (3)
31#define H5000_GPIO_ACTION_BUTTON (4)
32#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */
33/* 6 not connected */
34#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */
35/* 8 not connected */
36#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */
37#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */
38#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */
39/*(12) not connected */
40#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */
41#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */
42/*(15) is CS1# */
43/*(16) not connected */
44/*(17) not connected */
45/*(18) is pcmcia ready */
46/*(19) is dreq1 */
47/*(20) is dreq0 */
48#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */
49/*(22) is not connected */
50#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */
51#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */
52#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */
53#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */
54/*(27) not connected */
55#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */
56#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */
57#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */
58#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */
59#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */
60/*(33) is CS5# */
61#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */
62#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */
63#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */
64#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */
65#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */
66#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */
67#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */
68#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */
69
70#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */
71#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */
72#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */
73#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */
74
75#define H5000_GPIO_IRDA_RXD (46)
76#define H5000_GPIO_IRDA_TXD (47)
77
78#define H5000_GPIO_POE_N (48) /* used for pcmcia */
79#define H5000_GPIO_PWE_N (49) /* used for pcmcia */
80#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */
81#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */
82#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */
83#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */
84#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */
85#define H5000_GPIO_PREG_N (55) /* used for pcmcia */
86#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */
87#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */
88
89#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */
90/*(59) not connected */
91#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */
92#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */
93#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */
94/*(63) is not connected */
95#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */
96#define H5000_GPIO_CHG_EN (65) /* to sc801 en */
97#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */
98#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */
99#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */
100/*(69) is not connected */
101#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */
102#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71)
103#define H5000_GPIO_BT_M_RESET (72)
104#define H5000_GPIO_STD_CHG_RATE (73)
105#define H5000_GPIO_SD_WP_N (74)
106#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */
107#define H5000_GPIO_HEADPHONE_DETECT (76)
108#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */
109/*(78) is CS2# */
110/*(79) is CS3# */
111/*(80) is CS4# */
112
113#endif /* __ASM_ARCH_H5000_H */
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index a582a6d9b92b..e2d6784aa7ef 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -102,6 +102,9 @@
102 * PXA930 B0 0x69056835 0x5E643013 102 * PXA930 B0 0x69056835 0x5E643013
103 * PXA930 B1 0x69056837 0x7E643013 103 * PXA930 B1 0x69056837 0x7E643013
104 * PXA930 B2 0x69056838 0x8E643013 104 * PXA930 B2 0x69056838 0x8E643013
105 *
106 * PXA935 A0 0x56056931 0x1E653013
107 * PXA935 B0 0x56056936 0x6E653013
105 */ 108 */
106#ifdef CONFIG_PXA25x 109#ifdef CONFIG_PXA25x
107#define __cpu_is_pxa210(id) \ 110#define __cpu_is_pxa210(id) \
@@ -178,12 +181,22 @@
178#define __cpu_is_pxa930(id) \ 181#define __cpu_is_pxa930(id) \
179 ({ \ 182 ({ \
180 unsigned int _id = (id) >> 4 & 0xfff; \ 183 unsigned int _id = (id) >> 4 & 0xfff; \
181 _id == 0x683; \ 184 _id == 0x683; \
182 }) 185 })
183#else 186#else
184#define __cpu_is_pxa930(id) (0) 187#define __cpu_is_pxa930(id) (0)
185#endif 188#endif
186 189
190#ifdef CONFIG_CPU_PXA935
191#define __cpu_is_pxa935(id) \
192 ({ \
193 unsigned int _id = (id) >> 4 & 0xfff; \
194 _id == 0x693; \
195 })
196#else
197#define __cpu_is_pxa935(id) (0)
198#endif
199
187#define cpu_is_pxa210() \ 200#define cpu_is_pxa210() \
188 ({ \ 201 ({ \
189 __cpu_is_pxa210(read_cpuid_id()); \ 202 __cpu_is_pxa210(read_cpuid_id()); \
@@ -204,8 +217,6 @@
204 __cpu_is_pxa25x(read_cpuid_id()); \ 217 __cpu_is_pxa25x(read_cpuid_id()); \
205 }) 218 })
206 219
207extern int cpu_is_pxa26x(void);
208
209#define cpu_is_pxa27x() \ 220#define cpu_is_pxa27x() \
210 ({ \ 221 ({ \
211 __cpu_is_pxa27x(read_cpuid_id()); \ 222 __cpu_is_pxa27x(read_cpuid_id()); \
@@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void);
232 __cpu_is_pxa930(id); \ 243 __cpu_is_pxa930(id); \
233 }) 244 })
234 245
246#define cpu_is_pxa935() \
247 ({ \
248 unsigned int id = read_cpuid(CPUID_ID); \
249 __cpu_is_pxa935(id); \
250 })
251
235/* 252/*
236 * CPUID Core Generation Bit 253 * CPUID Core Generation Bit
237 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 254 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void);
249 _id == 0x3; \ 266 _id == 0x3; \
250 }) 267 })
251 268
269#define __cpu_is_pxa9xx(id) \
270 ({ \
271 unsigned int _id = (id) >> 4 & 0xfff; \
272 _id == 0x683 || _id == 0x693; \
273 })
274
252#define cpu_is_pxa2xx() \ 275#define cpu_is_pxa2xx() \
253 ({ \ 276 ({ \
254 __cpu_is_pxa2xx(read_cpuid_id()); \ 277 __cpu_is_pxa2xx(read_cpuid_id()); \
@@ -259,21 +282,10 @@ extern int cpu_is_pxa26x(void);
259 __cpu_is_pxa3xx(read_cpuid_id()); \ 282 __cpu_is_pxa3xx(read_cpuid_id()); \
260 }) 283 })
261 284
262/* 285#define cpu_is_pxa9xx() \
263 * Handy routine to set GPIO alternate functions 286 ({ \
264 */ 287 __cpu_is_pxa9xx(read_cpuid_id()); \
265extern int pxa_gpio_mode( int gpio_mode ); 288 })
266
267/*
268 * Return GPIO level, nonzero means high, zero is low
269 */
270extern int pxa_gpio_get_value(unsigned gpio);
271
272/*
273 * Set output GPIO level
274 */
275extern void pxa_gpio_set_value(unsigned gpio, int value);
276
277/* 289/*
278 * return current memory and LCD clock frequency in units of 10kHz 290 * return current memory and LCD clock frequency in units of 10kHz
279 */ 291 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 617cab2cc8d0..a72869b73ee3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -158,4 +158,35 @@
158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) 158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) 159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
160 160
161#ifdef CONFIG_CPU_PXA26x
162/* GPIO */
163#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
164#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1)
165#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1)
166#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1)
167#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1)
168
169/* SDRAM */
170#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH)
171#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH)
172#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH)
173#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
174
175/* USB */
176#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1)
177#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2)
178#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2)
179#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW)
180#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
181#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH)
182
183/* ASSP */
184#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3)
185#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW)
186#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3)
187#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
188#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1)
189#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
190#endif
191
161#endif /* __ASM_ARCH_MFP_PXA25X_H */ 192#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index 122bdbd53182..da4f85a4f990 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -11,6 +11,12 @@
11#include <mach/mfp.h> 11#include <mach/mfp.h>
12#include <mach/mfp-pxa2xx.h> 12#include <mach/mfp-pxa2xx.h>
13 13
14/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
15 * bit is set, regardless of the GPIO configuration
16 */
17#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0)
18#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0)
19
14/* GPIO */ 20/* GPIO */
15#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) 21#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
16#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) 22#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0)
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
index 8483cb511831..02868447b0b1 100644
--- a/arch/arm/mach-pxa/include/mach/mioa701.h
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -10,12 +10,14 @@
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) 10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
11 11
12/* Global GPIOs */ 12/* Global GPIOs */
13#define GPIO9_CHARGE_nEN 9 13#define GPIO9_CHARGE_EN 9
14#define GPIO18_POWEROFF 18 14#define GPIO18_POWEROFF 18
15#define GPIO87_LCD_POWER 87 15#define GPIO87_LCD_POWER 87
16#define GPIO96_AC_DETECT 96
17#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */
16 18
17/* USB */ 19/* USB */
18#define GPIO13_USB_DETECT 13 20#define GPIO13_nUSB_DETECT 13
19#define GPIO22_USB_ENABLE 22 21#define GPIO22_USB_ENABLE 22
20 22
21/* SDIO bits */ 23/* SDIO bits */
@@ -24,7 +26,10 @@
24#define GPIO91_SDIO_EN 91 26#define GPIO91_SDIO_EN 91
25 27
26/* Bluetooth */ 28/* Bluetooth */
29#define GPIO14_BT_nACTIVITY 14
27#define GPIO83_BT_ON 83 30#define GPIO83_BT_ON 83
31#define GPIO77_BT_UNKNOWN1 77
32#define GPIO86_BT_MAYBE_nRESET 86
28 33
29/* GPS */ 34/* GPS */
30#define GPIO23_GPS_UNKNOWN1 23 35#define GPIO23_GPS_UNKNOWN1 23
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 15295d960000..31d615aa7723 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -13,6 +13,7 @@
13#ifndef __PXA_REGS_H 13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H 14#define __PXA_REGS_H
15 15
16#include <mach/hardware.h>
16 17
17/* 18/*
18 * PXA Chip selects 19 * PXA Chip selects
@@ -123,298 +124,6 @@
123#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ 124#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
124#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 125#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
125 126
126
127/*
128 * UARTs
129 */
130
131/* Full Function UART (FFUART) */
132#define FFUART FFRBR
133#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
134#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
135#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
136#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
137#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
138#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
139#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
140#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
141#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
142#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
143#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
144#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
145#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
146
147/* Bluetooth UART (BTUART) */
148#define BTUART BTRBR
149#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
150#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
151#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
152#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
153#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
154#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
155#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
156#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
157#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
158#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
159#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
160#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
161#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
162
163/* Standard UART (STUART) */
164#define STUART STRBR
165#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
166#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
167#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
168#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
169#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
170#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
171#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
172#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
173#define STMSR __REG(0x40700018) /* Reserved */
174#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
175#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
176#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
177#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
178
179/* Hardware UART (HWUART) */
180#define HWUART HWRBR
181#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
182#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
183#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
184#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
185#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
186#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
187#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
188#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
189#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
190#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
191#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
192#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
193#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
194#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
195#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
196#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
197
198#define IER_DMAE (1 << 7) /* DMA Requests Enable */
199#define IER_UUE (1 << 6) /* UART Unit Enable */
200#define IER_NRZE (1 << 5) /* NRZ coding Enable */
201#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
202#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
203#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
204#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
205#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
206
207#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
208#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
209#define IIR_TOD (1 << 3) /* Time Out Detected */
210#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
211#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
212#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
213
214#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
215#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
216#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
217#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
218#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
219#define FCR_ITL_1 (0)
220#define FCR_ITL_8 (FCR_ITL1)
221#define FCR_ITL_16 (FCR_ITL2)
222#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
223
224#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
225#define LCR_SB (1 << 6) /* Set Break */
226#define LCR_STKYP (1 << 5) /* Sticky Parity */
227#define LCR_EPS (1 << 4) /* Even Parity Select */
228#define LCR_PEN (1 << 3) /* Parity Enable */
229#define LCR_STB (1 << 2) /* Stop Bit */
230#define LCR_WLS1 (1 << 1) /* Word Length Select */
231#define LCR_WLS0 (1 << 0) /* Word Length Select */
232
233#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
234#define LSR_TEMT (1 << 6) /* Transmitter Empty */
235#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
236#define LSR_BI (1 << 4) /* Break Interrupt */
237#define LSR_FE (1 << 3) /* Framing Error */
238#define LSR_PE (1 << 2) /* Parity Error */
239#define LSR_OE (1 << 1) /* Overrun Error */
240#define LSR_DR (1 << 0) /* Data Ready */
241
242#define MCR_LOOP (1 << 4)
243#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
244#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
245#define MCR_RTS (1 << 1) /* Request to Send */
246#define MCR_DTR (1 << 0) /* Data Terminal Ready */
247
248#define MSR_DCD (1 << 7) /* Data Carrier Detect */
249#define MSR_RI (1 << 6) /* Ring Indicator */
250#define MSR_DSR (1 << 5) /* Data Set Ready */
251#define MSR_CTS (1 << 4) /* Clear To Send */
252#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
253#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
254#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
255#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
256
257/*
258 * IrSR (Infrared Selection Register)
259 */
260#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
261#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
262#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
263#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
264#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
265
266
267/*
268 * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
269 */
270
271/*
272 * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
273 */
274
275/*
276 * AC97 Controller registers
277 */
278
279#define POCR __REG(0x40500000) /* PCM Out Control Register */
280#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
281#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
282
283#define PICR __REG(0x40500004) /* PCM In Control Register */
284#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
285#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
286
287#define MCCR __REG(0x40500008) /* Mic In Control Register */
288#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
289#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
290
291#define GCR __REG(0x4050000C) /* Global Control Register */
292#ifdef CONFIG_PXA3xx
293#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
294#endif
295#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
296#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
297#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
298#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
299#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
300#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
301#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
302#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
303#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
304#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
305#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
306
307#define POSR __REG(0x40500010) /* PCM Out Status Register */
308#define POSR_FIFOE (1 << 4) /* FIFO error */
309#define POSR_FSR (1 << 2) /* FIFO Service Request */
310
311#define PISR __REG(0x40500014) /* PCM In Status Register */
312#define PISR_FIFOE (1 << 4) /* FIFO error */
313#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
314#define PISR_FSR (1 << 2) /* FIFO Service Request */
315
316#define MCSR __REG(0x40500018) /* Mic In Status Register */
317#define MCSR_FIFOE (1 << 4) /* FIFO error */
318#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
319#define MCSR_FSR (1 << 2) /* FIFO Service Request */
320
321#define GSR __REG(0x4050001C) /* Global Status Register */
322#define GSR_CDONE (1 << 19) /* Command Done */
323#define GSR_SDONE (1 << 18) /* Status Done */
324#define GSR_RDCS (1 << 15) /* Read Completion Status */
325#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
326#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
327#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
328#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
329#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
330#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
331#define GSR_PCR (1 << 8) /* Primary Codec Ready */
332#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
333#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
334#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
335#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
336#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
337#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
338#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
339
340#define CAR __REG(0x40500020) /* CODEC Access Register */
341#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
342
343#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
344#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
345
346#define MOCR __REG(0x40500100) /* Modem Out Control Register */
347#define MOCR_FEIE (1 << 3) /* FIFO Error */
348#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
349
350#define MICR __REG(0x40500108) /* Modem In Control Register */
351#define MICR_FEIE (1 << 3) /* FIFO Error */
352#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
353
354#define MOSR __REG(0x40500110) /* Modem Out Status Register */
355#define MOSR_FIFOE (1 << 4) /* FIFO error */
356#define MOSR_FSR (1 << 2) /* FIFO Service Request */
357
358#define MISR __REG(0x40500118) /* Modem In Status Register */
359#define MISR_FIFOE (1 << 4) /* FIFO error */
360#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
361#define MISR_FSR (1 << 2) /* FIFO Service Request */
362
363#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
364
365#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
366#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
367#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
368#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
369
370
371/*
372 * Fast Infrared Communication Port
373 */
374
375#define FICP __REG(0x40800000) /* Start of FICP area */
376#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
377#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
378#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
379#define ICDR __REG(0x4080000c) /* ICP Data Register */
380#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
381#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
382
383#define ICCR0_AME (1 << 7) /* Address match enable */
384#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
385#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
386#define ICCR0_RXE (1 << 4) /* Receive enable */
387#define ICCR0_TXE (1 << 3) /* Transmit enable */
388#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
389#define ICCR0_LBM (1 << 1) /* Loopback mode */
390#define ICCR0_ITR (1 << 0) /* IrDA transmission */
391
392#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
393#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
394#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
395#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
396#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
397#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
398
399#ifdef CONFIG_PXA27x
400#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
401#endif
402#define ICSR0_FRE (1 << 5) /* Framing error */
403#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
404#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
405#define ICSR0_RAB (1 << 2) /* Receiver abort */
406#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
407#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
408
409#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
410#define ICSR1_CRE (1 << 5) /* CRC error */
411#define ICSR1_EOF (1 << 4) /* End of frame */
412#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
413#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
414#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
415#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
416
417
418/* 127/*
419 * Real Time Clock 128 * Real Time Clock
420 */ 129 */
@@ -463,19 +172,6 @@
463 172
464 173
465/* 174/*
466 * Pulse Width Modulator
467 */
468
469#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
470#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
471#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
472
473#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
474#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
475#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
476
477
478/*
479 * Interrupt Controller 175 * Interrupt Controller
480 */ 176 */
481 177
@@ -496,19 +192,6 @@
496 * General Purpose I/O 192 * General Purpose I/O
497 */ 193 */
498 194
499#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
500#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
501#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
502#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
503
504#define GPLR_OFFSET 0x00
505#define GPDR_OFFSET 0x0C
506#define GPSR_OFFSET 0x18
507#define GPCR_OFFSET 0x24
508#define GRER_OFFSET 0x30
509#define GFER_OFFSET 0x3C
510#define GEDR_OFFSET 0x48
511
512#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ 195#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
513#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ 196#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
514#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ 197#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
@@ -558,10 +241,6 @@
558 241
559#define GPIO_bit(x) (1 << ((x) & 0x1f)) 242#define GPIO_bit(x) (1 << ((x) & 0x1f))
560 243
561#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
562
563/* Interrupt Controller */
564
565#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) 244#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
566#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) 245#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
567#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) 246#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -580,189 +259,5 @@
580#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) 259#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
581#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ 260#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
582 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) 261 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
583#else
584
585#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
586#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
587#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
588#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
589#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
590#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
591#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
592#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
593
594#endif
595
596/*
597 * Power Manager - see pxa2xx-regs.h
598 */
599
600/*
601 * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
602 */
603
604/*
605 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
606 */
607
608/*
609 * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
610 */
611
612#ifdef CONFIG_PXA27x
613
614/* Camera Interface */
615#define CICR0 __REG(0x50000000)
616#define CICR1 __REG(0x50000004)
617#define CICR2 __REG(0x50000008)
618#define CICR3 __REG(0x5000000C)
619#define CICR4 __REG(0x50000010)
620#define CISR __REG(0x50000014)
621#define CIFR __REG(0x50000018)
622#define CITOR __REG(0x5000001C)
623#define CIBR0 __REG(0x50000028)
624#define CIBR1 __REG(0x50000030)
625#define CIBR2 __REG(0x50000038)
626
627#define CICR0_DMAEN (1 << 31) /* DMA request enable */
628#define CICR0_PAR_EN (1 << 30) /* Parity enable */
629#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
630#define CICR0_ENB (1 << 28) /* Camera interface enable */
631#define CICR0_DIS (1 << 27) /* Camera interface disable */
632#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
633#define CICR0_TOM (1 << 9) /* Time-out mask */
634#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
635#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
636#define CICR0_EOLM (1 << 6) /* End-of-line mask */
637#define CICR0_PERRM (1 << 5) /* Parity-error mask */
638#define CICR0_QDM (1 << 4) /* Quick-disable mask */
639#define CICR0_CDM (1 << 3) /* Disable-done mask */
640#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
641#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
642#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
643
644#define CICR1_TBIT (1 << 31) /* Transparency bit */
645#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
646#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
647#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
648#define CICR1_RGB_F (1 << 11) /* RGB format */
649#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
650#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
651#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
652#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
653#define CICR1_DW (0x7 << 0) /* Data width mask */
654
655#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
656 wait count mask */
657#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
658 wait count mask */
659#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
660#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
661 wait count mask */
662#define CICR2_FSW (0x7 << 0) /* Frame stabilization
663 wait count mask */
664
665#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
666 wait count mask */
667#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
668 wait count mask */
669#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
670#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
671 wait count mask */
672#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
673
674#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
675#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
676#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
677#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
678#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
679#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
680#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
681#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
682
683#define CISR_FTO (1 << 15) /* FIFO time-out */
684#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
685#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
686#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
687#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
688#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
689#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
690#define CISR_EOL (1 << 8) /* End of line */
691#define CISR_PAR_ERR (1 << 7) /* Parity error */
692#define CISR_CQD (1 << 6) /* Camera interface quick disable */
693#define CISR_CDD (1 << 5) /* Camera interface disable done */
694#define CISR_SOF (1 << 4) /* Start of frame */
695#define CISR_EOF (1 << 3) /* End of frame */
696#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
697#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
698#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
699
700#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
701#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
702#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
703#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
704#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
705#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
706#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
707#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
708
709#define SRAM_SIZE 0x40000 /* 4x64K */
710
711#define SRAM_MEM_PHYS 0x5C000000
712
713#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
714#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
715
716#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
717#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
718#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
719#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
720
721#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
722#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
723#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
724#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
725
726#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
727#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
728#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
729#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
730
731#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
732#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
733#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
734#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
735
736#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
737#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
738#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
739#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
740
741#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
742
743#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
744#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
745#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
746
747#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
748#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
749#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
750
751#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
752#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
753#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
754
755#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
756#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
757#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
758
759#endif
760
761/* PWRMODE register M field values */
762
763#define PWRMODE_IDLE 0x1
764#define PWRMODE_STANDBY 0x2
765#define PWRMODE_SLEEP 0x3
766#define PWRMODE_DEEPSLEEP 0x7
767 262
768#endif 263#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index 6ef1dd09970b..d83393e25273 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -365,4 +365,9 @@
365#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) 365#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
366#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) 366#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
367 367
368/*
369 * Handy routine to set GPIO alternate functions
370 */
371extern int pxa_gpio_mode( int gpio_mode );
372
368#endif /* __ASM_ARCH_PXA2XX_GPIO_H */ 373#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 806ecfea44bf..77102d695cc7 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -49,6 +49,11 @@
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ 49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ 50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51 51
52#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
56
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ 57#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ 58#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ 59#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
@@ -243,4 +248,11 @@
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 248#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 249#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245 250
251/* PWRMODE register M field values */
252
253#define PWRMODE_IDLE 0x1
254#define PWRMODE_STANDBY 0x2
255#define PWRMODE_SLEEP 0x3
256#define PWRMODE_DEEPSLEEP 0x7
257
246#endif 258#endif
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
new file mode 100644
index 000000000000..e41b9d202b8c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h
@@ -0,0 +1,99 @@
1#ifndef __ASM_ARCH_REGS_AC97_H
2#define __ASM_ARCH_REGS_AC97_H
3
4/*
5 * AC97 Controller registers
6 */
7
8#define POCR __REG(0x40500000) /* PCM Out Control Register */
9#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
10#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
11
12#define PICR __REG(0x40500004) /* PCM In Control Register */
13#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
14#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
15
16#define MCCR __REG(0x40500008) /* Mic In Control Register */
17#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
18#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
19
20#define GCR __REG(0x4050000C) /* Global Control Register */
21#ifdef CONFIG_PXA3xx
22#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
23#endif
24#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
25#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
26#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
27#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
28#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
29#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
30#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
31#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
32#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
33#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
34#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
35
36#define POSR __REG(0x40500010) /* PCM Out Status Register */
37#define POSR_FIFOE (1 << 4) /* FIFO error */
38#define POSR_FSR (1 << 2) /* FIFO Service Request */
39
40#define PISR __REG(0x40500014) /* PCM In Status Register */
41#define PISR_FIFOE (1 << 4) /* FIFO error */
42#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
43#define PISR_FSR (1 << 2) /* FIFO Service Request */
44
45#define MCSR __REG(0x40500018) /* Mic In Status Register */
46#define MCSR_FIFOE (1 << 4) /* FIFO error */
47#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
48#define MCSR_FSR (1 << 2) /* FIFO Service Request */
49
50#define GSR __REG(0x4050001C) /* Global Status Register */
51#define GSR_CDONE (1 << 19) /* Command Done */
52#define GSR_SDONE (1 << 18) /* Status Done */
53#define GSR_RDCS (1 << 15) /* Read Completion Status */
54#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
55#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
56#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
57#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
58#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
59#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
60#define GSR_PCR (1 << 8) /* Primary Codec Ready */
61#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
62#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
63#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
64#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
65#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
66#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
67#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
68
69#define CAR __REG(0x40500020) /* CODEC Access Register */
70#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
71
72#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
73#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
74
75#define MOCR __REG(0x40500100) /* Modem Out Control Register */
76#define MOCR_FEIE (1 << 3) /* FIFO Error */
77#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
78
79#define MICR __REG(0x40500108) /* Modem In Control Register */
80#define MICR_FEIE (1 << 3) /* FIFO Error */
81#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
82
83#define MOSR __REG(0x40500110) /* Modem Out Status Register */
84#define MOSR_FIFOE (1 << 4) /* FIFO error */
85#define MOSR_FSR (1 << 2) /* FIFO Service Request */
86
87#define MISR __REG(0x40500118) /* Modem In Status Register */
88#define MISR_FIFOE (1 << 4) /* FIFO error */
89#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
90#define MISR_FSR (1 << 2) /* FIFO Service Request */
91
92#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
93
94#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
95#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
96#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
97#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
98
99#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h
new file mode 100644
index 000000000000..55aeb7fb72f6
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-uart.h
@@ -0,0 +1,143 @@
1#ifndef __ASM_ARCH_REGS_UART_H
2#define __ASM_ARCH_REGS_UART_H
3
4/*
5 * UARTs
6 */
7
8/* Full Function UART (FFUART) */
9#define FFUART FFRBR
10#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
20#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
21#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
22#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
23
24/* Bluetooth UART (BTUART) */
25#define BTUART BTRBR
26#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
27#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
28#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
29#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
30#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
31#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
32#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
33#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
34#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
35#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
36#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
37#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
38#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
39
40/* Standard UART (STUART) */
41#define STUART STRBR
42#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
43#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
44#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
45#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
46#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
47#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
48#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
49#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
50#define STMSR __REG(0x40700018) /* Reserved */
51#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
52#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
53#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
54#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
55
56/* Hardware UART (HWUART) */
57#define HWUART HWRBR
58#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
59#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
60#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
61#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
62#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
63#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
64#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
65#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
66#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
67#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
68#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
69#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
70#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
71#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
72#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
73#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
74
75#define IER_DMAE (1 << 7) /* DMA Requests Enable */
76#define IER_UUE (1 << 6) /* UART Unit Enable */
77#define IER_NRZE (1 << 5) /* NRZ coding Enable */
78#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
79#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
80#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
81#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
82#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
83
84#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
85#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
86#define IIR_TOD (1 << 3) /* Time Out Detected */
87#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
88#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
89#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
90
91#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
92#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
93#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
94#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
95#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
96#define FCR_ITL_1 (0)
97#define FCR_ITL_8 (FCR_ITL1)
98#define FCR_ITL_16 (FCR_ITL2)
99#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
100
101#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
102#define LCR_SB (1 << 6) /* Set Break */
103#define LCR_STKYP (1 << 5) /* Sticky Parity */
104#define LCR_EPS (1 << 4) /* Even Parity Select */
105#define LCR_PEN (1 << 3) /* Parity Enable */
106#define LCR_STB (1 << 2) /* Stop Bit */
107#define LCR_WLS1 (1 << 1) /* Word Length Select */
108#define LCR_WLS0 (1 << 0) /* Word Length Select */
109
110#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
111#define LSR_TEMT (1 << 6) /* Transmitter Empty */
112#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
113#define LSR_BI (1 << 4) /* Break Interrupt */
114#define LSR_FE (1 << 3) /* Framing Error */
115#define LSR_PE (1 << 2) /* Parity Error */
116#define LSR_OE (1 << 1) /* Overrun Error */
117#define LSR_DR (1 << 0) /* Data Ready */
118
119#define MCR_LOOP (1 << 4)
120#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
121#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
122#define MCR_RTS (1 << 1) /* Request to Send */
123#define MCR_DTR (1 << 0) /* Data Terminal Ready */
124
125#define MSR_DCD (1 << 7) /* Data Carrier Detect */
126#define MSR_RI (1 << 6) /* Ring Indicator */
127#define MSR_DSR (1 << 5) /* Data Set Ready */
128#define MSR_CTS (1 << 4) /* Clear To Send */
129#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
130#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
131#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
132#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
133
134/*
135 * IrSR (Infrared Selection Register)
136 */
137#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
138#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
139#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
140#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
141#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
142
143#endif /* __ASM_ARCH_REGS_UART_H */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 21e3e890af98..a9a4f302b6ef 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13#include <mach/pxa-regs.h> 13#include <mach/regs-uart.h>
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16#define __REG(x) ((volatile unsigned long *)x) 16#define __REG(x) ((volatile unsigned long *)x)
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index b4d00aba0e31..5609f52e36b1 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -20,6 +20,7 @@
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/gpio.h>
23#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
24#include <linux/smc91x.h> 25#include <linux/smc91x.h>
25 26
@@ -36,7 +37,6 @@
36 37
37#include <mach/pxa-regs.h> 38#include <mach/pxa-regs.h>
38#include <mach/mfp-pxa300.h> 39#include <mach/mfp-pxa300.h>
39#include <mach/gpio.h>
40#include <mach/pxafb.h> 40#include <mach/pxafb.h>
41#include <mach/ssp.h> 41#include <mach/ssp.h>
42#include <mach/pxa2xx_spi.h> 42#include <mach/pxa2xx_spi.h>
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 519138bc5f85..bf59cec27def 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -123,6 +123,10 @@ static unsigned long magician_pin_config[] __initdata = {
123 GPIO107_GPIO, /* DS1WM_IRQ */ 123 GPIO107_GPIO, /* DS1WM_IRQ */
124 GPIO108_GPIO, /* GSM_READY */ 124 GPIO108_GPIO, /* GSM_READY */
125 GPIO115_GPIO, /* nPEN_IRQ */ 125 GPIO115_GPIO, /* nPEN_IRQ */
126
127 /* I2C */
128 GPIO117_I2C_SCL,
129 GPIO118_I2C_SDA,
126}; 130};
127 131
128/* 132/*
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index f2c7ad8f2b6b..5f224968043c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -128,6 +128,10 @@ static unsigned long mainstone_pin_config[] = {
128 GPIO108_KP_MKOUT_5, 128 GPIO108_KP_MKOUT_5,
129 GPIO96_KP_MKOUT_6, 129 GPIO96_KP_MKOUT_6,
130 130
131 /* I2C */
132 GPIO117_I2C_SCL,
133 GPIO118_I2C_SDA,
134
131 /* GPIO */ 135 /* GPIO */
132 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, 136 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
133}; 137};
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 2061c00c8ead..33626de8cbf6 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -38,12 +38,13 @@ struct gpio_desc {
38 unsigned valid : 1; 38 unsigned valid : 1;
39 unsigned can_wakeup : 1; 39 unsigned can_wakeup : 1;
40 unsigned keypad_gpio : 1; 40 unsigned keypad_gpio : 1;
41 unsigned dir_inverted : 1;
41 unsigned int mask; /* bit mask in PWER or PKWR */ 42 unsigned int mask; /* bit mask in PWER or PKWR */
43 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
42 unsigned long config; 44 unsigned long config;
43}; 45};
44 46
45static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; 47static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
46static int gpio_nr;
47 48
48static unsigned long gpdr_lpm[4]; 49static unsigned long gpdr_lpm[4];
49 50
@@ -54,7 +55,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
54 int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ 55 int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
55 int shft = (gpio & 0xf) << 1; 56 int shft = (gpio & 0xf) << 1;
56 int fn = MFP_AF(c); 57 int fn = MFP_AF(c);
57 int dir = c & MFP_DIR_OUT; 58 int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
58 59
59 if (fn > 3) 60 if (fn > 3)
60 return -EINVAL; 61 return -EINVAL;
@@ -68,7 +69,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
68 else 69 else
69 GAFR_U(bank) = gafr; 70 GAFR_U(bank) = gafr;
70 71
71 if (dir == MFP_DIR_OUT) 72 if (is_out ^ gpio_desc[gpio].dir_inverted)
72 GPDR(gpio) |= mask; 73 GPDR(gpio) |= mask;
73 else 74 else
74 GPDR(gpio) &= ~mask; 75 GPDR(gpio) &= ~mask;
@@ -77,11 +78,11 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
77 switch (c & MFP_LPM_STATE_MASK) { 78 switch (c & MFP_LPM_STATE_MASK) {
78 case MFP_LPM_DRIVE_HIGH: 79 case MFP_LPM_DRIVE_HIGH:
79 PGSR(bank) |= mask; 80 PGSR(bank) |= mask;
80 dir = MFP_DIR_OUT; 81 is_out = 1;
81 break; 82 break;
82 case MFP_LPM_DRIVE_LOW: 83 case MFP_LPM_DRIVE_LOW:
83 PGSR(bank) &= ~mask; 84 PGSR(bank) &= ~mask;
84 dir = MFP_DIR_OUT; 85 is_out = 1;
85 break; 86 break;
86 case MFP_LPM_DEFAULT: 87 case MFP_LPM_DEFAULT:
87 break; 88 break;
@@ -92,7 +93,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
92 break; 93 break;
93 } 94 }
94 95
95 if (dir == MFP_DIR_OUT) 96 if (is_out ^ gpio_desc[gpio].dir_inverted)
96 gpdr_lpm[bank] |= mask; 97 gpdr_lpm[bank] |= mask;
97 else 98 else
98 gpdr_lpm[bank] &= ~mask; 99 gpdr_lpm[bank] &= ~mask;
@@ -106,7 +107,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
106 return -EINVAL; 107 return -EINVAL;
107 } 108 }
108 109
109 if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) { 110 if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
110 pr_warning("%s: output GPIO%d unable to wakeup\n", 111 pr_warning("%s: output GPIO%d unable to wakeup\n",
111 __func__, gpio); 112 __func__, gpio);
112 return -EINVAL; 113 return -EINVAL;
@@ -169,7 +170,7 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
169int gpio_set_wake(unsigned int gpio, unsigned int on) 170int gpio_set_wake(unsigned int gpio, unsigned int on)
170{ 171{
171 struct gpio_desc *d; 172 struct gpio_desc *d;
172 unsigned long c; 173 unsigned long c, mux_taken;
173 174
174 if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) 175 if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
175 return -EINVAL; 176 return -EINVAL;
@@ -183,9 +184,13 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
183 if (d->keypad_gpio) 184 if (d->keypad_gpio)
184 return -EINVAL; 185 return -EINVAL;
185 186
187 mux_taken = (PWER & d->mux_mask) & (~d->mask);
188 if (on && mux_taken)
189 return -EBUSY;
190
186 if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { 191 if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
187 if (on) { 192 if (on) {
188 PWER |= d->mask; 193 PWER = (PWER & ~d->mux_mask) | d->mask;
189 194
190 if (c & MFP_LPM_EDGE_RISE) 195 if (c & MFP_LPM_EDGE_RISE)
191 PRER |= d->mask; 196 PRER |= d->mask;
@@ -210,7 +215,7 @@ static void __init pxa25x_mfp_init(void)
210{ 215{
211 int i; 216 int i;
212 217
213 for (i = 0; i <= 84; i++) 218 for (i = 0; i <= pxa_last_gpio; i++)
214 gpio_desc[i].valid = 1; 219 gpio_desc[i].valid = 1;
215 220
216 for (i = 0; i <= 15; i++) { 221 for (i = 0; i <= 15; i++) {
@@ -218,7 +223,11 @@ static void __init pxa25x_mfp_init(void)
218 gpio_desc[i].mask = GPIO_bit(i); 223 gpio_desc[i].mask = GPIO_bit(i);
219 } 224 }
220 225
221 gpio_nr = 85; 226 /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
227 * direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
228 */
229 for (i = 86; i <= pxa_last_gpio; i++)
230 gpio_desc[i].dir_inverted = 1;
222} 231}
223#else 232#else
224static inline void pxa25x_mfp_init(void) {} 233static inline void pxa25x_mfp_init(void) {}
@@ -251,11 +260,27 @@ int keypad_set_wake(unsigned int on)
251 return 0; 260 return 0;
252} 261}
253 262
263#define PWER_WEMUX2_GPIO38 (1 << 16)
264#define PWER_WEMUX2_GPIO53 (2 << 16)
265#define PWER_WEMUX2_GPIO40 (3 << 16)
266#define PWER_WEMUX2_GPIO36 (4 << 16)
267#define PWER_WEMUX2_MASK (7 << 16)
268#define PWER_WEMUX3_GPIO31 (1 << 19)
269#define PWER_WEMUX3_GPIO113 (2 << 19)
270#define PWER_WEMUX3_MASK (3 << 19)
271
272#define INIT_GPIO_DESC_MUXED(mux, gpio) \
273do { \
274 gpio_desc[(gpio)].can_wakeup = 1; \
275 gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
276 gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \
277} while (0)
278
254static void __init pxa27x_mfp_init(void) 279static void __init pxa27x_mfp_init(void)
255{ 280{
256 int i, gpio; 281 int i, gpio;
257 282
258 for (i = 0; i <= 120; i++) { 283 for (i = 0; i <= pxa_last_gpio; i++) {
259 /* skip GPIO2, 5, 6, 7, 8, they are not 284 /* skip GPIO2, 5, 6, 7, 8, they are not
260 * valid pins allow configuration 285 * valid pins allow configuration
261 */ 286 */
@@ -286,7 +311,12 @@ static void __init pxa27x_mfp_init(void)
286 gpio_desc[35].can_wakeup = 1; 311 gpio_desc[35].can_wakeup = 1;
287 gpio_desc[35].mask = PWER_WE35; 312 gpio_desc[35].mask = PWER_WE35;
288 313
289 gpio_nr = 121; 314 INIT_GPIO_DESC_MUXED(WEMUX3, 31);
315 INIT_GPIO_DESC_MUXED(WEMUX3, 113);
316 INIT_GPIO_DESC_MUXED(WEMUX2, 38);
317 INIT_GPIO_DESC_MUXED(WEMUX2, 53);
318 INIT_GPIO_DESC_MUXED(WEMUX2, 40);
319 INIT_GPIO_DESC_MUXED(WEMUX2, 36);
290} 320}
291#else 321#else
292static inline void pxa27x_mfp_init(void) {} 322static inline void pxa27x_mfp_init(void) {}
@@ -300,7 +330,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
300{ 330{
301 int i; 331 int i;
302 332
303 for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { 333 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
304 334
305 saved_gafr[0][i] = GAFR_L(i); 335 saved_gafr[0][i] = GAFR_L(i);
306 saved_gafr[1][i] = GAFR_U(i); 336 saved_gafr[1][i] = GAFR_U(i);
@@ -315,7 +345,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d)
315{ 345{
316 int i; 346 int i;
317 347
318 for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { 348 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
319 GAFR_L(i) = saved_gafr[0][i]; 349 GAFR_L(i) = saved_gafr[0][i];
320 GAFR_U(i) = saved_gafr[1][i]; 350 GAFR_U(i) = saved_gafr[1][i];
321 GPDR(i * 32) = saved_gpdr[i]; 351 GPDR(i * 32) = saved_gpdr[i];
@@ -348,7 +378,7 @@ static int __init pxa2xx_mfp_init(void)
348 pxa27x_mfp_init(); 378 pxa27x_mfp_init();
349 379
350 /* initialize gafr_run[], pgsr_lpm[] from existing values */ 380 /* initialize gafr_run[], pgsr_lpm[] from existing values */
351 for (i = 0; i <= gpio_to_bank(gpio_nr); i++) 381 for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
352 gpdr_lpm[i] = GPDR(i * 32); 382 gpdr_lpm[i] = GPDR(i * 32);
353 383
354 return sysdev_class_register(&pxa2xx_mfp_sysclass); 384 return sysdev_class_register(&pxa2xx_mfp_sysclass);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 782903fe9c6c..2b427e015b6f 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -34,7 +34,7 @@
34#include <linux/irq.h> 34#include <linux/irq.h>
35#include <linux/pda_power.h> 35#include <linux/pda_power.h>
36#include <linux/power_supply.h> 36#include <linux/power_supply.h>
37#include <linux/wm97xx.h> 37#include <linux/wm97xx_batt.h>
38#include <linux/mtd/physmap.h> 38#include <linux/mtd/physmap.h>
39 39
40#include <asm/mach-types.h> 40#include <asm/mach-types.h>
@@ -46,6 +46,9 @@
46#include <mach/mmc.h> 46#include <mach/mmc.h>
47#include <mach/udc.h> 47#include <mach/udc.h>
48#include <mach/pxa27x-udc.h> 48#include <mach/pxa27x-udc.h>
49#include <mach/i2c.h>
50#include <mach/camera.h>
51#include <media/soc_camera.h>
49 52
50#include <mach/mioa701.h> 53#include <mach/mioa701.h>
51 54
@@ -54,10 +57,11 @@
54 57
55static unsigned long mioa701_pin_config[] = { 58static unsigned long mioa701_pin_config[] = {
56 /* Mio global */ 59 /* Mio global */
57 MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW), 60 MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW),
58 MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), 61 MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW),
59 MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), 62 MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH),
60 MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), 63 MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH),
64 MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0),
61 65
62 /* Backlight PWM 0 */ 66 /* Backlight PWM 0 */
63 GPIO16_PWM0_OUT, 67 GPIO16_PWM0_OUT,
@@ -74,7 +78,7 @@ static unsigned long mioa701_pin_config[] = {
74 MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), 78 MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW),
75 79
76 /* USB */ 80 /* USB */
77 MIO_CFG_IN(GPIO13_USB_DETECT, AF0), 81 MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0),
78 MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), 82 MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW),
79 83
80 /* LCD */ 84 /* LCD */
@@ -98,12 +102,29 @@ static unsigned long mioa701_pin_config[] = {
98 GPIO75_LCD_LCLK, 102 GPIO75_LCD_LCLK,
99 GPIO76_LCD_PCLK, 103 GPIO76_LCD_PCLK,
100 104
105 /* QCI */
106 GPIO12_CIF_DD_7,
107 GPIO17_CIF_DD_6,
108 GPIO50_CIF_DD_3,
109 GPIO51_CIF_DD_2,
110 GPIO52_CIF_DD_4,
111 GPIO53_CIF_MCLK,
112 GPIO54_CIF_PCLK,
113 GPIO55_CIF_DD_1,
114 GPIO81_CIF_DD_0,
115 GPIO82_CIF_DD_5,
116 GPIO84_CIF_FV,
117 GPIO85_CIF_LV,
118
101 /* Bluetooth */ 119 /* Bluetooth */
120 MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0),
102 GPIO44_BTUART_CTS, 121 GPIO44_BTUART_CTS,
103 GPIO42_BTUART_RXD, 122 GPIO42_BTUART_RXD,
104 GPIO45_BTUART_RTS, 123 GPIO45_BTUART_RTS,
105 GPIO43_BTUART_TXD, 124 GPIO43_BTUART_TXD,
106 MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), 125 MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW),
126 MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH),
127 MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH),
107 128
108 /* GPS */ 129 /* GPS */
109 MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), 130 MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW),
@@ -151,16 +172,16 @@ static unsigned long mioa701_pin_config[] = {
151 GPIO104_KP_MKOUT_1, 172 GPIO104_KP_MKOUT_1,
152 GPIO105_KP_MKOUT_2, 173 GPIO105_KP_MKOUT_2,
153 174
175 /* I2C */
176 GPIO117_I2C_SCL,
177 GPIO118_I2C_SDA,
178
154 /* Unknown */ 179 /* Unknown */
155 MFP_CFG_IN(GPIO14, AF0),
156 MFP_CFG_IN(GPIO20, AF0), 180 MFP_CFG_IN(GPIO20, AF0),
157 MFP_CFG_IN(GPIO21, AF0), 181 MFP_CFG_IN(GPIO21, AF0),
158 MFP_CFG_IN(GPIO33, AF0), 182 MFP_CFG_IN(GPIO33, AF0),
159 MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), 183 MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH),
160 MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), 184 MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH),
161 MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH),
162 MFP_CFG_IN(GPIO80, AF0),
163 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH),
164 MFP_CFG_IN(GPIO96, AF0), 185 MFP_CFG_IN(GPIO96, AF0),
165 MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), 186 MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
166}; 187};
@@ -407,7 +428,7 @@ static void udc_power_command(int cmd)
407 428
408static int is_usb_connected(void) 429static int is_usb_connected(void)
409{ 430{
410 return !!gpio_get_value(GPIO13_USB_DETECT); 431 return !gpio_get_value(GPIO13_nUSB_DETECT);
411} 432}
412 433
413static struct pxa2xx_udc_mach_info mioa701_udc_info = { 434static struct pxa2xx_udc_mach_info mioa701_udc_info = {
@@ -659,13 +680,19 @@ static char *supplicants[] = {
659 "mioa701_battery" 680 "mioa701_battery"
660}; 681};
661 682
683static int is_ac_connected(void)
684{
685 return gpio_get_value(GPIO96_AC_DETECT);
686}
687
662static void mioa701_set_charge(int flags) 688static void mioa701_set_charge(int flags)
663{ 689{
664 gpio_set_value(GPIO9_CHARGE_nEN, !flags); 690 gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB));
665} 691}
666 692
667static struct pda_power_pdata power_pdata = { 693static struct pda_power_pdata power_pdata = {
668 .is_ac_online = is_usb_connected, 694 .is_ac_online = is_ac_connected,
695 .is_usb_online = is_usb_connected,
669 .set_charge = mioa701_set_charge, 696 .set_charge = mioa701_set_charge,
670 .supplied_to = supplicants, 697 .supplied_to = supplicants,
671 .num_supplicants = ARRAY_SIZE(supplicants), 698 .num_supplicants = ARRAY_SIZE(supplicants),
@@ -674,8 +701,15 @@ static struct pda_power_pdata power_pdata = {
674static struct resource power_resources[] = { 701static struct resource power_resources[] = {
675 [0] = { 702 [0] = {
676 .name = "ac", 703 .name = "ac",
677 .start = gpio_to_irq(GPIO13_USB_DETECT), 704 .start = gpio_to_irq(GPIO96_AC_DETECT),
678 .end = gpio_to_irq(GPIO13_USB_DETECT), 705 .end = gpio_to_irq(GPIO96_AC_DETECT),
706 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
707 IORESOURCE_IRQ_LOWEDGE,
708 },
709 [1] = {
710 .name = "usb",
711 .start = gpio_to_irq(GPIO13_nUSB_DETECT),
712 .end = gpio_to_irq(GPIO13_nUSB_DETECT),
679 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | 713 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
680 IORESOURCE_IRQ_LOWEDGE, 714 IORESOURCE_IRQ_LOWEDGE,
681 }, 715 },
@@ -691,120 +725,43 @@ static struct platform_device power_dev = {
691 }, 725 },
692}; 726};
693 727
694#if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX) 728static struct wm97xx_batt_info mioa701_battery_data = {
695static struct wm97xx *battery_wm; 729 .batt_aux = WM97XX_AUX_ID1,
696 730 .temp_aux = -1,
697static enum power_supply_property battery_props[] = { 731 .charge_gpio = -1,
698 POWER_SUPPLY_PROP_STATUS, 732 .min_voltage = 0xc00,
699 POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, 733 .max_voltage = 0xfc0,
700 POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, 734 .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION,
701 POWER_SUPPLY_PROP_VOLTAGE_NOW, 735 .batt_div = 1,
702 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, /* Necessary for apm */ 736 .batt_mult = 1,
737 .batt_name = "mioa701_battery",
703}; 738};
704 739
705static int get_battery_voltage(void) 740/*
706{ 741 * Camera interface
707 int adc = -1; 742 */
708 743struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
709 if (battery_wm) 744 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
710 adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1); 745 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
711 return adc; 746 .mclk_10khz = 5000,
712}
713
714static int get_battery_status(struct power_supply *b)
715{
716 int status;
717
718 if (is_usb_connected())
719 status = POWER_SUPPLY_STATUS_CHARGING;
720 else
721 status = POWER_SUPPLY_STATUS_DISCHARGING;
722
723 return status;
724}
725
726static int get_property(struct power_supply *b,
727 enum power_supply_property psp,
728 union power_supply_propval *val)
729{
730 int rc = 0;
731
732 switch (psp) {
733 case POWER_SUPPLY_PROP_STATUS:
734 val->intval = get_battery_status(b);
735 break;
736 case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
737 val->intval = 0xfd0;
738 break;
739 case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
740 val->intval = 0xc00;
741 break;
742 case POWER_SUPPLY_PROP_VOLTAGE_NOW:
743 val->intval = get_battery_voltage();
744 break;
745 case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
746 val->intval = 100;
747 break;
748 default:
749 val->intval = -1;
750 rc = -1;
751 }
752
753 return rc;
754}; 747};
755 748
756static struct power_supply battery_ps = { 749static struct soc_camera_link iclink = {
757 .name = "mioa701_battery", 750 .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */
758 .type = POWER_SUPPLY_TYPE_BATTERY,
759 .get_property = get_property,
760 .properties = battery_props,
761 .num_properties = ARRAY_SIZE(battery_props),
762}; 751};
763 752
764static int battery_probe(struct platform_device *pdev) 753/* Board I2C devices. */
765{ 754static struct i2c_board_info __initdata mioa701_i2c_devices[] = {
766 struct wm97xx *wm = platform_get_drvdata(pdev); 755 {
767 int rc; 756 /* Must initialize before the camera(s) */
768 757 I2C_BOARD_INFO("mt9m111", 0x5d),
769 battery_wm = wm; 758 .platform_data = &iclink,
770
771 rc = power_supply_register(NULL, &battery_ps);
772 if (rc)
773 dev_err(&pdev->dev,
774 "Could not register mioa701 battery -> %d\n", rc);
775 return rc;
776}
777
778static int battery_remove(struct platform_device *pdev)
779{
780 battery_wm = NULL;
781 return 0;
782}
783
784static struct platform_driver mioa701_battery_driver = {
785 .driver = {
786 .name = "wm97xx-battery",
787 }, 759 },
788 .probe = battery_probe,
789 .remove = battery_remove
790}; 760};
791 761
792static int __init mioa701_battery_init(void) 762struct i2c_pxa_platform_data i2c_pdata = {
793{ 763 .fast_mode = 1,
794 int rc; 764};
795
796 rc = platform_driver_register(&mioa701_battery_driver);
797 if (rc)
798 printk(KERN_ERR "Could not register mioa701 battery driver\n");
799 return rc;
800}
801
802#else
803static int __init mioa701_battery_init(void)
804{
805 return 0;
806}
807#endif
808 765
809/* 766/*
810 * Mio global 767 * Mio global
@@ -851,17 +808,17 @@ static void mioa701_machine_exit(void);
851static void mioa701_poweroff(void) 808static void mioa701_poweroff(void)
852{ 809{
853 mioa701_machine_exit(); 810 mioa701_machine_exit();
854 gpio_set_value(GPIO18_POWEROFF, 1); 811 arm_machine_restart('s');
855} 812}
856 813
857static void mioa701_restart(char c) 814static void mioa701_restart(char c)
858{ 815{
859 mioa701_machine_exit(); 816 mioa701_machine_exit();
860 arm_machine_restart(c); 817 arm_machine_restart('s');
861} 818}
862 819
863struct gpio_ress global_gpios[] = { 820struct gpio_ress global_gpios[] = {
864 MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"), 821 MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"),
865 MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), 822 MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"),
866 MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") 823 MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power")
867}; 824};
@@ -879,12 +836,16 @@ static void __init mioa701_machine_init(void)
879 set_pxa_fb_info(&mioa701_pxafb_info); 836 set_pxa_fb_info(&mioa701_pxafb_info);
880 pxa_set_mci_info(&mioa701_mci_info); 837 pxa_set_mci_info(&mioa701_mci_info);
881 pxa_set_keypad_info(&mioa701_keypad_info); 838 pxa_set_keypad_info(&mioa701_keypad_info);
839 wm97xx_bat_set_pdata(&mioa701_battery_data);
882 udc_init(); 840 udc_init();
883 pm_power_off = mioa701_poweroff; 841 pm_power_off = mioa701_poweroff;
884 arm_pm_restart = mioa701_restart; 842 arm_pm_restart = mioa701_restart;
885 platform_add_devices(devices, ARRAY_SIZE(devices)); 843 platform_add_devices(devices, ARRAY_SIZE(devices));
886 gsm_init(); 844 gsm_init();
887 mioa701_battery_init(); 845
846 pxa_set_i2c_info(&i2c_pdata);
847 pxa_set_camera_info(&mioa701_pxacamera_platform_data);
848 i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
888} 849}
889 850
890static void mioa701_machine_exit(void) 851static void mioa701_machine_exit(void)
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index f601425f1b1e..1e7515452285 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -55,6 +55,10 @@ static unsigned long pcm990_pin_config[] __initdata = {
55 GPIO89_USBH1_PEN, 55 GPIO89_USBH1_PEN,
56 /* PWM0 */ 56 /* PWM0 */
57 GPIO16_PWM0_OUT, 57 GPIO16_PWM0_OUT,
58
59 /* I2C */
60 GPIO117_I2C_SCL,
61 GPIO118_I2C_SDA,
58}; 62};
59 63
60/* 64/*
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 2e3bd8b1523b..ae88855bf974 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -20,6 +20,7 @@
20#include <linux/fb.h> 20#include <linux/fb.h>
21#include <linux/pm.h> 21#include <linux/pm.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/mtd/physmap.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h> 26#include <linux/spi/ads7846.h>
@@ -413,9 +414,40 @@ static struct pxafb_mach_info poodle_fb_info = {
413 .lcd_conn = LCD_COLOR_TFT_16BPP, 414 .lcd_conn = LCD_COLOR_TFT_16BPP,
414}; 415};
415 416
417static struct mtd_partition sharpsl_rom_parts[] = {
418 {
419 .name ="Boot PROM Filesystem",
420 .offset = 0x00120000,
421 .size = MTDPART_SIZ_FULL,
422 },
423};
424
425static struct physmap_flash_data sharpsl_rom_data = {
426 .width = 2,
427 .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
428 .parts = sharpsl_rom_parts,
429};
430
431static struct resource sharpsl_rom_resources[] = {
432 {
433 .start = 0x00000000,
434 .end = 0x007fffff,
435 .flags = IORESOURCE_MEM,
436 },
437};
438
439static struct platform_device sharpsl_rom_device = {
440 .name = "physmap-flash",
441 .id = -1,
442 .resource = sharpsl_rom_resources,
443 .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
444 .dev.platform_data = &sharpsl_rom_data,
445};
446
416static struct platform_device *devices[] __initdata = { 447static struct platform_device *devices[] __initdata = {
417 &poodle_locomo_device, 448 &poodle_locomo_device,
418 &poodle_scoop_device, 449 &poodle_scoop_device,
450 &sharpsl_rom_device,
419}; 451};
420 452
421static void poodle_poweroff(void) 453static void poodle_poweroff(void)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 344b3282caf9..6c57522e2469 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -36,12 +36,6 @@
36#include "devices.h" 36#include "devices.h"
37#include "clock.h" 37#include "clock.h"
38 38
39int cpu_is_pxa26x(void)
40{
41 return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0);
42}
43EXPORT_SYMBOL_GPL(cpu_is_pxa26x);
44
45/* 39/*
46 * Various clock factors driven by the CCCR register. 40 * Various clock factors driven by the CCCR register.
47 */ 41 */
@@ -319,13 +313,21 @@ void __init pxa25x_init_irq(void)
319 pxa_init_gpio(85, pxa25x_set_wake); 313 pxa_init_gpio(85, pxa25x_set_wake);
320} 314}
321 315
316#ifdef CONFIG_CPU_PXA26x
317void __init pxa26x_init_irq(void)
318{
319 pxa_init_irq(32, pxa25x_set_wake);
320 pxa_init_gpio(90, pxa25x_set_wake);
321}
322#endif
323
322static struct platform_device *pxa25x_devices[] __initdata = { 324static struct platform_device *pxa25x_devices[] __initdata = {
323 &pxa25x_device_udc, 325 &pxa25x_device_udc,
324 &pxa_device_ffuart, 326 &pxa_device_ffuart,
325 &pxa_device_btuart, 327 &pxa_device_btuart,
326 &pxa_device_stuart, 328 &pxa_device_stuart,
327 &pxa_device_i2s, 329 &pxa_device_i2s,
328 &pxa_device_rtc, 330 &sa1100_device_rtc,
329 &pxa25x_device_ssp, 331 &pxa25x_device_ssp,
330 &pxa25x_device_nssp, 332 &pxa25x_device_nssp,
331 &pxa25x_device_assp, 333 &pxa25x_device_assp,
@@ -371,7 +373,7 @@ static int __init pxa25x_init(void)
371 } 373 }
372 374
373 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ 375 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
374 if (cpu_is_pxa255() || cpu_is_pxa26x()) { 376 if (cpu_is_pxa255()) {
375 clks_register(&pxa25x_hwuart_clkreg, 1); 377 clks_register(&pxa25x_hwuart_clkreg, 1);
376 ret = platform_device_register(&pxa_device_hwuart); 378 ret = platform_device_register(&pxa_device_hwuart);
377 } 379 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 15c8e5b9f9bc..411bec54fdc4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -332,38 +332,18 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on)
332void __init pxa27x_init_irq(void) 332void __init pxa27x_init_irq(void)
333{ 333{
334 pxa_init_irq(34, pxa27x_set_wake); 334 pxa_init_irq(34, pxa27x_set_wake);
335 pxa_init_gpio(128, pxa27x_set_wake); 335 pxa_init_gpio(121, pxa27x_set_wake);
336} 336}
337 337
338/* 338/*
339 * device registration specific to PXA27x. 339 * device registration specific to PXA27x.
340 */ 340 */
341
342static struct resource i2c_power_resources[] = {
343 {
344 .start = 0x40f00180,
345 .end = 0x40f001a3,
346 .flags = IORESOURCE_MEM,
347 }, {
348 .start = IRQ_PWRI2C,
349 .end = IRQ_PWRI2C,
350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354struct platform_device pxa27x_device_i2c_power = {
355 .name = "pxa2xx-i2c",
356 .id = 1,
357 .resource = i2c_power_resources,
358 .num_resources = ARRAY_SIZE(i2c_power_resources),
359};
360
361void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) 341void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
362{ 342{
363 local_irq_disable(); 343 local_irq_disable();
364 PCFR |= PCFR_PI2CEN; 344 PCFR |= PCFR_PI2CEN;
365 local_irq_enable(); 345 local_irq_enable();
366 pxa27x_device_i2c_power.dev.platform_data = info; 346 pxa_register_device(&pxa27x_device_i2c_power, info);
367} 347}
368 348
369static struct platform_device *devices[] __initdata = { 349static struct platform_device *devices[] __initdata = {
@@ -372,8 +352,8 @@ static struct platform_device *devices[] __initdata = {
372 &pxa_device_btuart, 352 &pxa_device_btuart,
373 &pxa_device_stuart, 353 &pxa_device_stuart,
374 &pxa_device_i2s, 354 &pxa_device_i2s,
355 &sa1100_device_rtc,
375 &pxa_device_rtc, 356 &pxa_device_rtc,
376 &pxa27x_device_i2c_power,
377 &pxa27x_device_ssp1, 357 &pxa27x_device_ssp1,
378 &pxa27x_device_ssp2, 358 &pxa27x_device_ssp2,
379 &pxa27x_device_ssp3, 359 &pxa27x_device_ssp3,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index b7e53829d376..490893824e78 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -29,6 +29,7 @@
29#include <mach/pm.h> 29#include <mach/pm.h>
30#include <mach/dma.h> 30#include <mach/dma.h>
31#include <mach/ssp.h> 31#include <mach/ssp.h>
32#include <mach/i2c.h>
32 33
33#include "generic.h" 34#include "generic.h"
34#include "devices.h" 35#include "devices.h"
@@ -544,28 +545,9 @@ void __init pxa3xx_init_irq(void)
544 * device registration specific to PXA3xx. 545 * device registration specific to PXA3xx.
545 */ 546 */
546 547
547static struct resource i2c_power_resources[] = {
548 {
549 .start = 0x40f500c0,
550 .end = 0x40f500d3,
551 .flags = IORESOURCE_MEM,
552 }, {
553 .start = IRQ_PWRI2C,
554 .end = IRQ_PWRI2C,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559struct platform_device pxa3xx_device_i2c_power = {
560 .name = "pxa2xx-i2c",
561 .id = 1,
562 .resource = i2c_power_resources,
563 .num_resources = ARRAY_SIZE(i2c_power_resources),
564};
565
566void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) 548void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
567{ 549{
568 pxa3xx_device_i2c_power.dev.platform_data = info; 550 pxa_register_device(&pxa3xx_device_i2c_power, info);
569} 551}
570 552
571static struct platform_device *devices[] __initdata = { 553static struct platform_device *devices[] __initdata = {
@@ -574,6 +556,7 @@ static struct platform_device *devices[] __initdata = {
574 &pxa_device_btuart, 556 &pxa_device_btuart,
575 &pxa_device_stuart, 557 &pxa_device_stuart,
576 &pxa_device_i2s, 558 &pxa_device_i2s,
559 &sa1100_device_rtc,
577 &pxa_device_rtc, 560 &pxa_device_rtc,
578 &pxa27x_device_ssp1, 561 &pxa27x_device_ssp1,
579 &pxa27x_device_ssp2, 562 &pxa27x_device_ssp2,
@@ -581,7 +564,6 @@ static struct platform_device *devices[] __initdata = {
581 &pxa3xx_device_ssp4, 564 &pxa3xx_device_ssp4,
582 &pxa27x_device_pwm0, 565 &pxa27x_device_pwm0,
583 &pxa27x_device_pwm1, 566 &pxa27x_device_pwm1,
584 &pxa3xx_device_i2c_power,
585}; 567};
586 568
587static struct sys_device pxa3xx_sysdev[] = { 569static struct sys_device pxa3xx_sysdev[] = {
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 3be76ee2bdbf..7299d87a1cb3 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -22,6 +22,7 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/leds.h> 23#include <linux/leds.h>
24#include <linux/mmc/host.h> 24#include <linux/mmc/host.h>
25#include <linux/mtd/physmap.h>
25#include <linux/pm.h> 26#include <linux/pm.h>
26#include <linux/backlight.h> 27#include <linux/backlight.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -122,6 +123,10 @@ static unsigned long spitz_pin_config[] __initdata = {
122 GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */ 123 GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */
123 GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */ 124 GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */
124 125
126 /* I2C */
127 GPIO117_I2C_SCL,
128 GPIO118_I2C_SDA,
129
125 GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, 130 GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
126}; 131};
127 132
@@ -609,10 +614,41 @@ static struct pxafb_mach_info spitz_pxafb_info = {
609}; 614};
610 615
611 616
617static struct mtd_partition sharpsl_rom_parts[] = {
618 {
619 .name ="Boot PROM Filesystem",
620 .offset = 0x00140000,
621 .size = MTDPART_SIZ_FULL,
622 },
623};
624
625static struct physmap_flash_data sharpsl_rom_data = {
626 .width = 2,
627 .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
628 .parts = sharpsl_rom_parts,
629};
630
631static struct resource sharpsl_rom_resources[] = {
632 {
633 .start = 0x00000000,
634 .end = 0x007fffff,
635 .flags = IORESOURCE_MEM,
636 },
637};
638
639static struct platform_device sharpsl_rom_device = {
640 .name = "physmap-flash",
641 .id = -1,
642 .resource = sharpsl_rom_resources,
643 .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
644 .dev.platform_data = &sharpsl_rom_data,
645};
646
612static struct platform_device *devices[] __initdata = { 647static struct platform_device *devices[] __initdata = {
613 &spitzscoop_device, 648 &spitzscoop_device,
614 &spitzkbd_device, 649 &spitzkbd_device,
615 &spitzled_device, 650 &spitzled_device,
651 &sharpsl_rom_device,
616}; 652};
617 653
618static void spitz_poweroff(void) 654static void spitz_poweroff(void)
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 224897a67d15..3332e5d0356c 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -25,6 +25,7 @@
25#include <linux/mfd/tmio.h> 25#include <linux/mfd/tmio.h>
26#include <linux/mtd/nand.h> 26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
28#include <linux/mtd/physmap.h>
28#include <linux/pm.h> 29#include <linux/pm.h>
29#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
30#include <linux/input.h> 31#include <linux/input.h>
@@ -733,6 +734,45 @@ static void tosa_tc6393xb_teardown(struct platform_device *dev)
733 gpio_free(TOSA_GPIO_CARD_VCC_ON); 734 gpio_free(TOSA_GPIO_CARD_VCC_ON);
734} 735}
735 736
737#ifdef CONFIG_MFD_TC6393XB
738static struct fb_videomode tosa_tc6393xb_lcd_mode[] = {
739 {
740 .xres = 480,
741 .yres = 640,
742 .pixclock = 0x002cdf00,/* PLL divisor */
743 .left_margin = 0x004c,
744 .right_margin = 0x005b,
745 .upper_margin = 0x0001,
746 .lower_margin = 0x000d,
747 .hsync_len = 0x0002,
748 .vsync_len = 0x0001,
749 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
750 .vmode = FB_VMODE_NONINTERLACED,
751 },{
752 .xres = 240,
753 .yres = 320,
754 .pixclock = 0x00e7f203,/* PLL divisor */
755 .left_margin = 0x0024,
756 .right_margin = 0x002f,
757 .upper_margin = 0x0001,
758 .lower_margin = 0x000d,
759 .hsync_len = 0x0002,
760 .vsync_len = 0x0001,
761 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
762 .vmode = FB_VMODE_NONINTERLACED,
763 }
764};
765
766static struct tmio_fb_data tosa_tc6393xb_fb_config = {
767 .lcd_set_power = tc6393xb_lcd_set_power,
768 .lcd_mode = tc6393xb_lcd_mode,
769 .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode),
770 .modes = &tosa_tc6393xb_lcd_mode[0],
771 .height = 82,
772 .width = 60,
773};
774#endif
775
736static struct tc6393xb_platform_data tosa_tc6393xb_data = { 776static struct tc6393xb_platform_data tosa_tc6393xb_data = {
737 .scr_pll2cr = 0x0cc1, 777 .scr_pll2cr = 0x0cc1,
738 .scr_gper = 0x3300, 778 .scr_gper = 0x3300,
@@ -748,6 +788,9 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = {
748 .resume = tosa_tc6393xb_resume, 788 .resume = tosa_tc6393xb_resume,
749 789
750 .nand_data = &tosa_tc6393xb_nand_config, 790 .nand_data = &tosa_tc6393xb_nand_config,
791#ifdef CONFIG_MFD_TC6393XB
792 .fb_data = &tosa_tc6393xb_fb_config,
793#endif
751 794
752 .resume_restore = 1, 795 .resume_restore = 1,
753}; 796};
@@ -789,6 +832,36 @@ static struct spi_board_info spi_board_info[] __initdata = {
789 }, 832 },
790}; 833};
791 834
835static struct mtd_partition sharpsl_rom_parts[] = {
836 {
837 .name ="Boot PROM Filesystem",
838 .offset = 0x00160000,
839 .size = MTDPART_SIZ_FULL,
840 },
841};
842
843static struct physmap_flash_data sharpsl_rom_data = {
844 .width = 2,
845 .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
846 .parts = sharpsl_rom_parts,
847};
848
849static struct resource sharpsl_rom_resources[] = {
850 {
851 .start = 0x00000000,
852 .end = 0x007fffff,
853 .flags = IORESOURCE_MEM,
854 },
855};
856
857static struct platform_device sharpsl_rom_device = {
858 .name = "physmap-flash",
859 .id = -1,
860 .resource = sharpsl_rom_resources,
861 .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
862 .dev.platform_data = &sharpsl_rom_data,
863};
864
792static struct platform_device *devices[] __initdata = { 865static struct platform_device *devices[] __initdata = {
793 &tosascoop_device, 866 &tosascoop_device,
794 &tosascoop_jc_device, 867 &tosascoop_jc_device,
@@ -798,6 +871,7 @@ static struct platform_device *devices[] __initdata = {
798 &tosa_gpio_keys_device, 871 &tosa_gpio_keys_device,
799 &tosaled_device, 872 &tosaled_device,
800 &tosa_bt_device, 873 &tosa_bt_device,
874 &sharpsl_rom_device,
801}; 875};
802 876
803static void tosa_poweroff(void) 877static void tosa_poweroff(void)
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 813804433466..218d2001f1df 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/gpio.h>
21#include <linux/pwm_backlight.h> 22#include <linux/pwm_backlight.h>
22#include <linux/smc91x.h> 23#include <linux/smc91x.h>
23 24
@@ -25,7 +26,6 @@
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/audio.h> 28#include <mach/audio.h>
28#include <mach/gpio.h>
29#include <mach/pxafb.h> 29#include <mach/pxafb.h>
30#include <mach/zylonite.h> 30#include <mach/zylonite.h>
31#include <mach/mmc.h> 31#include <mach/mmc.h>
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 0f244744daae..28e4e623780b 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -16,8 +16,8 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19 20
20#include <mach/gpio.h>
21#include <mach/mfp-pxa320.h> 21#include <mach/mfp-pxa320.h>
22#include <mach/zylonite.h> 22#include <mach/zylonite.h>
23 23
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8f6cf56c11c0..33515c214b92 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -481,3 +481,28 @@ __xsc3_proc_info:
481 .long xsc3_mc_user_fns 481 .long xsc3_mc_user_fns
482 .long xsc3_cache_fns 482 .long xsc3_cache_fns
483 .size __xsc3_proc_info, . - __xsc3_proc_info 483 .size __xsc3_proc_info, . - __xsc3_proc_info
484
485/* Note: PXA935 changed its implementor ID from Intel to Marvell */
486
487 .type __xsc3_pxa935_proc_info,#object
488__xsc3_pxa935_proc_info:
489 .long 0x56056000
490 .long 0xffffe000
491 .long PMD_TYPE_SECT | \
492 PMD_SECT_BUFFERABLE | \
493 PMD_SECT_CACHEABLE | \
494 PMD_SECT_AP_WRITE | \
495 PMD_SECT_AP_READ
496 .long PMD_TYPE_SECT | \
497 PMD_SECT_AP_WRITE | \
498 PMD_SECT_AP_READ
499 b __xsc3_setup
500 .long cpu_arch_name
501 .long cpu_elf_name
502 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
503 .long cpu_xsc3_name
504 .long xsc3_processor_functions
505 .long v4wbi_tlb_fns
506 .long xsc3_mc_user_fns
507 .long xsc3_cache_fns
508 .size __xsc3_pxa935_proc_info, . - __xsc3_pxa935_proc_info
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index ba648750a8d9..1d11e2be9ef8 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -31,7 +31,7 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/wm97xx.h> 32#include <linux/wm97xx.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <mach/pxa-regs.h> 34#include <mach/regs-ac97.h>
35 35
36#define VERSION "0.13" 36#define VERSION "0.13"
37 37
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 6586f0b13363..70a77625107d 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -39,6 +39,8 @@
39#include <mach/pxa-regs.h> 39#include <mach/pxa-regs.h>
40#include <mach/camera.h> 40#include <mach/camera.h>
41 41
42#include "pxa_camera.h"
43
42#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 44#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43#define PXA_CAM_DRV_NAME "pxa27x-camera" 45#define PXA_CAM_DRV_NAME "pxa27x-camera"
44 46
diff --git a/drivers/media/video/pxa_camera.h b/drivers/media/video/pxa_camera.h
new file mode 100644
index 000000000000..89cbfc9a35c5
--- /dev/null
+++ b/drivers/media/video/pxa_camera.h
@@ -0,0 +1,95 @@
1/* Camera Interface */
2#define CICR0 __REG(0x50000000)
3#define CICR1 __REG(0x50000004)
4#define CICR2 __REG(0x50000008)
5#define CICR3 __REG(0x5000000C)
6#define CICR4 __REG(0x50000010)
7#define CISR __REG(0x50000014)
8#define CIFR __REG(0x50000018)
9#define CITOR __REG(0x5000001C)
10#define CIBR0 __REG(0x50000028)
11#define CIBR1 __REG(0x50000030)
12#define CIBR2 __REG(0x50000038)
13
14#define CICR0_DMAEN (1 << 31) /* DMA request enable */
15#define CICR0_PAR_EN (1 << 30) /* Parity enable */
16#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
17#define CICR0_ENB (1 << 28) /* Camera interface enable */
18#define CICR0_DIS (1 << 27) /* Camera interface disable */
19#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
20#define CICR0_TOM (1 << 9) /* Time-out mask */
21#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
22#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
23#define CICR0_EOLM (1 << 6) /* End-of-line mask */
24#define CICR0_PERRM (1 << 5) /* Parity-error mask */
25#define CICR0_QDM (1 << 4) /* Quick-disable mask */
26#define CICR0_CDM (1 << 3) /* Disable-done mask */
27#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
28#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
29#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
30
31#define CICR1_TBIT (1 << 31) /* Transparency bit */
32#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
33#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
34#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
35#define CICR1_RGB_F (1 << 11) /* RGB format */
36#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
37#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
38#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
39#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
40#define CICR1_DW (0x7 << 0) /* Data width mask */
41
42#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
43 wait count mask */
44#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
45 wait count mask */
46#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
47#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
48 wait count mask */
49#define CICR2_FSW (0x7 << 0) /* Frame stabilization
50 wait count mask */
51
52#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
53 wait count mask */
54#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
55 wait count mask */
56#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
57#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
58 wait count mask */
59#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
60
61#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
62#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
63#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
64#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
65#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
66#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
67#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
68#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
69
70#define CISR_FTO (1 << 15) /* FIFO time-out */
71#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
72#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
73#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
74#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
75#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
76#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
77#define CISR_EOL (1 << 8) /* End of line */
78#define CISR_PAR_ERR (1 << 7) /* Parity error */
79#define CISR_CQD (1 << 6) /* Camera interface quick disable */
80#define CISR_CDD (1 << 5) /* Camera interface disable done */
81#define CISR_SOF (1 << 4) /* Start of frame */
82#define CISR_EOF (1 << 3) /* End of frame */
83#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
84#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
85#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
86
87#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
88#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
89#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
90#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
91#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
92#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
93#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
94#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
95
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 61c922a8356f..ce5752ab579d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -20,8 +20,8 @@
20#include <linux/mtd/partitions.h> 20#include <linux/mtd/partitions.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <asm/dma.h>
24 23
24#include <mach/dma.h>
25#include <mach/pxa-regs.h> 25#include <mach/pxa-regs.h>
26#include <mach/pxa3xx_nand.h> 26#include <mach/pxa3xx_nand.h>
27 27
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 37424f01ebee..0e081292f4f7 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -26,6 +26,49 @@
26#include <mach/irda.h> 26#include <mach/irda.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/pxa-regs.h> 28#include <mach/pxa-regs.h>
29#include <mach/regs-uart.h>
30
31#define FICP __REG(0x40800000) /* Start of FICP area */
32#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
33#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
34#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
35#define ICDR __REG(0x4080000c) /* ICP Data Register */
36#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
37#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
38
39#define ICCR0_AME (1 << 7) /* Address match enable */
40#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
41#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
42#define ICCR0_RXE (1 << 4) /* Receive enable */
43#define ICCR0_TXE (1 << 3) /* Transmit enable */
44#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
45#define ICCR0_LBM (1 << 1) /* Loopback mode */
46#define ICCR0_ITR (1 << 0) /* IrDA transmission */
47
48#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
49#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
50#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
51#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
52#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
53#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
54
55#ifdef CONFIG_PXA27x
56#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
57#endif
58#define ICSR0_FRE (1 << 5) /* Framing error */
59#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
60#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
61#define ICSR0_RAB (1 << 2) /* Receiver abort */
62#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
63#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
64
65#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
66#define ICSR1_CRE (1 << 5) /* CRC error */
67#define ICSR1_EOF (1 << 4) /* End of frame */
68#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
69#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
70#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
71#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
29 72
30#define IrSR_RXPL_NEG_IS_ZERO (1<<4) 73#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
31#define IrSR_RXPL_POS_IS_ZERO 0x0 74#define IrSR_RXPL_POS_IS_ZERO 0x0
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index cc7d85bdfb3e..870b4c33f108 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -200,6 +200,9 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
200 200
201 201
202#ifdef SMC_USE_PXA_DMA 202#ifdef SMC_USE_PXA_DMA
203
204#include <mach/dma.h>
205
203/* 206/*
204 * Define the request and free functions 207 * Define the request and free functions
205 * These are unfortunately architecture specific as no generic allocation 208 * These are unfortunately architecture specific as no generic allocation
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index 8ea314bc00c1..f6e3b86bb0be 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -48,6 +48,7 @@
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <asm/irq.h> 49#include <asm/irq.h>
50#include <mach/pxa-regs.h> 50#include <mach/pxa-regs.h>
51#include <mach/regs-uart.h>
51 52
52 53
53struct uart_pxa_port { 54struct uart_pxa_port {
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 0bc2c5a127b9..afe7a65c5603 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -69,9 +69,6 @@
69#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 69#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
70 LCCR3_PCD | LCCR3_BPP) 70 LCCR3_PCD | LCCR3_BPP)
71 71
72static void (*pxafb_backlight_power)(int);
73static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
74
75static int pxafb_activate_var(struct fb_var_screeninfo *var, 72static int pxafb_activate_var(struct fb_var_screeninfo *var,
76 struct pxafb_info *); 73 struct pxafb_info *);
77static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 74static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
@@ -814,6 +811,7 @@ static int pxafb_smart_init(struct pxafb_info *fbi)
814 __func__); 811 __func__);
815 return PTR_ERR(fbi->smart_thread); 812 return PTR_ERR(fbi->smart_thread);
816 } 813 }
814
817 return 0; 815 return 0;
818} 816}
819#else 817#else
@@ -976,16 +974,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
976{ 974{
977 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 975 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
978 976
979 if (pxafb_backlight_power) 977 if (fbi->backlight_power)
980 pxafb_backlight_power(on); 978 fbi->backlight_power(on);
981} 979}
982 980
983static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 981static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
984{ 982{
985 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 983 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
986 984
987 if (pxafb_lcd_power) 985 if (fbi->lcd_power)
988 pxafb_lcd_power(on, &fbi->fb.var); 986 fbi->lcd_power(on, &fbi->fb.var);
989} 987}
990 988
991static void pxafb_setup_gpio(struct pxafb_info *fbi) 989static void pxafb_setup_gpio(struct pxafb_info *fbi)
@@ -1748,8 +1746,7 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1748 ret = -EINVAL; 1746 ret = -EINVAL;
1749 goto failed; 1747 goto failed;
1750 } 1748 }
1751 pxafb_backlight_power = inf->pxafb_backlight_power; 1749
1752 pxafb_lcd_power = inf->pxafb_lcd_power;
1753 fbi = pxafb_init_fbinfo(&dev->dev); 1750 fbi = pxafb_init_fbinfo(&dev->dev);
1754 if (!fbi) { 1751 if (!fbi) {
1755 /* only reason for pxafb_init_fbinfo to fail is kmalloc */ 1752 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
@@ -1758,6 +1755,9 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1758 goto failed; 1755 goto failed;
1759 } 1756 }
1760 1757
1758 fbi->backlight_power = inf->pxafb_backlight_power;
1759 fbi->lcd_power = inf->pxafb_lcd_power;
1760
1761 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 1761 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1762 if (r == NULL) { 1762 if (r == NULL) {
1763 dev_err(&dev->dev, "no I/O memory resource defined\n"); 1763 dev_err(&dev->dev, "no I/O memory resource defined\n");
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 31541b86f13d..d8eb93fa03a3 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -124,6 +124,9 @@ struct pxafb_info {
124 struct notifier_block freq_transition; 124 struct notifier_block freq_transition;
125 struct notifier_block freq_policy; 125 struct notifier_block freq_policy;
126#endif 126#endif
127
128 void (*lcd_power)(int, struct fb_var_screeninfo *);
129 void (*backlight_power)(int);
127}; 130};
128 131
129#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member) 132#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
index 34c1d94f921e..ef6539eea579 100644
--- a/sound/arm/pxa2xx-ac97-lib.c
+++ b/sound/arm/pxa2xx-ac97-lib.c
@@ -22,7 +22,7 @@
22 22
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <mach/pxa-regs.h> 25#include <mach/regs-ac97.h>
26#include <mach/pxa2xx-gpio.h> 26#include <mach/pxa2xx-gpio.h>
27#include <mach/audio.h> 27#include <mach/audio.h>
28 28
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index c2635beb4c88..85cf591d4e11 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -22,6 +22,7 @@
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/pxa-regs.h> 24#include <mach/pxa-regs.h>
25#include <mach/regs-ac97.h>
25#include <mach/audio.h> 26#include <mach/audio.h>
26 27
27#include "pxa2xx-pcm.h" 28#include "pxa2xx-pcm.h"
diff --git a/sound/arm/pxa2xx-pcm.h b/sound/arm/pxa2xx-pcm.h
index 5c4a4d38a083..65f86b56ba42 100644
--- a/sound/arm/pxa2xx-pcm.h
+++ b/sound/arm/pxa2xx-pcm.h
@@ -9,7 +9,7 @@
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12#include <asm/dma.h> 12#include <mach/dma.h>
13 13
14struct pxa2xx_runtime_data { 14struct pxa2xx_runtime_data {
15 int dma_ch; 15 int dma_ch;
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index a7a3a9c5c6ff..5e727393cfd4 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -21,6 +21,7 @@
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/pxa-regs.h> 23#include <mach/pxa-regs.h>
24#include <mach/regs-ac97.h>
24 25
25#include "pxa2xx-pcm.h" 26#include "pxa2xx-pcm.h"
26#include "pxa2xx-ac97.h" 27#include "pxa2xx-ac97.h"
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 10:46:35 -0400