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-rw-r--r--arch/ia64/kernel/perfmon.c2
-rw-r--r--arch/ia64/kernel/perfmon_montecito.h269
-rw-r--r--arch/ia64/mm/init.c36
-rw-r--r--arch/ia64/pci/pci.c19
-rw-r--r--arch/ia64/sn/include/xtalk/hubdev.h10
-rw-r--r--arch/ia64/sn/include/xtalk/xbow.h206
-rw-r--r--arch/ia64/sn/include/xtalk/xwidgetdev.h46
-rw-r--r--arch/ia64/sn/kernel/io_init.c10
-rw-r--r--arch/ia64/sn/kernel/irq.c10
-rw-r--r--arch/ia64/sn/kernel/tiocx.c18
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_ate.c16
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c44
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_provider.c12
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_reg.c28
-rw-r--r--arch/ia64/sn/pci/tioca_provider.c36
-rw-r--r--arch/ia64/sn/pci/tioce_provider.c68
-rw-r--r--include/asm-ia64/pal.h2
-rw-r--r--include/asm-ia64/processor.h4
-rw-r--r--include/asm-ia64/sn/intr.h2
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h48
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h14
-rw-r--r--include/asm-ia64/sn/pcidev.h4
-rw-r--r--include/asm-ia64/sn/pic.h204
-rw-r--r--include/asm-ia64/sn/shubio.h1620
-rw-r--r--include/asm-ia64/sn/sn_sal.h12
-rw-r--r--include/asm-ia64/sn/tioca.h82
-rw-r--r--include/asm-ia64/sn/tioca_provider.h56
-rw-r--r--include/asm-ia64/sn/tioce.h662
-rw-r--r--include/asm-ia64/sn/tioce_provider.h30
-rw-r--r--include/asm-ia64/sn/tiocp.h254
-rw-r--r--include/asm-ia64/sn/tiocx.h14
31 files changed, 2082 insertions, 1756 deletions
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index bd87cb6b7a81..2ea4b39efffa 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -628,9 +628,11 @@ static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count,
628 628
629#include "perfmon_itanium.h" 629#include "perfmon_itanium.h"
630#include "perfmon_mckinley.h" 630#include "perfmon_mckinley.h"
631#include "perfmon_montecito.h"
631#include "perfmon_generic.h" 632#include "perfmon_generic.h"
632 633
633static pmu_config_t *pmu_confs[]={ 634static pmu_config_t *pmu_confs[]={
635 &pmu_conf_mont,
634 &pmu_conf_mck, 636 &pmu_conf_mck,
635 &pmu_conf_ita, 637 &pmu_conf_ita,
636 &pmu_conf_gen, /* must be last */ 638 &pmu_conf_gen, /* must be last */
diff --git a/arch/ia64/kernel/perfmon_montecito.h b/arch/ia64/kernel/perfmon_montecito.h
new file mode 100644
index 000000000000..cd06ac6a686c
--- /dev/null
+++ b/arch/ia64/kernel/perfmon_montecito.h
@@ -0,0 +1,269 @@
1/*
2 * This file contains the Montecito PMU register description tables
3 * and pmc checker used by perfmon.c.
4 *
5 * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
6 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
7 */
8static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
9
10#define RDEP_MONT_ETB (RDEP(38)|RDEP(39)|RDEP(48)|RDEP(49)|RDEP(50)|RDEP(51)|RDEP(52)|RDEP(53)|RDEP(54)|\
11 RDEP(55)|RDEP(56)|RDEP(57)|RDEP(58)|RDEP(59)|RDEP(60)|RDEP(61)|RDEP(62)|RDEP(63))
12#define RDEP_MONT_DEAR (RDEP(32)|RDEP(33)|RDEP(36))
13#define RDEP_MONT_IEAR (RDEP(34)|RDEP(35))
14
15static pfm_reg_desc_t pfm_mont_pmc_desc[PMU_MAX_PMCS]={
16/* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
17/* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
18/* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
19/* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
20/* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, 0}, {0,0, 0, 0}},
21/* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, 0}, {0,0, 0, 0}},
22/* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, 0}, {0,0, 0, 0}},
23/* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, 0}, {0,0, 0, 0}},
24/* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, 0}, {0,0, 0, 0}},
25/* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, 0}, {0,0, 0, 0}},
26/* pmc10 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(10),0, 0, 0}, {0,0, 0, 0}},
27/* pmc11 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(11),0, 0, 0}, {0,0, 0, 0}},
28/* pmc12 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(12),0, 0, 0}, {0,0, 0, 0}},
29/* pmc13 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(13),0, 0, 0}, {0,0, 0, 0}},
30/* pmc14 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(14),0, 0, 0}, {0,0, 0, 0}},
31/* pmc15 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(15),0, 0, 0}, {0,0, 0, 0}},
32/* pmc16 */ { PFM_REG_NOTIMPL, },
33/* pmc17 */ { PFM_REG_NOTIMPL, },
34/* pmc18 */ { PFM_REG_NOTIMPL, },
35/* pmc19 */ { PFM_REG_NOTIMPL, },
36/* pmc20 */ { PFM_REG_NOTIMPL, },
37/* pmc21 */ { PFM_REG_NOTIMPL, },
38/* pmc22 */ { PFM_REG_NOTIMPL, },
39/* pmc23 */ { PFM_REG_NOTIMPL, },
40/* pmc24 */ { PFM_REG_NOTIMPL, },
41/* pmc25 */ { PFM_REG_NOTIMPL, },
42/* pmc26 */ { PFM_REG_NOTIMPL, },
43/* pmc27 */ { PFM_REG_NOTIMPL, },
44/* pmc28 */ { PFM_REG_NOTIMPL, },
45/* pmc29 */ { PFM_REG_NOTIMPL, },
46/* pmc30 */ { PFM_REG_NOTIMPL, },
47/* pmc31 */ { PFM_REG_NOTIMPL, },
48/* pmc32 */ { PFM_REG_CONFIG, 0, 0x30f01ffffffffff, 0x30f01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
49/* pmc33 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
50/* pmc34 */ { PFM_REG_CONFIG, 0, 0xf01ffffffffff, 0xf01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
51/* pmc35 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
52/* pmc36 */ { PFM_REG_CONFIG, 0, 0xfffffff0, 0xf, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
53/* pmc37 */ { PFM_REG_MONITOR, 4, 0x0, 0x3fff, NULL, pfm_mont_pmc_check, {RDEP_MONT_IEAR, 0, 0, 0}, {0, 0, 0, 0}},
54/* pmc38 */ { PFM_REG_CONFIG, 0, 0xdb6, 0x2492, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
55/* pmc39 */ { PFM_REG_MONITOR, 6, 0x0, 0xffcf, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
56/* pmc40 */ { PFM_REG_MONITOR, 6, 0x2000000, 0xf01cf, NULL, pfm_mont_pmc_check, {RDEP_MONT_DEAR,0, 0, 0}, {0,0, 0, 0}},
57/* pmc41 */ { PFM_REG_CONFIG, 0, 0x00002078fefefefe, 0x1e00018181818, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
58/* pmc42 */ { PFM_REG_MONITOR, 6, 0x0, 0x7ff4f, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
59 { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
60};
61
62static pfm_reg_desc_t pfm_mont_pmd_desc[PMU_MAX_PMDS]={
63/* pmd0 */ { PFM_REG_NOTIMPL, },
64/* pmd1 */ { PFM_REG_NOTIMPL, },
65/* pmd2 */ { PFM_REG_NOTIMPL, },
66/* pmd3 */ { PFM_REG_NOTIMPL, },
67/* pmd4 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(4),0, 0, 0}},
68/* pmd5 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(5),0, 0, 0}},
69/* pmd6 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(6),0, 0, 0}},
70/* pmd7 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(7),0, 0, 0}},
71/* pmd8 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(8),0, 0, 0}},
72/* pmd9 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(9),0, 0, 0}},
73/* pmd10 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(10),0, 0, 0}},
74/* pmd11 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(11),0, 0, 0}},
75/* pmd12 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(12),0, 0, 0}},
76/* pmd13 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(13),0, 0, 0}},
77/* pmd14 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(14),0, 0, 0}},
78/* pmd15 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(15),0, 0, 0}},
79/* pmd16 */ { PFM_REG_NOTIMPL, },
80/* pmd17 */ { PFM_REG_NOTIMPL, },
81/* pmd18 */ { PFM_REG_NOTIMPL, },
82/* pmd19 */ { PFM_REG_NOTIMPL, },
83/* pmd20 */ { PFM_REG_NOTIMPL, },
84/* pmd21 */ { PFM_REG_NOTIMPL, },
85/* pmd22 */ { PFM_REG_NOTIMPL, },
86/* pmd23 */ { PFM_REG_NOTIMPL, },
87/* pmd24 */ { PFM_REG_NOTIMPL, },
88/* pmd25 */ { PFM_REG_NOTIMPL, },
89/* pmd26 */ { PFM_REG_NOTIMPL, },
90/* pmd27 */ { PFM_REG_NOTIMPL, },
91/* pmd28 */ { PFM_REG_NOTIMPL, },
92/* pmd29 */ { PFM_REG_NOTIMPL, },
93/* pmd30 */ { PFM_REG_NOTIMPL, },
94/* pmd31 */ { PFM_REG_NOTIMPL, },
95/* pmd32 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(33)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
96/* pmd33 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
97/* pmd34 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(35),0, 0, 0}, {RDEP(37),0, 0, 0}},
98/* pmd35 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(34),0, 0, 0}, {RDEP(37),0, 0, 0}},
99/* pmd36 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(33),0, 0, 0}, {RDEP(40),0, 0, 0}},
100/* pmd37 */ { PFM_REG_NOTIMPL, },
101/* pmd38 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
102/* pmd39 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
103/* pmd40 */ { PFM_REG_NOTIMPL, },
104/* pmd41 */ { PFM_REG_NOTIMPL, },
105/* pmd42 */ { PFM_REG_NOTIMPL, },
106/* pmd43 */ { PFM_REG_NOTIMPL, },
107/* pmd44 */ { PFM_REG_NOTIMPL, },
108/* pmd45 */ { PFM_REG_NOTIMPL, },
109/* pmd46 */ { PFM_REG_NOTIMPL, },
110/* pmd47 */ { PFM_REG_NOTIMPL, },
111/* pmd48 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
112/* pmd49 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
113/* pmd50 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
114/* pmd51 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
115/* pmd52 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
116/* pmd53 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
117/* pmd54 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
118/* pmd55 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
119/* pmd56 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
120/* pmd57 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
121/* pmd58 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
122/* pmd59 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
123/* pmd60 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
124/* pmd61 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
125/* pmd62 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
126/* pmd63 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
127 { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
128};
129
130/*
131 * PMC reserved fields must have their power-up values preserved
132 */
133static int
134pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
135{
136 unsigned long tmp1, tmp2, ival = *val;
137
138 /* remove reserved areas from user value */
139 tmp1 = ival & PMC_RSVD_MASK(cnum);
140
141 /* get reserved fields values */
142 tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
143
144 *val = tmp1 | tmp2;
145
146 DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
147 cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
148 return 0;
149}
150
151/*
152 * task can be NULL if the context is unloaded
153 */
154static int
155pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
156{
157 int ret = 0;
158 unsigned long val32 = 0, val38 = 0, val41 = 0;
159 unsigned long tmpval;
160 int check_case1 = 0;
161 int is_loaded;
162
163 /* first preserve the reserved fields */
164 pfm_mont_reserved(cnum, val, regs);
165
166 tmpval = *val;
167
168 /* sanity check */
169 if (ctx == NULL) return -EINVAL;
170
171 is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
172
173 /*
174 * we must clear the debug registers if pmc41 has a value which enable
175 * memory pipeline event constraints. In this case we need to clear the
176 * the debug registers if they have not yet been accessed. This is required
177 * to avoid picking stale state.
178 * PMC41 is "active" if:
179 * one of the pmc41.cfg_dtagXX field is different from 0x3
180 * AND
181 * at the corresponding pmc41.en_dbrpXX is set.
182 * AND
183 * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
184 */
185 DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded));
186
187 if (cnum == 41 && is_loaded
188 && (tmpval & 0x1e00000000000) && (tmpval & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
189
190 DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval));
191
192 /* don't mix debug with perfmon */
193 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
194
195 /*
196 * a count of 0 will mark the debug registers if:
197 * AND
198 */
199 ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
200 if (ret) return ret;
201 }
202 /*
203 * we must clear the (instruction) debug registers if:
204 * pmc38.ig_ibrpX is 0 (enabled)
205 * AND
206 * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
207 */
208 if (cnum == 38 && is_loaded && ((tmpval & 0x492UL) != 0x492UL) && ctx->ctx_fl_using_dbreg == 0) {
209
210 DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval));
211
212 /* don't mix debug with perfmon */
213 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
214
215 /*
216 * a count of 0 will mark the debug registers as in use and also
217 * ensure that they are properly cleared.
218 */
219 ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
220 if (ret) return ret;
221
222 }
223 switch(cnum) {
224 case 32: val32 = *val;
225 val38 = ctx->ctx_pmcs[38];
226 val41 = ctx->ctx_pmcs[41];
227 check_case1 = 1;
228 break;
229 case 38: val38 = *val;
230 val32 = ctx->ctx_pmcs[32];
231 val41 = ctx->ctx_pmcs[41];
232 check_case1 = 1;
233 break;
234 case 41: val41 = *val;
235 val32 = ctx->ctx_pmcs[32];
236 val38 = ctx->ctx_pmcs[38];
237 check_case1 = 1;
238 break;
239 }
240 /* check illegal configuration which can produce inconsistencies in tagging
241 * i-side events in L1D and L2 caches
242 */
243 if (check_case1) {
244 ret = (((val41 >> 45) & 0xf) == 0 && ((val32>>57) & 0x1) == 0)
245 && ((((val38>>1) & 0x3) == 0x2 || ((val38>>1) & 0x3) == 0)
246 || (((val38>>4) & 0x3) == 0x2 || ((val38>>4) & 0x3) == 0));
247 if (ret) {
248 DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32));
249 return -EINVAL;
250 }
251 }
252 *val = tmpval;
253 return 0;
254}
255
256/*
257 * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
258 */
259static pmu_config_t pmu_conf_mont={
260 .pmu_name = "Montecito",
261 .pmu_family = 0x20,
262 .flags = PFM_PMU_IRQ_RESEND,
263 .ovfl_val = (1UL << 47) - 1,
264 .pmd_desc = pfm_mont_pmd_desc,
265 .pmc_desc = pfm_mont_pmc_desc,
266 .num_ibrs = 8,
267 .num_dbrs = 8,
268 .use_rr_dbregs = 1 /* debug register are use for range retrictions */
269};
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index e3215ba64ffd..b38b6d213c15 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -635,3 +635,39 @@ mem_init (void)
635 ia32_mem_init(); 635 ia32_mem_init();
636#endif 636#endif
637} 637}
638
639#ifdef CONFIG_MEMORY_HOTPLUG
640void online_page(struct page *page)
641{
642 ClearPageReserved(page);
643 set_page_count(page, 1);
644 __free_page(page);
645 totalram_pages++;
646 num_physpages++;
647}
648
649int add_memory(u64 start, u64 size)
650{
651 pg_data_t *pgdat;
652 struct zone *zone;
653 unsigned long start_pfn = start >> PAGE_SHIFT;
654 unsigned long nr_pages = size >> PAGE_SHIFT;
655 int ret;
656
657 pgdat = NODE_DATA(0);
658
659 zone = pgdat->node_zones + ZONE_NORMAL;
660 ret = __add_pages(zone, start_pfn, nr_pages);
661
662 if (ret)
663 printk("%s: Problem encountered in __add_pages() as ret=%d\n",
664 __FUNCTION__, ret);
665
666 return ret;
667}
668
669int remove_memory(u64 start, u64 size)
670{
671 return -EINVAL;
672}
673#endif
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 30dbc98bf0b3..d27ecdcb6fca 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -454,14 +454,13 @@ static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
454 return 0; 454 return 0;
455} 455}
456 456
457static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) 457static void __devinit
458pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
458{ 459{
459 struct pci_bus_region region; 460 struct pci_bus_region region;
460 int i; 461 int i;
461 int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
462 PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
463 462
464 for (i = 0; i < limit; i++) { 463 for (i = start; i < limit; i++) {
465 if (!dev->resource[i].flags) 464 if (!dev->resource[i].flags)
466 continue; 465 continue;
467 region.start = dev->resource[i].start; 466 region.start = dev->resource[i].start;
@@ -472,6 +471,16 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
472 } 471 }
473} 472}
474 473
474static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
475{
476 pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
477}
478
479static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
480{
481 pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
482}
483
475/* 484/*
476 * Called after each bus is probed, but before its children are examined. 485 * Called after each bus is probed, but before its children are examined.
477 */ 486 */
@@ -482,7 +491,7 @@ pcibios_fixup_bus (struct pci_bus *b)
482 491
483 if (b->self) { 492 if (b->self) {
484 pci_read_bridge_bases(b); 493 pci_read_bridge_bases(b);
485 pcibios_fixup_device_resources(b->self); 494 pcibios_fixup_bridge_resources(b->self);
486 } 495 }
487 list_for_each_entry(dev, &b->devices, bus_list) 496 list_for_each_entry(dev, &b->devices, bus_list)
488 pcibios_fixup_device_resources(dev); 497 pcibios_fixup_device_resources(dev);
diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h
index 4d417c301201..7c88e9a58516 100644
--- a/arch/ia64/sn/include/xtalk/hubdev.h
+++ b/arch/ia64/sn/include/xtalk/hubdev.h
@@ -40,8 +40,8 @@ struct sn_flush_device_common {
40 unsigned long sfdl_force_int_addr; 40 unsigned long sfdl_force_int_addr;
41 unsigned long sfdl_flush_value; 41 unsigned long sfdl_flush_value;
42 volatile unsigned long *sfdl_flush_addr; 42 volatile unsigned long *sfdl_flush_addr;
43 uint32_t sfdl_persistent_busnum; 43 u32 sfdl_persistent_busnum;
44 uint32_t sfdl_persistent_segment; 44 u32 sfdl_persistent_segment;
45 struct pcibus_info *sfdl_pcibus_info; 45 struct pcibus_info *sfdl_pcibus_info;
46}; 46};
47 47
@@ -56,7 +56,7 @@ struct sn_flush_device_kernel {
56 */ 56 */
57struct sn_flush_nasid_entry { 57struct sn_flush_nasid_entry {
58 struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num 58 struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num
59 uint64_t iio_itte[8]; 59 u64 iio_itte[8];
60}; 60};
61 61
62struct hubdev_info { 62struct hubdev_info {
@@ -70,8 +70,8 @@ struct hubdev_info {
70 70
71 void *hdi_nodepda; 71 void *hdi_nodepda;
72 void *hdi_node_vertex; 72 void *hdi_node_vertex;
73 uint32_t max_segment_number; 73 u32 max_segment_number;
74 uint32_t max_pcibus_number; 74 u32 max_pcibus_number;
75}; 75};
76 76
77extern void hubdev_init_node(nodepda_t *, cnodeid_t); 77extern void hubdev_init_node(nodepda_t *, cnodeid_t);
diff --git a/arch/ia64/sn/include/xtalk/xbow.h b/arch/ia64/sn/include/xtalk/xbow.h
index ec56b3432f17..90f37a4133d0 100644
--- a/arch/ia64/sn/include/xtalk/xbow.h
+++ b/arch/ia64/sn/include/xtalk/xbow.h
@@ -3,7 +3,8 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved. 6 * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All Rights
7 * Reserved.
7 */ 8 */
8#ifndef _ASM_IA64_SN_XTALK_XBOW_H 9#ifndef _ASM_IA64_SN_XTALK_XBOW_H
9#define _ASM_IA64_SN_XTALK_XBOW_H 10#define _ASM_IA64_SN_XTALK_XBOW_H
@@ -21,94 +22,94 @@
21 22
22/* Register set for each xbow link */ 23/* Register set for each xbow link */
23typedef volatile struct xb_linkregs_s { 24typedef volatile struct xb_linkregs_s {
24/* 25/*
25 * we access these through synergy unswizzled space, so the address 26 * we access these through synergy unswizzled space, so the address
26 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) 27 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
27 * That's why we put the register first and filler second. 28 * That's why we put the register first and filler second.
28 */ 29 */
29 uint32_t link_ibf; 30 u32 link_ibf;
30 uint32_t filler0; /* filler for proper alignment */ 31 u32 filler0; /* filler for proper alignment */
31 uint32_t link_control; 32 u32 link_control;
32 uint32_t filler1; 33 u32 filler1;
33 uint32_t link_status; 34 u32 link_status;
34 uint32_t filler2; 35 u32 filler2;
35 uint32_t link_arb_upper; 36 u32 link_arb_upper;
36 uint32_t filler3; 37 u32 filler3;
37 uint32_t link_arb_lower; 38 u32 link_arb_lower;
38 uint32_t filler4; 39 u32 filler4;
39 uint32_t link_status_clr; 40 u32 link_status_clr;
40 uint32_t filler5; 41 u32 filler5;
41 uint32_t link_reset; 42 u32 link_reset;
42 uint32_t filler6; 43 u32 filler6;
43 uint32_t link_aux_status; 44 u32 link_aux_status;
44 uint32_t filler7; 45 u32 filler7;
45} xb_linkregs_t; 46} xb_linkregs_t;
46 47
47typedef volatile struct xbow_s { 48typedef volatile struct xbow_s {
48 /* standard widget configuration 0x000000-0x000057 */ 49 /* standard widget configuration 0x000000-0x000057 */
49 struct widget_cfg xb_widget; /* 0x000000 */ 50 struct widget_cfg xb_widget; /* 0x000000 */
50 51
51 /* helper fieldnames for accessing bridge widget */ 52 /* helper fieldnames for accessing bridge widget */
52 53
53#define xb_wid_id xb_widget.w_id 54#define xb_wid_id xb_widget.w_id
54#define xb_wid_stat xb_widget.w_status 55#define xb_wid_stat xb_widget.w_status
55#define xb_wid_err_upper xb_widget.w_err_upper_addr 56#define xb_wid_err_upper xb_widget.w_err_upper_addr
56#define xb_wid_err_lower xb_widget.w_err_lower_addr 57#define xb_wid_err_lower xb_widget.w_err_lower_addr
57#define xb_wid_control xb_widget.w_control 58#define xb_wid_control xb_widget.w_control
58#define xb_wid_req_timeout xb_widget.w_req_timeout 59#define xb_wid_req_timeout xb_widget.w_req_timeout
59#define xb_wid_int_upper xb_widget.w_intdest_upper_addr 60#define xb_wid_int_upper xb_widget.w_intdest_upper_addr
60#define xb_wid_int_lower xb_widget.w_intdest_lower_addr 61#define xb_wid_int_lower xb_widget.w_intdest_lower_addr
61#define xb_wid_err_cmdword xb_widget.w_err_cmd_word 62#define xb_wid_err_cmdword xb_widget.w_err_cmd_word
62#define xb_wid_llp xb_widget.w_llp_cfg 63#define xb_wid_llp xb_widget.w_llp_cfg
63#define xb_wid_stat_clr xb_widget.w_tflush 64#define xb_wid_stat_clr xb_widget.w_tflush
64 65
65/* 66/*
66 * we access these through synergy unswizzled space, so the address 67 * we access these through synergy unswizzled space, so the address
67 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) 68 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
68 * That's why we put the register first and filler second. 69 * That's why we put the register first and filler second.
69 */ 70 */
70 /* xbow-specific widget configuration 0x000058-0x0000FF */ 71 /* xbow-specific widget configuration 0x000058-0x0000FF */
71 uint32_t xb_wid_arb_reload; /* 0x00005C */ 72 u32 xb_wid_arb_reload; /* 0x00005C */
72 uint32_t _pad_000058; 73 u32 _pad_000058;
73 uint32_t xb_perf_ctr_a; /* 0x000064 */ 74 u32 xb_perf_ctr_a; /* 0x000064 */
74 uint32_t _pad_000060; 75 u32 _pad_000060;
75 uint32_t xb_perf_ctr_b; /* 0x00006c */ 76 u32 xb_perf_ctr_b; /* 0x00006c */
76 uint32_t _pad_000068; 77 u32 _pad_000068;
77 uint32_t xb_nic; /* 0x000074 */ 78 u32 xb_nic; /* 0x000074 */
78 uint32_t _pad_000070; 79 u32 _pad_000070;
79 80
80 /* Xbridge only */ 81 /* Xbridge only */
81 uint32_t xb_w0_rst_fnc; /* 0x00007C */ 82 u32 xb_w0_rst_fnc; /* 0x00007C */
82 uint32_t _pad_000078; 83 u32 _pad_000078;
83 uint32_t xb_l8_rst_fnc; /* 0x000084 */ 84 u32 xb_l8_rst_fnc; /* 0x000084 */
84 uint32_t _pad_000080; 85 u32 _pad_000080;
85 uint32_t xb_l9_rst_fnc; /* 0x00008c */ 86 u32 xb_l9_rst_fnc; /* 0x00008c */
86 uint32_t _pad_000088; 87 u32 _pad_000088;
87 uint32_t xb_la_rst_fnc; /* 0x000094 */ 88 u32 xb_la_rst_fnc; /* 0x000094 */
88 uint32_t _pad_000090; 89 u32 _pad_000090;
89 uint32_t xb_lb_rst_fnc; /* 0x00009c */ 90 u32 xb_lb_rst_fnc; /* 0x00009c */
90 uint32_t _pad_000098; 91 u32 _pad_000098;
91 uint32_t xb_lc_rst_fnc; /* 0x0000a4 */ 92 u32 xb_lc_rst_fnc; /* 0x0000a4 */
92 uint32_t _pad_0000a0; 93 u32 _pad_0000a0;
93 uint32_t xb_ld_rst_fnc; /* 0x0000ac */ 94 u32 xb_ld_rst_fnc; /* 0x0000ac */
94 uint32_t _pad_0000a8; 95 u32 _pad_0000a8;
95 uint32_t xb_le_rst_fnc; /* 0x0000b4 */ 96 u32 xb_le_rst_fnc; /* 0x0000b4 */
96 uint32_t _pad_0000b0; 97 u32 _pad_0000b0;
97 uint32_t xb_lf_rst_fnc; /* 0x0000bc */ 98 u32 xb_lf_rst_fnc; /* 0x0000bc */
98 uint32_t _pad_0000b8; 99 u32 _pad_0000b8;
99 uint32_t xb_lock; /* 0x0000c4 */ 100 u32 xb_lock; /* 0x0000c4 */
100 uint32_t _pad_0000c0; 101 u32 _pad_0000c0;
101 uint32_t xb_lock_clr; /* 0x0000cc */ 102 u32 xb_lock_clr; /* 0x0000cc */
102 uint32_t _pad_0000c8; 103 u32 _pad_0000c8;
103 /* end of Xbridge only */ 104 /* end of Xbridge only */
104 uint32_t _pad_0000d0[12]; 105 u32 _pad_0000d0[12];
105 106
106 /* Link Specific Registers, port 8..15 0x000100-0x000300 */ 107 /* Link Specific Registers, port 8..15 0x000100-0x000300 */
107 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS]; 108 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
108#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
109
110} xbow_t; 109} xbow_t;
111 110
111#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
112
112#define XB_FLAGS_EXISTS 0x1 /* device exists */ 113#define XB_FLAGS_EXISTS 0x1 /* device exists */
113#define XB_FLAGS_MASTER 0x2 114#define XB_FLAGS_MASTER 0x2
114#define XB_FLAGS_SLAVE 0x0 115#define XB_FLAGS_SLAVE 0x0
@@ -160,7 +161,7 @@ typedef volatile struct xbow_s {
160/* End of Xbridge only */ 161/* End of Xbridge only */
161 162
162/* used only in ide, but defined here within the reserved portion */ 163/* used only in ide, but defined here within the reserved portion */
163/* of the widget0 address space (before 0xf4) */ 164/* of the widget0 address space (before 0xf4) */
164#define XBOW_WID_UNDEF 0xe4 165#define XBOW_WID_UNDEF 0xe4
165 166
166/* xbow link register set base, legal value for x is 0x8..0xf */ 167/* xbow link register set base, legal value for x is 0x8..0xf */
@@ -179,29 +180,37 @@ typedef volatile struct xbow_s {
179 180
180/* link_control(x) */ 181/* link_control(x) */
181#define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */ 182#define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
182 /* reserved: 0x40000000 */ 183/* reserved: 0x40000000 */
183#define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */ 184#define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
184#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */ 185#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer
185#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */ 186 level */
186#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */ 187#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8
187#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */ 188 bit mode */
188#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */ 189#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP
189#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */ 190 packet */
190#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */ 191#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit
191 /* reserved: 0x0000fe00 */ 192 mask */
193#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit
194 shift */
195#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination
196 */
197#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input
198 buffer */
199/* reserved: 0x0000fe00 */
192#define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */ 200#define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
193#define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */ 201#define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
194#define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */ 202#define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
195#define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */ 203#define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
196#define XB_CTRL_RCV_IE 0x00000010 /* receive */ 204#define XB_CTRL_RCV_IE 0x00000010 /* receive */
197#define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */ 205#define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
198 /* reserved: 0x00000004 */ 206/* reserved: 0x00000004 */
199#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */ 207#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request
208 timeout */
200#define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */ 209#define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
201 210
202/* link_status(x) */ 211/* link_status(x) */
203#define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE 212#define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
204 /* reserved: 0x7ff80000 */ 213/* reserved: 0x7ff80000 */
205#define XB_STAT_MULTI_ERR 0x00040000 /* multi error */ 214#define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
206#define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE 215#define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
207#define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE 216#define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
@@ -211,7 +220,7 @@ typedef volatile struct xbow_s {
211#define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE 220#define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
212#define XB_STAT_RCV_ERR XB_CTRL_RCV_IE 221#define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
213#define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE 222#define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
214 /* reserved: 0x00000004 */ 223/* reserved: 0x00000004 */
215#define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE 224#define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
216#define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE 225#define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
217 226
@@ -222,7 +231,7 @@ typedef volatile struct xbow_s {
222#define XB_AUX_LINKFAIL_RST_BAD 0x00000040 231#define XB_AUX_LINKFAIL_RST_BAD 0x00000040
223#define XB_AUX_STAT_PRESENT 0x00000020 232#define XB_AUX_STAT_PRESENT 0x00000020
224#define XB_AUX_STAT_PORT_WIDTH 0x00000010 233#define XB_AUX_STAT_PORT_WIDTH 0x00000010
225 /* reserved: 0x0000000f */ 234/* reserved: 0x0000000f */
226 235
227/* 236/*
228 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper 237 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
@@ -238,7 +247,8 @@ typedef volatile struct xbow_s {
238/* XBOW_WID_STAT */ 247/* XBOW_WID_STAT */
239#define XB_WID_STAT_LINK_INTR_SHFT (24) 248#define XB_WID_STAT_LINK_INTR_SHFT (24)
240#define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT) 249#define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
241#define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT)) 250#define XB_WID_STAT_LINK_INTR(x) \
251 (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
242#define XB_WID_STAT_WIDGET0_INTR 0x00800000 252#define XB_WID_STAT_WIDGET0_INTR 0x00800000
243#define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */ 253#define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
244#define XB_WID_STAT_REG_ACC_ERR 0x00000020 254#define XB_WID_STAT_REG_ACC_ERR 0x00000020
@@ -264,7 +274,7 @@ typedef volatile struct xbow_s {
264#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ 274#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
265#define XBOW_WIDGET_MFGR_NUM 0x0 275#define XBOW_WIDGET_MFGR_NUM 0x0
266#define XXBOW_WIDGET_MFGR_NUM 0x0 276#define XXBOW_WIDGET_MFGR_NUM 0x0
267#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ 277#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */
268 278
269#define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ 279#define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
270#define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ 280#define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
@@ -279,13 +289,13 @@ typedef volatile struct xbow_s {
279#define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ 289#define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
280 290
281#define IS_XBRIDGE_XBOW(wid) \ 291#define IS_XBRIDGE_XBOW(wid) \
282 (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ 292 (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
283 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) 293 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
284 294
285#define IS_PIC_XBOW(wid) \ 295#define IS_PIC_XBOW(wid) \
286 (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ 296 (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
287 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) 297 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
288 298
289#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) 299#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
290 300
291#endif /* _ASM_IA64_SN_XTALK_XBOW_H */ 301#endif /* _ASM_IA64_SN_XTALK_XBOW_H */
diff --git a/arch/ia64/sn/include/xtalk/xwidgetdev.h b/arch/ia64/sn/include/xtalk/xwidgetdev.h
index c5f4bc5cc033..2800eda0fd68 100644
--- a/arch/ia64/sn/include/xtalk/xwidgetdev.h
+++ b/arch/ia64/sn/include/xtalk/xwidgetdev.h
@@ -25,28 +25,28 @@
25 25
26/* widget configuration registers */ 26/* widget configuration registers */
27struct widget_cfg{ 27struct widget_cfg{
28 uint32_t w_id; /* 0x04 */ 28 u32 w_id; /* 0x04 */
29 uint32_t w_pad_0; /* 0x00 */ 29 u32 w_pad_0; /* 0x00 */
30 uint32_t w_status; /* 0x0c */ 30 u32 w_status; /* 0x0c */
31 uint32_t w_pad_1; /* 0x08 */ 31 u32 w_pad_1; /* 0x08 */
32 uint32_t w_err_upper_addr; /* 0x14 */ 32 u32 w_err_upper_addr; /* 0x14 */
33 uint32_t w_pad_2; /* 0x10 */ 33 u32 w_pad_2; /* 0x10 */
34 uint32_t w_err_lower_addr; /* 0x1c */ 34 u32 w_err_lower_addr; /* 0x1c */
35 uint32_t w_pad_3; /* 0x18 */ 35 u32 w_pad_3; /* 0x18 */
36 uint32_t w_control; /* 0x24 */ 36 u32 w_control; /* 0x24 */
37 uint32_t w_pad_4; /* 0x20 */ 37 u32 w_pad_4; /* 0x20 */
38 uint32_t w_req_timeout; /* 0x2c */ 38 u32 w_req_timeout; /* 0x2c */
39 uint32_t w_pad_5; /* 0x28 */ 39 u32 w_pad_5; /* 0x28 */
40 uint32_t w_intdest_upper_addr; /* 0x34 */ 40 u32 w_intdest_upper_addr; /* 0x34 */
41 uint32_t w_pad_6; /* 0x30 */ 41 u32 w_pad_6; /* 0x30 */
42 uint32_t w_intdest_lower_addr; /* 0x3c */ 42 u32 w_intdest_lower_addr; /* 0x3c */
43 uint32_t w_pad_7; /* 0x38 */ 43 u32 w_pad_7; /* 0x38 */
44 uint32_t w_err_cmd_word; /* 0x44 */ 44 u32 w_err_cmd_word; /* 0x44 */
45 uint32_t w_pad_8; /* 0x40 */ 45 u32 w_pad_8; /* 0x40 */
46 uint32_t w_llp_cfg; /* 0x4c */ 46 u32 w_llp_cfg; /* 0x4c */
47 uint32_t w_pad_9; /* 0x48 */ 47 u32 w_pad_9; /* 0x48 */
48 uint32_t w_tflush; /* 0x54 */ 48 u32 w_tflush; /* 0x54 */
49 uint32_t w_pad_10; /* 0x50 */ 49 u32 w_pad_10; /* 0x50 */
50}; 50};
51 51
52/* 52/*
@@ -63,7 +63,7 @@ struct xwidget_info{
63 struct xwidget_hwid xwi_hwid; /* Widget Identification */ 63 struct xwidget_hwid xwi_hwid; /* Widget Identification */
64 char xwi_masterxid; /* Hub's Widget Port Number */ 64 char xwi_masterxid; /* Hub's Widget Port Number */
65 void *xwi_hubinfo; /* Hub's provider private info */ 65 void *xwi_hubinfo; /* Hub's provider private info */
66 uint64_t *xwi_hub_provider; /* prom provider functions */ 66 u64 *xwi_hub_provider; /* prom provider functions */
67 void *xwi_vertex; 67 void *xwi_vertex;
68}; 68};
69 69
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 258d9d7aff98..233d55115d33 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -132,8 +132,8 @@ static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
132 * Retrieve the pci device information given the bus and device|function number. 132 * Retrieve the pci device information given the bus and device|function number.
133 */ 133 */
134static inline u64 134static inline u64
135sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev, 135sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
136 u64 sn_irq_info) 136 u64 sn_irq_info)
137{ 137{
138 struct ia64_sal_retval ret_stuff; 138 struct ia64_sal_retval ret_stuff;
139 ret_stuff.status = 0; 139 ret_stuff.status = 0;
@@ -141,7 +141,7 @@ sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
141 141
142 SAL_CALL_NOLOCK(ret_stuff, 142 SAL_CALL_NOLOCK(ret_stuff,
143 (u64) SN_SAL_IOIF_GET_PCIDEV_INFO, 143 (u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
144 (u64) segment, (u64) bus_number, (u64) devfn, 144 (u64) segment, (u64) bus_number, (u64) devfn,
145 (u64) pci_dev, 145 (u64) pci_dev,
146 sn_irq_info, 0, 0); 146 sn_irq_info, 0, 0);
147 return ret_stuff.v0; 147 return ret_stuff.v0;
@@ -268,7 +268,7 @@ static void sn_fixup_ionodes(void)
268 */ 268 */
269static void 269static void
270sn_pci_window_fixup(struct pci_dev *dev, unsigned int count, 270sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
271 int64_t * pci_addrs) 271 s64 * pci_addrs)
272{ 272{
273 struct pci_controller *controller = PCI_CONTROLLER(dev->bus); 273 struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
274 unsigned int i; 274 unsigned int i;
@@ -328,7 +328,7 @@ void sn_pci_fixup_slot(struct pci_dev *dev)
328 struct pci_bus *host_pci_bus; 328 struct pci_bus *host_pci_bus;
329 struct pci_dev *host_pci_dev; 329 struct pci_dev *host_pci_dev;
330 struct pcidev_info *pcidev_info; 330 struct pcidev_info *pcidev_info;
331 int64_t pci_addrs[PCI_ROM_RESOURCE + 1]; 331 s64 pci_addrs[PCI_ROM_RESOURCE + 1];
332 struct sn_irq_info *sn_irq_info; 332 struct sn_irq_info *sn_irq_info;
333 unsigned long size; 333 unsigned long size;
334 unsigned int bus_no, devfn; 334 unsigned int bus_no, devfn;
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index 01d18b7b5bb3..ec37084bdc17 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -28,7 +28,7 @@ extern int sn_ioif_inited;
28static struct list_head **sn_irq_lh; 28static struct list_head **sn_irq_lh;
29static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */ 29static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */
30 30
31static inline uint64_t sn_intr_alloc(nasid_t local_nasid, int local_widget, 31static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
32 u64 sn_irq_info, 32 u64 sn_irq_info,
33 int req_irq, nasid_t req_nasid, 33 int req_irq, nasid_t req_nasid,
34 int req_slice) 34 int req_slice)
@@ -123,7 +123,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
123 123
124 list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, 124 list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
125 sn_irq_lh[irq], list) { 125 sn_irq_lh[irq], list) {
126 uint64_t bridge; 126 u64 bridge;
127 int local_widget, status; 127 int local_widget, status;
128 nasid_t local_nasid; 128 nasid_t local_nasid;
129 struct sn_irq_info *new_irq_info; 129 struct sn_irq_info *new_irq_info;
@@ -134,7 +134,7 @@ static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
134 break; 134 break;
135 memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); 135 memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
136 136
137 bridge = (uint64_t) new_irq_info->irq_bridge; 137 bridge = (u64) new_irq_info->irq_bridge;
138 if (!bridge) { 138 if (!bridge) {
139 kfree(new_irq_info); 139 kfree(new_irq_info);
140 break; /* irq is not a device interrupt */ 140 break; /* irq is not a device interrupt */
@@ -349,10 +349,10 @@ static void force_interrupt(int irq)
349 */ 349 */
350static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) 350static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
351{ 351{
352 uint64_t regval; 352 u64 regval;
353 int irr_reg_num; 353 int irr_reg_num;
354 int irr_bit; 354 int irr_bit;
355 uint64_t irr_reg; 355 u64 irr_reg;
356 struct pcidev_info *pcidev_info; 356 struct pcidev_info *pcidev_info;
357 struct pcibus_info *pcibus_info; 357 struct pcibus_info *pcibus_info;
358 358
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index 6a7939b16a1c..d263d3e8fbb9 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -245,7 +245,7 @@ static int cx_device_reload(struct cx_dev *cx_dev)
245 cx_dev->bt); 245 cx_dev->bt);
246} 246}
247 247
248static inline uint64_t tiocx_intr_alloc(nasid_t nasid, int widget, 248static inline u64 tiocx_intr_alloc(nasid_t nasid, int widget,
249 u64 sn_irq_info, 249 u64 sn_irq_info,
250 int req_irq, nasid_t req_nasid, 250 int req_irq, nasid_t req_nasid,
251 int req_slice) 251 int req_slice)
@@ -302,7 +302,7 @@ struct sn_irq_info *tiocx_irq_alloc(nasid_t nasid, int widget, int irq,
302 302
303void tiocx_irq_free(struct sn_irq_info *sn_irq_info) 303void tiocx_irq_free(struct sn_irq_info *sn_irq_info)
304{ 304{
305 uint64_t bridge = (uint64_t) sn_irq_info->irq_bridge; 305 u64 bridge = (u64) sn_irq_info->irq_bridge;
306 nasid_t nasid = NASID_GET(bridge); 306 nasid_t nasid = NASID_GET(bridge);
307 int widget; 307 int widget;
308 308
@@ -313,12 +313,12 @@ void tiocx_irq_free(struct sn_irq_info *sn_irq_info)
313 } 313 }
314} 314}
315 315
316uint64_t tiocx_dma_addr(uint64_t addr) 316u64 tiocx_dma_addr(u64 addr)
317{ 317{
318 return PHYS_TO_TIODMA(addr); 318 return PHYS_TO_TIODMA(addr);
319} 319}
320 320
321uint64_t tiocx_swin_base(int nasid) 321u64 tiocx_swin_base(int nasid)
322{ 322{
323 return TIO_SWIN_BASE(nasid, TIOCX_CORELET); 323 return TIO_SWIN_BASE(nasid, TIOCX_CORELET);
324} 324}
@@ -335,8 +335,8 @@ EXPORT_SYMBOL(tiocx_swin_base);
335 335
336static void tio_conveyor_set(nasid_t nasid, int enable_flag) 336static void tio_conveyor_set(nasid_t nasid, int enable_flag)
337{ 337{
338 uint64_t ice_frz; 338 u64 ice_frz;
339 uint64_t disable_cb = (1ull << 61); 339 u64 disable_cb = (1ull << 61);
340 340
341 if (!(nasid & 1)) 341 if (!(nasid & 1))
342 return; 342 return;
@@ -388,7 +388,7 @@ static int is_fpga_tio(int nasid, int *bt)
388 388
389static int bitstream_loaded(nasid_t nasid) 389static int bitstream_loaded(nasid_t nasid)
390{ 390{
391 uint64_t cx_credits; 391 u64 cx_credits;
392 392
393 cx_credits = REMOTE_HUB_L(nasid, TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3); 393 cx_credits = REMOTE_HUB_L(nasid, TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3);
394 cx_credits &= TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK; 394 cx_credits &= TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK;
@@ -404,14 +404,14 @@ static int tiocx_reload(struct cx_dev *cx_dev)
404 nasid_t nasid = cx_dev->cx_id.nasid; 404 nasid_t nasid = cx_dev->cx_id.nasid;
405 405
406 if (bitstream_loaded(nasid)) { 406 if (bitstream_loaded(nasid)) {
407 uint64_t cx_id; 407 u64 cx_id;
408 int rv; 408 int rv;
409 409
410 rv = ia64_sn_sysctl_tio_clock_reset(nasid); 410 rv = ia64_sn_sysctl_tio_clock_reset(nasid);
411 if (rv) { 411 if (rv) {
412 printk(KERN_ALERT "CX port JTAG reset failed.\n"); 412 printk(KERN_ALERT "CX port JTAG reset failed.\n");
413 } else { 413 } else {
414 cx_id = *(volatile uint64_t *) 414 cx_id = *(volatile u64 *)
415 (TIO_SWIN_BASE(nasid, TIOCX_CORELET) + 415 (TIO_SWIN_BASE(nasid, TIOCX_CORELET) +
416 WIDGET_ID); 416 WIDGET_ID);
417 part_num = XWIDGET_PART_NUM(cx_id); 417 part_num = XWIDGET_PART_NUM(cx_id);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
index d1647b863e61..aa3fa5152a32 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
@@ -18,10 +18,10 @@ int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */
18 * mark_ate: Mark the ate as either free or inuse. 18 * mark_ate: Mark the ate as either free or inuse.
19 */ 19 */
20static void mark_ate(struct ate_resource *ate_resource, int start, int number, 20static void mark_ate(struct ate_resource *ate_resource, int start, int number,
21 uint64_t value) 21 u64 value)
22{ 22{
23 23
24 uint64_t *ate = ate_resource->ate; 24 u64 *ate = ate_resource->ate;
25 int index; 25 int index;
26 int length = 0; 26 int length = 0;
27 27
@@ -38,7 +38,7 @@ static int find_free_ate(struct ate_resource *ate_resource, int start,
38 int count) 38 int count)
39{ 39{
40 40
41 uint64_t *ate = ate_resource->ate; 41 u64 *ate = ate_resource->ate;
42 int index; 42 int index;
43 int start_free; 43 int start_free;
44 44
@@ -119,7 +119,7 @@ static inline int alloc_ate_resource(struct ate_resource *ate_resource,
119int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count) 119int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
120{ 120{
121 int status = 0; 121 int status = 0;
122 uint64_t flag; 122 u64 flag;
123 123
124 flag = pcibr_lock(pcibus_info); 124 flag = pcibr_lock(pcibus_info);
125 status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count); 125 status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count);
@@ -139,7 +139,7 @@ int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
139 * Setup an Address Translation Entry as specified. Use either the Bridge 139 * Setup an Address Translation Entry as specified. Use either the Bridge
140 * internal maps or the external map RAM, as appropriate. 140 * internal maps or the external map RAM, as appropriate.
141 */ 141 */
142static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info, 142static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info,
143 int ate_index) 143 int ate_index)
144{ 144{
145 if (ate_index < pcibus_info->pbi_int_ate_size) { 145 if (ate_index < pcibus_info->pbi_int_ate_size) {
@@ -153,7 +153,7 @@ static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info,
153 */ 153 */
154void inline 154void inline
155ate_write(struct pcibus_info *pcibus_info, int ate_index, int count, 155ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
156 volatile uint64_t ate) 156 volatile u64 ate)
157{ 157{
158 while (count-- > 0) { 158 while (count-- > 0) {
159 if (ate_index < pcibus_info->pbi_int_ate_size) { 159 if (ate_index < pcibus_info->pbi_int_ate_size) {
@@ -171,9 +171,9 @@ ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
171void pcibr_ate_free(struct pcibus_info *pcibus_info, int index) 171void pcibr_ate_free(struct pcibus_info *pcibus_info, int index)
172{ 172{
173 173
174 volatile uint64_t ate; 174 volatile u64 ate;
175 int count; 175 int count;
176 uint64_t flags; 176 u64 flags;
177 177
178 if (pcibr_invalidate_ate) { 178 if (pcibr_invalidate_ate) {
179 /* For debugging purposes, clear the valid bit in the ATE */ 179 /* For debugging purposes, clear the valid bit in the ATE */
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index e68332d93171..54ce5b7ceed2 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -41,21 +41,21 @@ extern int sn_ioif_inited;
41 41
42static dma_addr_t 42static dma_addr_t
43pcibr_dmamap_ate32(struct pcidev_info *info, 43pcibr_dmamap_ate32(struct pcidev_info *info,
44 uint64_t paddr, size_t req_size, uint64_t flags) 44 u64 paddr, size_t req_size, u64 flags)
45{ 45{
46 46
47 struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; 47 struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
48 struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info-> 48 struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
49 pdi_pcibus_info; 49 pdi_pcibus_info;
50 uint8_t internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info-> 50 u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
51 pdi_linux_pcidev->devfn)) - 1; 51 pdi_linux_pcidev->devfn)) - 1;
52 int ate_count; 52 int ate_count;
53 int ate_index; 53 int ate_index;
54 uint64_t ate_flags = flags | PCI32_ATE_V; 54 u64 ate_flags = flags | PCI32_ATE_V;
55 uint64_t ate; 55 u64 ate;
56 uint64_t pci_addr; 56 u64 pci_addr;
57 uint64_t xio_addr; 57 u64 xio_addr;
58 uint64_t offset; 58 u64 offset;
59 59
60 /* PIC in PCI-X mode does not supports 32bit PageMap mode */ 60 /* PIC in PCI-X mode does not supports 32bit PageMap mode */
61 if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) { 61 if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
@@ -109,12 +109,12 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
109} 109}
110 110
111static dma_addr_t 111static dma_addr_t
112pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr, 112pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
113 uint64_t dma_attributes) 113 u64 dma_attributes)
114{ 114{
115 struct pcibus_info *pcibus_info = (struct pcibus_info *) 115 struct pcibus_info *pcibus_info = (struct pcibus_info *)
116 ((info->pdi_host_pcidev_info)->pdi_pcibus_info); 116 ((info->pdi_host_pcidev_info)->pdi_pcibus_info);
117 uint64_t pci_addr; 117 u64 pci_addr;
118 118
119 /* Translate to Crosstalk View of Physical Address */ 119 /* Translate to Crosstalk View of Physical Address */
120 pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : 120 pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
@@ -127,7 +127,7 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
127 /* Handle Bridge Chipset differences */ 127 /* Handle Bridge Chipset differences */
128 if (IS_PIC_SOFT(pcibus_info)) { 128 if (IS_PIC_SOFT(pcibus_info)) {
129 pci_addr |= 129 pci_addr |=
130 ((uint64_t) pcibus_info-> 130 ((u64) pcibus_info->
131 pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT); 131 pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
132 } else 132 } else
133 pci_addr |= TIOCP_PCI64_CMDTYPE_MEM; 133 pci_addr |= TIOCP_PCI64_CMDTYPE_MEM;
@@ -142,17 +142,17 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
142 142
143static dma_addr_t 143static dma_addr_t
144pcibr_dmatrans_direct32(struct pcidev_info * info, 144pcibr_dmatrans_direct32(struct pcidev_info * info,
145 uint64_t paddr, size_t req_size, uint64_t flags) 145 u64 paddr, size_t req_size, u64 flags)
146{ 146{
147 147
148 struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; 148 struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
149 struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info-> 149 struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
150 pdi_pcibus_info; 150 pdi_pcibus_info;
151 uint64_t xio_addr; 151 u64 xio_addr;
152 152
153 uint64_t xio_base; 153 u64 xio_base;
154 uint64_t offset; 154 u64 offset;
155 uint64_t endoff; 155 u64 endoff;
156 156
157 if (IS_PCIX(pcibus_info)) { 157 if (IS_PCIX(pcibus_info)) {
158 return 0; 158 return 0;
@@ -209,14 +209,14 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
209 * unlike the PIC Device(x) Write Request Buffer Flush register. 209 * unlike the PIC Device(x) Write Request Buffer Flush register.
210 */ 210 */
211 211
212void sn_dma_flush(uint64_t addr) 212void sn_dma_flush(u64 addr)
213{ 213{
214 nasid_t nasid; 214 nasid_t nasid;
215 int is_tio; 215 int is_tio;
216 int wid_num; 216 int wid_num;
217 int i, j; 217 int i, j;
218 uint64_t flags; 218 u64 flags;
219 uint64_t itte; 219 u64 itte;
220 struct hubdev_info *hubinfo; 220 struct hubdev_info *hubinfo;
221 volatile struct sn_flush_device_kernel *p; 221 volatile struct sn_flush_device_kernel *p;
222 volatile struct sn_flush_device_common *common; 222 volatile struct sn_flush_device_common *common;
@@ -299,8 +299,8 @@ void sn_dma_flush(uint64_t addr)
299 * If CE ever needs the sn_dma_flush mechanism, we will have 299 * If CE ever needs the sn_dma_flush mechanism, we will have
300 * to account for that here and in tioce_bus_fixup(). 300 * to account for that here and in tioce_bus_fixup().
301 */ 301 */
302 uint32_t tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID)); 302 u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
303 uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id); 303 u32 revnum = XWIDGET_PART_REV_NUM(tio_id);
304 304
305 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */ 305 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
306 if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) { 306 if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
@@ -315,7 +315,7 @@ void sn_dma_flush(uint64_t addr)
315 *common->sfdl_flush_addr = 0; 315 *common->sfdl_flush_addr = 0;
316 316
317 /* force an interrupt. */ 317 /* force an interrupt. */
318 *(volatile uint32_t *)(common->sfdl_force_int_addr) = 1; 318 *(volatile u32 *)(common->sfdl_force_int_addr) = 1;
319 319
320 /* wait for the interrupt to come back. */ 320 /* wait for the interrupt to come back. */
321 while (*(common->sfdl_flush_addr) != 0x10f) 321 while (*(common->sfdl_flush_addr) != 0x10f)
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index e328e948175d..77a1262751d3 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -23,7 +23,7 @@ int
23sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp) 23sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
24{ 24{
25 struct ia64_sal_retval ret_stuff; 25 struct ia64_sal_retval ret_stuff;
26 uint64_t busnum; 26 u64 busnum;
27 27
28 ret_stuff.status = 0; 28 ret_stuff.status = 0;
29 ret_stuff.v0 = 0; 29 ret_stuff.v0 = 0;
@@ -40,7 +40,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
40 void *resp) 40 void *resp)
41{ 41{
42 struct ia64_sal_retval ret_stuff; 42 struct ia64_sal_retval ret_stuff;
43 uint64_t busnum; 43 u64 busnum;
44 44
45 ret_stuff.status = 0; 45 ret_stuff.status = 0;
46 ret_stuff.v0 = 0; 46 ret_stuff.v0 = 0;
@@ -56,7 +56,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
56static int sal_pcibr_error_interrupt(struct pcibus_info *soft) 56static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
57{ 57{
58 struct ia64_sal_retval ret_stuff; 58 struct ia64_sal_retval ret_stuff;
59 uint64_t busnum; 59 u64 busnum;
60 int segment; 60 int segment;
61 ret_stuff.status = 0; 61 ret_stuff.status = 0;
62 ret_stuff.v0 = 0; 62 ret_stuff.v0 = 0;
@@ -159,9 +159,9 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
159 /* Setup the PMU ATE map */ 159 /* Setup the PMU ATE map */
160 soft->pbi_int_ate_resource.lowest_free_index = 0; 160 soft->pbi_int_ate_resource.lowest_free_index = 0;
161 soft->pbi_int_ate_resource.ate = 161 soft->pbi_int_ate_resource.ate =
162 kmalloc(soft->pbi_int_ate_size * sizeof(uint64_t), GFP_KERNEL); 162 kmalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
163 memset(soft->pbi_int_ate_resource.ate, 0, 163 memset(soft->pbi_int_ate_resource.ate, 0,
164 (soft->pbi_int_ate_size * sizeof(uint64_t))); 164 (soft->pbi_int_ate_size * sizeof(u64)));
165 165
166 if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) { 166 if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
167 /* TIO PCI Bridge: find nearest node with CPUs */ 167 /* TIO PCI Bridge: find nearest node with CPUs */
@@ -203,7 +203,7 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
203 struct pcidev_info *pcidev_info; 203 struct pcidev_info *pcidev_info;
204 struct pcibus_info *pcibus_info; 204 struct pcibus_info *pcibus_info;
205 int bit = sn_irq_info->irq_int_bit; 205 int bit = sn_irq_info->irq_int_bit;
206 uint64_t xtalk_addr = sn_irq_info->irq_xtalkaddr; 206 u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
207 207
208 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 208 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
209 if (pcidev_info) { 209 if (pcidev_info) {
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 79fdb91d7259..8b8bbd51d433 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -23,7 +23,7 @@ union br_ptr {
23/* 23/*
24 * Control Register Access -- Read/Write 0000_0020 24 * Control Register Access -- Read/Write 0000_0020
25 */ 25 */
26void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) 26void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
27{ 27{
28 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 28 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
29 29
@@ -43,7 +43,7 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
43 } 43 }
44} 44}
45 45
46void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) 46void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
47{ 47{
48 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 48 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
49 49
@@ -66,10 +66,10 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
66/* 66/*
67 * PCI/PCIX Target Flush Register Access -- Read Only 0000_0050 67 * PCI/PCIX Target Flush Register Access -- Read Only 0000_0050
68 */ 68 */
69uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) 69u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
70{ 70{
71 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 71 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
72 uint64_t ret = 0; 72 u64 ret = 0;
73 73
74 if (pcibus_info) { 74 if (pcibus_info) {
75 switch (pcibus_info->pbi_bridge_type) { 75 switch (pcibus_info->pbi_bridge_type) {
@@ -96,10 +96,10 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
96/* 96/*
97 * Interrupt Status Register Access -- Read Only 0000_0100 97 * Interrupt Status Register Access -- Read Only 0000_0100
98 */ 98 */
99uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) 99u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
100{ 100{
101 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 101 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
102 uint64_t ret = 0; 102 u64 ret = 0;
103 103
104 if (pcibus_info) { 104 if (pcibus_info) {
105 switch (pcibus_info->pbi_bridge_type) { 105 switch (pcibus_info->pbi_bridge_type) {
@@ -121,7 +121,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
121/* 121/*
122 * Interrupt Enable Register Access -- Read/Write 0000_0108 122 * Interrupt Enable Register Access -- Read/Write 0000_0108
123 */ 123 */
124void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) 124void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
125{ 125{
126 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 126 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
127 127
@@ -141,7 +141,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
141 } 141 }
142} 142}
143 143
144void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) 144void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
145{ 145{
146 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 146 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
147 147
@@ -165,7 +165,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
165 * Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168 165 * Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168
166 */ 166 */
167void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, 167void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
168 uint64_t addr) 168 u64 addr)
169{ 169{
170 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 170 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
171 171
@@ -217,10 +217,10 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
217/* 217/*
218 * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258 218 * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
219 */ 219 */
220uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) 220u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
221{ 221{
222 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 222 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
223 uint64_t ret = 0; 223 u64 ret = 0;
224 224
225 if (pcibus_info) { 225 if (pcibus_info) {
226 switch (pcibus_info->pbi_bridge_type) { 226 switch (pcibus_info->pbi_bridge_type) {
@@ -242,7 +242,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
242} 242}
243 243
244void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, 244void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
245 uint64_t val) 245 u64 val)
246{ 246{
247 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 247 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
248 248
@@ -262,10 +262,10 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
262 } 262 }
263} 263}
264 264
265uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) 265u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
266{ 266{
267 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; 267 union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
268 uint64_t __iomem *ret = NULL; 268 u64 __iomem *ret = NULL;
269 269
270 if (pcibus_info) { 270 if (pcibus_info) {
271 switch (pcibus_info->pbi_bridge_type) { 271 switch (pcibus_info->pbi_bridge_type) {
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 27aa1842dacc..7571a4025529 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -16,7 +16,7 @@
16#include <asm/sn/pcibus_provider_defs.h> 16#include <asm/sn/pcibus_provider_defs.h>
17#include <asm/sn/tioca_provider.h> 17#include <asm/sn/tioca_provider.h>
18 18
19uint32_t tioca_gart_found; 19u32 tioca_gart_found;
20EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */ 20EXPORT_SYMBOL(tioca_gart_found); /* used by agp-sgi */
21 21
22LIST_HEAD(tioca_list); 22LIST_HEAD(tioca_list);
@@ -34,8 +34,8 @@ static int tioca_gart_init(struct tioca_kernel *);
34static int 34static int
35tioca_gart_init(struct tioca_kernel *tioca_kern) 35tioca_gart_init(struct tioca_kernel *tioca_kern)
36{ 36{
37 uint64_t ap_reg; 37 u64 ap_reg;
38 uint64_t offset; 38 u64 offset;
39 struct page *tmp; 39 struct page *tmp;
40 struct tioca_common *tioca_common; 40 struct tioca_common *tioca_common;
41 struct tioca __iomem *ca_base; 41 struct tioca __iomem *ca_base;
@@ -214,7 +214,7 @@ void
214tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) 214tioca_fastwrite_enable(struct tioca_kernel *tioca_kern)
215{ 215{
216 int cap_ptr; 216 int cap_ptr;
217 uint32_t reg; 217 u32 reg;
218 struct tioca __iomem *tioca_base; 218 struct tioca __iomem *tioca_base;
219 struct pci_dev *pdev; 219 struct pci_dev *pdev;
220 struct tioca_common *common; 220 struct tioca_common *common;
@@ -276,7 +276,7 @@ EXPORT_SYMBOL(tioca_fastwrite_enable); /* used by agp-sgi */
276 * We will always use 0x1 276 * We will always use 0x1
277 * 55:55 - Swap bytes Currently unused 277 * 55:55 - Swap bytes Currently unused
278 */ 278 */
279static uint64_t 279static u64
280tioca_dma_d64(unsigned long paddr) 280tioca_dma_d64(unsigned long paddr)
281{ 281{
282 dma_addr_t bus_addr; 282 dma_addr_t bus_addr;
@@ -318,15 +318,15 @@ tioca_dma_d64(unsigned long paddr)
318 * and so a given CA can only directly target nodes in the range 318 * and so a given CA can only directly target nodes in the range
319 * xxx - xxx+255. 319 * xxx - xxx+255.
320 */ 320 */
321static uint64_t 321static u64
322tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) 322tioca_dma_d48(struct pci_dev *pdev, u64 paddr)
323{ 323{
324 struct tioca_common *tioca_common; 324 struct tioca_common *tioca_common;
325 struct tioca __iomem *ca_base; 325 struct tioca __iomem *ca_base;
326 uint64_t ct_addr; 326 u64 ct_addr;
327 dma_addr_t bus_addr; 327 dma_addr_t bus_addr;
328 uint32_t node_upper; 328 u32 node_upper;
329 uint64_t agp_dma_extn; 329 u64 agp_dma_extn;
330 struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); 330 struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
331 331
332 tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; 332 tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
@@ -367,10 +367,10 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
367 * dma_addr_t is guarenteed to be contiguous in CA bus space. 367 * dma_addr_t is guarenteed to be contiguous in CA bus space.
368 */ 368 */
369static dma_addr_t 369static dma_addr_t
370tioca_dma_mapped(struct pci_dev *pdev, uint64_t paddr, size_t req_size) 370tioca_dma_mapped(struct pci_dev *pdev, u64 paddr, size_t req_size)
371{ 371{
372 int i, ps, ps_shift, entry, entries, mapsize, last_entry; 372 int i, ps, ps_shift, entry, entries, mapsize, last_entry;
373 uint64_t xio_addr, end_xio_addr; 373 u64 xio_addr, end_xio_addr;
374 struct tioca_common *tioca_common; 374 struct tioca_common *tioca_common;
375 struct tioca_kernel *tioca_kern; 375 struct tioca_kernel *tioca_kern;
376 dma_addr_t bus_addr = 0; 376 dma_addr_t bus_addr = 0;
@@ -514,10 +514,10 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
514 * The mapping mode used is based on the devices dma_mask. As a last resort 514 * The mapping mode used is based on the devices dma_mask. As a last resort
515 * use the GART mapped mode. 515 * use the GART mapped mode.
516 */ 516 */
517static uint64_t 517static u64
518tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) 518tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count)
519{ 519{
520 uint64_t mapaddr; 520 u64 mapaddr;
521 521
522 /* 522 /*
523 * If card is 64 or 48 bit addresable, use a direct mapping. 32 523 * If card is 64 or 48 bit addresable, use a direct mapping. 32
@@ -554,8 +554,8 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
554{ 554{
555 struct tioca_common *soft = arg; 555 struct tioca_common *soft = arg;
556 struct ia64_sal_retval ret_stuff; 556 struct ia64_sal_retval ret_stuff;
557 uint64_t segment; 557 u64 segment;
558 uint64_t busnum; 558 u64 busnum;
559 ret_stuff.status = 0; 559 ret_stuff.status = 0;
560 ret_stuff.v0 = 0; 560 ret_stuff.v0 = 0;
561 561
@@ -620,7 +620,7 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
620 INIT_LIST_HEAD(&tioca_kern->ca_dmamaps); 620 INIT_LIST_HEAD(&tioca_kern->ca_dmamaps);
621 tioca_kern->ca_closest_node = 621 tioca_kern->ca_closest_node =
622 nasid_to_cnodeid(tioca_common->ca_closest_nasid); 622 nasid_to_cnodeid(tioca_common->ca_closest_nasid);
623 tioca_common->ca_kernel_private = (uint64_t) tioca_kern; 623 tioca_common->ca_kernel_private = (u64) tioca_kern;
624 624
625 bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment, 625 bus = pci_find_bus(tioca_common->ca_common.bs_persist_segment,
626 tioca_common->ca_common.bs_persist_busnum); 626 tioca_common->ca_common.bs_persist_busnum);
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index dda196c9e324..e52831ed93eb 100644
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -81,10 +81,10 @@
81 * 61 - 0 since this is not an MSI transaction 81 * 61 - 0 since this is not an MSI transaction
82 * 60:54 - reserved, MBZ 82 * 60:54 - reserved, MBZ
83 */ 83 */
84static uint64_t 84static u64
85tioce_dma_d64(unsigned long ct_addr) 85tioce_dma_d64(unsigned long ct_addr)
86{ 86{
87 uint64_t bus_addr; 87 u64 bus_addr;
88 88
89 bus_addr = ct_addr | (1UL << 63); 89 bus_addr = ct_addr | (1UL << 63);
90 90
@@ -141,9 +141,9 @@ pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
141 * length, and if enough resources exist, fill in the ATE's and construct a 141 * length, and if enough resources exist, fill in the ATE's and construct a
142 * tioce_dmamap struct to track the mapping. 142 * tioce_dmamap struct to track the mapping.
143 */ 143 */
144static uint64_t 144static u64
145tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, 145tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
146 uint64_t ct_addr, int len) 146 u64 ct_addr, int len)
147{ 147{
148 int i; 148 int i;
149 int j; 149 int j;
@@ -152,11 +152,11 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
152 int entries; 152 int entries;
153 int nates; 153 int nates;
154 int pagesize; 154 int pagesize;
155 uint64_t *ate_shadow; 155 u64 *ate_shadow;
156 uint64_t *ate_reg; 156 u64 *ate_reg;
157 uint64_t addr; 157 u64 addr;
158 struct tioce *ce_mmr; 158 struct tioce *ce_mmr;
159 uint64_t bus_base; 159 u64 bus_base;
160 struct tioce_dmamap *map; 160 struct tioce_dmamap *map;
161 161
162 ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base; 162 ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
@@ -224,7 +224,7 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
224 224
225 addr = ct_addr; 225 addr = ct_addr;
226 for (j = 0; j < nates; j++) { 226 for (j = 0; j < nates; j++) {
227 uint64_t ate; 227 u64 ate;
228 228
229 ate = ATE_MAKE(addr, pagesize); 229 ate = ATE_MAKE(addr, pagesize);
230 ate_shadow[i + j] = ate; 230 ate_shadow[i + j] = ate;
@@ -252,15 +252,15 @@ tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port,
252 * 252 *
253 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. 253 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
254 */ 254 */
255static uint64_t 255static u64
256tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr) 256tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr)
257{ 257{
258 int dma_ok; 258 int dma_ok;
259 int port; 259 int port;
260 struct tioce *ce_mmr; 260 struct tioce *ce_mmr;
261 struct tioce_kernel *ce_kern; 261 struct tioce_kernel *ce_kern;
262 uint64_t ct_upper; 262 u64 ct_upper;
263 uint64_t ct_lower; 263 u64 ct_lower;
264 dma_addr_t bus_addr; 264 dma_addr_t bus_addr;
265 265
266 ct_upper = ct_addr & ~0x3fffffffUL; 266 ct_upper = ct_addr & ~0x3fffffffUL;
@@ -269,7 +269,7 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
269 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); 269 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port);
270 270
271 if (ce_kern->ce_port[port].dirmap_refcnt == 0) { 271 if (ce_kern->ce_port[port].dirmap_refcnt == 0) {
272 uint64_t tmp; 272 u64 tmp;
273 273
274 ce_kern->ce_port[port].dirmap_shadow = ct_upper; 274 ce_kern->ce_port[port].dirmap_shadow = ct_upper;
275 writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]); 275 writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]);
@@ -295,10 +295,10 @@ tioce_dma_d32(struct pci_dev *pdev, uint64_t ct_addr)
295 * Given a TIOCE bus address, set the appropriate bit to indicate barrier 295 * Given a TIOCE bus address, set the appropriate bit to indicate barrier
296 * attributes. 296 * attributes.
297 */ 297 */
298static uint64_t 298static u64
299tioce_dma_barrier(uint64_t bus_addr, int on) 299tioce_dma_barrier(u64 bus_addr, int on)
300{ 300{
301 uint64_t barrier_bit; 301 u64 barrier_bit;
302 302
303 /* barrier not supported in M40/M40S mode */ 303 /* barrier not supported in M40/M40S mode */
304 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr)) 304 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr))
@@ -351,7 +351,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
351 351
352 list_for_each_entry(map, &ce_kern->ce_dmamap_list, 352 list_for_each_entry(map, &ce_kern->ce_dmamap_list,
353 ce_dmamap_list) { 353 ce_dmamap_list) {
354 uint64_t last; 354 u64 last;
355 355
356 last = map->pci_start + map->nbytes - 1; 356 last = map->pci_start + map->nbytes - 1;
357 if (bus_addr >= map->pci_start && bus_addr <= last) 357 if (bus_addr >= map->pci_start && bus_addr <= last)
@@ -385,17 +385,17 @@ tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
385 * This is the main wrapper for mapping host physical pages to CE PCI space. 385 * This is the main wrapper for mapping host physical pages to CE PCI space.
386 * The mapping mode used is based on the device's dma_mask. 386 * The mapping mode used is based on the device's dma_mask.
387 */ 387 */
388static uint64_t 388static u64
389tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count, 389tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
390 int barrier) 390 int barrier)
391{ 391{
392 unsigned long flags; 392 unsigned long flags;
393 uint64_t ct_addr; 393 u64 ct_addr;
394 uint64_t mapaddr = 0; 394 u64 mapaddr = 0;
395 struct tioce_kernel *ce_kern; 395 struct tioce_kernel *ce_kern;
396 struct tioce_dmamap *map; 396 struct tioce_dmamap *map;
397 int port; 397 int port;
398 uint64_t dma_mask; 398 u64 dma_mask;
399 399
400 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; 400 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask;
401 401
@@ -425,7 +425,7 @@ tioce_do_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count,
425 * address bits than this device can support. 425 * address bits than this device can support.
426 */ 426 */
427 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { 427 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) {
428 uint64_t last; 428 u64 last;
429 429
430 last = map->ct_start + map->nbytes - 1; 430 last = map->ct_start + map->nbytes - 1;
431 if (ct_addr >= map->ct_start && 431 if (ct_addr >= map->ct_start &&
@@ -501,8 +501,8 @@ dma_map_done:
501 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear 501 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
502 * in the address. 502 * in the address.
503 */ 503 */
504static uint64_t 504static u64
505tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) 505tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count)
506{ 506{
507 return tioce_do_dma_map(pdev, paddr, byte_count, 0); 507 return tioce_do_dma_map(pdev, paddr, byte_count, 0);
508} 508}
@@ -515,8 +515,8 @@ tioce_dma(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
515 * 515 *
516 * Simply call tioce_do_dma_map() to create a map with the barrier bit set 516 * Simply call tioce_do_dma_map() to create a map with the barrier bit set
517 * in the address. 517 * in the address.
518 */ static uint64_t 518 */ static u64
519tioce_dma_consistent(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) 519tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count)
520{ 520{
521 return tioce_do_dma_map(pdev, paddr, byte_count, 1); 521 return tioce_do_dma_map(pdev, paddr, byte_count, 1);
522} 522}
@@ -551,7 +551,7 @@ tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
551tioce_kern_init(struct tioce_common *tioce_common) 551tioce_kern_init(struct tioce_common *tioce_common)
552{ 552{
553 int i; 553 int i;
554 uint32_t tmp; 554 u32 tmp;
555 struct tioce *tioce_mmr; 555 struct tioce *tioce_mmr;
556 struct tioce_kernel *tioce_kern; 556 struct tioce_kernel *tioce_kern;
557 557
@@ -563,7 +563,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
563 tioce_kern->ce_common = tioce_common; 563 tioce_kern->ce_common = tioce_common;
564 spin_lock_init(&tioce_kern->ce_lock); 564 spin_lock_init(&tioce_kern->ce_lock);
565 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); 565 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list);
566 tioce_common->ce_kernel_private = (uint64_t) tioce_kern; 566 tioce_common->ce_kernel_private = (u64) tioce_kern;
567 567
568 /* 568 /*
569 * Determine the secondary bus number of the port2 logical PPB. 569 * Determine the secondary bus number of the port2 logical PPB.
@@ -575,7 +575,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
575 raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment, 575 raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment,
576 tioce_common->ce_pcibus.bs_persist_busnum, 576 tioce_common->ce_pcibus.bs_persist_busnum,
577 PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp); 577 PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp);
578 tioce_kern->ce_port1_secondary = (uint8_t) tmp; 578 tioce_kern->ce_port1_secondary = (u8) tmp;
579 579
580 /* 580 /*
581 * Set PMU pagesize to the largest size available, and zero out 581 * Set PMU pagesize to the largest size available, and zero out
@@ -615,7 +615,7 @@ tioce_force_interrupt(struct sn_irq_info *sn_irq_info)
615 struct pcidev_info *pcidev_info; 615 struct pcidev_info *pcidev_info;
616 struct tioce_common *ce_common; 616 struct tioce_common *ce_common;
617 struct tioce *ce_mmr; 617 struct tioce *ce_mmr;
618 uint64_t force_int_val; 618 u64 force_int_val;
619 619
620 if (!sn_irq_info->irq_bridge) 620 if (!sn_irq_info->irq_bridge)
621 return; 621 return;
@@ -687,7 +687,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
687 struct tioce_common *ce_common; 687 struct tioce_common *ce_common;
688 struct tioce *ce_mmr; 688 struct tioce *ce_mmr;
689 int bit; 689 int bit;
690 uint64_t vector; 690 u64 vector;
691 691
692 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 692 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
693 if (!pcidev_info) 693 if (!pcidev_info)
@@ -699,7 +699,7 @@ tioce_target_interrupt(struct sn_irq_info *sn_irq_info)
699 bit = sn_irq_info->irq_int_bit; 699 bit = sn_irq_info->irq_int_bit;
700 700
701 __sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); 701 __sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
702 vector = (uint64_t)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; 702 vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT;
703 vector |= sn_irq_info->irq_xtalkaddr; 703 vector |= sn_irq_info->irq_xtalkaddr;
704 writeq(vector, &ce_mmr->ce_adm_int_dest[bit]); 704 writeq(vector, &ce_mmr->ce_adm_int_dest[bit]);
705 __sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); 705 __sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit));
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index e828377ad295..7708ec669a33 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -927,7 +927,7 @@ static inline s64
927ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) 927ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
928{ 928{
929 struct ia64_pal_retval iprv; 929 struct ia64_pal_retval iprv;
930 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); 930 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
931 if (vector) 931 if (vector)
932 *vector = iprv.v0; 932 *vector = iprv.v0;
933 *progress = iprv.v1; 933 *progress = iprv.v1;
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 8c648bf72bbd..09b99029ac1a 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -25,8 +25,8 @@
25 * Limits for PMC and PMD are set to less than maximum architected values 25 * Limits for PMC and PMD are set to less than maximum architected values
26 * but should be sufficient for a while 26 * but should be sufficient for a while
27 */ 27 */
28#define IA64_NUM_PMC_REGS 32 28#define IA64_NUM_PMC_REGS 64
29#define IA64_NUM_PMD_REGS 32 29#define IA64_NUM_PMD_REGS 64
30 30
31#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000) 31#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
32#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000) 32#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e35074f526d9..a3431372c6e7 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -40,7 +40,7 @@ struct sn_irq_info {
40 int irq_cpuid; /* kernel logical cpuid */ 40 int irq_cpuid; /* kernel logical cpuid */
41 int irq_irq; /* the IRQ number */ 41 int irq_irq; /* the IRQ number */
42 int irq_int_bit; /* Bridge interrupt pin */ 42 int irq_int_bit; /* Bridge interrupt pin */
43 uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ 43 u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
44 int irq_bridge_type;/* pciio asic type (pciio.h) */ 44 int irq_bridge_type;/* pciio asic type (pciio.h) */
45 void *irq_bridge; /* bridge generating irq */ 45 void *irq_bridge; /* bridge generating irq */
46 void *irq_pciioinfo; /* associated pciio_info_t */ 46 void *irq_pciioinfo; /* associated pciio_info_t */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 2b42d9ece26b..9334078b089a 100644
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -44,9 +44,9 @@
44#define PCI32_MAPPED_BASE 0x40000000 44#define PCI32_MAPPED_BASE 0x40000000
45#define PCI32_DIRECT_BASE 0x80000000 45#define PCI32_DIRECT_BASE 0x80000000
46 46
47#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ 47#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
48 (uint64_t)(x) >= PCI32_MAPPED_BASE) 48 (u64)(x) >= PCI32_MAPPED_BASE)
49#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) 49#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
50 50
51 51
52/* 52/*
@@ -63,7 +63,7 @@
63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) 63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
64 64
65#define MINIMAL_ATE_FLAG(addr, size) \ 65#define MINIMAL_ATE_FLAG(addr, size) \
66 (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0) 66 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
67 67
68/* bit 29 of the pci address is the SWAP bit */ 68/* bit 29 of the pci address is the SWAP bit */
69#define ATE_SWAPSHIFT 29 69#define ATE_SWAPSHIFT 29
@@ -90,27 +90,27 @@
90 * PMU resources. 90 * PMU resources.
91 */ 91 */
92struct ate_resource{ 92struct ate_resource{
93 uint64_t *ate; 93 u64 *ate;
94 uint64_t num_ate; 94 u64 num_ate;
95 uint64_t lowest_free_index; 95 u64 lowest_free_index;
96}; 96};
97 97
98struct pcibus_info { 98struct pcibus_info {
99 struct pcibus_bussoft pbi_buscommon; /* common header */ 99 struct pcibus_bussoft pbi_buscommon; /* common header */
100 uint32_t pbi_moduleid; 100 u32 pbi_moduleid;
101 short pbi_bridge_type; 101 short pbi_bridge_type;
102 short pbi_bridge_mode; 102 short pbi_bridge_mode;
103 103
104 struct ate_resource pbi_int_ate_resource; 104 struct ate_resource pbi_int_ate_resource;
105 uint64_t pbi_int_ate_size; 105 u64 pbi_int_ate_size;
106 106
107 uint64_t pbi_dir_xbase; 107 u64 pbi_dir_xbase;
108 char pbi_hub_xid; 108 char pbi_hub_xid;
109 109
110 uint64_t pbi_devreg[8]; 110 u64 pbi_devreg[8];
111 111
112 uint32_t pbi_valid_devices; 112 u32 pbi_valid_devices;
113 uint32_t pbi_enabled_devices; 113 u32 pbi_enabled_devices;
114 114
115 spinlock_t pbi_lock; 115 spinlock_t pbi_lock;
116}; 116};
@@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
136/* 136/*
137 * prototypes for the bridge asic register access routines in pcibr_reg.c 137 * prototypes for the bridge asic register access routines in pcibr_reg.c
138 */ 138 */
139extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t); 139extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
140extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t); 140extern void pcireg_control_bit_set(struct pcibus_info *, u64);
141extern uint64_t pcireg_tflush_get(struct pcibus_info *); 141extern u64 pcireg_tflush_get(struct pcibus_info *);
142extern uint64_t pcireg_intr_status_get(struct pcibus_info *); 142extern u64 pcireg_intr_status_get(struct pcibus_info *);
143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t); 143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t); 144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t); 145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
146extern void pcireg_force_intr_set(struct pcibus_info *, int); 146extern void pcireg_force_intr_set(struct pcibus_info *, int);
147extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int); 147extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
148extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t); 148extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
149extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int); 149extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info); 150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info); 151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
152extern int pcibr_ate_alloc(struct pcibus_info *, int); 152extern int pcibr_ate_alloc(struct pcibus_info *, int);
153extern void pcibr_ate_free(struct pcibus_info *, int); 153extern void pcibr_ate_free(struct pcibus_info *, int);
154extern void ate_write(struct pcibus_info *, int, int, uint64_t); 154extern void ate_write(struct pcibus_info *, int, int, u64);
155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, 155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
156 void *resp); 156 void *resp);
157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device, 157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index ad0e8e8ae53f..ce3f6c328241 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -29,13 +29,13 @@
29 */ 29 */
30 30
31struct pcibus_bussoft { 31struct pcibus_bussoft {
32 uint32_t bs_asic_type; /* chipset type */ 32 u32 bs_asic_type; /* chipset type */
33 uint32_t bs_xid; /* xwidget id */ 33 u32 bs_xid; /* xwidget id */
34 uint32_t bs_persist_busnum; /* Persistent Bus Number */ 34 u32 bs_persist_busnum; /* Persistent Bus Number */
35 uint32_t bs_persist_segment; /* Segment Number */ 35 u32 bs_persist_segment; /* Segment Number */
36 uint64_t bs_legacy_io; /* legacy io pio addr */ 36 u64 bs_legacy_io; /* legacy io pio addr */
37 uint64_t bs_legacy_mem; /* legacy mem pio addr */ 37 u64 bs_legacy_mem; /* legacy mem pio addr */
38 uint64_t bs_base; /* widget base */ 38 u64 bs_base; /* widget base */
39 struct xwidget_info *bs_xwidget_info; 39 struct xwidget_info *bs_xwidget_info;
40}; 40};
41 41
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index f65d222ca5e8..38cdffbc4c7b 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -55,8 +55,8 @@ struct sn_pci_controller {
55#define PCIIO_VENDOR_ID_NONE (-1) 55#define PCIIO_VENDOR_ID_NONE (-1)
56 56
57struct pcidev_info { 57struct pcidev_info {
58 uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */ 58 u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
59 uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */ 59 u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
60 60
61 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */ 61 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
62 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */ 62 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
index 0de82e6b0893..5f9da5fd6e56 100644
--- a/include/asm-ia64/sn/pic.h
+++ b/include/asm-ia64/sn/pic.h
@@ -74,120 +74,120 @@ struct pic {
74 /* 0x000000-0x00FFFF -- Local Registers */ 74 /* 0x000000-0x00FFFF -- Local Registers */
75 75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */ 76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 uint64_t p_wid_id; /* 0x000000 */ 77 u64 p_wid_id; /* 0x000000 */
78 uint64_t p_wid_stat; /* 0x000008 */ 78 u64 p_wid_stat; /* 0x000008 */
79 uint64_t p_wid_err_upper; /* 0x000010 */ 79 u64 p_wid_err_upper; /* 0x000010 */
80 uint64_t p_wid_err_lower; /* 0x000018 */ 80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower 81 #define p_wid_err p_wid_err_lower
82 uint64_t p_wid_control; /* 0x000020 */ 82 u64 p_wid_control; /* 0x000020 */
83 uint64_t p_wid_req_timeout; /* 0x000028 */ 83 u64 p_wid_req_timeout; /* 0x000028 */
84 uint64_t p_wid_int_upper; /* 0x000030 */ 84 u64 p_wid_int_upper; /* 0x000030 */
85 uint64_t p_wid_int_lower; /* 0x000038 */ 85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower 86 #define p_wid_int p_wid_int_lower
87 uint64_t p_wid_err_cmdword; /* 0x000040 */ 87 u64 p_wid_err_cmdword; /* 0x000040 */
88 uint64_t p_wid_llp; /* 0x000048 */ 88 u64 p_wid_llp; /* 0x000048 */
89 uint64_t p_wid_tflush; /* 0x000050 */ 89 u64 p_wid_tflush; /* 0x000050 */
90 90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ 91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 uint64_t p_wid_aux_err; /* 0x000058 */ 92 u64 p_wid_aux_err; /* 0x000058 */
93 uint64_t p_wid_resp_upper; /* 0x000060 */ 93 u64 p_wid_resp_upper; /* 0x000060 */
94 uint64_t p_wid_resp_lower; /* 0x000068 */ 94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower 95 #define p_wid_resp p_wid_resp_lower
96 uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */ 96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 uint64_t p_wid_addr_lkerr; /* 0x000078 */ 97 u64 p_wid_addr_lkerr; /* 0x000078 */
98 98
99 /* 0x000080-0x00008F -- PMU & MAP */ 99 /* 0x000080-0x00008F -- PMU & MAP */
100 uint64_t p_dir_map; /* 0x000080 */ 100 u64 p_dir_map; /* 0x000080 */
101 uint64_t _pad_000088; /* 0x000088 */ 101 u64 _pad_000088; /* 0x000088 */
102 102
103 /* 0x000090-0x00009F -- SSRAM */ 103 /* 0x000090-0x00009F -- SSRAM */
104 uint64_t p_map_fault; /* 0x000090 */ 104 u64 p_map_fault; /* 0x000090 */
105 uint64_t _pad_000098; /* 0x000098 */ 105 u64 _pad_000098; /* 0x000098 */
106 106
107 /* 0x0000A0-0x0000AF -- Arbitration */ 107 /* 0x0000A0-0x0000AF -- Arbitration */
108 uint64_t p_arb; /* 0x0000A0 */ 108 u64 p_arb; /* 0x0000A0 */
109 uint64_t _pad_0000A8; /* 0x0000A8 */ 109 u64 _pad_0000A8; /* 0x0000A8 */
110 110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 uint64_t p_ate_parity_err; /* 0x0000B0 */ 112 u64 p_ate_parity_err; /* 0x0000B0 */
113 uint64_t _pad_0000B8; /* 0x0000B8 */ 113 u64 _pad_0000B8; /* 0x0000B8 */
114 114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */ 115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 uint64_t p_bus_timeout; /* 0x0000C0 */ 116 u64 p_bus_timeout; /* 0x0000C0 */
117 uint64_t p_pci_cfg; /* 0x0000C8 */ 117 u64 p_pci_cfg; /* 0x0000C8 */
118 uint64_t p_pci_err_upper; /* 0x0000D0 */ 118 u64 p_pci_err_upper; /* 0x0000D0 */
119 uint64_t p_pci_err_lower; /* 0x0000D8 */ 119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower 120 #define p_pci_err p_pci_err_lower
121 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122 122
123 /* 0x000100-0x0001FF -- Interrupt */ 123 /* 0x000100-0x0001FF -- Interrupt */
124 uint64_t p_int_status; /* 0x000100 */ 124 u64 p_int_status; /* 0x000100 */
125 uint64_t p_int_enable; /* 0x000108 */ 125 u64 p_int_enable; /* 0x000108 */
126 uint64_t p_int_rst_stat; /* 0x000110 */ 126 u64 p_int_rst_stat; /* 0x000110 */
127 uint64_t p_int_mode; /* 0x000118 */ 127 u64 p_int_mode; /* 0x000118 */
128 uint64_t p_int_device; /* 0x000120 */ 128 u64 p_int_device; /* 0x000120 */
129 uint64_t p_int_host_err; /* 0x000128 */ 129 u64 p_int_host_err; /* 0x000128 */
130 uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */ 130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 uint64_t p_err_int_view; /* 0x000170 */ 131 u64 p_err_int_view; /* 0x000170 */
132 uint64_t p_mult_int; /* 0x000178 */ 132 u64 p_mult_int; /* 0x000178 */
133 uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */ 133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */ 134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135 135
136 /* 0x000200-0x000298 -- Device */ 136 /* 0x000200-0x000298 -- Device */
137 uint64_t p_device[4]; /* 0x0002{00,,,18} */ 137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */ 139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */ 141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */ 142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */ 143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 uint64_t p_resp_status; /* 0x000290 */ 144 u64 p_resp_status; /* 0x000290 */
145 uint64_t p_resp_clear; /* 0x000298 */ 145 u64 p_resp_clear; /* 0x000298 */
146 146
147 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148 148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct { 150 struct {
151 uint64_t upper; /* 0x0003{00,,,F0} */ 151 u64 upper; /* 0x0003{00,,,F0} */
152 uint64_t lower; /* 0x0003{08,,,F8} */ 152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16]; 153 } p_buf_addr_match[16];
154 154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct { 156 struct {
157 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 uint64_t inflight; /* 0x000{410,,,5D0} */ 159 u64 inflight; /* 0x000{410,,,5D0} */
160 uint64_t prefetch; /* 0x000{418,,,5D8} */ 160 u64 prefetch; /* 0x000{418,,,5D8} */
161 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 uint64_t max_latency; /* 0x000{430,,,5F0} */ 163 u64 max_latency; /* 0x000{430,,,5F0} */
164 uint64_t clear_all; /* 0x000{438,,,5F8} */ 164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8]; 165 } p_buf_count[8];
166 166
167 167
168 /* 0x000600-0x0009FF -- PCI/X registers */ 168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */ 169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */ 170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 uint64_t p_pcix_bus_err_data; /* 0x000610 */ 171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 uint64_t p_pcix_pio_split_addr; /* 0x000618 */ 172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 uint64_t p_pcix_pio_split_attr; /* 0x000620 */ 173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */ 174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */ 175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 uint64_t p_pcix_timeout; /* 0x000638 */ 176 u64 p_pcix_timeout; /* 0x000638 */
177 177
178 uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */ 178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179 179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct { 181 struct {
182 uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */ 182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */ 183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16]; 184 } p_pcix_read_buf_64[16];
185 185
186 struct { 186 struct {
187 uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */ 187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */ 188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */ 189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8]; 191 } p_pcix_write_buf_64[8];
192 192
193 /* End of Local Registers -- Start of Address Map space */ 193 /* End of Local Registers -- Start of Address Map space */
@@ -195,45 +195,45 @@ struct pic {
195 char _pad_000c00[0x010000 - 0x000c00]; 195 char _pad_000c00[0x010000 - 0x000c00];
196 196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ 197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */ 198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199 199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ 200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ 201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202 202
203 char _pad_014000[0x18000 - 0x014000]; 203 char _pad_014000[0x18000 - 0x014000];
204 204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */ 205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209 209
210 char _pad_019800[0x20000 - 0x019800]; 210 char _pad_019800[0x20000 - 0x019800];
211 211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ 212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union { 213 union {
214 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union { 218 union {
219 uint8_t c[0x100 / 1]; 219 u8 c[0x100 / 1];
220 uint16_t s[0x100 / 2]; 220 u16 s[0x100 / 2];
221 uint32_t l[0x100 / 4]; 221 u32 l[0x100 / 4];
222 uint64_t d[0x100 / 8]; 222 u64 d[0x100 / 8];
223 } f[8]; 223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ 224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225 225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union { 227 union {
228 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union { 232 union {
233 uint8_t c[0x100 / 1]; 233 u8 c[0x100 / 1];
234 uint16_t s[0x100 / 2]; 234 u16 s[0x100 / 2];
235 uint32_t l[0x100 / 4]; 235 u32 l[0x100 / 4];
236 uint64_t d[0x100 / 8]; 236 u64 d[0x100 / 8];
237 } f[8]; 237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */ 238 } p_type1_cfg; /* 0x028000-0x029000 */
239 239
@@ -241,20 +241,20 @@ struct pic {
241 241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union { 243 union {
244 uint8_t c[8 / 1]; 244 u8 c[8 / 1];
245 uint16_t s[8 / 2]; 245 u16 s[8 / 2];
246 uint32_t l[8 / 4]; 246 u32 l[8 / 4];
247 uint64_t d[8 / 8]; 247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */ 248 } p_pci_iack; /* 0x030000-0x030007 */
249 249
250 char _pad_030007[0x040000-0x030008]; 250 char _pad_030007[0x040000-0x030008];
251 251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */ 252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union { 253 union {
254 uint8_t c[8 / 1]; 254 u8 c[8 / 1];
255 uint16_t s[8 / 2]; 255 u16 s[8 / 2];
256 uint32_t l[8 / 4]; 256 u32 l[8 / 4];
257 uint64_t d[8 / 8]; 257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */ 258 } p_pcix_cycle; /* 0x040000-0x040007 */
259}; 259};
260 260
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
index 831b72111fdc..22a6f18a5313 100644
--- a/include/asm-ia64/sn/shubio.h
+++ b/include/asm-ia64/sn/shubio.h
@@ -227,13 +227,13 @@
227 ************************************************************************/ 227 ************************************************************************/
228 228
229typedef union ii_wid_u { 229typedef union ii_wid_u {
230 uint64_t ii_wid_regval; 230 u64 ii_wid_regval;
231 struct { 231 struct {
232 uint64_t w_rsvd_1:1; 232 u64 w_rsvd_1:1;
233 uint64_t w_mfg_num:11; 233 u64 w_mfg_num:11;
234 uint64_t w_part_num:16; 234 u64 w_part_num:16;
235 uint64_t w_rev_num:4; 235 u64 w_rev_num:4;
236 uint64_t w_rsvd:32; 236 u64 w_rsvd:32;
237 } ii_wid_fld_s; 237 } ii_wid_fld_s;
238} ii_wid_u_t; 238} ii_wid_u_t;
239 239
@@ -246,18 +246,18 @@ typedef union ii_wid_u {
246 ************************************************************************/ 246 ************************************************************************/
247 247
248typedef union ii_wstat_u { 248typedef union ii_wstat_u {
249 uint64_t ii_wstat_regval; 249 u64 ii_wstat_regval;
250 struct { 250 struct {
251 uint64_t w_pending:4; 251 u64 w_pending:4;
252 uint64_t w_xt_crd_to:1; 252 u64 w_xt_crd_to:1;
253 uint64_t w_xt_tail_to:1; 253 u64 w_xt_tail_to:1;
254 uint64_t w_rsvd_3:3; 254 u64 w_rsvd_3:3;
255 uint64_t w_tx_mx_rty:1; 255 u64 w_tx_mx_rty:1;
256 uint64_t w_rsvd_2:6; 256 u64 w_rsvd_2:6;
257 uint64_t w_llp_tx_cnt:8; 257 u64 w_llp_tx_cnt:8;
258 uint64_t w_rsvd_1:8; 258 u64 w_rsvd_1:8;
259 uint64_t w_crazy:1; 259 u64 w_crazy:1;
260 uint64_t w_rsvd:31; 260 u64 w_rsvd:31;
261 } ii_wstat_fld_s; 261 } ii_wstat_fld_s;
262} ii_wstat_u_t; 262} ii_wstat_u_t;
263 263
@@ -269,16 +269,16 @@ typedef union ii_wstat_u {
269 ************************************************************************/ 269 ************************************************************************/
270 270
271typedef union ii_wcr_u { 271typedef union ii_wcr_u {
272 uint64_t ii_wcr_regval; 272 u64 ii_wcr_regval;
273 struct { 273 struct {
274 uint64_t w_wid:4; 274 u64 w_wid:4;
275 uint64_t w_tag:1; 275 u64 w_tag:1;
276 uint64_t w_rsvd_1:8; 276 u64 w_rsvd_1:8;
277 uint64_t w_dst_crd:3; 277 u64 w_dst_crd:3;
278 uint64_t w_f_bad_pkt:1; 278 u64 w_f_bad_pkt:1;
279 uint64_t w_dir_con:1; 279 u64 w_dir_con:1;
280 uint64_t w_e_thresh:5; 280 u64 w_e_thresh:5;
281 uint64_t w_rsvd:41; 281 u64 w_rsvd:41;
282 } ii_wcr_fld_s; 282 } ii_wcr_fld_s;
283} ii_wcr_u_t; 283} ii_wcr_u_t;
284 284
@@ -310,9 +310,9 @@ typedef union ii_wcr_u {
310 ************************************************************************/ 310 ************************************************************************/
311 311
312typedef union ii_ilapr_u { 312typedef union ii_ilapr_u {
313 uint64_t ii_ilapr_regval; 313 u64 ii_ilapr_regval;
314 struct { 314 struct {
315 uint64_t i_region:64; 315 u64 i_region:64;
316 } ii_ilapr_fld_s; 316 } ii_ilapr_fld_s;
317} ii_ilapr_u_t; 317} ii_ilapr_u_t;
318 318
@@ -330,9 +330,9 @@ typedef union ii_ilapr_u {
330 ************************************************************************/ 330 ************************************************************************/
331 331
332typedef union ii_ilapo_u { 332typedef union ii_ilapo_u {
333 uint64_t ii_ilapo_regval; 333 u64 ii_ilapo_regval;
334 struct { 334 struct {
335 uint64_t i_io_ovrride:64; 335 u64 i_io_ovrride:64;
336 } ii_ilapo_fld_s; 336 } ii_ilapo_fld_s;
337} ii_ilapo_u_t; 337} ii_ilapo_u_t;
338 338
@@ -344,12 +344,12 @@ typedef union ii_ilapo_u {
344 ************************************************************************/ 344 ************************************************************************/
345 345
346typedef union ii_iowa_u { 346typedef union ii_iowa_u {
347 uint64_t ii_iowa_regval; 347 u64 ii_iowa_regval;
348 struct { 348 struct {
349 uint64_t i_w0_oac:1; 349 u64 i_w0_oac:1;
350 uint64_t i_rsvd_1:7; 350 u64 i_rsvd_1:7;
351 uint64_t i_wx_oac:8; 351 u64 i_wx_oac:8;
352 uint64_t i_rsvd:48; 352 u64 i_rsvd:48;
353 } ii_iowa_fld_s; 353 } ii_iowa_fld_s;
354} ii_iowa_u_t; 354} ii_iowa_u_t;
355 355
@@ -363,12 +363,12 @@ typedef union ii_iowa_u {
363 ************************************************************************/ 363 ************************************************************************/
364 364
365typedef union ii_iiwa_u { 365typedef union ii_iiwa_u {
366 uint64_t ii_iiwa_regval; 366 u64 ii_iiwa_regval;
367 struct { 367 struct {
368 uint64_t i_w0_iac:1; 368 u64 i_w0_iac:1;
369 uint64_t i_rsvd_1:7; 369 u64 i_rsvd_1:7;
370 uint64_t i_wx_iac:8; 370 u64 i_wx_iac:8;
371 uint64_t i_rsvd:48; 371 u64 i_rsvd:48;
372 } ii_iiwa_fld_s; 372 } ii_iiwa_fld_s;
373} ii_iiwa_u_t; 373} ii_iiwa_u_t;
374 374
@@ -392,16 +392,16 @@ typedef union ii_iiwa_u {
392 ************************************************************************/ 392 ************************************************************************/
393 393
394typedef union ii_iidem_u { 394typedef union ii_iidem_u {
395 uint64_t ii_iidem_regval; 395 u64 ii_iidem_regval;
396 struct { 396 struct {
397 uint64_t i_w8_dxs:8; 397 u64 i_w8_dxs:8;
398 uint64_t i_w9_dxs:8; 398 u64 i_w9_dxs:8;
399 uint64_t i_wa_dxs:8; 399 u64 i_wa_dxs:8;
400 uint64_t i_wb_dxs:8; 400 u64 i_wb_dxs:8;
401 uint64_t i_wc_dxs:8; 401 u64 i_wc_dxs:8;
402 uint64_t i_wd_dxs:8; 402 u64 i_wd_dxs:8;
403 uint64_t i_we_dxs:8; 403 u64 i_we_dxs:8;
404 uint64_t i_wf_dxs:8; 404 u64 i_wf_dxs:8;
405 } ii_iidem_fld_s; 405 } ii_iidem_fld_s;
406} ii_iidem_u_t; 406} ii_iidem_u_t;
407 407
@@ -413,22 +413,22 @@ typedef union ii_iidem_u {
413 ************************************************************************/ 413 ************************************************************************/
414 414
415typedef union ii_ilcsr_u { 415typedef union ii_ilcsr_u {
416 uint64_t ii_ilcsr_regval; 416 u64 ii_ilcsr_regval;
417 struct { 417 struct {
418 uint64_t i_nullto:6; 418 u64 i_nullto:6;
419 uint64_t i_rsvd_4:2; 419 u64 i_rsvd_4:2;
420 uint64_t i_wrmrst:1; 420 u64 i_wrmrst:1;
421 uint64_t i_rsvd_3:1; 421 u64 i_rsvd_3:1;
422 uint64_t i_llp_en:1; 422 u64 i_llp_en:1;
423 uint64_t i_bm8:1; 423 u64 i_bm8:1;
424 uint64_t i_llp_stat:2; 424 u64 i_llp_stat:2;
425 uint64_t i_remote_power:1; 425 u64 i_remote_power:1;
426 uint64_t i_rsvd_2:1; 426 u64 i_rsvd_2:1;
427 uint64_t i_maxrtry:10; 427 u64 i_maxrtry:10;
428 uint64_t i_d_avail_sel:2; 428 u64 i_d_avail_sel:2;
429 uint64_t i_rsvd_1:4; 429 u64 i_rsvd_1:4;
430 uint64_t i_maxbrst:10; 430 u64 i_maxbrst:10;
431 uint64_t i_rsvd:22; 431 u64 i_rsvd:22;
432 432
433 } ii_ilcsr_fld_s; 433 } ii_ilcsr_fld_s;
434} ii_ilcsr_u_t; 434} ii_ilcsr_u_t;
@@ -441,11 +441,11 @@ typedef union ii_ilcsr_u {
441 ************************************************************************/ 441 ************************************************************************/
442 442
443typedef union ii_illr_u { 443typedef union ii_illr_u {
444 uint64_t ii_illr_regval; 444 u64 ii_illr_regval;
445 struct { 445 struct {
446 uint64_t i_sn_cnt:16; 446 u64 i_sn_cnt:16;
447 uint64_t i_cb_cnt:16; 447 u64 i_cb_cnt:16;
448 uint64_t i_rsvd:32; 448 u64 i_rsvd:32;
449 } ii_illr_fld_s; 449 } ii_illr_fld_s;
450} ii_illr_u_t; 450} ii_illr_u_t;
451 451
@@ -464,19 +464,19 @@ typedef union ii_illr_u {
464 ************************************************************************/ 464 ************************************************************************/
465 465
466typedef union ii_iidsr_u { 466typedef union ii_iidsr_u {
467 uint64_t ii_iidsr_regval; 467 u64 ii_iidsr_regval;
468 struct { 468 struct {
469 uint64_t i_level:8; 469 u64 i_level:8;
470 uint64_t i_pi_id:1; 470 u64 i_pi_id:1;
471 uint64_t i_node:11; 471 u64 i_node:11;
472 uint64_t i_rsvd_3:4; 472 u64 i_rsvd_3:4;
473 uint64_t i_enable:1; 473 u64 i_enable:1;
474 uint64_t i_rsvd_2:3; 474 u64 i_rsvd_2:3;
475 uint64_t i_int_sent:2; 475 u64 i_int_sent:2;
476 uint64_t i_rsvd_1:2; 476 u64 i_rsvd_1:2;
477 uint64_t i_pi0_forward_int:1; 477 u64 i_pi0_forward_int:1;
478 uint64_t i_pi1_forward_int:1; 478 u64 i_pi1_forward_int:1;
479 uint64_t i_rsvd:30; 479 u64 i_rsvd:30;
480 } ii_iidsr_fld_s; 480 } ii_iidsr_fld_s;
481} ii_iidsr_u_t; 481} ii_iidsr_u_t;
482 482
@@ -492,13 +492,13 @@ typedef union ii_iidsr_u {
492 ************************************************************************/ 492 ************************************************************************/
493 493
494typedef union ii_igfx0_u { 494typedef union ii_igfx0_u {
495 uint64_t ii_igfx0_regval; 495 u64 ii_igfx0_regval;
496 struct { 496 struct {
497 uint64_t i_w_num:4; 497 u64 i_w_num:4;
498 uint64_t i_pi_id:1; 498 u64 i_pi_id:1;
499 uint64_t i_n_num:12; 499 u64 i_n_num:12;
500 uint64_t i_p_num:1; 500 u64 i_p_num:1;
501 uint64_t i_rsvd:46; 501 u64 i_rsvd:46;
502 } ii_igfx0_fld_s; 502 } ii_igfx0_fld_s;
503} ii_igfx0_u_t; 503} ii_igfx0_u_t;
504 504
@@ -514,13 +514,13 @@ typedef union ii_igfx0_u {
514 ************************************************************************/ 514 ************************************************************************/
515 515
516typedef union ii_igfx1_u { 516typedef union ii_igfx1_u {
517 uint64_t ii_igfx1_regval; 517 u64 ii_igfx1_regval;
518 struct { 518 struct {
519 uint64_t i_w_num:4; 519 u64 i_w_num:4;
520 uint64_t i_pi_id:1; 520 u64 i_pi_id:1;
521 uint64_t i_n_num:12; 521 u64 i_n_num:12;
522 uint64_t i_p_num:1; 522 u64 i_p_num:1;
523 uint64_t i_rsvd:46; 523 u64 i_rsvd:46;
524 } ii_igfx1_fld_s; 524 } ii_igfx1_fld_s;
525} ii_igfx1_u_t; 525} ii_igfx1_u_t;
526 526
@@ -532,9 +532,9 @@ typedef union ii_igfx1_u {
532 ************************************************************************/ 532 ************************************************************************/
533 533
534typedef union ii_iscr0_u { 534typedef union ii_iscr0_u {
535 uint64_t ii_iscr0_regval; 535 u64 ii_iscr0_regval;
536 struct { 536 struct {
537 uint64_t i_scratch:64; 537 u64 i_scratch:64;
538 } ii_iscr0_fld_s; 538 } ii_iscr0_fld_s;
539} ii_iscr0_u_t; 539} ii_iscr0_u_t;
540 540
@@ -546,9 +546,9 @@ typedef union ii_iscr0_u {
546 ************************************************************************/ 546 ************************************************************************/
547 547
548typedef union ii_iscr1_u { 548typedef union ii_iscr1_u {
549 uint64_t ii_iscr1_regval; 549 u64 ii_iscr1_regval;
550 struct { 550 struct {
551 uint64_t i_scratch:64; 551 u64 i_scratch:64;
552 } ii_iscr1_fld_s; 552 } ii_iscr1_fld_s;
553} ii_iscr1_u_t; 553} ii_iscr1_u_t;
554 554
@@ -580,13 +580,13 @@ typedef union ii_iscr1_u {
580 ************************************************************************/ 580 ************************************************************************/
581 581
582typedef union ii_itte1_u { 582typedef union ii_itte1_u {
583 uint64_t ii_itte1_regval; 583 u64 ii_itte1_regval;
584 struct { 584 struct {
585 uint64_t i_offset:5; 585 u64 i_offset:5;
586 uint64_t i_rsvd_1:3; 586 u64 i_rsvd_1:3;
587 uint64_t i_w_num:4; 587 u64 i_w_num:4;
588 uint64_t i_iosp:1; 588 u64 i_iosp:1;
589 uint64_t i_rsvd:51; 589 u64 i_rsvd:51;
590 } ii_itte1_fld_s; 590 } ii_itte1_fld_s;
591} ii_itte1_u_t; 591} ii_itte1_u_t;
592 592
@@ -618,13 +618,13 @@ typedef union ii_itte1_u {
618 ************************************************************************/ 618 ************************************************************************/
619 619
620typedef union ii_itte2_u { 620typedef union ii_itte2_u {
621 uint64_t ii_itte2_regval; 621 u64 ii_itte2_regval;
622 struct { 622 struct {
623 uint64_t i_offset:5; 623 u64 i_offset:5;
624 uint64_t i_rsvd_1:3; 624 u64 i_rsvd_1:3;
625 uint64_t i_w_num:4; 625 u64 i_w_num:4;
626 uint64_t i_iosp:1; 626 u64 i_iosp:1;
627 uint64_t i_rsvd:51; 627 u64 i_rsvd:51;
628 } ii_itte2_fld_s; 628 } ii_itte2_fld_s;
629} ii_itte2_u_t; 629} ii_itte2_u_t;
630 630
@@ -656,13 +656,13 @@ typedef union ii_itte2_u {
656 ************************************************************************/ 656 ************************************************************************/
657 657
658typedef union ii_itte3_u { 658typedef union ii_itte3_u {
659 uint64_t ii_itte3_regval; 659 u64 ii_itte3_regval;
660 struct { 660 struct {
661 uint64_t i_offset:5; 661 u64 i_offset:5;
662 uint64_t i_rsvd_1:3; 662 u64 i_rsvd_1:3;
663 uint64_t i_w_num:4; 663 u64 i_w_num:4;
664 uint64_t i_iosp:1; 664 u64 i_iosp:1;
665 uint64_t i_rsvd:51; 665 u64 i_rsvd:51;
666 } ii_itte3_fld_s; 666 } ii_itte3_fld_s;
667} ii_itte3_u_t; 667} ii_itte3_u_t;
668 668
@@ -694,13 +694,13 @@ typedef union ii_itte3_u {
694 ************************************************************************/ 694 ************************************************************************/
695 695
696typedef union ii_itte4_u { 696typedef union ii_itte4_u {
697 uint64_t ii_itte4_regval; 697 u64 ii_itte4_regval;
698 struct { 698 struct {
699 uint64_t i_offset:5; 699 u64 i_offset:5;
700 uint64_t i_rsvd_1:3; 700 u64 i_rsvd_1:3;
701 uint64_t i_w_num:4; 701 u64 i_w_num:4;
702 uint64_t i_iosp:1; 702 u64 i_iosp:1;
703 uint64_t i_rsvd:51; 703 u64 i_rsvd:51;
704 } ii_itte4_fld_s; 704 } ii_itte4_fld_s;
705} ii_itte4_u_t; 705} ii_itte4_u_t;
706 706
@@ -732,13 +732,13 @@ typedef union ii_itte4_u {
732 ************************************************************************/ 732 ************************************************************************/
733 733
734typedef union ii_itte5_u { 734typedef union ii_itte5_u {
735 uint64_t ii_itte5_regval; 735 u64 ii_itte5_regval;
736 struct { 736 struct {
737 uint64_t i_offset:5; 737 u64 i_offset:5;
738 uint64_t i_rsvd_1:3; 738 u64 i_rsvd_1:3;
739 uint64_t i_w_num:4; 739 u64 i_w_num:4;
740 uint64_t i_iosp:1; 740 u64 i_iosp:1;
741 uint64_t i_rsvd:51; 741 u64 i_rsvd:51;
742 } ii_itte5_fld_s; 742 } ii_itte5_fld_s;
743} ii_itte5_u_t; 743} ii_itte5_u_t;
744 744
@@ -770,13 +770,13 @@ typedef union ii_itte5_u {
770 ************************************************************************/ 770 ************************************************************************/
771 771
772typedef union ii_itte6_u { 772typedef union ii_itte6_u {
773 uint64_t ii_itte6_regval; 773 u64 ii_itte6_regval;
774 struct { 774 struct {
775 uint64_t i_offset:5; 775 u64 i_offset:5;
776 uint64_t i_rsvd_1:3; 776 u64 i_rsvd_1:3;
777 uint64_t i_w_num:4; 777 u64 i_w_num:4;
778 uint64_t i_iosp:1; 778 u64 i_iosp:1;
779 uint64_t i_rsvd:51; 779 u64 i_rsvd:51;
780 } ii_itte6_fld_s; 780 } ii_itte6_fld_s;
781} ii_itte6_u_t; 781} ii_itte6_u_t;
782 782
@@ -808,13 +808,13 @@ typedef union ii_itte6_u {
808 ************************************************************************/ 808 ************************************************************************/
809 809
810typedef union ii_itte7_u { 810typedef union ii_itte7_u {
811 uint64_t ii_itte7_regval; 811 u64 ii_itte7_regval;
812 struct { 812 struct {
813 uint64_t i_offset:5; 813 u64 i_offset:5;
814 uint64_t i_rsvd_1:3; 814 u64 i_rsvd_1:3;
815 uint64_t i_w_num:4; 815 u64 i_w_num:4;
816 uint64_t i_iosp:1; 816 u64 i_iosp:1;
817 uint64_t i_rsvd:51; 817 u64 i_rsvd:51;
818 } ii_itte7_fld_s; 818 } ii_itte7_fld_s;
819} ii_itte7_u_t; 819} ii_itte7_u_t;
820 820
@@ -843,22 +843,22 @@ typedef union ii_itte7_u {
843 ************************************************************************/ 843 ************************************************************************/
844 844
845typedef union ii_iprb0_u { 845typedef union ii_iprb0_u {
846 uint64_t ii_iprb0_regval; 846 u64 ii_iprb0_regval;
847 struct { 847 struct {
848 uint64_t i_c:8; 848 u64 i_c:8;
849 uint64_t i_na:14; 849 u64 i_na:14;
850 uint64_t i_rsvd_2:2; 850 u64 i_rsvd_2:2;
851 uint64_t i_nb:14; 851 u64 i_nb:14;
852 uint64_t i_rsvd_1:2; 852 u64 i_rsvd_1:2;
853 uint64_t i_m:2; 853 u64 i_m:2;
854 uint64_t i_f:1; 854 u64 i_f:1;
855 uint64_t i_of_cnt:5; 855 u64 i_of_cnt:5;
856 uint64_t i_error:1; 856 u64 i_error:1;
857 uint64_t i_rd_to:1; 857 u64 i_rd_to:1;
858 uint64_t i_spur_wr:1; 858 u64 i_spur_wr:1;
859 uint64_t i_spur_rd:1; 859 u64 i_spur_rd:1;
860 uint64_t i_rsvd:11; 860 u64 i_rsvd:11;
861 uint64_t i_mult_err:1; 861 u64 i_mult_err:1;
862 } ii_iprb0_fld_s; 862 } ii_iprb0_fld_s;
863} ii_iprb0_u_t; 863} ii_iprb0_u_t;
864 864
@@ -887,22 +887,22 @@ typedef union ii_iprb0_u {
887 ************************************************************************/ 887 ************************************************************************/
888 888
889typedef union ii_iprb8_u { 889typedef union ii_iprb8_u {
890 uint64_t ii_iprb8_regval; 890 u64 ii_iprb8_regval;
891 struct { 891 struct {
892 uint64_t i_c:8; 892 u64 i_c:8;
893 uint64_t i_na:14; 893 u64 i_na:14;
894 uint64_t i_rsvd_2:2; 894 u64 i_rsvd_2:2;
895 uint64_t i_nb:14; 895 u64 i_nb:14;
896 uint64_t i_rsvd_1:2; 896 u64 i_rsvd_1:2;
897 uint64_t i_m:2; 897 u64 i_m:2;
898 uint64_t i_f:1; 898 u64 i_f:1;
899 uint64_t i_of_cnt:5; 899 u64 i_of_cnt:5;
900 uint64_t i_error:1; 900 u64 i_error:1;
901 uint64_t i_rd_to:1; 901 u64 i_rd_to:1;
902 uint64_t i_spur_wr:1; 902 u64 i_spur_wr:1;
903 uint64_t i_spur_rd:1; 903 u64 i_spur_rd:1;
904 uint64_t i_rsvd:11; 904 u64 i_rsvd:11;
905 uint64_t i_mult_err:1; 905 u64 i_mult_err:1;
906 } ii_iprb8_fld_s; 906 } ii_iprb8_fld_s;
907} ii_iprb8_u_t; 907} ii_iprb8_u_t;
908 908
@@ -931,22 +931,22 @@ typedef union ii_iprb8_u {
931 ************************************************************************/ 931 ************************************************************************/
932 932
933typedef union ii_iprb9_u { 933typedef union ii_iprb9_u {
934 uint64_t ii_iprb9_regval; 934 u64 ii_iprb9_regval;
935 struct { 935 struct {
936 uint64_t i_c:8; 936 u64 i_c:8;
937 uint64_t i_na:14; 937 u64 i_na:14;
938 uint64_t i_rsvd_2:2; 938 u64 i_rsvd_2:2;
939 uint64_t i_nb:14; 939 u64 i_nb:14;
940 uint64_t i_rsvd_1:2; 940 u64 i_rsvd_1:2;
941 uint64_t i_m:2; 941 u64 i_m:2;
942 uint64_t i_f:1; 942 u64 i_f:1;
943 uint64_t i_of_cnt:5; 943 u64 i_of_cnt:5;
944 uint64_t i_error:1; 944 u64 i_error:1;
945 uint64_t i_rd_to:1; 945 u64 i_rd_to:1;
946 uint64_t i_spur_wr:1; 946 u64 i_spur_wr:1;
947 uint64_t i_spur_rd:1; 947 u64 i_spur_rd:1;
948 uint64_t i_rsvd:11; 948 u64 i_rsvd:11;
949 uint64_t i_mult_err:1; 949 u64 i_mult_err:1;
950 } ii_iprb9_fld_s; 950 } ii_iprb9_fld_s;
951} ii_iprb9_u_t; 951} ii_iprb9_u_t;
952 952
@@ -975,22 +975,22 @@ typedef union ii_iprb9_u {
975 ************************************************************************/ 975 ************************************************************************/
976 976
977typedef union ii_iprba_u { 977typedef union ii_iprba_u {
978 uint64_t ii_iprba_regval; 978 u64 ii_iprba_regval;
979 struct { 979 struct {
980 uint64_t i_c:8; 980 u64 i_c:8;
981 uint64_t i_na:14; 981 u64 i_na:14;
982 uint64_t i_rsvd_2:2; 982 u64 i_rsvd_2:2;
983 uint64_t i_nb:14; 983 u64 i_nb:14;
984 uint64_t i_rsvd_1:2; 984 u64 i_rsvd_1:2;
985 uint64_t i_m:2; 985 u64 i_m:2;
986 uint64_t i_f:1; 986 u64 i_f:1;
987 uint64_t i_of_cnt:5; 987 u64 i_of_cnt:5;
988 uint64_t i_error:1; 988 u64 i_error:1;
989 uint64_t i_rd_to:1; 989 u64 i_rd_to:1;
990 uint64_t i_spur_wr:1; 990 u64 i_spur_wr:1;
991 uint64_t i_spur_rd:1; 991 u64 i_spur_rd:1;
992 uint64_t i_rsvd:11; 992 u64 i_rsvd:11;
993 uint64_t i_mult_err:1; 993 u64 i_mult_err:1;
994 } ii_iprba_fld_s; 994 } ii_iprba_fld_s;
995} ii_iprba_u_t; 995} ii_iprba_u_t;
996 996
@@ -1019,22 +1019,22 @@ typedef union ii_iprba_u {
1019 ************************************************************************/ 1019 ************************************************************************/
1020 1020
1021typedef union ii_iprbb_u { 1021typedef union ii_iprbb_u {
1022 uint64_t ii_iprbb_regval; 1022 u64 ii_iprbb_regval;
1023 struct { 1023 struct {
1024 uint64_t i_c:8; 1024 u64 i_c:8;
1025 uint64_t i_na:14; 1025 u64 i_na:14;
1026 uint64_t i_rsvd_2:2; 1026 u64 i_rsvd_2:2;
1027 uint64_t i_nb:14; 1027 u64 i_nb:14;
1028 uint64_t i_rsvd_1:2; 1028 u64 i_rsvd_1:2;
1029 uint64_t i_m:2; 1029 u64 i_m:2;
1030 uint64_t i_f:1; 1030 u64 i_f:1;
1031 uint64_t i_of_cnt:5; 1031 u64 i_of_cnt:5;
1032 uint64_t i_error:1; 1032 u64 i_error:1;
1033 uint64_t i_rd_to:1; 1033 u64 i_rd_to:1;
1034 uint64_t i_spur_wr:1; 1034 u64 i_spur_wr:1;
1035 uint64_t i_spur_rd:1; 1035 u64 i_spur_rd:1;
1036 uint64_t i_rsvd:11; 1036 u64 i_rsvd:11;
1037 uint64_t i_mult_err:1; 1037 u64 i_mult_err:1;
1038 } ii_iprbb_fld_s; 1038 } ii_iprbb_fld_s;
1039} ii_iprbb_u_t; 1039} ii_iprbb_u_t;
1040 1040
@@ -1063,22 +1063,22 @@ typedef union ii_iprbb_u {
1063 ************************************************************************/ 1063 ************************************************************************/
1064 1064
1065typedef union ii_iprbc_u { 1065typedef union ii_iprbc_u {
1066 uint64_t ii_iprbc_regval; 1066 u64 ii_iprbc_regval;
1067 struct { 1067 struct {
1068 uint64_t i_c:8; 1068 u64 i_c:8;
1069 uint64_t i_na:14; 1069 u64 i_na:14;
1070 uint64_t i_rsvd_2:2; 1070 u64 i_rsvd_2:2;
1071 uint64_t i_nb:14; 1071 u64 i_nb:14;
1072 uint64_t i_rsvd_1:2; 1072 u64 i_rsvd_1:2;
1073 uint64_t i_m:2; 1073 u64 i_m:2;
1074 uint64_t i_f:1; 1074 u64 i_f:1;
1075 uint64_t i_of_cnt:5; 1075 u64 i_of_cnt:5;
1076 uint64_t i_error:1; 1076 u64 i_error:1;
1077 uint64_t i_rd_to:1; 1077 u64 i_rd_to:1;
1078 uint64_t i_spur_wr:1; 1078 u64 i_spur_wr:1;
1079 uint64_t i_spur_rd:1; 1079 u64 i_spur_rd:1;
1080 uint64_t i_rsvd:11; 1080 u64 i_rsvd:11;
1081 uint64_t i_mult_err:1; 1081 u64 i_mult_err:1;
1082 } ii_iprbc_fld_s; 1082 } ii_iprbc_fld_s;
1083} ii_iprbc_u_t; 1083} ii_iprbc_u_t;
1084 1084
@@ -1107,22 +1107,22 @@ typedef union ii_iprbc_u {
1107 ************************************************************************/ 1107 ************************************************************************/
1108 1108
1109typedef union ii_iprbd_u { 1109typedef union ii_iprbd_u {
1110 uint64_t ii_iprbd_regval; 1110 u64 ii_iprbd_regval;
1111 struct { 1111 struct {
1112 uint64_t i_c:8; 1112 u64 i_c:8;
1113 uint64_t i_na:14; 1113 u64 i_na:14;
1114 uint64_t i_rsvd_2:2; 1114 u64 i_rsvd_2:2;
1115 uint64_t i_nb:14; 1115 u64 i_nb:14;
1116 uint64_t i_rsvd_1:2; 1116 u64 i_rsvd_1:2;
1117 uint64_t i_m:2; 1117 u64 i_m:2;
1118 uint64_t i_f:1; 1118 u64 i_f:1;
1119 uint64_t i_of_cnt:5; 1119 u64 i_of_cnt:5;
1120 uint64_t i_error:1; 1120 u64 i_error:1;
1121 uint64_t i_rd_to:1; 1121 u64 i_rd_to:1;
1122 uint64_t i_spur_wr:1; 1122 u64 i_spur_wr:1;
1123 uint64_t i_spur_rd:1; 1123 u64 i_spur_rd:1;
1124 uint64_t i_rsvd:11; 1124 u64 i_rsvd:11;
1125 uint64_t i_mult_err:1; 1125 u64 i_mult_err:1;
1126 } ii_iprbd_fld_s; 1126 } ii_iprbd_fld_s;
1127} ii_iprbd_u_t; 1127} ii_iprbd_u_t;
1128 1128
@@ -1151,22 +1151,22 @@ typedef union ii_iprbd_u {
1151 ************************************************************************/ 1151 ************************************************************************/
1152 1152
1153typedef union ii_iprbe_u { 1153typedef union ii_iprbe_u {
1154 uint64_t ii_iprbe_regval; 1154 u64 ii_iprbe_regval;
1155 struct { 1155 struct {
1156 uint64_t i_c:8; 1156 u64 i_c:8;
1157 uint64_t i_na:14; 1157 u64 i_na:14;
1158 uint64_t i_rsvd_2:2; 1158 u64 i_rsvd_2:2;
1159 uint64_t i_nb:14; 1159 u64 i_nb:14;
1160 uint64_t i_rsvd_1:2; 1160 u64 i_rsvd_1:2;
1161 uint64_t i_m:2; 1161 u64 i_m:2;
1162 uint64_t i_f:1; 1162 u64 i_f:1;
1163 uint64_t i_of_cnt:5; 1163 u64 i_of_cnt:5;
1164 uint64_t i_error:1; 1164 u64 i_error:1;
1165 uint64_t i_rd_to:1; 1165 u64 i_rd_to:1;
1166 uint64_t i_spur_wr:1; 1166 u64 i_spur_wr:1;
1167 uint64_t i_spur_rd:1; 1167 u64 i_spur_rd:1;
1168 uint64_t i_rsvd:11; 1168 u64 i_rsvd:11;
1169 uint64_t i_mult_err:1; 1169 u64 i_mult_err:1;
1170 } ii_iprbe_fld_s; 1170 } ii_iprbe_fld_s;
1171} ii_iprbe_u_t; 1171} ii_iprbe_u_t;
1172 1172
@@ -1195,22 +1195,22 @@ typedef union ii_iprbe_u {
1195 ************************************************************************/ 1195 ************************************************************************/
1196 1196
1197typedef union ii_iprbf_u { 1197typedef union ii_iprbf_u {
1198 uint64_t ii_iprbf_regval; 1198 u64 ii_iprbf_regval;
1199 struct { 1199 struct {
1200 uint64_t i_c:8; 1200 u64 i_c:8;
1201 uint64_t i_na:14; 1201 u64 i_na:14;
1202 uint64_t i_rsvd_2:2; 1202 u64 i_rsvd_2:2;
1203 uint64_t i_nb:14; 1203 u64 i_nb:14;
1204 uint64_t i_rsvd_1:2; 1204 u64 i_rsvd_1:2;
1205 uint64_t i_m:2; 1205 u64 i_m:2;
1206 uint64_t i_f:1; 1206 u64 i_f:1;
1207 uint64_t i_of_cnt:5; 1207 u64 i_of_cnt:5;
1208 uint64_t i_error:1; 1208 u64 i_error:1;
1209 uint64_t i_rd_to:1; 1209 u64 i_rd_to:1;
1210 uint64_t i_spur_wr:1; 1210 u64 i_spur_wr:1;
1211 uint64_t i_spur_rd:1; 1211 u64 i_spur_rd:1;
1212 uint64_t i_rsvd:11; 1212 u64 i_rsvd:11;
1213 uint64_t i_mult_err:1; 1213 u64 i_mult_err:1;
1214 } ii_iprbe_fld_s; 1214 } ii_iprbe_fld_s;
1215} ii_iprbf_u_t; 1215} ii_iprbf_u_t;
1216 1216
@@ -1232,10 +1232,10 @@ typedef union ii_iprbf_u {
1232 ************************************************************************/ 1232 ************************************************************************/
1233 1233
1234typedef union ii_ixcc_u { 1234typedef union ii_ixcc_u {
1235 uint64_t ii_ixcc_regval; 1235 u64 ii_ixcc_regval;
1236 struct { 1236 struct {
1237 uint64_t i_time_out:26; 1237 u64 i_time_out:26;
1238 uint64_t i_rsvd:38; 1238 u64 i_rsvd:38;
1239 } ii_ixcc_fld_s; 1239 } ii_ixcc_fld_s;
1240} ii_ixcc_u_t; 1240} ii_ixcc_u_t;
1241 1241
@@ -1256,16 +1256,16 @@ typedef union ii_ixcc_u {
1256 ************************************************************************/ 1256 ************************************************************************/
1257 1257
1258typedef union ii_imem_u { 1258typedef union ii_imem_u {
1259 uint64_t ii_imem_regval; 1259 u64 ii_imem_regval;
1260 struct { 1260 struct {
1261 uint64_t i_w0_esd:1; 1261 u64 i_w0_esd:1;
1262 uint64_t i_rsvd_3:3; 1262 u64 i_rsvd_3:3;
1263 uint64_t i_b0_esd:1; 1263 u64 i_b0_esd:1;
1264 uint64_t i_rsvd_2:3; 1264 u64 i_rsvd_2:3;
1265 uint64_t i_b1_esd:1; 1265 u64 i_b1_esd:1;
1266 uint64_t i_rsvd_1:3; 1266 u64 i_rsvd_1:3;
1267 uint64_t i_clr_precise:1; 1267 u64 i_clr_precise:1;
1268 uint64_t i_rsvd:51; 1268 u64 i_rsvd:51;
1269 } ii_imem_fld_s; 1269 } ii_imem_fld_s;
1270} ii_imem_u_t; 1270} ii_imem_u_t;
1271 1271
@@ -1294,13 +1294,13 @@ typedef union ii_imem_u {
1294 ************************************************************************/ 1294 ************************************************************************/
1295 1295
1296typedef union ii_ixtt_u { 1296typedef union ii_ixtt_u {
1297 uint64_t ii_ixtt_regval; 1297 u64 ii_ixtt_regval;
1298 struct { 1298 struct {
1299 uint64_t i_tail_to:26; 1299 u64 i_tail_to:26;
1300 uint64_t i_rsvd_1:6; 1300 u64 i_rsvd_1:6;
1301 uint64_t i_rrsp_ps:23; 1301 u64 i_rrsp_ps:23;
1302 uint64_t i_rrsp_to:5; 1302 u64 i_rrsp_to:5;
1303 uint64_t i_rsvd:4; 1303 u64 i_rsvd:4;
1304 } ii_ixtt_fld_s; 1304 } ii_ixtt_fld_s;
1305} ii_ixtt_u_t; 1305} ii_ixtt_u_t;
1306 1306
@@ -1316,37 +1316,37 @@ typedef union ii_ixtt_u {
1316 ************************************************************************/ 1316 ************************************************************************/
1317 1317
1318typedef union ii_ieclr_u { 1318typedef union ii_ieclr_u {
1319 uint64_t ii_ieclr_regval; 1319 u64 ii_ieclr_regval;
1320 struct { 1320 struct {
1321 uint64_t i_e_prb_0:1; 1321 u64 i_e_prb_0:1;
1322 uint64_t i_rsvd:7; 1322 u64 i_rsvd:7;
1323 uint64_t i_e_prb_8:1; 1323 u64 i_e_prb_8:1;
1324 uint64_t i_e_prb_9:1; 1324 u64 i_e_prb_9:1;
1325 uint64_t i_e_prb_a:1; 1325 u64 i_e_prb_a:1;
1326 uint64_t i_e_prb_b:1; 1326 u64 i_e_prb_b:1;
1327 uint64_t i_e_prb_c:1; 1327 u64 i_e_prb_c:1;
1328 uint64_t i_e_prb_d:1; 1328 u64 i_e_prb_d:1;
1329 uint64_t i_e_prb_e:1; 1329 u64 i_e_prb_e:1;
1330 uint64_t i_e_prb_f:1; 1330 u64 i_e_prb_f:1;
1331 uint64_t i_e_crazy:1; 1331 u64 i_e_crazy:1;
1332 uint64_t i_e_bte_0:1; 1332 u64 i_e_bte_0:1;
1333 uint64_t i_e_bte_1:1; 1333 u64 i_e_bte_1:1;
1334 uint64_t i_reserved_1:10; 1334 u64 i_reserved_1:10;
1335 uint64_t i_spur_rd_hdr:1; 1335 u64 i_spur_rd_hdr:1;
1336 uint64_t i_cam_intr_to:1; 1336 u64 i_cam_intr_to:1;
1337 uint64_t i_cam_overflow:1; 1337 u64 i_cam_overflow:1;
1338 uint64_t i_cam_read_miss:1; 1338 u64 i_cam_read_miss:1;
1339 uint64_t i_ioq_rep_underflow:1; 1339 u64 i_ioq_rep_underflow:1;
1340 uint64_t i_ioq_req_underflow:1; 1340 u64 i_ioq_req_underflow:1;
1341 uint64_t i_ioq_rep_overflow:1; 1341 u64 i_ioq_rep_overflow:1;
1342 uint64_t i_ioq_req_overflow:1; 1342 u64 i_ioq_req_overflow:1;
1343 uint64_t i_iiq_rep_overflow:1; 1343 u64 i_iiq_rep_overflow:1;
1344 uint64_t i_iiq_req_overflow:1; 1344 u64 i_iiq_req_overflow:1;
1345 uint64_t i_ii_xn_rep_cred_overflow:1; 1345 u64 i_ii_xn_rep_cred_overflow:1;
1346 uint64_t i_ii_xn_req_cred_overflow:1; 1346 u64 i_ii_xn_req_cred_overflow:1;
1347 uint64_t i_ii_xn_invalid_cmd:1; 1347 u64 i_ii_xn_invalid_cmd:1;
1348 uint64_t i_xn_ii_invalid_cmd:1; 1348 u64 i_xn_ii_invalid_cmd:1;
1349 uint64_t i_reserved_2:21; 1349 u64 i_reserved_2:21;
1350 } ii_ieclr_fld_s; 1350 } ii_ieclr_fld_s;
1351} ii_ieclr_u_t; 1351} ii_ieclr_u_t;
1352 1352
@@ -1360,12 +1360,12 @@ typedef union ii_ieclr_u {
1360 ************************************************************************/ 1360 ************************************************************************/
1361 1361
1362typedef union ii_ibcr_u { 1362typedef union ii_ibcr_u {
1363 uint64_t ii_ibcr_regval; 1363 u64 ii_ibcr_regval;
1364 struct { 1364 struct {
1365 uint64_t i_count:4; 1365 u64 i_count:4;
1366 uint64_t i_rsvd_1:4; 1366 u64 i_rsvd_1:4;
1367 uint64_t i_soft_reset:1; 1367 u64 i_soft_reset:1;
1368 uint64_t i_rsvd:55; 1368 u64 i_rsvd:55;
1369 } ii_ibcr_fld_s; 1369 } ii_ibcr_fld_s;
1370} ii_ibcr_u_t; 1370} ii_ibcr_u_t;
1371 1371
@@ -1399,22 +1399,22 @@ typedef union ii_ibcr_u {
1399 ************************************************************************/ 1399 ************************************************************************/
1400 1400
1401typedef union ii_ixsm_u { 1401typedef union ii_ixsm_u {
1402 uint64_t ii_ixsm_regval; 1402 u64 ii_ixsm_regval;
1403 struct { 1403 struct {
1404 uint64_t i_byte_en:32; 1404 u64 i_byte_en:32;
1405 uint64_t i_reserved:1; 1405 u64 i_reserved:1;
1406 uint64_t i_tag:3; 1406 u64 i_tag:3;
1407 uint64_t i_alt_pactyp:4; 1407 u64 i_alt_pactyp:4;
1408 uint64_t i_bo:1; 1408 u64 i_bo:1;
1409 uint64_t i_error:1; 1409 u64 i_error:1;
1410 uint64_t i_vbpm:1; 1410 u64 i_vbpm:1;
1411 uint64_t i_gbr:1; 1411 u64 i_gbr:1;
1412 uint64_t i_ds:2; 1412 u64 i_ds:2;
1413 uint64_t i_ct:1; 1413 u64 i_ct:1;
1414 uint64_t i_tnum:5; 1414 u64 i_tnum:5;
1415 uint64_t i_pactyp:4; 1415 u64 i_pactyp:4;
1416 uint64_t i_sidn:4; 1416 u64 i_sidn:4;
1417 uint64_t i_didn:4; 1417 u64 i_didn:4;
1418 } ii_ixsm_fld_s; 1418 } ii_ixsm_fld_s;
1419} ii_ixsm_u_t; 1419} ii_ixsm_u_t;
1420 1420
@@ -1426,11 +1426,11 @@ typedef union ii_ixsm_u {
1426 ************************************************************************/ 1426 ************************************************************************/
1427 1427
1428typedef union ii_ixss_u { 1428typedef union ii_ixss_u {
1429 uint64_t ii_ixss_regval; 1429 u64 ii_ixss_regval;
1430 struct { 1430 struct {
1431 uint64_t i_sideband:8; 1431 u64 i_sideband:8;
1432 uint64_t i_rsvd:55; 1432 u64 i_rsvd:55;
1433 uint64_t i_valid:1; 1433 u64 i_valid:1;
1434 } ii_ixss_fld_s; 1434 } ii_ixss_fld_s;
1435} ii_ixss_u_t; 1435} ii_ixss_u_t;
1436 1436
@@ -1447,17 +1447,17 @@ typedef union ii_ixss_u {
1447 ************************************************************************/ 1447 ************************************************************************/
1448 1448
1449typedef union ii_ilct_u { 1449typedef union ii_ilct_u {
1450 uint64_t ii_ilct_regval; 1450 u64 ii_ilct_regval;
1451 struct { 1451 struct {
1452 uint64_t i_test_seed:20; 1452 u64 i_test_seed:20;
1453 uint64_t i_test_mask:8; 1453 u64 i_test_mask:8;
1454 uint64_t i_test_data:20; 1454 u64 i_test_data:20;
1455 uint64_t i_test_valid:1; 1455 u64 i_test_valid:1;
1456 uint64_t i_test_cberr:1; 1456 u64 i_test_cberr:1;
1457 uint64_t i_test_flit:3; 1457 u64 i_test_flit:3;
1458 uint64_t i_test_clear:1; 1458 u64 i_test_clear:1;
1459 uint64_t i_test_err_capture:1; 1459 u64 i_test_err_capture:1;
1460 uint64_t i_rsvd:9; 1460 u64 i_rsvd:9;
1461 } ii_ilct_fld_s; 1461 } ii_ilct_fld_s;
1462} ii_ilct_u_t; 1462} ii_ilct_u_t;
1463 1463
@@ -1482,20 +1482,20 @@ typedef union ii_ilct_u {
1482 ************************************************************************/ 1482 ************************************************************************/
1483 1483
1484typedef union ii_iieph1_u { 1484typedef union ii_iieph1_u {
1485 uint64_t ii_iieph1_regval; 1485 u64 ii_iieph1_regval;
1486 struct { 1486 struct {
1487 uint64_t i_command:7; 1487 u64 i_command:7;
1488 uint64_t i_rsvd_5:1; 1488 u64 i_rsvd_5:1;
1489 uint64_t i_suppl:14; 1489 u64 i_suppl:14;
1490 uint64_t i_rsvd_4:1; 1490 u64 i_rsvd_4:1;
1491 uint64_t i_source:14; 1491 u64 i_source:14;
1492 uint64_t i_rsvd_3:1; 1492 u64 i_rsvd_3:1;
1493 uint64_t i_err_type:4; 1493 u64 i_err_type:4;
1494 uint64_t i_rsvd_2:4; 1494 u64 i_rsvd_2:4;
1495 uint64_t i_overrun:1; 1495 u64 i_overrun:1;
1496 uint64_t i_rsvd_1:3; 1496 u64 i_rsvd_1:3;
1497 uint64_t i_valid:1; 1497 u64 i_valid:1;
1498 uint64_t i_rsvd:13; 1498 u64 i_rsvd:13;
1499 } ii_iieph1_fld_s; 1499 } ii_iieph1_fld_s;
1500} ii_iieph1_u_t; 1500} ii_iieph1_u_t;
1501 1501
@@ -1511,13 +1511,13 @@ typedef union ii_iieph1_u {
1511 ************************************************************************/ 1511 ************************************************************************/
1512 1512
1513typedef union ii_iieph2_u { 1513typedef union ii_iieph2_u {
1514 uint64_t ii_iieph2_regval; 1514 u64 ii_iieph2_regval;
1515 struct { 1515 struct {
1516 uint64_t i_rsvd_0:3; 1516 u64 i_rsvd_0:3;
1517 uint64_t i_address:47; 1517 u64 i_address:47;
1518 uint64_t i_rsvd_1:10; 1518 u64 i_rsvd_1:10;
1519 uint64_t i_tail:1; 1519 u64 i_tail:1;
1520 uint64_t i_rsvd:3; 1520 u64 i_rsvd:3;
1521 } ii_iieph2_fld_s; 1521 } ii_iieph2_fld_s;
1522} ii_iieph2_u_t; 1522} ii_iieph2_u_t;
1523 1523
@@ -1532,9 +1532,9 @@ typedef union ii_iieph2_u {
1532 ************************************************************************/ 1532 ************************************************************************/
1533 1533
1534typedef union ii_islapr_u { 1534typedef union ii_islapr_u {
1535 uint64_t ii_islapr_regval; 1535 u64 ii_islapr_regval;
1536 struct { 1536 struct {
1537 uint64_t i_region:64; 1537 u64 i_region:64;
1538 } ii_islapr_fld_s; 1538 } ii_islapr_fld_s;
1539} ii_islapr_u_t; 1539} ii_islapr_u_t;
1540 1540
@@ -1547,10 +1547,10 @@ typedef union ii_islapr_u {
1547 ************************************************************************/ 1547 ************************************************************************/
1548 1548
1549typedef union ii_islapo_u { 1549typedef union ii_islapo_u {
1550 uint64_t ii_islapo_regval; 1550 u64 ii_islapo_regval;
1551 struct { 1551 struct {
1552 uint64_t i_io_sbx_ovrride:56; 1552 u64 i_io_sbx_ovrride:56;
1553 uint64_t i_rsvd:8; 1553 u64 i_rsvd:8;
1554 } ii_islapo_fld_s; 1554 } ii_islapo_fld_s;
1555} ii_islapo_u_t; 1555} ii_islapo_u_t;
1556 1556
@@ -1563,14 +1563,14 @@ typedef union ii_islapo_u {
1563 ************************************************************************/ 1563 ************************************************************************/
1564 1564
1565typedef union ii_iwi_u { 1565typedef union ii_iwi_u {
1566 uint64_t ii_iwi_regval; 1566 u64 ii_iwi_regval;
1567 struct { 1567 struct {
1568 uint64_t i_prescale:24; 1568 u64 i_prescale:24;
1569 uint64_t i_rsvd:8; 1569 u64 i_rsvd:8;
1570 uint64_t i_timeout:8; 1570 u64 i_timeout:8;
1571 uint64_t i_rsvd1:8; 1571 u64 i_rsvd1:8;
1572 uint64_t i_intrpt_retry_period:8; 1572 u64 i_intrpt_retry_period:8;
1573 uint64_t i_rsvd2:8; 1573 u64 i_rsvd2:8;
1574 } ii_iwi_fld_s; 1574 } ii_iwi_fld_s;
1575} ii_iwi_u_t; 1575} ii_iwi_u_t;
1576 1576
@@ -1582,26 +1582,26 @@ typedef union ii_iwi_u {
1582 ************************************************************************/ 1582 ************************************************************************/
1583 1583
1584typedef union ii_iwel_u { 1584typedef union ii_iwel_u {
1585 uint64_t ii_iwel_regval; 1585 u64 ii_iwel_regval;
1586 struct { 1586 struct {
1587 uint64_t i_intr_timed_out:1; 1587 u64 i_intr_timed_out:1;
1588 uint64_t i_rsvd:7; 1588 u64 i_rsvd:7;
1589 uint64_t i_cam_overflow:1; 1589 u64 i_cam_overflow:1;
1590 uint64_t i_cam_read_miss:1; 1590 u64 i_cam_read_miss:1;
1591 uint64_t i_rsvd1:2; 1591 u64 i_rsvd1:2;
1592 uint64_t i_ioq_rep_underflow:1; 1592 u64 i_ioq_rep_underflow:1;
1593 uint64_t i_ioq_req_underflow:1; 1593 u64 i_ioq_req_underflow:1;
1594 uint64_t i_ioq_rep_overflow:1; 1594 u64 i_ioq_rep_overflow:1;
1595 uint64_t i_ioq_req_overflow:1; 1595 u64 i_ioq_req_overflow:1;
1596 uint64_t i_iiq_rep_overflow:1; 1596 u64 i_iiq_rep_overflow:1;
1597 uint64_t i_iiq_req_overflow:1; 1597 u64 i_iiq_req_overflow:1;
1598 uint64_t i_rsvd2:6; 1598 u64 i_rsvd2:6;
1599 uint64_t i_ii_xn_rep_cred_over_under:1; 1599 u64 i_ii_xn_rep_cred_over_under:1;
1600 uint64_t i_ii_xn_req_cred_over_under:1; 1600 u64 i_ii_xn_req_cred_over_under:1;
1601 uint64_t i_rsvd3:6; 1601 u64 i_rsvd3:6;
1602 uint64_t i_ii_xn_invalid_cmd:1; 1602 u64 i_ii_xn_invalid_cmd:1;
1603 uint64_t i_xn_ii_invalid_cmd:1; 1603 u64 i_xn_ii_invalid_cmd:1;
1604 uint64_t i_rsvd4:30; 1604 u64 i_rsvd4:30;
1605 } ii_iwel_fld_s; 1605 } ii_iwel_fld_s;
1606} ii_iwel_u_t; 1606} ii_iwel_u_t;
1607 1607
@@ -1612,22 +1612,22 @@ typedef union ii_iwel_u {
1612 ************************************************************************/ 1612 ************************************************************************/
1613 1613
1614typedef union ii_iwc_u { 1614typedef union ii_iwc_u {
1615 uint64_t ii_iwc_regval; 1615 u64 ii_iwc_regval;
1616 struct { 1616 struct {
1617 uint64_t i_dma_byte_swap:1; 1617 u64 i_dma_byte_swap:1;
1618 uint64_t i_rsvd:3; 1618 u64 i_rsvd:3;
1619 uint64_t i_cam_read_lines_reset:1; 1619 u64 i_cam_read_lines_reset:1;
1620 uint64_t i_rsvd1:3; 1620 u64 i_rsvd1:3;
1621 uint64_t i_ii_xn_cred_over_under_log:1; 1621 u64 i_ii_xn_cred_over_under_log:1;
1622 uint64_t i_rsvd2:19; 1622 u64 i_rsvd2:19;
1623 uint64_t i_xn_rep_iq_depth:5; 1623 u64 i_xn_rep_iq_depth:5;
1624 uint64_t i_rsvd3:3; 1624 u64 i_rsvd3:3;
1625 uint64_t i_xn_req_iq_depth:5; 1625 u64 i_xn_req_iq_depth:5;
1626 uint64_t i_rsvd4:3; 1626 u64 i_rsvd4:3;
1627 uint64_t i_iiq_depth:6; 1627 u64 i_iiq_depth:6;
1628 uint64_t i_rsvd5:12; 1628 u64 i_rsvd5:12;
1629 uint64_t i_force_rep_cred:1; 1629 u64 i_force_rep_cred:1;
1630 uint64_t i_force_req_cred:1; 1630 u64 i_force_req_cred:1;
1631 } ii_iwc_fld_s; 1631 } ii_iwc_fld_s;
1632} ii_iwc_u_t; 1632} ii_iwc_u_t;
1633 1633
@@ -1638,12 +1638,12 @@ typedef union ii_iwc_u {
1638 ************************************************************************/ 1638 ************************************************************************/
1639 1639
1640typedef union ii_iws_u { 1640typedef union ii_iws_u {
1641 uint64_t ii_iws_regval; 1641 u64 ii_iws_regval;
1642 struct { 1642 struct {
1643 uint64_t i_xn_rep_iq_credits:5; 1643 u64 i_xn_rep_iq_credits:5;
1644 uint64_t i_rsvd:3; 1644 u64 i_rsvd:3;
1645 uint64_t i_xn_req_iq_credits:5; 1645 u64 i_xn_req_iq_credits:5;
1646 uint64_t i_rsvd1:51; 1646 u64 i_rsvd1:51;
1647 } ii_iws_fld_s; 1647 } ii_iws_fld_s;
1648} ii_iws_u_t; 1648} ii_iws_u_t;
1649 1649
@@ -1654,26 +1654,26 @@ typedef union ii_iws_u {
1654 ************************************************************************/ 1654 ************************************************************************/
1655 1655
1656typedef union ii_iweim_u { 1656typedef union ii_iweim_u {
1657 uint64_t ii_iweim_regval; 1657 u64 ii_iweim_regval;
1658 struct { 1658 struct {
1659 uint64_t i_intr_timed_out:1; 1659 u64 i_intr_timed_out:1;
1660 uint64_t i_rsvd:7; 1660 u64 i_rsvd:7;
1661 uint64_t i_cam_overflow:1; 1661 u64 i_cam_overflow:1;
1662 uint64_t i_cam_read_miss:1; 1662 u64 i_cam_read_miss:1;
1663 uint64_t i_rsvd1:2; 1663 u64 i_rsvd1:2;
1664 uint64_t i_ioq_rep_underflow:1; 1664 u64 i_ioq_rep_underflow:1;
1665 uint64_t i_ioq_req_underflow:1; 1665 u64 i_ioq_req_underflow:1;
1666 uint64_t i_ioq_rep_overflow:1; 1666 u64 i_ioq_rep_overflow:1;
1667 uint64_t i_ioq_req_overflow:1; 1667 u64 i_ioq_req_overflow:1;
1668 uint64_t i_iiq_rep_overflow:1; 1668 u64 i_iiq_rep_overflow:1;
1669 uint64_t i_iiq_req_overflow:1; 1669 u64 i_iiq_req_overflow:1;
1670 uint64_t i_rsvd2:6; 1670 u64 i_rsvd2:6;
1671 uint64_t i_ii_xn_rep_cred_overflow:1; 1671 u64 i_ii_xn_rep_cred_overflow:1;
1672 uint64_t i_ii_xn_req_cred_overflow:1; 1672 u64 i_ii_xn_req_cred_overflow:1;
1673 uint64_t i_rsvd3:6; 1673 u64 i_rsvd3:6;
1674 uint64_t i_ii_xn_invalid_cmd:1; 1674 u64 i_ii_xn_invalid_cmd:1;
1675 uint64_t i_xn_ii_invalid_cmd:1; 1675 u64 i_xn_ii_invalid_cmd:1;
1676 uint64_t i_rsvd4:30; 1676 u64 i_rsvd4:30;
1677 } ii_iweim_fld_s; 1677 } ii_iweim_fld_s;
1678} ii_iweim_u_t; 1678} ii_iweim_u_t;
1679 1679
@@ -1688,13 +1688,13 @@ typedef union ii_iweim_u {
1688 ************************************************************************/ 1688 ************************************************************************/
1689 1689
1690typedef union ii_ipca_u { 1690typedef union ii_ipca_u {
1691 uint64_t ii_ipca_regval; 1691 u64 ii_ipca_regval;
1692 struct { 1692 struct {
1693 uint64_t i_wid:4; 1693 u64 i_wid:4;
1694 uint64_t i_adjust:1; 1694 u64 i_adjust:1;
1695 uint64_t i_rsvd_1:3; 1695 u64 i_rsvd_1:3;
1696 uint64_t i_field:2; 1696 u64 i_field:2;
1697 uint64_t i_rsvd:54; 1697 u64 i_rsvd:54;
1698 } ii_ipca_fld_s; 1698 } ii_ipca_fld_s;
1699} ii_ipca_u_t; 1699} ii_ipca_u_t;
1700 1700
@@ -1709,12 +1709,12 @@ typedef union ii_ipca_u {
1709 ************************************************************************/ 1709 ************************************************************************/
1710 1710
1711typedef union ii_iprte0a_u { 1711typedef union ii_iprte0a_u {
1712 uint64_t ii_iprte0a_regval; 1712 u64 ii_iprte0a_regval;
1713 struct { 1713 struct {
1714 uint64_t i_rsvd_1:54; 1714 u64 i_rsvd_1:54;
1715 uint64_t i_widget:4; 1715 u64 i_widget:4;
1716 uint64_t i_to_cnt:5; 1716 u64 i_to_cnt:5;
1717 uint64_t i_vld:1; 1717 u64 i_vld:1;
1718 } ii_iprte0a_fld_s; 1718 } ii_iprte0a_fld_s;
1719} ii_iprte0a_u_t; 1719} ii_iprte0a_u_t;
1720 1720
@@ -1729,12 +1729,12 @@ typedef union ii_iprte0a_u {
1729 ************************************************************************/ 1729 ************************************************************************/
1730 1730
1731typedef union ii_iprte1a_u { 1731typedef union ii_iprte1a_u {
1732 uint64_t ii_iprte1a_regval; 1732 u64 ii_iprte1a_regval;
1733 struct { 1733 struct {
1734 uint64_t i_rsvd_1:54; 1734 u64 i_rsvd_1:54;
1735 uint64_t i_widget:4; 1735 u64 i_widget:4;
1736 uint64_t i_to_cnt:5; 1736 u64 i_to_cnt:5;
1737 uint64_t i_vld:1; 1737 u64 i_vld:1;
1738 } ii_iprte1a_fld_s; 1738 } ii_iprte1a_fld_s;
1739} ii_iprte1a_u_t; 1739} ii_iprte1a_u_t;
1740 1740
@@ -1749,12 +1749,12 @@ typedef union ii_iprte1a_u {
1749 ************************************************************************/ 1749 ************************************************************************/
1750 1750
1751typedef union ii_iprte2a_u { 1751typedef union ii_iprte2a_u {
1752 uint64_t ii_iprte2a_regval; 1752 u64 ii_iprte2a_regval;
1753 struct { 1753 struct {
1754 uint64_t i_rsvd_1:54; 1754 u64 i_rsvd_1:54;
1755 uint64_t i_widget:4; 1755 u64 i_widget:4;
1756 uint64_t i_to_cnt:5; 1756 u64 i_to_cnt:5;
1757 uint64_t i_vld:1; 1757 u64 i_vld:1;
1758 } ii_iprte2a_fld_s; 1758 } ii_iprte2a_fld_s;
1759} ii_iprte2a_u_t; 1759} ii_iprte2a_u_t;
1760 1760
@@ -1769,12 +1769,12 @@ typedef union ii_iprte2a_u {
1769 ************************************************************************/ 1769 ************************************************************************/
1770 1770
1771typedef union ii_iprte3a_u { 1771typedef union ii_iprte3a_u {
1772 uint64_t ii_iprte3a_regval; 1772 u64 ii_iprte3a_regval;
1773 struct { 1773 struct {
1774 uint64_t i_rsvd_1:54; 1774 u64 i_rsvd_1:54;
1775 uint64_t i_widget:4; 1775 u64 i_widget:4;
1776 uint64_t i_to_cnt:5; 1776 u64 i_to_cnt:5;
1777 uint64_t i_vld:1; 1777 u64 i_vld:1;
1778 } ii_iprte3a_fld_s; 1778 } ii_iprte3a_fld_s;
1779} ii_iprte3a_u_t; 1779} ii_iprte3a_u_t;
1780 1780
@@ -1789,12 +1789,12 @@ typedef union ii_iprte3a_u {
1789 ************************************************************************/ 1789 ************************************************************************/
1790 1790
1791typedef union ii_iprte4a_u { 1791typedef union ii_iprte4a_u {
1792 uint64_t ii_iprte4a_regval; 1792 u64 ii_iprte4a_regval;
1793 struct { 1793 struct {
1794 uint64_t i_rsvd_1:54; 1794 u64 i_rsvd_1:54;
1795 uint64_t i_widget:4; 1795 u64 i_widget:4;
1796 uint64_t i_to_cnt:5; 1796 u64 i_to_cnt:5;
1797 uint64_t i_vld:1; 1797 u64 i_vld:1;
1798 } ii_iprte4a_fld_s; 1798 } ii_iprte4a_fld_s;
1799} ii_iprte4a_u_t; 1799} ii_iprte4a_u_t;
1800 1800
@@ -1809,12 +1809,12 @@ typedef union ii_iprte4a_u {
1809 ************************************************************************/ 1809 ************************************************************************/
1810 1810
1811typedef union ii_iprte5a_u { 1811typedef union ii_iprte5a_u {
1812 uint64_t ii_iprte5a_regval; 1812 u64 ii_iprte5a_regval;
1813 struct { 1813 struct {
1814 uint64_t i_rsvd_1:54; 1814 u64 i_rsvd_1:54;
1815 uint64_t i_widget:4; 1815 u64 i_widget:4;
1816 uint64_t i_to_cnt:5; 1816 u64 i_to_cnt:5;
1817 uint64_t i_vld:1; 1817 u64 i_vld:1;
1818 } ii_iprte5a_fld_s; 1818 } ii_iprte5a_fld_s;
1819} ii_iprte5a_u_t; 1819} ii_iprte5a_u_t;
1820 1820
@@ -1829,12 +1829,12 @@ typedef union ii_iprte5a_u {
1829 ************************************************************************/ 1829 ************************************************************************/
1830 1830
1831typedef union ii_iprte6a_u { 1831typedef union ii_iprte6a_u {
1832 uint64_t ii_iprte6a_regval; 1832 u64 ii_iprte6a_regval;
1833 struct { 1833 struct {
1834 uint64_t i_rsvd_1:54; 1834 u64 i_rsvd_1:54;
1835 uint64_t i_widget:4; 1835 u64 i_widget:4;
1836 uint64_t i_to_cnt:5; 1836 u64 i_to_cnt:5;
1837 uint64_t i_vld:1; 1837 u64 i_vld:1;
1838 } ii_iprte6a_fld_s; 1838 } ii_iprte6a_fld_s;
1839} ii_iprte6a_u_t; 1839} ii_iprte6a_u_t;
1840 1840
@@ -1849,12 +1849,12 @@ typedef union ii_iprte6a_u {
1849 ************************************************************************/ 1849 ************************************************************************/
1850 1850
1851typedef union ii_iprte7a_u { 1851typedef union ii_iprte7a_u {
1852 uint64_t ii_iprte7a_regval; 1852 u64 ii_iprte7a_regval;
1853 struct { 1853 struct {
1854 uint64_t i_rsvd_1:54; 1854 u64 i_rsvd_1:54;
1855 uint64_t i_widget:4; 1855 u64 i_widget:4;
1856 uint64_t i_to_cnt:5; 1856 u64 i_to_cnt:5;
1857 uint64_t i_vld:1; 1857 u64 i_vld:1;
1858 } ii_iprtea7_fld_s; 1858 } ii_iprtea7_fld_s;
1859} ii_iprte7a_u_t; 1859} ii_iprte7a_u_t;
1860 1860
@@ -1869,12 +1869,12 @@ typedef union ii_iprte7a_u {
1869 ************************************************************************/ 1869 ************************************************************************/
1870 1870
1871typedef union ii_iprte0b_u { 1871typedef union ii_iprte0b_u {
1872 uint64_t ii_iprte0b_regval; 1872 u64 ii_iprte0b_regval;
1873 struct { 1873 struct {
1874 uint64_t i_rsvd_1:3; 1874 u64 i_rsvd_1:3;
1875 uint64_t i_address:47; 1875 u64 i_address:47;
1876 uint64_t i_init:3; 1876 u64 i_init:3;
1877 uint64_t i_source:11; 1877 u64 i_source:11;
1878 } ii_iprte0b_fld_s; 1878 } ii_iprte0b_fld_s;
1879} ii_iprte0b_u_t; 1879} ii_iprte0b_u_t;
1880 1880
@@ -1889,12 +1889,12 @@ typedef union ii_iprte0b_u {
1889 ************************************************************************/ 1889 ************************************************************************/
1890 1890
1891typedef union ii_iprte1b_u { 1891typedef union ii_iprte1b_u {
1892 uint64_t ii_iprte1b_regval; 1892 u64 ii_iprte1b_regval;
1893 struct { 1893 struct {
1894 uint64_t i_rsvd_1:3; 1894 u64 i_rsvd_1:3;
1895 uint64_t i_address:47; 1895 u64 i_address:47;
1896 uint64_t i_init:3; 1896 u64 i_init:3;
1897 uint64_t i_source:11; 1897 u64 i_source:11;
1898 } ii_iprte1b_fld_s; 1898 } ii_iprte1b_fld_s;
1899} ii_iprte1b_u_t; 1899} ii_iprte1b_u_t;
1900 1900
@@ -1909,12 +1909,12 @@ typedef union ii_iprte1b_u {
1909 ************************************************************************/ 1909 ************************************************************************/
1910 1910
1911typedef union ii_iprte2b_u { 1911typedef union ii_iprte2b_u {
1912 uint64_t ii_iprte2b_regval; 1912 u64 ii_iprte2b_regval;
1913 struct { 1913 struct {
1914 uint64_t i_rsvd_1:3; 1914 u64 i_rsvd_1:3;
1915 uint64_t i_address:47; 1915 u64 i_address:47;
1916 uint64_t i_init:3; 1916 u64 i_init:3;
1917 uint64_t i_source:11; 1917 u64 i_source:11;
1918 } ii_iprte2b_fld_s; 1918 } ii_iprte2b_fld_s;
1919} ii_iprte2b_u_t; 1919} ii_iprte2b_u_t;
1920 1920
@@ -1929,12 +1929,12 @@ typedef union ii_iprte2b_u {
1929 ************************************************************************/ 1929 ************************************************************************/
1930 1930
1931typedef union ii_iprte3b_u { 1931typedef union ii_iprte3b_u {
1932 uint64_t ii_iprte3b_regval; 1932 u64 ii_iprte3b_regval;
1933 struct { 1933 struct {
1934 uint64_t i_rsvd_1:3; 1934 u64 i_rsvd_1:3;
1935 uint64_t i_address:47; 1935 u64 i_address:47;
1936 uint64_t i_init:3; 1936 u64 i_init:3;
1937 uint64_t i_source:11; 1937 u64 i_source:11;
1938 } ii_iprte3b_fld_s; 1938 } ii_iprte3b_fld_s;
1939} ii_iprte3b_u_t; 1939} ii_iprte3b_u_t;
1940 1940
@@ -1949,12 +1949,12 @@ typedef union ii_iprte3b_u {
1949 ************************************************************************/ 1949 ************************************************************************/
1950 1950
1951typedef union ii_iprte4b_u { 1951typedef union ii_iprte4b_u {
1952 uint64_t ii_iprte4b_regval; 1952 u64 ii_iprte4b_regval;
1953 struct { 1953 struct {
1954 uint64_t i_rsvd_1:3; 1954 u64 i_rsvd_1:3;
1955 uint64_t i_address:47; 1955 u64 i_address:47;
1956 uint64_t i_init:3; 1956 u64 i_init:3;
1957 uint64_t i_source:11; 1957 u64 i_source:11;
1958 } ii_iprte4b_fld_s; 1958 } ii_iprte4b_fld_s;
1959} ii_iprte4b_u_t; 1959} ii_iprte4b_u_t;
1960 1960
@@ -1969,12 +1969,12 @@ typedef union ii_iprte4b_u {
1969 ************************************************************************/ 1969 ************************************************************************/
1970 1970
1971typedef union ii_iprte5b_u { 1971typedef union ii_iprte5b_u {
1972 uint64_t ii_iprte5b_regval; 1972 u64 ii_iprte5b_regval;
1973 struct { 1973 struct {
1974 uint64_t i_rsvd_1:3; 1974 u64 i_rsvd_1:3;
1975 uint64_t i_address:47; 1975 u64 i_address:47;
1976 uint64_t i_init:3; 1976 u64 i_init:3;
1977 uint64_t i_source:11; 1977 u64 i_source:11;
1978 } ii_iprte5b_fld_s; 1978 } ii_iprte5b_fld_s;
1979} ii_iprte5b_u_t; 1979} ii_iprte5b_u_t;
1980 1980
@@ -1989,12 +1989,12 @@ typedef union ii_iprte5b_u {
1989 ************************************************************************/ 1989 ************************************************************************/
1990 1990
1991typedef union ii_iprte6b_u { 1991typedef union ii_iprte6b_u {
1992 uint64_t ii_iprte6b_regval; 1992 u64 ii_iprte6b_regval;
1993 struct { 1993 struct {
1994 uint64_t i_rsvd_1:3; 1994 u64 i_rsvd_1:3;
1995 uint64_t i_address:47; 1995 u64 i_address:47;
1996 uint64_t i_init:3; 1996 u64 i_init:3;
1997 uint64_t i_source:11; 1997 u64 i_source:11;
1998 1998
1999 } ii_iprte6b_fld_s; 1999 } ii_iprte6b_fld_s;
2000} ii_iprte6b_u_t; 2000} ii_iprte6b_u_t;
@@ -2010,12 +2010,12 @@ typedef union ii_iprte6b_u {
2010 ************************************************************************/ 2010 ************************************************************************/
2011 2011
2012typedef union ii_iprte7b_u { 2012typedef union ii_iprte7b_u {
2013 uint64_t ii_iprte7b_regval; 2013 u64 ii_iprte7b_regval;
2014 struct { 2014 struct {
2015 uint64_t i_rsvd_1:3; 2015 u64 i_rsvd_1:3;
2016 uint64_t i_address:47; 2016 u64 i_address:47;
2017 uint64_t i_init:3; 2017 u64 i_init:3;
2018 uint64_t i_source:11; 2018 u64 i_source:11;
2019 } ii_iprte7b_fld_s; 2019 } ii_iprte7b_fld_s;
2020} ii_iprte7b_u_t; 2020} ii_iprte7b_u_t;
2021 2021
@@ -2038,13 +2038,13 @@ typedef union ii_iprte7b_u {
2038 ************************************************************************/ 2038 ************************************************************************/
2039 2039
2040typedef union ii_ipdr_u { 2040typedef union ii_ipdr_u {
2041 uint64_t ii_ipdr_regval; 2041 u64 ii_ipdr_regval;
2042 struct { 2042 struct {
2043 uint64_t i_te:3; 2043 u64 i_te:3;
2044 uint64_t i_rsvd_1:1; 2044 u64 i_rsvd_1:1;
2045 uint64_t i_pnd:1; 2045 u64 i_pnd:1;
2046 uint64_t i_init_rpcnt:1; 2046 u64 i_init_rpcnt:1;
2047 uint64_t i_rsvd:58; 2047 u64 i_rsvd:58;
2048 } ii_ipdr_fld_s; 2048 } ii_ipdr_fld_s;
2049} ii_ipdr_u_t; 2049} ii_ipdr_u_t;
2050 2050
@@ -2066,11 +2066,11 @@ typedef union ii_ipdr_u {
2066 ************************************************************************/ 2066 ************************************************************************/
2067 2067
2068typedef union ii_icdr_u { 2068typedef union ii_icdr_u {
2069 uint64_t ii_icdr_regval; 2069 u64 ii_icdr_regval;
2070 struct { 2070 struct {
2071 uint64_t i_crb_num:4; 2071 u64 i_crb_num:4;
2072 uint64_t i_pnd:1; 2072 u64 i_pnd:1;
2073 uint64_t i_rsvd:59; 2073 u64 i_rsvd:59;
2074 } ii_icdr_fld_s; 2074 } ii_icdr_fld_s;
2075} ii_icdr_u_t; 2075} ii_icdr_u_t;
2076 2076
@@ -2092,13 +2092,13 @@ typedef union ii_icdr_u {
2092 ************************************************************************/ 2092 ************************************************************************/
2093 2093
2094typedef union ii_ifdr_u { 2094typedef union ii_ifdr_u {
2095 uint64_t ii_ifdr_regval; 2095 u64 ii_ifdr_regval;
2096 struct { 2096 struct {
2097 uint64_t i_ioq_max_rq:7; 2097 u64 i_ioq_max_rq:7;
2098 uint64_t i_set_ioq_rq:1; 2098 u64 i_set_ioq_rq:1;
2099 uint64_t i_ioq_max_rp:7; 2099 u64 i_ioq_max_rp:7;
2100 uint64_t i_set_ioq_rp:1; 2100 u64 i_set_ioq_rp:1;
2101 uint64_t i_rsvd:48; 2101 u64 i_rsvd:48;
2102 } ii_ifdr_fld_s; 2102 } ii_ifdr_fld_s;
2103} ii_ifdr_u_t; 2103} ii_ifdr_u_t;
2104 2104
@@ -2114,12 +2114,12 @@ typedef union ii_ifdr_u {
2114 ************************************************************************/ 2114 ************************************************************************/
2115 2115
2116typedef union ii_iiap_u { 2116typedef union ii_iiap_u {
2117 uint64_t ii_iiap_regval; 2117 u64 ii_iiap_regval;
2118 struct { 2118 struct {
2119 uint64_t i_rq_mls:6; 2119 u64 i_rq_mls:6;
2120 uint64_t i_rsvd_1:2; 2120 u64 i_rsvd_1:2;
2121 uint64_t i_rp_mls:6; 2121 u64 i_rp_mls:6;
2122 uint64_t i_rsvd:50; 2122 u64 i_rsvd:50;
2123 } ii_iiap_fld_s; 2123 } ii_iiap_fld_s;
2124} ii_iiap_u_t; 2124} ii_iiap_u_t;
2125 2125
@@ -2133,22 +2133,22 @@ typedef union ii_iiap_u {
2133 ************************************************************************/ 2133 ************************************************************************/
2134 2134
2135typedef union ii_icmr_u { 2135typedef union ii_icmr_u {
2136 uint64_t ii_icmr_regval; 2136 u64 ii_icmr_regval;
2137 struct { 2137 struct {
2138 uint64_t i_sp_msg:1; 2138 u64 i_sp_msg:1;
2139 uint64_t i_rd_hdr:1; 2139 u64 i_rd_hdr:1;
2140 uint64_t i_rsvd_4:2; 2140 u64 i_rsvd_4:2;
2141 uint64_t i_c_cnt:4; 2141 u64 i_c_cnt:4;
2142 uint64_t i_rsvd_3:4; 2142 u64 i_rsvd_3:4;
2143 uint64_t i_clr_rqpd:1; 2143 u64 i_clr_rqpd:1;
2144 uint64_t i_clr_rppd:1; 2144 u64 i_clr_rppd:1;
2145 uint64_t i_rsvd_2:2; 2145 u64 i_rsvd_2:2;
2146 uint64_t i_fc_cnt:4; 2146 u64 i_fc_cnt:4;
2147 uint64_t i_crb_vld:15; 2147 u64 i_crb_vld:15;
2148 uint64_t i_crb_mark:15; 2148 u64 i_crb_mark:15;
2149 uint64_t i_rsvd_1:2; 2149 u64 i_rsvd_1:2;
2150 uint64_t i_precise:1; 2150 u64 i_precise:1;
2151 uint64_t i_rsvd:11; 2151 u64 i_rsvd:11;
2152 } ii_icmr_fld_s; 2152 } ii_icmr_fld_s;
2153} ii_icmr_u_t; 2153} ii_icmr_u_t;
2154 2154
@@ -2161,13 +2161,13 @@ typedef union ii_icmr_u {
2161 ************************************************************************/ 2161 ************************************************************************/
2162 2162
2163typedef union ii_iccr_u { 2163typedef union ii_iccr_u {
2164 uint64_t ii_iccr_regval; 2164 u64 ii_iccr_regval;
2165 struct { 2165 struct {
2166 uint64_t i_crb_num:4; 2166 u64 i_crb_num:4;
2167 uint64_t i_rsvd_1:4; 2167 u64 i_rsvd_1:4;
2168 uint64_t i_cmd:8; 2168 u64 i_cmd:8;
2169 uint64_t i_pending:1; 2169 u64 i_pending:1;
2170 uint64_t i_rsvd:47; 2170 u64 i_rsvd:47;
2171 } ii_iccr_fld_s; 2171 } ii_iccr_fld_s;
2172} ii_iccr_u_t; 2172} ii_iccr_u_t;
2173 2173
@@ -2178,10 +2178,10 @@ typedef union ii_iccr_u {
2178 ************************************************************************/ 2178 ************************************************************************/
2179 2179
2180typedef union ii_icto_u { 2180typedef union ii_icto_u {
2181 uint64_t ii_icto_regval; 2181 u64 ii_icto_regval;
2182 struct { 2182 struct {
2183 uint64_t i_timeout:8; 2183 u64 i_timeout:8;
2184 uint64_t i_rsvd:56; 2184 u64 i_rsvd:56;
2185 } ii_icto_fld_s; 2185 } ii_icto_fld_s;
2186} ii_icto_u_t; 2186} ii_icto_u_t;
2187 2187
@@ -2197,10 +2197,10 @@ typedef union ii_icto_u {
2197 ************************************************************************/ 2197 ************************************************************************/
2198 2198
2199typedef union ii_ictp_u { 2199typedef union ii_ictp_u {
2200 uint64_t ii_ictp_regval; 2200 u64 ii_ictp_regval;
2201 struct { 2201 struct {
2202 uint64_t i_prescale:24; 2202 u64 i_prescale:24;
2203 uint64_t i_rsvd:40; 2203 u64 i_rsvd:40;
2204 } ii_ictp_fld_s; 2204 } ii_ictp_fld_s;
2205} ii_ictp_u_t; 2205} ii_ictp_u_t;
2206 2206
@@ -2228,14 +2228,14 @@ typedef union ii_ictp_u {
2228 ************************************************************************/ 2228 ************************************************************************/
2229 2229
2230typedef union ii_icrb0_a_u { 2230typedef union ii_icrb0_a_u {
2231 uint64_t ii_icrb0_a_regval; 2231 u64 ii_icrb0_a_regval;
2232 struct { 2232 struct {
2233 uint64_t ia_iow:1; 2233 u64 ia_iow:1;
2234 uint64_t ia_vld:1; 2234 u64 ia_vld:1;
2235 uint64_t ia_addr:47; 2235 u64 ia_addr:47;
2236 uint64_t ia_tnum:5; 2236 u64 ia_tnum:5;
2237 uint64_t ia_sidn:4; 2237 u64 ia_sidn:4;
2238 uint64_t ia_rsvd:6; 2238 u64 ia_rsvd:6;
2239 } ii_icrb0_a_fld_s; 2239 } ii_icrb0_a_fld_s;
2240} ii_icrb0_a_u_t; 2240} ii_icrb0_a_u_t;
2241 2241
@@ -2249,30 +2249,30 @@ typedef union ii_icrb0_a_u {
2249 ************************************************************************/ 2249 ************************************************************************/
2250 2250
2251typedef union ii_icrb0_b_u { 2251typedef union ii_icrb0_b_u {
2252 uint64_t ii_icrb0_b_regval; 2252 u64 ii_icrb0_b_regval;
2253 struct { 2253 struct {
2254 uint64_t ib_xt_err:1; 2254 u64 ib_xt_err:1;
2255 uint64_t ib_mark:1; 2255 u64 ib_mark:1;
2256 uint64_t ib_ln_uce:1; 2256 u64 ib_ln_uce:1;
2257 uint64_t ib_errcode:3; 2257 u64 ib_errcode:3;
2258 uint64_t ib_error:1; 2258 u64 ib_error:1;
2259 uint64_t ib_stall__bte_1:1; 2259 u64 ib_stall__bte_1:1;
2260 uint64_t ib_stall__bte_0:1; 2260 u64 ib_stall__bte_0:1;
2261 uint64_t ib_stall__intr:1; 2261 u64 ib_stall__intr:1;
2262 uint64_t ib_stall_ib:1; 2262 u64 ib_stall_ib:1;
2263 uint64_t ib_intvn:1; 2263 u64 ib_intvn:1;
2264 uint64_t ib_wb:1; 2264 u64 ib_wb:1;
2265 uint64_t ib_hold:1; 2265 u64 ib_hold:1;
2266 uint64_t ib_ack:1; 2266 u64 ib_ack:1;
2267 uint64_t ib_resp:1; 2267 u64 ib_resp:1;
2268 uint64_t ib_ack_cnt:11; 2268 u64 ib_ack_cnt:11;
2269 uint64_t ib_rsvd:7; 2269 u64 ib_rsvd:7;
2270 uint64_t ib_exc:5; 2270 u64 ib_exc:5;
2271 uint64_t ib_init:3; 2271 u64 ib_init:3;
2272 uint64_t ib_imsg:8; 2272 u64 ib_imsg:8;
2273 uint64_t ib_imsgtype:2; 2273 u64 ib_imsgtype:2;
2274 uint64_t ib_use_old:1; 2274 u64 ib_use_old:1;
2275 uint64_t ib_rsvd_1:11; 2275 u64 ib_rsvd_1:11;
2276 } ii_icrb0_b_fld_s; 2276 } ii_icrb0_b_fld_s;
2277} ii_icrb0_b_u_t; 2277} ii_icrb0_b_u_t;
2278 2278
@@ -2286,17 +2286,17 @@ typedef union ii_icrb0_b_u {
2286 ************************************************************************/ 2286 ************************************************************************/
2287 2287
2288typedef union ii_icrb0_c_u { 2288typedef union ii_icrb0_c_u {
2289 uint64_t ii_icrb0_c_regval; 2289 u64 ii_icrb0_c_regval;
2290 struct { 2290 struct {
2291 uint64_t ic_source:15; 2291 u64 ic_source:15;
2292 uint64_t ic_size:2; 2292 u64 ic_size:2;
2293 uint64_t ic_ct:1; 2293 u64 ic_ct:1;
2294 uint64_t ic_bte_num:1; 2294 u64 ic_bte_num:1;
2295 uint64_t ic_gbr:1; 2295 u64 ic_gbr:1;
2296 uint64_t ic_resprqd:1; 2296 u64 ic_resprqd:1;
2297 uint64_t ic_bo:1; 2297 u64 ic_bo:1;
2298 uint64_t ic_suppl:15; 2298 u64 ic_suppl:15;
2299 uint64_t ic_rsvd:27; 2299 u64 ic_rsvd:27;
2300 } ii_icrb0_c_fld_s; 2300 } ii_icrb0_c_fld_s;
2301} ii_icrb0_c_u_t; 2301} ii_icrb0_c_u_t;
2302 2302
@@ -2310,14 +2310,14 @@ typedef union ii_icrb0_c_u {
2310 ************************************************************************/ 2310 ************************************************************************/
2311 2311
2312typedef union ii_icrb0_d_u { 2312typedef union ii_icrb0_d_u {
2313 uint64_t ii_icrb0_d_regval; 2313 u64 ii_icrb0_d_regval;
2314 struct { 2314 struct {
2315 uint64_t id_pa_be:43; 2315 u64 id_pa_be:43;
2316 uint64_t id_bte_op:1; 2316 u64 id_bte_op:1;
2317 uint64_t id_pr_psc:4; 2317 u64 id_pr_psc:4;
2318 uint64_t id_pr_cnt:4; 2318 u64 id_pr_cnt:4;
2319 uint64_t id_sleep:1; 2319 u64 id_sleep:1;
2320 uint64_t id_rsvd:11; 2320 u64 id_rsvd:11;
2321 } ii_icrb0_d_fld_s; 2321 } ii_icrb0_d_fld_s;
2322} ii_icrb0_d_u_t; 2322} ii_icrb0_d_u_t;
2323 2323
@@ -2331,14 +2331,14 @@ typedef union ii_icrb0_d_u {
2331 ************************************************************************/ 2331 ************************************************************************/
2332 2332
2333typedef union ii_icrb0_e_u { 2333typedef union ii_icrb0_e_u {
2334 uint64_t ii_icrb0_e_regval; 2334 u64 ii_icrb0_e_regval;
2335 struct { 2335 struct {
2336 uint64_t ie_timeout:8; 2336 u64 ie_timeout:8;
2337 uint64_t ie_context:15; 2337 u64 ie_context:15;
2338 uint64_t ie_rsvd:1; 2338 u64 ie_rsvd:1;
2339 uint64_t ie_tvld:1; 2339 u64 ie_tvld:1;
2340 uint64_t ie_cvld:1; 2340 u64 ie_cvld:1;
2341 uint64_t ie_rsvd_0:38; 2341 u64 ie_rsvd_0:38;
2342 } ii_icrb0_e_fld_s; 2342 } ii_icrb0_e_fld_s;
2343} ii_icrb0_e_u_t; 2343} ii_icrb0_e_u_t;
2344 2344
@@ -2351,12 +2351,12 @@ typedef union ii_icrb0_e_u {
2351 ************************************************************************/ 2351 ************************************************************************/
2352 2352
2353typedef union ii_icsml_u { 2353typedef union ii_icsml_u {
2354 uint64_t ii_icsml_regval; 2354 u64 ii_icsml_regval;
2355 struct { 2355 struct {
2356 uint64_t i_tt_addr:47; 2356 u64 i_tt_addr:47;
2357 uint64_t i_newsuppl_ex:14; 2357 u64 i_newsuppl_ex:14;
2358 uint64_t i_reserved:2; 2358 u64 i_reserved:2;
2359 uint64_t i_overflow:1; 2359 u64 i_overflow:1;
2360 } ii_icsml_fld_s; 2360 } ii_icsml_fld_s;
2361} ii_icsml_u_t; 2361} ii_icsml_u_t;
2362 2362
@@ -2369,10 +2369,10 @@ typedef union ii_icsml_u {
2369 ************************************************************************/ 2369 ************************************************************************/
2370 2370
2371typedef union ii_icsmm_u { 2371typedef union ii_icsmm_u {
2372 uint64_t ii_icsmm_regval; 2372 u64 ii_icsmm_regval;
2373 struct { 2373 struct {
2374 uint64_t i_tt_ack_cnt:11; 2374 u64 i_tt_ack_cnt:11;
2375 uint64_t i_reserved:53; 2375 u64 i_reserved:53;
2376 } ii_icsmm_fld_s; 2376 } ii_icsmm_fld_s;
2377} ii_icsmm_u_t; 2377} ii_icsmm_u_t;
2378 2378
@@ -2385,48 +2385,48 @@ typedef union ii_icsmm_u {
2385 ************************************************************************/ 2385 ************************************************************************/
2386 2386
2387typedef union ii_icsmh_u { 2387typedef union ii_icsmh_u {
2388 uint64_t ii_icsmh_regval; 2388 u64 ii_icsmh_regval;
2389 struct { 2389 struct {
2390 uint64_t i_tt_vld:1; 2390 u64 i_tt_vld:1;
2391 uint64_t i_xerr:1; 2391 u64 i_xerr:1;
2392 uint64_t i_ft_cwact_o:1; 2392 u64 i_ft_cwact_o:1;
2393 uint64_t i_ft_wact_o:1; 2393 u64 i_ft_wact_o:1;
2394 uint64_t i_ft_active_o:1; 2394 u64 i_ft_active_o:1;
2395 uint64_t i_sync:1; 2395 u64 i_sync:1;
2396 uint64_t i_mnusg:1; 2396 u64 i_mnusg:1;
2397 uint64_t i_mnusz:1; 2397 u64 i_mnusz:1;
2398 uint64_t i_plusz:1; 2398 u64 i_plusz:1;
2399 uint64_t i_plusg:1; 2399 u64 i_plusg:1;
2400 uint64_t i_tt_exc:5; 2400 u64 i_tt_exc:5;
2401 uint64_t i_tt_wb:1; 2401 u64 i_tt_wb:1;
2402 uint64_t i_tt_hold:1; 2402 u64 i_tt_hold:1;
2403 uint64_t i_tt_ack:1; 2403 u64 i_tt_ack:1;
2404 uint64_t i_tt_resp:1; 2404 u64 i_tt_resp:1;
2405 uint64_t i_tt_intvn:1; 2405 u64 i_tt_intvn:1;
2406 uint64_t i_g_stall_bte1:1; 2406 u64 i_g_stall_bte1:1;
2407 uint64_t i_g_stall_bte0:1; 2407 u64 i_g_stall_bte0:1;
2408 uint64_t i_g_stall_il:1; 2408 u64 i_g_stall_il:1;
2409 uint64_t i_g_stall_ib:1; 2409 u64 i_g_stall_ib:1;
2410 uint64_t i_tt_imsg:8; 2410 u64 i_tt_imsg:8;
2411 uint64_t i_tt_imsgtype:2; 2411 u64 i_tt_imsgtype:2;
2412 uint64_t i_tt_use_old:1; 2412 u64 i_tt_use_old:1;
2413 uint64_t i_tt_respreqd:1; 2413 u64 i_tt_respreqd:1;
2414 uint64_t i_tt_bte_num:1; 2414 u64 i_tt_bte_num:1;
2415 uint64_t i_cbn:1; 2415 u64 i_cbn:1;
2416 uint64_t i_match:1; 2416 u64 i_match:1;
2417 uint64_t i_rpcnt_lt_34:1; 2417 u64 i_rpcnt_lt_34:1;
2418 uint64_t i_rpcnt_ge_34:1; 2418 u64 i_rpcnt_ge_34:1;
2419 uint64_t i_rpcnt_lt_18:1; 2419 u64 i_rpcnt_lt_18:1;
2420 uint64_t i_rpcnt_ge_18:1; 2420 u64 i_rpcnt_ge_18:1;
2421 uint64_t i_rpcnt_lt_2:1; 2421 u64 i_rpcnt_lt_2:1;
2422 uint64_t i_rpcnt_ge_2:1; 2422 u64 i_rpcnt_ge_2:1;
2423 uint64_t i_rqcnt_lt_18:1; 2423 u64 i_rqcnt_lt_18:1;
2424 uint64_t i_rqcnt_ge_18:1; 2424 u64 i_rqcnt_ge_18:1;
2425 uint64_t i_rqcnt_lt_2:1; 2425 u64 i_rqcnt_lt_2:1;
2426 uint64_t i_rqcnt_ge_2:1; 2426 u64 i_rqcnt_ge_2:1;
2427 uint64_t i_tt_device:7; 2427 u64 i_tt_device:7;
2428 uint64_t i_tt_init:3; 2428 u64 i_tt_init:3;
2429 uint64_t i_reserved:5; 2429 u64 i_reserved:5;
2430 } ii_icsmh_fld_s; 2430 } ii_icsmh_fld_s;
2431} ii_icsmh_u_t; 2431} ii_icsmh_u_t;
2432 2432
@@ -2439,14 +2439,14 @@ typedef union ii_icsmh_u {
2439 ************************************************************************/ 2439 ************************************************************************/
2440 2440
2441typedef union ii_idbss_u { 2441typedef union ii_idbss_u {
2442 uint64_t ii_idbss_regval; 2442 u64 ii_idbss_regval;
2443 struct { 2443 struct {
2444 uint64_t i_iioclk_core_submenu:3; 2444 u64 i_iioclk_core_submenu:3;
2445 uint64_t i_rsvd:5; 2445 u64 i_rsvd:5;
2446 uint64_t i_fsbclk_wrapper_submenu:3; 2446 u64 i_fsbclk_wrapper_submenu:3;
2447 uint64_t i_rsvd_1:5; 2447 u64 i_rsvd_1:5;
2448 uint64_t i_iioclk_menu:5; 2448 u64 i_iioclk_menu:5;
2449 uint64_t i_rsvd_2:43; 2449 u64 i_rsvd_2:43;
2450 } ii_idbss_fld_s; 2450 } ii_idbss_fld_s;
2451} ii_idbss_u_t; 2451} ii_idbss_u_t;
2452 2452
@@ -2466,13 +2466,13 @@ typedef union ii_idbss_u {
2466 ************************************************************************/ 2466 ************************************************************************/
2467 2467
2468typedef union ii_ibls0_u { 2468typedef union ii_ibls0_u {
2469 uint64_t ii_ibls0_regval; 2469 u64 ii_ibls0_regval;
2470 struct { 2470 struct {
2471 uint64_t i_length:16; 2471 u64 i_length:16;
2472 uint64_t i_error:1; 2472 u64 i_error:1;
2473 uint64_t i_rsvd_1:3; 2473 u64 i_rsvd_1:3;
2474 uint64_t i_busy:1; 2474 u64 i_busy:1;
2475 uint64_t i_rsvd:43; 2475 u64 i_rsvd:43;
2476 } ii_ibls0_fld_s; 2476 } ii_ibls0_fld_s;
2477} ii_ibls0_u_t; 2477} ii_ibls0_u_t;
2478 2478
@@ -2487,11 +2487,11 @@ typedef union ii_ibls0_u {
2487 ************************************************************************/ 2487 ************************************************************************/
2488 2488
2489typedef union ii_ibsa0_u { 2489typedef union ii_ibsa0_u {
2490 uint64_t ii_ibsa0_regval; 2490 u64 ii_ibsa0_regval;
2491 struct { 2491 struct {
2492 uint64_t i_rsvd_1:7; 2492 u64 i_rsvd_1:7;
2493 uint64_t i_addr:42; 2493 u64 i_addr:42;
2494 uint64_t i_rsvd:15; 2494 u64 i_rsvd:15;
2495 } ii_ibsa0_fld_s; 2495 } ii_ibsa0_fld_s;
2496} ii_ibsa0_u_t; 2496} ii_ibsa0_u_t;
2497 2497
@@ -2506,11 +2506,11 @@ typedef union ii_ibsa0_u {
2506 ************************************************************************/ 2506 ************************************************************************/
2507 2507
2508typedef union ii_ibda0_u { 2508typedef union ii_ibda0_u {
2509 uint64_t ii_ibda0_regval; 2509 u64 ii_ibda0_regval;
2510 struct { 2510 struct {
2511 uint64_t i_rsvd_1:7; 2511 u64 i_rsvd_1:7;
2512 uint64_t i_addr:42; 2512 u64 i_addr:42;
2513 uint64_t i_rsvd:15; 2513 u64 i_rsvd:15;
2514 } ii_ibda0_fld_s; 2514 } ii_ibda0_fld_s;
2515} ii_ibda0_u_t; 2515} ii_ibda0_u_t;
2516 2516
@@ -2527,14 +2527,14 @@ typedef union ii_ibda0_u {
2527 ************************************************************************/ 2527 ************************************************************************/
2528 2528
2529typedef union ii_ibct0_u { 2529typedef union ii_ibct0_u {
2530 uint64_t ii_ibct0_regval; 2530 u64 ii_ibct0_regval;
2531 struct { 2531 struct {
2532 uint64_t i_zerofill:1; 2532 u64 i_zerofill:1;
2533 uint64_t i_rsvd_2:3; 2533 u64 i_rsvd_2:3;
2534 uint64_t i_notify:1; 2534 u64 i_notify:1;
2535 uint64_t i_rsvd_1:3; 2535 u64 i_rsvd_1:3;
2536 uint64_t i_poison:1; 2536 u64 i_poison:1;
2537 uint64_t i_rsvd:55; 2537 u64 i_rsvd:55;
2538 } ii_ibct0_fld_s; 2538 } ii_ibct0_fld_s;
2539} ii_ibct0_u_t; 2539} ii_ibct0_u_t;
2540 2540
@@ -2546,11 +2546,11 @@ typedef union ii_ibct0_u {
2546 ************************************************************************/ 2546 ************************************************************************/
2547 2547
2548typedef union ii_ibna0_u { 2548typedef union ii_ibna0_u {
2549 uint64_t ii_ibna0_regval; 2549 u64 ii_ibna0_regval;
2550 struct { 2550 struct {
2551 uint64_t i_rsvd_1:7; 2551 u64 i_rsvd_1:7;
2552 uint64_t i_addr:42; 2552 u64 i_addr:42;
2553 uint64_t i_rsvd:15; 2553 u64 i_rsvd:15;
2554 } ii_ibna0_fld_s; 2554 } ii_ibna0_fld_s;
2555} ii_ibna0_u_t; 2555} ii_ibna0_u_t;
2556 2556
@@ -2563,13 +2563,13 @@ typedef union ii_ibna0_u {
2563 ************************************************************************/ 2563 ************************************************************************/
2564 2564
2565typedef union ii_ibia0_u { 2565typedef union ii_ibia0_u {
2566 uint64_t ii_ibia0_regval; 2566 u64 ii_ibia0_regval;
2567 struct { 2567 struct {
2568 uint64_t i_rsvd_2:1; 2568 u64 i_rsvd_2:1;
2569 uint64_t i_node_id:11; 2569 u64 i_node_id:11;
2570 uint64_t i_rsvd_1:4; 2570 u64 i_rsvd_1:4;
2571 uint64_t i_level:7; 2571 u64 i_level:7;
2572 uint64_t i_rsvd:41; 2572 u64 i_rsvd:41;
2573 } ii_ibia0_fld_s; 2573 } ii_ibia0_fld_s;
2574} ii_ibia0_u_t; 2574} ii_ibia0_u_t;
2575 2575
@@ -2589,13 +2589,13 @@ typedef union ii_ibia0_u {
2589 ************************************************************************/ 2589 ************************************************************************/
2590 2590
2591typedef union ii_ibls1_u { 2591typedef union ii_ibls1_u {
2592 uint64_t ii_ibls1_regval; 2592 u64 ii_ibls1_regval;
2593 struct { 2593 struct {
2594 uint64_t i_length:16; 2594 u64 i_length:16;
2595 uint64_t i_error:1; 2595 u64 i_error:1;
2596 uint64_t i_rsvd_1:3; 2596 u64 i_rsvd_1:3;
2597 uint64_t i_busy:1; 2597 u64 i_busy:1;
2598 uint64_t i_rsvd:43; 2598 u64 i_rsvd:43;
2599 } ii_ibls1_fld_s; 2599 } ii_ibls1_fld_s;
2600} ii_ibls1_u_t; 2600} ii_ibls1_u_t;
2601 2601
@@ -2610,11 +2610,11 @@ typedef union ii_ibls1_u {
2610 ************************************************************************/ 2610 ************************************************************************/
2611 2611
2612typedef union ii_ibsa1_u { 2612typedef union ii_ibsa1_u {
2613 uint64_t ii_ibsa1_regval; 2613 u64 ii_ibsa1_regval;
2614 struct { 2614 struct {
2615 uint64_t i_rsvd_1:7; 2615 u64 i_rsvd_1:7;
2616 uint64_t i_addr:33; 2616 u64 i_addr:33;
2617 uint64_t i_rsvd:24; 2617 u64 i_rsvd:24;
2618 } ii_ibsa1_fld_s; 2618 } ii_ibsa1_fld_s;
2619} ii_ibsa1_u_t; 2619} ii_ibsa1_u_t;
2620 2620
@@ -2629,11 +2629,11 @@ typedef union ii_ibsa1_u {
2629 ************************************************************************/ 2629 ************************************************************************/
2630 2630
2631typedef union ii_ibda1_u { 2631typedef union ii_ibda1_u {
2632 uint64_t ii_ibda1_regval; 2632 u64 ii_ibda1_regval;
2633 struct { 2633 struct {
2634 uint64_t i_rsvd_1:7; 2634 u64 i_rsvd_1:7;
2635 uint64_t i_addr:33; 2635 u64 i_addr:33;
2636 uint64_t i_rsvd:24; 2636 u64 i_rsvd:24;
2637 } ii_ibda1_fld_s; 2637 } ii_ibda1_fld_s;
2638} ii_ibda1_u_t; 2638} ii_ibda1_u_t;
2639 2639
@@ -2650,14 +2650,14 @@ typedef union ii_ibda1_u {
2650 ************************************************************************/ 2650 ************************************************************************/
2651 2651
2652typedef union ii_ibct1_u { 2652typedef union ii_ibct1_u {
2653 uint64_t ii_ibct1_regval; 2653 u64 ii_ibct1_regval;
2654 struct { 2654 struct {
2655 uint64_t i_zerofill:1; 2655 u64 i_zerofill:1;
2656 uint64_t i_rsvd_2:3; 2656 u64 i_rsvd_2:3;
2657 uint64_t i_notify:1; 2657 u64 i_notify:1;
2658 uint64_t i_rsvd_1:3; 2658 u64 i_rsvd_1:3;
2659 uint64_t i_poison:1; 2659 u64 i_poison:1;
2660 uint64_t i_rsvd:55; 2660 u64 i_rsvd:55;
2661 } ii_ibct1_fld_s; 2661 } ii_ibct1_fld_s;
2662} ii_ibct1_u_t; 2662} ii_ibct1_u_t;
2663 2663
@@ -2669,11 +2669,11 @@ typedef union ii_ibct1_u {
2669 ************************************************************************/ 2669 ************************************************************************/
2670 2670
2671typedef union ii_ibna1_u { 2671typedef union ii_ibna1_u {
2672 uint64_t ii_ibna1_regval; 2672 u64 ii_ibna1_regval;
2673 struct { 2673 struct {
2674 uint64_t i_rsvd_1:7; 2674 u64 i_rsvd_1:7;
2675 uint64_t i_addr:33; 2675 u64 i_addr:33;
2676 uint64_t i_rsvd:24; 2676 u64 i_rsvd:24;
2677 } ii_ibna1_fld_s; 2677 } ii_ibna1_fld_s;
2678} ii_ibna1_u_t; 2678} ii_ibna1_u_t;
2679 2679
@@ -2686,13 +2686,13 @@ typedef union ii_ibna1_u {
2686 ************************************************************************/ 2686 ************************************************************************/
2687 2687
2688typedef union ii_ibia1_u { 2688typedef union ii_ibia1_u {
2689 uint64_t ii_ibia1_regval; 2689 u64 ii_ibia1_regval;
2690 struct { 2690 struct {
2691 uint64_t i_pi_id:1; 2691 u64 i_pi_id:1;
2692 uint64_t i_node_id:8; 2692 u64 i_node_id:8;
2693 uint64_t i_rsvd_1:7; 2693 u64 i_rsvd_1:7;
2694 uint64_t i_level:7; 2694 u64 i_level:7;
2695 uint64_t i_rsvd:41; 2695 u64 i_rsvd:41;
2696 } ii_ibia1_fld_s; 2696 } ii_ibia1_fld_s;
2697} ii_ibia1_u_t; 2697} ii_ibia1_u_t;
2698 2698
@@ -2712,12 +2712,12 @@ typedef union ii_ibia1_u {
2712 ************************************************************************/ 2712 ************************************************************************/
2713 2713
2714typedef union ii_ipcr_u { 2714typedef union ii_ipcr_u {
2715 uint64_t ii_ipcr_regval; 2715 u64 ii_ipcr_regval;
2716 struct { 2716 struct {
2717 uint64_t i_ippr0_c:4; 2717 u64 i_ippr0_c:4;
2718 uint64_t i_ippr1_c:4; 2718 u64 i_ippr1_c:4;
2719 uint64_t i_icct:8; 2719 u64 i_icct:8;
2720 uint64_t i_rsvd:48; 2720 u64 i_rsvd:48;
2721 } ii_ipcr_fld_s; 2721 } ii_ipcr_fld_s;
2722} ii_ipcr_u_t; 2722} ii_ipcr_u_t;
2723 2723
@@ -2728,10 +2728,10 @@ typedef union ii_ipcr_u {
2728 ************************************************************************/ 2728 ************************************************************************/
2729 2729
2730typedef union ii_ippr_u { 2730typedef union ii_ippr_u {
2731 uint64_t ii_ippr_regval; 2731 u64 ii_ippr_regval;
2732 struct { 2732 struct {
2733 uint64_t i_ippr0:32; 2733 u64 i_ippr0:32;
2734 uint64_t i_ippr1:32; 2734 u64 i_ippr1:32;
2735 } ii_ippr_fld_s; 2735 } ii_ippr_fld_s;
2736} ii_ippr_u_t; 2736} ii_ippr_u_t;
2737 2737
@@ -3267,15 +3267,15 @@ typedef ii_icrb0_e_u_t icrbe_t;
3267#define IO_PERF_SETS 32 3267#define IO_PERF_SETS 32
3268 3268
3269/* Bit for the widget in inbound access register */ 3269/* Bit for the widget in inbound access register */
3270#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3270#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
3271/* Bit for the widget in outbound access register */ 3271/* Bit for the widget in outbound access register */
3272#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) 3272#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
3273 3273
3274/* NOTE: The following define assumes that we are going to get 3274/* NOTE: The following define assumes that we are going to get
3275 * widget numbers from 8 thru F and the device numbers within 3275 * widget numbers from 8 thru F and the device numbers within
3276 * widget from 0 thru 7. 3276 * widget from 0 thru 7.
3277 */ 3277 */
3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) 3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
3279 3279
3280/* IO Interrupt Destination Register */ 3280/* IO Interrupt Destination Register */
3281#define IIO_IIDSR_SENT_SHIFT 28 3281#define IIO_IIDSR_SENT_SHIFT 28
@@ -3302,9 +3302,9 @@ typedef ii_icrb0_e_u_t icrbe_t;
3302 */ 3302 */
3303 3303
3304typedef union hubii_wcr_u { 3304typedef union hubii_wcr_u {
3305 uint64_t wcr_reg_value; 3305 u64 wcr_reg_value;
3306 struct { 3306 struct {
3307 uint64_t wcr_widget_id:4, /* LLP crossbar credit */ 3307 u64 wcr_widget_id:4, /* LLP crossbar credit */
3308 wcr_tag_mode:1, /* Tag mode */ 3308 wcr_tag_mode:1, /* Tag mode */
3309 wcr_rsvd1:8, /* Reserved */ 3309 wcr_rsvd1:8, /* Reserved */
3310 wcr_xbar_crd:3, /* LLP crossbar credit */ 3310 wcr_xbar_crd:3, /* LLP crossbar credit */
@@ -3324,9 +3324,9 @@ performance registers */
3324 performed */ 3324 performed */
3325 3325
3326typedef union io_perf_sel { 3326typedef union io_perf_sel {
3327 uint64_t perf_sel_reg; 3327 u64 perf_sel_reg;
3328 struct { 3328 struct {
3329 uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; 3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
3330 } perf_sel_bits; 3330 } perf_sel_bits;
3331} io_perf_sel_t; 3331} io_perf_sel_t;
3332 3332
@@ -3334,24 +3334,24 @@ typedef union io_perf_sel {
3334 hardware problems there is only one counter, not two. */ 3334 hardware problems there is only one counter, not two. */
3335 3335
3336typedef union io_perf_cnt { 3336typedef union io_perf_cnt {
3337 uint64_t perf_cnt; 3337 u64 perf_cnt;
3338 struct { 3338 struct {
3339 uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; 3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
3340 } perf_cnt_bits; 3340 } perf_cnt_bits;
3341 3341
3342} io_perf_cnt_t; 3342} io_perf_cnt_t;
3343 3343
3344typedef union iprte_a { 3344typedef union iprte_a {
3345 uint64_t entry; 3345 u64 entry;
3346 struct { 3346 struct {
3347 uint64_t i_rsvd_1:3; 3347 u64 i_rsvd_1:3;
3348 uint64_t i_addr:38; 3348 u64 i_addr:38;
3349 uint64_t i_init:3; 3349 u64 i_init:3;
3350 uint64_t i_source:8; 3350 u64 i_source:8;
3351 uint64_t i_rsvd:2; 3351 u64 i_rsvd:2;
3352 uint64_t i_widget:4; 3352 u64 i_widget:4;
3353 uint64_t i_to_cnt:5; 3353 u64 i_to_cnt:5;
3354 uint64_t i_vld:1; 3354 u64 i_vld:1;
3355 } iprte_fields; 3355 } iprte_fields;
3356} iprte_a_t; 3356} iprte_a_t;
3357 3357
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 8b9e10e7cdba..e77f0c9b7d3d 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -273,7 +273,7 @@ ia64_sn_console_putc(char ch)
273 ret_stuff.v0 = 0; 273 ret_stuff.v0 = 0;
274 ret_stuff.v1 = 0; 274 ret_stuff.v1 = 0;
275 ret_stuff.v2 = 0; 275 ret_stuff.v2 = 0;
276 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); 276 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
277 277
278 return ret_stuff.status; 278 return ret_stuff.status;
279} 279}
@@ -290,7 +290,7 @@ ia64_sn_console_putb(const char *buf, int len)
290 ret_stuff.v0 = 0; 290 ret_stuff.v0 = 0;
291 ret_stuff.v1 = 0; 291 ret_stuff.v1 = 0;
292 ret_stuff.v2 = 0; 292 ret_stuff.v2 = 0;
293 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); 293 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
294 294
295 if ( ret_stuff.status == 0 ) { 295 if ( ret_stuff.status == 0 ) {
296 return ret_stuff.v0; 296 return ret_stuff.v0;
@@ -310,7 +310,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
310 ret_stuff.v0 = 0; 310 ret_stuff.v0 = 0;
311 ret_stuff.v1 = 0; 311 ret_stuff.v1 = 0;
312 ret_stuff.v2 = 0; 312 ret_stuff.v2 = 0;
313 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); 313 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
314 314
315 return ret_stuff.status; 315 return ret_stuff.status;
316} 316}
@@ -398,7 +398,7 @@ ia64_sn_console_intr_status(void)
398 * Enable an interrupt on the SAL console device. 398 * Enable an interrupt on the SAL console device.
399 */ 399 */
400static inline void 400static inline void
401ia64_sn_console_intr_enable(uint64_t intr) 401ia64_sn_console_intr_enable(u64 intr)
402{ 402{
403 struct ia64_sal_retval ret_stuff; 403 struct ia64_sal_retval ret_stuff;
404 404
@@ -415,7 +415,7 @@ ia64_sn_console_intr_enable(uint64_t intr)
415 * Disable an interrupt on the SAL console device. 415 * Disable an interrupt on the SAL console device.
416 */ 416 */
417static inline void 417static inline void
418ia64_sn_console_intr_disable(uint64_t intr) 418ia64_sn_console_intr_disable(u64 intr)
419{ 419{
420 struct ia64_sal_retval ret_stuff; 420 struct ia64_sal_retval ret_stuff;
421 421
@@ -441,7 +441,7 @@ ia64_sn_console_xmit_chars(char *buf, int len)
441 ret_stuff.v1 = 0; 441 ret_stuff.v1 = 0;
442 ret_stuff.v2 = 0; 442 ret_stuff.v2 = 0;
443 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS, 443 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
444 (uint64_t)buf, (uint64_t)len, 444 (u64)buf, (u64)len,
445 0, 0, 0, 0, 0); 445 0, 0, 0, 0, 0);
446 446
447 if (ret_stuff.status == 0) { 447 if (ret_stuff.status == 0) {
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
index bc1aacfb9483..666222d7f0f6 100644
--- a/include/asm-ia64/sn/tioca.h
+++ b/include/asm-ia64/sn/tioca.h
@@ -19,47 +19,47 @@
19 */ 19 */
20 20
21struct tioca { 21struct tioca {
22 uint64_t ca_id; /* 0x000000 */ 22 u64 ca_id; /* 0x000000 */
23 uint64_t ca_control1; /* 0x000008 */ 23 u64 ca_control1; /* 0x000008 */
24 uint64_t ca_control2; /* 0x000010 */ 24 u64 ca_control2; /* 0x000010 */
25 uint64_t ca_status1; /* 0x000018 */ 25 u64 ca_status1; /* 0x000018 */
26 uint64_t ca_status2; /* 0x000020 */ 26 u64 ca_status2; /* 0x000020 */
27 uint64_t ca_gart_aperature; /* 0x000028 */ 27 u64 ca_gart_aperature; /* 0x000028 */
28 uint64_t ca_gfx_detach; /* 0x000030 */ 28 u64 ca_gfx_detach; /* 0x000030 */
29 uint64_t ca_inta_dest_addr; /* 0x000038 */ 29 u64 ca_inta_dest_addr; /* 0x000038 */
30 uint64_t ca_intb_dest_addr; /* 0x000040 */ 30 u64 ca_intb_dest_addr; /* 0x000040 */
31 uint64_t ca_err_int_dest_addr; /* 0x000048 */ 31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 uint64_t ca_int_status; /* 0x000050 */ 32 u64 ca_int_status; /* 0x000050 */
33 uint64_t ca_int_status_alias; /* 0x000058 */ 33 u64 ca_int_status_alias; /* 0x000058 */
34 uint64_t ca_mult_error; /* 0x000060 */ 34 u64 ca_mult_error; /* 0x000060 */
35 uint64_t ca_mult_error_alias; /* 0x000068 */ 35 u64 ca_mult_error_alias; /* 0x000068 */
36 uint64_t ca_first_error; /* 0x000070 */ 36 u64 ca_first_error; /* 0x000070 */
37 uint64_t ca_int_mask; /* 0x000078 */ 37 u64 ca_int_mask; /* 0x000078 */
38 uint64_t ca_crm_pkterr_type; /* 0x000080 */ 38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ 39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ 40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ 41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 uint64_t ca_crm_tnumto; /* 0x0000A0 */ 42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 uint64_t ca_gart_err; /* 0x0000A8 */ 43 u64 ca_gart_err; /* 0x0000A8 */
44 uint64_t ca_pcierr_type; /* 0x0000B0 */ 44 u64 ca_pcierr_type; /* 0x0000B0 */
45 uint64_t ca_pcierr_addr; /* 0x0000B8 */ 45 u64 ca_pcierr_addr; /* 0x0000B8 */
46 46
47 uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ 47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48 48
49 uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ 49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ 50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ 51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 uint64_t ca_force_inta; /* 0x0000F0 */ 52 u64 ca_force_inta; /* 0x0000F0 */
53 uint64_t ca_force_intb; /* 0x0000F8 */ 53 u64 ca_force_intb; /* 0x0000F8 */
54 uint64_t ca_debug_vector_sel; /* 0x000100 */ 54 u64 ca_debug_vector_sel; /* 0x000100 */
55 uint64_t ca_debug_mux_core_sel; /* 0x000108 */ 55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ 56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 uint64_t ca_debug_domain_sel; /* 0x000118 */ 57 u64 ca_debug_domain_sel; /* 0x000118 */
58 58
59 uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ 59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60 60
61 uint64_t ca_gart_ptr_table; /* 0x200 */ 61 u64 ca_gart_ptr_table; /* 0x200 */
62 uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ 62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63}; 63};
64 64
65/* 65/*
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b532ef6148ed..ab7fe2463468 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -56,31 +56,31 @@ struct tioca_kernel {
56 /* 56 /*
57 * General GART stuff 57 * General GART stuff
58 */ 58 */
59 uint64_t ca_ap_size; /* size of aperature in bytes */ 59 u64 ca_ap_size; /* size of aperature in bytes */
60 uint32_t ca_gart_entries; /* # uint64_t entries in gart */ 60 u32 ca_gart_entries; /* # u64 entries in gart */
61 uint32_t ca_ap_pagesize; /* aperature page size in bytes */ 61 u32 ca_ap_pagesize; /* aperature page size in bytes */
62 uint64_t ca_ap_bus_base; /* bus address of CA aperature */ 62 u64 ca_ap_bus_base; /* bus address of CA aperature */
63 uint64_t ca_gart_size; /* gart size in bytes */ 63 u64 ca_gart_size; /* gart size in bytes */
64 uint64_t *ca_gart; /* gart table vaddr */ 64 u64 *ca_gart; /* gart table vaddr */
65 uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */ 65 u64 ca_gart_coretalk_addr; /* gart coretalk addr */
66 uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */ 66 u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
67 67
68 /* PCI GART convenience values */ 68 /* PCI GART convenience values */
69 uint64_t ca_pciap_base; /* pci aperature bus base address */ 69 u64 ca_pciap_base; /* pci aperature bus base address */
70 uint64_t ca_pciap_size; /* pci aperature size (bytes) */ 70 u64 ca_pciap_size; /* pci aperature size (bytes) */
71 uint64_t ca_pcigart_base; /* gfx GART bus base address */ 71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 uint64_t *ca_pcigart; /* gfx GART vm address */ 72 u64 *ca_pcigart; /* gfx GART vm address */
73 uint32_t ca_pcigart_entries; 73 u32 ca_pcigart_entries;
74 uint32_t ca_pcigart_start; /* PCI start index in ca_gart */ 74 u32 ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap; 75 void *ca_pcigart_pagemap;
76 76
77 /* AGP GART convenience values */ 77 /* AGP GART convenience values */
78 uint64_t ca_gfxap_base; /* gfx aperature bus base address */ 78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */ 79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 uint64_t ca_gfxgart_base; /* gfx GART bus base address */ 80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 uint64_t *ca_gfxgart; /* gfx GART vm address */ 81 u64 *ca_gfxgart; /* gfx GART vm address */
82 uint32_t ca_gfxgart_entries; 82 u32 ca_gfxgart_entries;
83 uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */ 83 u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
84}; 84};
85 85
86/* 86/*
@@ -93,11 +93,11 @@ struct tioca_kernel {
93struct tioca_common { 93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */ 94 struct pcibus_bussoft ca_common; /* common pciio header */
95 95
96 uint32_t ca_rev; 96 u32 ca_rev;
97 uint32_t ca_closest_nasid; 97 u32 ca_closest_nasid;
98 98
99 uint64_t ca_prom_private; 99 u64 ca_prom_private;
100 uint64_t ca_kernel_private; 100 u64 ca_kernel_private;
101}; 101};
102 102
103/** 103/**
@@ -139,9 +139,9 @@ tioca_paddr_to_gart(unsigned long paddr)
139 */ 139 */
140 140
141static inline unsigned long 141static inline unsigned long
142tioca_physpage_to_gart(uint64_t page_addr) 142tioca_physpage_to_gart(u64 page_addr)
143{ 143{
144 uint64_t coretalk_addr; 144 u64 coretalk_addr;
145 145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr); 146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) { 147 if (!coretalk_addr) {
@@ -161,7 +161,7 @@ tioca_physpage_to_gart(uint64_t page_addr)
161static inline void 161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel) 162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{ 163{
164 volatile uint64_t tmp; 164 volatile u64 tmp;
165 volatile struct tioca *ca_base; 165 volatile struct tioca *ca_base;
166 struct tioca_common *tioca_common; 166 struct tioca_common *tioca_common;
167 167
@@ -200,7 +200,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
200 tmp = __sn_readq_relaxed(&ca_base->ca_control2); 200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern u32 tioca_gart_found;
204extern struct list_head tioca_list; 204extern struct list_head tioca_list;
205extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
index ecaddf960086..d4c990712eac 100644
--- a/include/asm-ia64/sn/tioce.h
+++ b/include/asm-ia64/sn/tioce.h
@@ -35,72 +35,72 @@ typedef volatile struct tioce {
35 /* 35 /*
36 * ADMIN : Administration Registers 36 * ADMIN : Administration Registers
37 */ 37 */
38 uint64_t ce_adm_id; /* 0x000000 */ 38 u64 ce_adm_id; /* 0x000000 */
39 uint64_t ce_pad_000008; /* 0x000008 */ 39 u64 ce_pad_000008; /* 0x000008 */
40 uint64_t ce_adm_dyn_credit_status; /* 0x000010 */ 40 u64 ce_adm_dyn_credit_status; /* 0x000010 */
41 uint64_t ce_adm_last_credit_status; /* 0x000018 */ 41 u64 ce_adm_last_credit_status; /* 0x000018 */
42 uint64_t ce_adm_credit_limit; /* 0x000020 */ 42 u64 ce_adm_credit_limit; /* 0x000020 */
43 uint64_t ce_adm_force_credit; /* 0x000028 */ 43 u64 ce_adm_force_credit; /* 0x000028 */
44 uint64_t ce_adm_control; /* 0x000030 */ 44 u64 ce_adm_control; /* 0x000030 */
45 uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */ 45 u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
46 uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */ 46 u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
47 uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */ 47 u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
48 uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */ 48 u64 ce_adm_ssp_debug_sel; /* 0x000050 */
49 uint64_t ce_adm_int_status; /* 0x000058 */ 49 u64 ce_adm_int_status; /* 0x000058 */
50 uint64_t ce_adm_int_status_alias; /* 0x000060 */ 50 u64 ce_adm_int_status_alias; /* 0x000060 */
51 uint64_t ce_adm_int_mask; /* 0x000068 */ 51 u64 ce_adm_int_mask; /* 0x000068 */
52 uint64_t ce_adm_int_pending; /* 0x000070 */ 52 u64 ce_adm_int_pending; /* 0x000070 */
53 uint64_t ce_adm_force_int; /* 0x000078 */ 53 u64 ce_adm_force_int; /* 0x000078 */
54 uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */ 54 u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
55 uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */ 55 u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
56 uint64_t ce_adm_error_summary; /* 0x000100 */ 56 u64 ce_adm_error_summary; /* 0x000100 */
57 uint64_t ce_adm_error_summary_alias; /* 0x000108 */ 57 u64 ce_adm_error_summary_alias; /* 0x000108 */
58 uint64_t ce_adm_error_mask; /* 0x000110 */ 58 u64 ce_adm_error_mask; /* 0x000110 */
59 uint64_t ce_adm_first_error; /* 0x000118 */ 59 u64 ce_adm_first_error; /* 0x000118 */
60 uint64_t ce_adm_error_overflow; /* 0x000120 */ 60 u64 ce_adm_error_overflow; /* 0x000120 */
61 uint64_t ce_adm_error_overflow_alias; /* 0x000128 */ 61 u64 ce_adm_error_overflow_alias; /* 0x000128 */
62 uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */ 62 u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
63 uint64_t ce_adm_tnum_error; /* 0x000140 */ 63 u64 ce_adm_tnum_error; /* 0x000140 */
64 uint64_t ce_adm_mmr_err_detail; /* 0x000148 */ 64 u64 ce_adm_mmr_err_detail; /* 0x000148 */
65 uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */ 65 u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
66 uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */ 66 u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
67 uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */ 67 u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
68 uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */ 68 u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
69 uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */ 69 u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
70 uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */ 70 u64 ce_adm_pcie_debug_sel; /* 0x000178 */
71 uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */ 71 u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
72 72
73 uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */ 73 u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
74 uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */ 74 u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
75 uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */ 75 u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
76 uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */ 76 u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
77 uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */ 77 u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
78 uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */ 78 u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
79 uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */ 79 u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
80 uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */ 80 u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
81 uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */ 81 u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
82 uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */ 82 u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
83 uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */ 83 u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
84 uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */ 84 u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
85 uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */ 85 u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
86 uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */ 86 u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
87 uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */ 87 u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
88 uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */ 88 u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
89 uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */ 89 u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
90 90
91 uint64_t ce_adm_bap_ctrl; /* 0x000400 */ 91 u64 ce_adm_bap_ctrl; /* 0x000400 */
92 uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */ 92 u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
93 93
94 uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */ 94 u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
95 uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */ 95 u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
96 96
97 uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */ 97 u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
98 uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */ 98 u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
99 99
100 uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */ 100 u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
101 uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */ 101 u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
102 102
103 uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */ 103 u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
104 104
105 /* 105 /*
106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2) 106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
@@ -109,141 +109,141 @@ typedef volatile struct tioce {
109 */ 109 */
110 #define ce_lsi(link_num) ce_lsi[link_num-1] 110 #define ce_lsi(link_num) ce_lsi[link_num-1]
111 struct ce_lsi_reg { 111 struct ce_lsi_reg {
112 uint64_t ce_lsi_lpu_id; /* 0x00z000 */ 112 u64 ce_lsi_lpu_id; /* 0x00z000 */
113 uint64_t ce_lsi_rst; /* 0x00z008 */ 113 u64 ce_lsi_rst; /* 0x00z008 */
114 uint64_t ce_lsi_dbg_stat; /* 0x00z010 */ 114 u64 ce_lsi_dbg_stat; /* 0x00z010 */
115 uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */ 115 u64 ce_lsi_dbg_cfg; /* 0x00z018 */
116 uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */ 116 u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
117 uint64_t ce_lsi_lk_stat; /* 0x00z028 */ 117 u64 ce_lsi_lk_stat; /* 0x00z028 */
118 uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */ 118 u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
119 uint64_t ce_lsi_int_and_stat; /* 0x00z040 */ 119 u64 ce_lsi_int_and_stat; /* 0x00z040 */
120 uint64_t ce_lsi_int_mask; /* 0x00z048 */ 120 u64 ce_lsi_int_mask; /* 0x00z048 */
121 uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */ 121 u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
122 uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */ 122 u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
123 uint64_t ce_pad_00z108; /* 0x00z108 */ 123 u64 ce_pad_00z108; /* 0x00z108 */
124 uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */ 124 u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
125 uint64_t ce_pad_00z118; /* 0x00z118 */ 125 u64 ce_pad_00z118; /* 0x00z118 */
126 uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */ 126 u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
127 uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */ 127 u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
128 uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */ 128 u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
129 uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */ 129 u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
130 uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */ 130 u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
131 uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */ 131 u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
132 uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */ 132 u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
133 uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */ 133 u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
134 uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */ 134 u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
135 uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */ 135 u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
136 uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */ 136 u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
137 uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */ 137 u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
138 uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */ 138 u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
139 uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */ 139 u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
140 uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */ 140 u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
141 uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */ 141 u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
142 uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */ 142 u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
143 uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */ 143 u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
144 uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */ 144 u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
145 uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */ 145 u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
146 uint64_t ce_lsi_rply_tmr; /* 0x00z418 */ 146 u64 ce_lsi_rply_tmr; /* 0x00z418 */
147 uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */ 147 u64 ce_lsi_rply_num_stat; /* 0x00z420 */
148 uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */ 148 u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
149 uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */ 149 u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
150 uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */ 150 u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
151 uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */ 151 u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
152 uint64_t ce_lsi_seq_cnt; /* 0x00z448 */ 152 u64 ce_lsi_seq_cnt; /* 0x00z448 */
153 uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */ 153 u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
154 uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */ 154 u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
155 uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */ 155 u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
156 uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */ 156 u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
157 uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */ 157 u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
158 uint64_t ce_pad_00z478; /* 0x00z478 */ 158 u64 ce_pad_00z478; /* 0x00z478 */
159 uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */ 159 u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
160 uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */ 160 u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
161 uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */ 161 u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
162 uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */ 162 u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
163 uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */ 163 u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
164 uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */ 164 u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
165 uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */ 165 u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
166 uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */ 166 u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
167 uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */ 167 u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
168 uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */ 168 u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
169 uint64_t ce_pad_00z4D8; /* 0x00z4D8 */ 169 u64 ce_pad_00z4D8; /* 0x00z4D8 */
170 uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */ 170 u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
171 uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */ 171 u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
172 uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */ 172 u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
173 uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */ 173 u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
174 uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */ 174 u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
175 uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */ 175 u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
176 uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */ 176 u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
177 uint64_t ce_pad_00z608; /* 0x00z608 */ 177 u64 ce_pad_00z608; /* 0x00z608 */
178 uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */ 178 u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
179 uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */ 179 u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
180 uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */ 180 u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
181 uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */ 181 u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
182 uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */ 182 u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
183 uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */ 183 u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
184 uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */ 184 u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
185 uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */ 185 u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
186 uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */ 186 u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
187 uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */ 187 u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
188 uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */ 188 u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
189 uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */ 189 u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
190 uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */ 190 u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
191 uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */ 191 u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
192 uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */ 192 u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
193 uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */ 193 u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
194 uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */ 194 u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
195 uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */ 195 u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
196 uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */ 196 u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
197 uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */ 197 u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
198 uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */ 198 u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
199 uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */ 199 u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
200 uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */ 200 u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
201 uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */ 201 u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
202 uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */ 202 u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
203 uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */ 203 u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
204 uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */ 204 u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
205 uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */ 205 u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
206 uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */ 206 u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
207 uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */ 207 u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
208 uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */ 208 u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
209 uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */ 209 u64 ce_lsi_gb_cfg1; /* 0x00z800 */
210 uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */ 210 u64 ce_lsi_gb_cfg2; /* 0x00z808 */
211 uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */ 211 u64 ce_lsi_gb_cfg3; /* 0x00z810 */
212 uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */ 212 u64 ce_lsi_gb_cfg4; /* 0x00z818 */
213 uint64_t ce_lsi_gb_stat; /* 0x00z820 */ 213 u64 ce_lsi_gb_stat; /* 0x00z820 */
214 uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */ 214 u64 ce_lsi_gb_int_stat; /* 0x00z828 */
215 uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */ 215 u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
216 uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */ 216 u64 ce_lsi_gb_int_mask; /* 0x00z838 */
217 uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */ 217 u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
218 uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */ 218 u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
219 uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */ 219 u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
220 } ce_lsi[2]; 220 } ce_lsi[2];
221 221
222 uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */ 222 u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
223 223
224 /* 224 /*
225 * CRM: Coretalk Receive Module Registers 225 * CRM: Coretalk Receive Module Registers
226 */ 226 */
227 uint64_t ce_crm_debug_mux; /* 0x004050 */ 227 u64 ce_crm_debug_mux; /* 0x004050 */
228 uint64_t ce_pad_004058; /* 0x004058 */ 228 u64 ce_pad_004058; /* 0x004058 */
229 uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */ 229 u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
230 uint64_t ce_crm_ssp_err_addr; /* 0x004068 */ 230 u64 ce_crm_ssp_err_addr; /* 0x004068 */
231 uint64_t ce_crm_ssp_err_syn; /* 0x004070 */ 231 u64 ce_crm_ssp_err_syn; /* 0x004070 */
232 232
233 uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */ 233 u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
234 234
235 /* 235 /*
236 * CXM: Coretalk Xmit Module Registers 236 * CXM: Coretalk Xmit Module Registers
237 */ 237 */
238 uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */ 238 u64 ce_cxm_dyn_credit_status; /* 0x005010 */
239 uint64_t ce_cxm_last_credit_status; /* 0x005018 */ 239 u64 ce_cxm_last_credit_status; /* 0x005018 */
240 uint64_t ce_cxm_credit_limit; /* 0x005020 */ 240 u64 ce_cxm_credit_limit; /* 0x005020 */
241 uint64_t ce_cxm_force_credit; /* 0x005028 */ 241 u64 ce_cxm_force_credit; /* 0x005028 */
242 uint64_t ce_cxm_disable_bypass; /* 0x005030 */ 242 u64 ce_cxm_disable_bypass; /* 0x005030 */
243 uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */ 243 u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
244 uint64_t ce_cxm_debug_mux; /* 0x005050 */ 244 u64 ce_cxm_debug_mux; /* 0x005050 */
245 245
246 uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */ 246 u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
247 247
248 /* 248 /*
249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2) 249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
@@ -258,209 +258,209 @@ typedef volatile struct tioce {
258 #define ce_utl(link_num) ce_dtl_utl[link_num-1] 258 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
259 struct ce_dtl_utl_reg { 259 struct ce_dtl_utl_reg {
260 /* DTL */ 260 /* DTL */
261 uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */ 261 u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
262 uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */ 262 u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
263 uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */ 263 u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
264 uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */ 264 u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
265 uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */ 265 u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
266 uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */ 266 u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
267 uint64_t ce_dtl_debug_sel; /* 0x00y050 */ 267 u64 ce_dtl_debug_sel; /* 0x00y050 */
268 uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */ 268 u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
269 269
270 /* UTL */ 270 /* UTL */
271 uint64_t ce_utl_utl_ctrl; /* 0x00z000 */ 271 u64 ce_utl_utl_ctrl; /* 0x00z000 */
272 uint64_t ce_utl_debug_sel; /* 0x00z008 */ 272 u64 ce_utl_debug_sel; /* 0x00z008 */
273 uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */ 273 u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
274 } ce_dtl_utl[2]; 274 } ce_dtl_utl[2];
275 275
276 uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */ 276 u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
277 277
278 /* 278 /*
279 * URE: Upstream Request Engine 279 * URE: Upstream Request Engine
280 */ 280 */
281 uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */ 281 u64 ce_ure_dyn_credit_status; /* 0x00B010 */
282 uint64_t ce_ure_last_credit_status; /* 0x00B018 */ 282 u64 ce_ure_last_credit_status; /* 0x00B018 */
283 uint64_t ce_ure_credit_limit; /* 0x00B020 */ 283 u64 ce_ure_credit_limit; /* 0x00B020 */
284 uint64_t ce_pad_00B028; /* 0x00B028 */ 284 u64 ce_pad_00B028; /* 0x00B028 */
285 uint64_t ce_ure_control; /* 0x00B030 */ 285 u64 ce_ure_control; /* 0x00B030 */
286 uint64_t ce_ure_status; /* 0x00B038 */ 286 u64 ce_ure_status; /* 0x00B038 */
287 uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */ 287 u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
288 uint64_t ce_ure_debug_sel; /* 0x00B050 */ 288 u64 ce_ure_debug_sel; /* 0x00B050 */
289 uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */ 289 u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
290 uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */ 290 u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
291 uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */ 291 u64 ce_ure_ssp_err_addr; /* 0x00B068 */
292 uint64_t ce_ure_page_map; /* 0x00B070 */ 292 u64 ce_ure_page_map; /* 0x00B070 */
293 uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */ 293 u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
294 uint64_t ce_ure_pipe_sel1; /* 0x00B088 */ 294 u64 ce_ure_pipe_sel1; /* 0x00B088 */
295 uint64_t ce_ure_pipe_mask1; /* 0x00B090 */ 295 u64 ce_ure_pipe_mask1; /* 0x00B090 */
296 uint64_t ce_ure_pipe_sel2; /* 0x00B098 */ 296 u64 ce_ure_pipe_sel2; /* 0x00B098 */
297 uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */ 297 u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
298 uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */ 298 u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
299 uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */ 299 u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
300 uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */ 300 u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
301 uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */ 301 u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
302 uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */ 302 u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
303 uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */ 303 u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
304 uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */ 304 u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
305 uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */ 305 u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
306 uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */ 306 u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
307 uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */ 307 u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
308 uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */ 308 u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
309 uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */ 309 u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
310 uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */ 310 u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
311 uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */ 311 u64 ce_ure_wr_tnum_val; /* 0x00B110 */
312 uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */ 312 u64 ce_ure_sram_err_addr0; /* 0x00B118 */
313 uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */ 313 u64 ce_ure_sram_err_addr1; /* 0x00B120 */
314 uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */ 314 u64 ce_ure_sram_err_addr2; /* 0x00B128 */
315 uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */ 315 u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
316 uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */ 316 u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
317 uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */ 317 u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
318 uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */ 318 u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
319 uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */ 319 u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
320 uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */ 320 u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
321 uint64_t ce_ure_buf_flush10; /* 0x00B160 */ 321 u64 ce_ure_buf_flush10; /* 0x00B160 */
322 uint64_t ce_ure_buf_flush11; /* 0x00B168 */ 322 u64 ce_ure_buf_flush11; /* 0x00B168 */
323 uint64_t ce_ure_buf_flush12; /* 0x00B170 */ 323 u64 ce_ure_buf_flush12; /* 0x00B170 */
324 uint64_t ce_ure_buf_flush13; /* 0x00B178 */ 324 u64 ce_ure_buf_flush13; /* 0x00B178 */
325 uint64_t ce_ure_buf_flush20; /* 0x00B180 */ 325 u64 ce_ure_buf_flush20; /* 0x00B180 */
326 uint64_t ce_ure_buf_flush21; /* 0x00B188 */ 326 u64 ce_ure_buf_flush21; /* 0x00B188 */
327 uint64_t ce_ure_buf_flush22; /* 0x00B190 */ 327 u64 ce_ure_buf_flush22; /* 0x00B190 */
328 uint64_t ce_ure_buf_flush23; /* 0x00B198 */ 328 u64 ce_ure_buf_flush23; /* 0x00B198 */
329 uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */ 329 u64 ce_ure_pcie_control1; /* 0x00B1A0 */
330 uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */ 330 u64 ce_ure_pcie_control2; /* 0x00B1A8 */
331 331
332 uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */ 332 u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
333 333
334 /* Upstream Data Buffer, Port1 */ 334 /* Upstream Data Buffer, Port1 */
335 struct ce_ure_maint_ups_dat1_data { 335 struct ce_ure_maint_ups_dat1_data {
336 uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */ 336 u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
337 uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */ 337 u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
338 uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */ 338 u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
339 } ce_ure_maint_ups_dat1; 339 } ce_ure_maint_ups_dat1;
340 340
341 /* Upstream Header Buffer, Port1 */ 341 /* Upstream Header Buffer, Port1 */
342 struct ce_ure_maint_ups_hdr1_data { 342 struct ce_ure_maint_ups_hdr1_data {
343 uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */ 343 u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
344 uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */ 344 u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
345 uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */ 345 u64 parity[512]; /* 0x011000 -- 0x011FF8 */
346 } ce_ure_maint_ups_hdr1; 346 } ce_ure_maint_ups_hdr1;
347 347
348 /* Upstream Data Buffer, Port2 */ 348 /* Upstream Data Buffer, Port2 */
349 struct ce_ure_maint_ups_dat2_data { 349 struct ce_ure_maint_ups_dat2_data {
350 uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */ 350 u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
351 uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */ 351 u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
352 uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */ 352 u64 parity[512]; /* 0x014000 -- 0x014FF8 */
353 } ce_ure_maint_ups_dat2; 353 } ce_ure_maint_ups_dat2;
354 354
355 /* Upstream Header Buffer, Port2 */ 355 /* Upstream Header Buffer, Port2 */
356 struct ce_ure_maint_ups_hdr2_data { 356 struct ce_ure_maint_ups_hdr2_data {
357 uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */ 357 u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
358 uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */ 358 u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
359 uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */ 359 u64 parity[512]; /* 0x017000 -- 0x017FF8 */
360 } ce_ure_maint_ups_hdr2; 360 } ce_ure_maint_ups_hdr2;
361 361
362 /* Downstream Data Buffer */ 362 /* Downstream Data Buffer */
363 struct ce_ure_maint_dns_dat_data { 363 struct ce_ure_maint_dns_dat_data {
364 uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */ 364 u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
365 uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */ 365 u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
366 uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */ 366 u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
367 } ce_ure_maint_dns_dat; 367 } ce_ure_maint_dns_dat;
368 368
369 /* Downstream Header Buffer */ 369 /* Downstream Header Buffer */
370 struct ce_ure_maint_dns_hdr_data { 370 struct ce_ure_maint_dns_hdr_data {
371 uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */ 371 u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
372 uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */ 372 u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
373 uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */ 373 u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
374 } ce_ure_maint_dns_hdr; 374 } ce_ure_maint_dns_hdr;
375 375
376 /* RCI Buffer Data */ 376 /* RCI Buffer Data */
377 struct ce_ure_maint_rci_data { 377 struct ce_ure_maint_rci_data {
378 uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */ 378 u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
379 uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */ 379 u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
380 } ce_ure_maint_rci; 380 } ce_ure_maint_rci;
381 381
382 /* Response Queue */ 382 /* Response Queue */
383 uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */ 383 u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
384 384
385 uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */ 385 u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
386 386
387 /* Admin Build-a-Packet Buffer */ 387 /* Admin Build-a-Packet Buffer */
388 struct ce_adm_maint_bap_buf_data { 388 struct ce_adm_maint_bap_buf_data {
389 uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */ 389 u64 data63_0[258]; /* 0x024000 -- 0x024808 */
390 uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */ 390 u64 data127_64[258]; /* 0x024810 -- 0x025018 */
391 uint64_t parity[258]; /* 0x025020 -- 0x025828 */ 391 u64 parity[258]; /* 0x025020 -- 0x025828 */
392 } ce_adm_maint_bap_buf; 392 } ce_adm_maint_bap_buf;
393 393
394 uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */ 394 u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
395 395
396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */ 396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
397 uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES]; 397 u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
398 398
399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */ 399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
400 uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES]; 400 u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
401 401
402 uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */ 402 u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
403 403
404 /* 404 /*
405 * DRE: Down Stream Request Engine 405 * DRE: Down Stream Request Engine
406 */ 406 */
407 uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */ 407 u64 ce_dre_dyn_credit_status1; /* 0x040010 */
408 uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */ 408 u64 ce_dre_dyn_credit_status2; /* 0x040018 */
409 uint64_t ce_dre_last_credit_status1; /* 0x040020 */ 409 u64 ce_dre_last_credit_status1; /* 0x040020 */
410 uint64_t ce_dre_last_credit_status2; /* 0x040028 */ 410 u64 ce_dre_last_credit_status2; /* 0x040028 */
411 uint64_t ce_dre_credit_limit1; /* 0x040030 */ 411 u64 ce_dre_credit_limit1; /* 0x040030 */
412 uint64_t ce_dre_credit_limit2; /* 0x040038 */ 412 u64 ce_dre_credit_limit2; /* 0x040038 */
413 uint64_t ce_dre_force_credit1; /* 0x040040 */ 413 u64 ce_dre_force_credit1; /* 0x040040 */
414 uint64_t ce_dre_force_credit2; /* 0x040048 */ 414 u64 ce_dre_force_credit2; /* 0x040048 */
415 uint64_t ce_dre_debug_mux1; /* 0x040050 */ 415 u64 ce_dre_debug_mux1; /* 0x040050 */
416 uint64_t ce_dre_debug_mux2; /* 0x040058 */ 416 u64 ce_dre_debug_mux2; /* 0x040058 */
417 uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */ 417 u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
418 uint64_t ce_dre_ssp_err_addr; /* 0x040068 */ 418 u64 ce_dre_ssp_err_addr; /* 0x040068 */
419 uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */ 419 u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
420 uint64_t ce_dre_comp_err_addr; /* 0x040078 */ 420 u64 ce_dre_comp_err_addr; /* 0x040078 */
421 uint64_t ce_dre_req_status; /* 0x040080 */ 421 u64 ce_dre_req_status; /* 0x040080 */
422 uint64_t ce_dre_config1; /* 0x040088 */ 422 u64 ce_dre_config1; /* 0x040088 */
423 uint64_t ce_dre_config2; /* 0x040090 */ 423 u64 ce_dre_config2; /* 0x040090 */
424 uint64_t ce_dre_config_req_status; /* 0x040098 */ 424 u64 ce_dre_config_req_status; /* 0x040098 */
425 uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */ 425 u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
426 uint64_t ce_dre_dyn_fifo; /* 0x040100 */ 426 u64 ce_dre_dyn_fifo; /* 0x040100 */
427 uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */ 427 u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
428 uint64_t ce_dre_last_fifo; /* 0x040120 */ 428 u64 ce_dre_last_fifo; /* 0x040120 */
429 429
430 uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */ 430 u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
431 431
432 /* DRE Downstream Head Queue */ 432 /* DRE Downstream Head Queue */
433 struct ce_dre_maint_ds_head_queue { 433 struct ce_dre_maint_ds_head_queue {
434 uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */ 434 u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
435 uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */ 435 u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
436 uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */ 436 u64 parity[32]; /* 0x040400 -- 0x0404F8 */
437 } ce_dre_maint_ds_head_q; 437 } ce_dre_maint_ds_head_q;
438 438
439 uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */ 439 u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
440 440
441 /* DRE Downstream Data Queue */ 441 /* DRE Downstream Data Queue */
442 struct ce_dre_maint_ds_data_queue { 442 struct ce_dre_maint_ds_data_queue {
443 uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */ 443 u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
444 uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */ 444 u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
445 uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */ 445 u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
446 uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */ 446 u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
447 uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */ 447 u64 parity[256]; /* 0x043000 -- 0x0437F8 */
448 uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */ 448 u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
449 } ce_dre_maint_ds_data_q; 449 } ce_dre_maint_ds_data_q;
450 450
451 /* DRE URE Upstream Response Queue */ 451 /* DRE URE Upstream Response Queue */
452 struct ce_dre_maint_ure_us_rsp_queue { 452 struct ce_dre_maint_ure_us_rsp_queue {
453 uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */ 453 u64 data63_0[8]; /* 0x044000 -- 0x044038 */
454 uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */ 454 u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
455 uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */ 455 u64 data127_64[8]; /* 0x044100 -- 0x044138 */
456 uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */ 456 u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
457 uint64_t parity[8]; /* 0x044200 -- 0x044238 */ 457 u64 parity[8]; /* 0x044200 -- 0x044238 */
458 uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */ 458 u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
459 } ce_dre_maint_ure_us_rsp_q; 459 } ce_dre_maint_ure_us_rsp_q;
460 460
461 uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */ 461 u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
462 462
463 uint64_t ce_end_of_struct; /* 0x044400 */ 463 u64 ce_end_of_struct; /* 0x044400 */
464} tioce_t; 464} tioce_t;
465 465
466 466
@@ -625,11 +625,11 @@ typedef volatile struct tioce {
625#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT) 625#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
626#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT) 626#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
627#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT) 627#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
628#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \ 628#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
629 CE_URE_BUS_MASK) 629 CE_URE_BUS_MASK)
630#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \ 630#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
631 CE_URE_DEV_MASK) 631 CE_URE_DEV_MASK)
632#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \ 632#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
633 CE_URE_FNC_MASK) 633 CE_URE_FNC_MASK)
634 634
635#define CE_URE_SEL1_SHFT 0 635#define CE_URE_SEL1_SHFT 0
@@ -660,9 +660,9 @@ typedef volatile struct tioce {
660#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT) 660#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
661#define CE_URE_PN2_SHFT 24 661#define CE_URE_PN2_SHFT 24
662#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT) 662#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
663#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \ 663#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
664 CE_URE_PN1_MASK) 664 CE_URE_PN1_MASK)
665#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \ 665#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
666 CE_URE_PN2_MASK) 666 CE_URE_PN2_MASK)
667 667
668/* ce_ure_pcie_control2 register bit masks & shifts */ 668/* ce_ure_pcie_control2 register bit masks & shifts */
@@ -681,9 +681,9 @@ typedef volatile struct tioce {
681#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT) 681#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
682#define CE_URE_PSN2_SHFT 32 682#define CE_URE_PSN2_SHFT 32
683#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT) 683#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
684#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \ 684#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
685 CE_URE_PSN1_MASK) 685 CE_URE_PSN1_MASK)
686#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \ 686#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
687 CE_URE_PSN2_MASK) 687 CE_URE_PSN2_MASK)
688 688
689/* 689/*
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
index cb414908671d..6d62b13f7ae7 100644
--- a/include/asm-ia64/sn/tioce_provider.h
+++ b/include/asm-ia64/sn/tioce_provider.h
@@ -21,9 +21,9 @@
21struct tioce_common { 21struct tioce_common {
22 struct pcibus_bussoft ce_pcibus; /* common pciio header */ 22 struct pcibus_bussoft ce_pcibus; /* common pciio header */
23 23
24 uint32_t ce_rev; 24 u32 ce_rev;
25 uint64_t ce_kernel_private; 25 u64 ce_kernel_private;
26 uint64_t ce_prom_private; 26 u64 ce_prom_private;
27}; 27};
28 28
29struct tioce_kernel { 29struct tioce_kernel {
@@ -31,31 +31,31 @@ struct tioce_kernel {
31 spinlock_t ce_lock; 31 spinlock_t ce_lock;
32 struct list_head ce_dmamap_list; 32 struct list_head ce_dmamap_list;
33 33
34 uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES]; 34 u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
35 uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES]; 35 u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
36 uint32_t ce_ate3240_pagesize; 36 u32 ce_ate3240_pagesize;
37 37
38 uint8_t ce_port1_secondary; 38 u8 ce_port1_secondary;
39 39
40 /* per-port resources */ 40 /* per-port resources */
41 struct { 41 struct {
42 int dirmap_refcnt; 42 int dirmap_refcnt;
43 uint64_t dirmap_shadow; 43 u64 dirmap_shadow;
44 } ce_port[TIOCE_NUM_PORTS]; 44 } ce_port[TIOCE_NUM_PORTS];
45}; 45};
46 46
47struct tioce_dmamap { 47struct tioce_dmamap {
48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */ 48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
49 uint32_t refcnt; 49 u32 refcnt;
50 50
51 uint64_t nbytes; /* # bytes mapped */ 51 u64 nbytes; /* # bytes mapped */
52 52
53 uint64_t ct_start; /* coretalk start address */ 53 u64 ct_start; /* coretalk start address */
54 uint64_t pci_start; /* bus start address */ 54 u64 pci_start; /* bus start address */
55 55
56 uint64_t *ate_hw; /* hw ptr of first ate in map */ 56 u64 *ate_hw; /* hw ptr of first ate in map */
57 uint64_t *ate_shadow; /* shadow ptr of firat ate */ 57 u64 *ate_shadow; /* shadow ptr of firat ate */
58 uint16_t ate_count; /* # ate's in the map */ 58 u16 ate_count; /* # ate's in the map */
59}; 59};
60 60
61extern int tioce_init_provider(void); 61extern int tioce_init_provider(void);
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
index 5f2489c9d2dd..f47c08ab483c 100644
--- a/include/asm-ia64/sn/tiocp.h
+++ b/include/asm-ia64/sn/tiocp.h
@@ -21,189 +21,189 @@ struct tiocp{
21 /* 0x000000-0x00FFFF -- Local Registers */ 21 /* 0x000000-0x00FFFF -- Local Registers */
22 22
23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */ 23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
24 uint64_t cp_id; /* 0x000000 */ 24 u64 cp_id; /* 0x000000 */
25 uint64_t cp_stat; /* 0x000008 */ 25 u64 cp_stat; /* 0x000008 */
26 uint64_t cp_err_upper; /* 0x000010 */ 26 u64 cp_err_upper; /* 0x000010 */
27 uint64_t cp_err_lower; /* 0x000018 */ 27 u64 cp_err_lower; /* 0x000018 */
28 #define cp_err cp_err_lower 28 #define cp_err cp_err_lower
29 uint64_t cp_control; /* 0x000020 */ 29 u64 cp_control; /* 0x000020 */
30 uint64_t cp_req_timeout; /* 0x000028 */ 30 u64 cp_req_timeout; /* 0x000028 */
31 uint64_t cp_intr_upper; /* 0x000030 */ 31 u64 cp_intr_upper; /* 0x000030 */
32 uint64_t cp_intr_lower; /* 0x000038 */ 32 u64 cp_intr_lower; /* 0x000038 */
33 #define cp_intr cp_intr_lower 33 #define cp_intr cp_intr_lower
34 uint64_t cp_err_cmdword; /* 0x000040 */ 34 u64 cp_err_cmdword; /* 0x000040 */
35 uint64_t _pad_000048; /* 0x000048 */ 35 u64 _pad_000048; /* 0x000048 */
36 uint64_t cp_tflush; /* 0x000050 */ 36 u64 cp_tflush; /* 0x000050 */
37 37
38 /* 0x000058-0x00007F -- Bridge-specific Configuration */ 38 /* 0x000058-0x00007F -- Bridge-specific Configuration */
39 uint64_t cp_aux_err; /* 0x000058 */ 39 u64 cp_aux_err; /* 0x000058 */
40 uint64_t cp_resp_upper; /* 0x000060 */ 40 u64 cp_resp_upper; /* 0x000060 */
41 uint64_t cp_resp_lower; /* 0x000068 */ 41 u64 cp_resp_lower; /* 0x000068 */
42 #define cp_resp cp_resp_lower 42 #define cp_resp cp_resp_lower
43 uint64_t cp_tst_pin_ctrl; /* 0x000070 */ 43 u64 cp_tst_pin_ctrl; /* 0x000070 */
44 uint64_t cp_addr_lkerr; /* 0x000078 */ 44 u64 cp_addr_lkerr; /* 0x000078 */
45 45
46 /* 0x000080-0x00008F -- PMU & MAP */ 46 /* 0x000080-0x00008F -- PMU & MAP */
47 uint64_t cp_dir_map; /* 0x000080 */ 47 u64 cp_dir_map; /* 0x000080 */
48 uint64_t _pad_000088; /* 0x000088 */ 48 u64 _pad_000088; /* 0x000088 */
49 49
50 /* 0x000090-0x00009F -- SSRAM */ 50 /* 0x000090-0x00009F -- SSRAM */
51 uint64_t cp_map_fault; /* 0x000090 */ 51 u64 cp_map_fault; /* 0x000090 */
52 uint64_t _pad_000098; /* 0x000098 */ 52 u64 _pad_000098; /* 0x000098 */
53 53
54 /* 0x0000A0-0x0000AF -- Arbitration */ 54 /* 0x0000A0-0x0000AF -- Arbitration */
55 uint64_t cp_arb; /* 0x0000A0 */ 55 u64 cp_arb; /* 0x0000A0 */
56 uint64_t _pad_0000A8; /* 0x0000A8 */ 56 u64 _pad_0000A8; /* 0x0000A8 */
57 57
58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
59 uint64_t cp_ate_parity_err; /* 0x0000B0 */ 59 u64 cp_ate_parity_err; /* 0x0000B0 */
60 uint64_t _pad_0000B8; /* 0x0000B8 */ 60 u64 _pad_0000B8; /* 0x0000B8 */
61 61
62 /* 0x0000C0-0x0000FF -- PCI/GIO */ 62 /* 0x0000C0-0x0000FF -- PCI/GIO */
63 uint64_t cp_bus_timeout; /* 0x0000C0 */ 63 u64 cp_bus_timeout; /* 0x0000C0 */
64 uint64_t cp_pci_cfg; /* 0x0000C8 */ 64 u64 cp_pci_cfg; /* 0x0000C8 */
65 uint64_t cp_pci_err_upper; /* 0x0000D0 */ 65 u64 cp_pci_err_upper; /* 0x0000D0 */
66 uint64_t cp_pci_err_lower; /* 0x0000D8 */ 66 u64 cp_pci_err_lower; /* 0x0000D8 */
67 #define cp_pci_err cp_pci_err_lower 67 #define cp_pci_err cp_pci_err_lower
68 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 68 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
69 69
70 /* 0x000100-0x0001FF -- Interrupt */ 70 /* 0x000100-0x0001FF -- Interrupt */
71 uint64_t cp_int_status; /* 0x000100 */ 71 u64 cp_int_status; /* 0x000100 */
72 uint64_t cp_int_enable; /* 0x000108 */ 72 u64 cp_int_enable; /* 0x000108 */
73 uint64_t cp_int_rst_stat; /* 0x000110 */ 73 u64 cp_int_rst_stat; /* 0x000110 */
74 uint64_t cp_int_mode; /* 0x000118 */ 74 u64 cp_int_mode; /* 0x000118 */
75 uint64_t cp_int_device; /* 0x000120 */ 75 u64 cp_int_device; /* 0x000120 */
76 uint64_t cp_int_host_err; /* 0x000128 */ 76 u64 cp_int_host_err; /* 0x000128 */
77 uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */ 77 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
78 uint64_t cp_err_int_view; /* 0x000170 */ 78 u64 cp_err_int_view; /* 0x000170 */
79 uint64_t cp_mult_int; /* 0x000178 */ 79 u64 cp_mult_int; /* 0x000178 */
80 uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */ 80 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
81 uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */ 81 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
82 82
83 /* 0x000200-0x000298 -- Device */ 83 /* 0x000200-0x000298 -- Device */
84 uint64_t cp_device[4]; /* 0x0002{00,,,18} */ 84 u64 cp_device[4]; /* 0x0002{00,,,18} */
85 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 85 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
86 uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */ 86 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
87 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 87 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
88 uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */ 88 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */ 89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */ 90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
91 uint64_t cp_resp_status; /* 0x000290 */ 91 u64 cp_resp_status; /* 0x000290 */
92 uint64_t cp_resp_clear; /* 0x000298 */ 92 u64 cp_resp_clear; /* 0x000298 */
93 93
94 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 94 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
95 95
96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
97 struct { 97 struct {
98 uint64_t upper; /* 0x0003{00,,,F0} */ 98 u64 upper; /* 0x0003{00,,,F0} */
99 uint64_t lower; /* 0x0003{08,,,F8} */ 99 u64 lower; /* 0x0003{08,,,F8} */
100 } cp_buf_addr_match[16]; 100 } cp_buf_addr_match[16];
101 101
102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
103 struct { 103 struct {
104 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 104 u64 flush_w_touch; /* 0x000{400,,,5C0} */
105 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 105 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
106 uint64_t inflight; /* 0x000{410,,,5D0} */ 106 u64 inflight; /* 0x000{410,,,5D0} */
107 uint64_t prefetch; /* 0x000{418,,,5D8} */ 107 u64 prefetch; /* 0x000{418,,,5D8} */
108 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 108 u64 total_pci_retry; /* 0x000{420,,,5E0} */
109 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 109 u64 max_pci_retry; /* 0x000{428,,,5E8} */
110 uint64_t max_latency; /* 0x000{430,,,5F0} */ 110 u64 max_latency; /* 0x000{430,,,5F0} */
111 uint64_t clear_all; /* 0x000{438,,,5F8} */ 111 u64 clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8]; 112 } cp_buf_count[8];
113 113
114 114
115 /* 0x000600-0x0009FF -- PCI/X registers */ 115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ 116 u64 cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */ 117 u64 cp_pcix_bus_err_attr; /* 0x000608 */
118 uint64_t cp_pcix_bus_err_data; /* 0x000610 */ 118 u64 cp_pcix_bus_err_data; /* 0x000610 */
119 uint64_t cp_pcix_pio_split_addr; /* 0x000618 */ 119 u64 cp_pcix_pio_split_addr; /* 0x000618 */
120 uint64_t cp_pcix_pio_split_attr; /* 0x000620 */ 120 u64 cp_pcix_pio_split_attr; /* 0x000620 */
121 uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */ 121 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
122 uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */ 122 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
123 uint64_t cp_pcix_timeout; /* 0x000638 */ 123 u64 cp_pcix_timeout; /* 0x000638 */
124 124
125 uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */ 125 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
126 126
127 /* 0x000700-0x000737 -- Debug Registers */ 127 /* 0x000700-0x000737 -- Debug Registers */
128 uint64_t cp_ct_debug_ctl; /* 0x000700 */ 128 u64 cp_ct_debug_ctl; /* 0x000700 */
129 uint64_t cp_br_debug_ctl; /* 0x000708 */ 129 u64 cp_br_debug_ctl; /* 0x000708 */
130 uint64_t cp_mux3_debug_ctl; /* 0x000710 */ 130 u64 cp_mux3_debug_ctl; /* 0x000710 */
131 uint64_t cp_mux4_debug_ctl; /* 0x000718 */ 131 u64 cp_mux4_debug_ctl; /* 0x000718 */
132 uint64_t cp_mux5_debug_ctl; /* 0x000720 */ 132 u64 cp_mux5_debug_ctl; /* 0x000720 */
133 uint64_t cp_mux6_debug_ctl; /* 0x000728 */ 133 u64 cp_mux6_debug_ctl; /* 0x000728 */
134 uint64_t cp_mux7_debug_ctl; /* 0x000730 */ 134 u64 cp_mux7_debug_ctl; /* 0x000730 */
135 135
136 uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */ 136 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
137 137
138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
139 struct { 139 struct {
140 uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */ 140 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
141 uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */ 141 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
142 } cp_pcix_read_buf_64[16]; 142 } cp_pcix_read_buf_64[16];
143 143
144 struct { 144 struct {
145 uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */ 145 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
146 uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */ 146 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
147 uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */ 147 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
148 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 148 u64 __pad1; /* 0x000{B18,,,BF8} */
149 } cp_pcix_write_buf_64[8]; 149 } cp_pcix_write_buf_64[8];
150 150
151 /* End of Local Registers -- Start of Address Map space */ 151 /* End of Local Registers -- Start of Address Map space */
152 152
153 char _pad_000c00[0x010000 - 0x000c00]; 153 char _pad_000c00[0x010000 - 0x000c00];
154 154
155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */ 155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
156 uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */ 156 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
157 157
158 char _pad_012000[0x14000 - 0x012000]; 158 char _pad_012000[0x14000 - 0x012000];
159 159
160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */ 160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
161 uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */ 161 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
162 162
163 char _pad_016000[0x18000 - 0x016000]; 163 char _pad_016000[0x18000 - 0x016000];
164 164
165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */ 165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
166 uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 166 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
167 uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 167 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
168 uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 168 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
169 169
170 char _pad_019800[0x1C000 - 0x019800]; 170 char _pad_019800[0x1C000 - 0x019800];
171 171
172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */ 172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
173 uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */ 173 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
174 uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */ 174 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
175 uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */ 175 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
176 176
177 char _pad_01F000[0x20000 - 0x01F000]; 177 char _pad_01F000[0x20000 - 0x01F000];
178 178
179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */ 179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
180 char _pad_020000[0x021000 - 0x20000]; 180 char _pad_020000[0x021000 - 0x20000];
181 181
182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */ 182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
183 union { 183 union {
184 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 184 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
185 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 185 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
186 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 186 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
187 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 187 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
188 union { 188 union {
189 uint8_t c[0x100 / 1]; 189 u8 c[0x100 / 1];
190 uint16_t s[0x100 / 2]; 190 u16 s[0x100 / 2];
191 uint32_t l[0x100 / 4]; 191 u32 l[0x100 / 4];
192 uint64_t d[0x100 / 8]; 192 u64 d[0x100 / 8];
193 } f[8]; 193 } f[8];
194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */ 194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
195 195
196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
197 union { 197 union {
198 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 198 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
199 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 199 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
200 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 200 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
201 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 201 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
202 union { 202 union {
203 uint8_t c[0x100 / 1]; 203 u8 c[0x100 / 1];
204 uint16_t s[0x100 / 2]; 204 u16 s[0x100 / 2];
205 uint32_t l[0x100 / 4]; 205 u32 l[0x100 / 4];
206 uint64_t d[0x100 / 8]; 206 u64 d[0x100 / 8];
207 } f[8]; 207 } f[8];
208 } cp_type1_cfg; /* 0x028000-0x029000 */ 208 } cp_type1_cfg; /* 0x028000-0x029000 */
209 209
@@ -211,30 +211,30 @@ struct tiocp{
211 211
212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
213 union { 213 union {
214 uint8_t c[8 / 1]; 214 u8 c[8 / 1];
215 uint16_t s[8 / 2]; 215 u16 s[8 / 2];
216 uint32_t l[8 / 4]; 216 u32 l[8 / 4];
217 uint64_t d[8 / 8]; 217 u64 d[8 / 8];
218 } cp_pci_iack; /* 0x030000-0x030007 */ 218 } cp_pci_iack; /* 0x030000-0x030007 */
219 219
220 char _pad_030007[0x040000-0x030008]; 220 char _pad_030007[0x040000-0x030008];
221 221
222 /* 0x040000-0x040007 -- PCIX Special Cycle */ 222 /* 0x040000-0x040007 -- PCIX Special Cycle */
223 union { 223 union {
224 uint8_t c[8 / 1]; 224 u8 c[8 / 1];
225 uint16_t s[8 / 2]; 225 u16 s[8 / 2];
226 uint32_t l[8 / 4]; 226 u32 l[8 / 4];
227 uint64_t d[8 / 8]; 227 u64 d[8 / 8];
228 } cp_pcix_cycle; /* 0x040000-0x040007 */ 228 } cp_pcix_cycle; /* 0x040000-0x040007 */
229 229
230 char _pad_040007[0x200000-0x040008]; 230 char _pad_040007[0x200000-0x040008];
231 231
232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */ 232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
233 union { 233 union {
234 uint8_t c[0x100000 / 1]; 234 u8 c[0x100000 / 1];
235 uint16_t s[0x100000 / 2]; 235 u16 s[0x100000 / 2];
236 uint32_t l[0x100000 / 4]; 236 u32 l[0x100000 / 4];
237 uint64_t d[0x100000 / 8]; 237 u64 d[0x100000 / 8];
238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */ 238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
239 239
240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)] 240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
@@ -243,10 +243,10 @@ struct tiocp{
243 243
244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */ 244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
245 union { 245 union {
246 uint8_t c[0x100000 / 1]; 246 u8 c[0x100000 / 1];
247 uint16_t s[0x100000 / 2]; 247 u16 s[0x100000 / 2];
248 uint32_t l[0x100000 / 4]; 248 u32 l[0x100000 / 4];
249 uint64_t d[0x100000 / 8]; 249 u64 d[0x100000 / 8];
250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */ 250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
251 251
252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)] 252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
index 5699e75e5024..d29728492f36 100644
--- a/include/asm-ia64/sn/tiocx.h
+++ b/include/asm-ia64/sn/tiocx.h
@@ -40,10 +40,10 @@ struct cx_drv {
40}; 40};
41 41
42/* create DMA address by stripping AS bits */ 42/* create DMA address by stripping AS bits */
43#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL) 43#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
44 44
45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \ 45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
46 ((((uint64_t)(a)) & 0xffffc000000000UL) <<2)) 46 ((((u64)(a)) & 0xffffc000000000UL) <<2))
47 47
48#define TIO_CE_ASIC_PARTNUM 0xce00 48#define TIO_CE_ASIC_PARTNUM 0xce00
49#define TIOCX_CORELET 3 49#define TIOCX_CORELET 3
@@ -63,10 +63,10 @@ extern int cx_device_unregister(struct cx_dev *);
63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int); 63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
64extern int cx_driver_unregister(struct cx_drv *); 64extern int cx_driver_unregister(struct cx_drv *);
65extern int cx_driver_register(struct cx_drv *); 65extern int cx_driver_register(struct cx_drv *);
66extern uint64_t tiocx_dma_addr(uint64_t addr); 66extern u64 tiocx_dma_addr(u64 addr);
67extern uint64_t tiocx_swin_base(int nasid); 67extern u64 tiocx_swin_base(int nasid);
68extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value); 68extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
69extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset); 69extern u64 tiocx_mmr_load(int nasid, u64 offset);
70 70
71#endif // __KERNEL__ 71#endif // __KERNEL__
72#endif // _ASM_IA64_SN_TIO_TIOCX__ 72#endif // _ASM_IA64_SN_TIO_TIOCX__
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 07:54:25 -0500