2 files changed, 0 insertions, 46 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e6da16a1f7bf..f61a4d8f012f 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7072,30 +7072,6 @@ static int tg3_chip_reset(struct tg3 *tp)
 
         tg3_mdio_start(tp);
 
-        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
-                u8 phy_addr;
-
-                phy_addr = tp->phy_addr;
-                tp->phy_addr = TG3_PHY_PCIE_ADDR;
-
-                tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                             TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
-                val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
-                      TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
-                      TG3_PCIEPHY_TX0CTRL1_NB_EN;
-                tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
-                udelay(10);
-
-                tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                             TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
-                val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
-                      TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
-                tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
-                udelay(10);
-
-                tp->phy_addr = phy_addr;
-        }
-
         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index be7ab91f4dda..0432399ca741 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2032,31 +2032,9 @@
 
 
 /* Currently this is fixed. */
-#define TG3_PHY_PCIE_ADDR               0x00
 #define TG3_PHY_MII_ADDR                0x01
 
 
-/*** Tigon3 specific PHY PCIE registers. ***/
-
-#define TG3_PCIEPHY_BLOCK_ADDR          0x1f
-#define  TG3_PCIEPHY_XGXS_BLK1          0x0801
-#define  TG3_PCIEPHY_TXB_BLK            0x0861
-#define  TG3_PCIEPHY_BLOCK_SHIFT        4
-
-/* TG3_PCIEPHY_TXB_BLK */
-#define TG3_PCIEPHY_TX0CTRL1            0x15
-#define  TG3_PCIEPHY_TX0CTRL1_TXOCM     0x0003
-#define  TG3_PCIEPHY_TX0CTRL1_RDCTL     0x0008
-#define  TG3_PCIEPHY_TX0CTRL1_TXCMV     0x0030
-#define  TG3_PCIEPHY_TX0CTRL1_TKSEL     0x0040
-#define  TG3_PCIEPHY_TX0CTRL1_NB_EN     0x0400
-
-/* TG3_PCIEPHY_XGXS_BLK1 */
-#define TG3_PCIEPHY_PWRMGMT4            0x1a
-#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
-#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN  0x4000
-
-
 /*** Tigon3 specific PHY MII registers. ***/
 #define  TG3_BMCR_SPEED1000             0x0040