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-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h50
-rw-r--r--arch/blackfin/mach-bf518/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h50
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h44
-rw-r--r--arch/blackfin/mach-bf533/include/mach/pll.h57
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h44
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h57
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h50
-rw-r--r--arch/blackfin/mach-bf538/include/mach/pll.h63
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h56
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h69
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h50
-rw-r--r--arch/blackfin/mach-bf561/include/mach/pll.h63
-rw-r--r--drivers/net/bfin_mac.c1
15 files changed, 436 insertions, 344 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index e548e9d1d6fa..29498e59e71f 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -1058,54 +1058,4 @@
1058/* These need to be last due to the cdef/linux inter-dependencies */ 1058/* These need to be last due to the cdef/linux inter-dependencies */
1059#include <asm/irq.h> 1059#include <asm/irq.h>
1060 1060
1061/* Writing to PLL_CTL initiates a PLL relock sequence. */
1062static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1063{
1064 unsigned long flags, iwr0, iwr1;
1065
1066 if (val == bfin_read_PLL_CTL())
1067 return;
1068
1069 local_irq_save_hw(flags);
1070 /* Enable the PLL Wakeup bit in SIC IWR */
1071 iwr0 = bfin_read32(SIC_IWR0);
1072 iwr1 = bfin_read32(SIC_IWR1);
1073 /* Only allow PPL Wakeup) */
1074 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1075 bfin_write32(SIC_IWR1, 0);
1076
1077 bfin_write16(PLL_CTL, val);
1078 SSYNC();
1079 asm("IDLE;");
1080
1081 bfin_write32(SIC_IWR0, iwr0);
1082 bfin_write32(SIC_IWR1, iwr1);
1083 local_irq_restore_hw(flags);
1084}
1085
1086/* Writing to VR_CTL initiates a PLL relock sequence. */
1087static __inline__ void bfin_write_VR_CTL(unsigned int val)
1088{
1089 unsigned long flags, iwr0, iwr1;
1090
1091 if (val == bfin_read_VR_CTL())
1092 return;
1093
1094 local_irq_save_hw(flags);
1095 /* Enable the PLL Wakeup bit in SIC IWR */
1096 iwr0 = bfin_read32(SIC_IWR0);
1097 iwr1 = bfin_read32(SIC_IWR1);
1098 /* Only allow PPL Wakeup) */
1099 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1100 bfin_write32(SIC_IWR1, 0);
1101
1102 bfin_write16(VR_CTL, val);
1103 SSYNC();
1104 asm("IDLE;");
1105
1106 bfin_write32(SIC_IWR0, iwr0);
1107 bfin_write32(SIC_IWR1, iwr1);
1108 local_irq_restore_hw(flags);
1109}
1110
1111#endif /* _CDEF_BF52X_H */ 1061#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
new file mode 100644
index 000000000000..9c19a077e91a
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 local_irq_restore_hw(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 local_irq_save_hw(flags);
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 local_irq_restore_hw(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 12f2ad45314e..11fb27bc427d 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -1110,54 +1110,4 @@
1110/* These need to be last due to the cdef/linux inter-dependencies */ 1110/* These need to be last due to the cdef/linux inter-dependencies */
1111#include <asm/irq.h> 1111#include <asm/irq.h>
1112 1112
1113/* Writing to PLL_CTL initiates a PLL relock sequence. */
1114static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1115{
1116 unsigned long flags, iwr0, iwr1;
1117
1118 if (val == bfin_read_PLL_CTL())
1119 return;
1120
1121 local_irq_save_hw(flags);
1122 /* Enable the PLL Wakeup bit in SIC IWR */
1123 iwr0 = bfin_read32(SIC_IWR0);
1124 iwr1 = bfin_read32(SIC_IWR1);
1125 /* Only allow PPL Wakeup) */
1126 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1127 bfin_write32(SIC_IWR1, 0);
1128
1129 bfin_write16(PLL_CTL, val);
1130 SSYNC();
1131 asm("IDLE;");
1132
1133 bfin_write32(SIC_IWR0, iwr0);
1134 bfin_write32(SIC_IWR1, iwr1);
1135 local_irq_restore_hw(flags);
1136}
1137
1138/* Writing to VR_CTL initiates a PLL relock sequence. */
1139static __inline__ void bfin_write_VR_CTL(unsigned int val)
1140{
1141 unsigned long flags, iwr0, iwr1;
1142
1143 if (val == bfin_read_VR_CTL())
1144 return;
1145
1146 local_irq_save_hw(flags);
1147 /* Enable the PLL Wakeup bit in SIC IWR */
1148 iwr0 = bfin_read32(SIC_IWR0);
1149 iwr1 = bfin_read32(SIC_IWR1);
1150 /* Only allow PPL Wakeup) */
1151 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1152 bfin_write32(SIC_IWR1, 0);
1153
1154 bfin_write16(VR_CTL, val);
1155 SSYNC();
1156 asm("IDLE;");
1157
1158 bfin_write32(SIC_IWR0, iwr0);
1159 bfin_write32(SIC_IWR1, iwr1);
1160 local_irq_restore_hw(flags);
1161}
1162
1163#endif /* _CDEF_BF52X_H */ 1113#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
new file mode 100644
index 000000000000..a9105226a994
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 local_irq_restore_hw(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 local_irq_save_hw(flags);
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 local_irq_restore_hw(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index feb2392c43ea..8edad6d60f64 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -697,48 +697,4 @@ BFIN_READ_FIO_FLAG(T)
697#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) 697#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
698#endif 698#endif
699 699
700/* Writing to PLL_CTL initiates a PLL relock sequence. */
701static __inline__ void bfin_write_PLL_CTL(unsigned int val)
702{
703 unsigned long flags, iwr;
704
705 if (val == bfin_read_PLL_CTL())
706 return;
707
708 local_irq_save_hw(flags);
709 /* Enable the PLL Wakeup bit in SIC IWR */
710 iwr = bfin_read32(SIC_IWR);
711 /* Only allow PPL Wakeup) */
712 bfin_write32(SIC_IWR, IWR_ENABLE(0));
713
714 bfin_write16(PLL_CTL, val);
715 SSYNC();
716 asm("IDLE;");
717
718 bfin_write32(SIC_IWR, iwr);
719 local_irq_restore_hw(flags);
720}
721
722/* Writing to VR_CTL initiates a PLL relock sequence. */
723static __inline__ void bfin_write_VR_CTL(unsigned int val)
724{
725 unsigned long flags, iwr;
726
727 if (val == bfin_read_VR_CTL())
728 return;
729
730 local_irq_save_hw(flags);
731 /* Enable the PLL Wakeup bit in SIC IWR */
732 iwr = bfin_read32(SIC_IWR);
733 /* Only allow PPL Wakeup) */
734 bfin_write32(SIC_IWR, IWR_ENABLE(0));
735
736 bfin_write16(VR_CTL, val);
737 SSYNC();
738 asm("IDLE;");
739
740 bfin_write32(SIC_IWR, iwr);
741 local_irq_restore_hw(flags);
742}
743
744#endif /* _CDEF_BF532_H */ 700#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
new file mode 100644
index 000000000000..9a0c9a2f1278
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 local_irq_restore_hw(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 local_irq_save_hw(flags);
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 local_irq_restore_hw(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index 91825c9bd226..fbeb35e14135 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1750,48 +1750,4 @@
1750/* These need to be last due to the cdef/linux inter-dependencies */ 1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h> 1751#include <asm/irq.h>
1752 1752
1753/* Writing to PLL_CTL initiates a PLL relock sequence. */
1754static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1755{
1756 unsigned long flags, iwr;
1757
1758 if (val == bfin_read_PLL_CTL())
1759 return;
1760
1761 local_irq_save_hw(flags);
1762 /* Enable the PLL Wakeup bit in SIC IWR */
1763 iwr = bfin_read32(SIC_IWR);
1764 /* Only allow PPL Wakeup) */
1765 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1766
1767 bfin_write16(PLL_CTL, val);
1768 SSYNC();
1769 asm("IDLE;");
1770
1771 bfin_write32(SIC_IWR, iwr);
1772 local_irq_restore_hw(flags);
1773}
1774
1775/* Writing to VR_CTL initiates a PLL relock sequence. */
1776static __inline__ void bfin_write_VR_CTL(unsigned int val)
1777{
1778 unsigned long flags, iwr;
1779
1780 if (val == bfin_read_VR_CTL())
1781 return;
1782
1783 local_irq_save_hw(flags);
1784 /* Enable the PLL Wakeup bit in SIC IWR */
1785 iwr = bfin_read32(SIC_IWR);
1786 /* Only allow PPL Wakeup) */
1787 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1788
1789 bfin_write16(VR_CTL, val);
1790 SSYNC();
1791 asm("IDLE;");
1792
1793 bfin_write32(SIC_IWR, iwr);
1794 local_irq_restore_hw(flags);
1795}
1796
1797#endif /* _CDEF_BF534_H */ 1753#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
new file mode 100644
index 000000000000..9a0c9a2f1278
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 local_irq_restore_hw(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 local_irq_save_hw(flags);
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 local_irq_restore_hw(flags);
55}
56
57#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 66aa722cf6c8..085b06b8c0a5 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -2027,54 +2027,4 @@
2027/* These need to be last due to the cdef/linux inter-dependencies */ 2027/* These need to be last due to the cdef/linux inter-dependencies */
2028#include <asm/irq.h> 2028#include <asm/irq.h>
2029 2029
2030/* Writing to PLL_CTL initiates a PLL relock sequence. */
2031static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2032{
2033 unsigned long flags, iwr0, iwr1;
2034
2035 if (val == bfin_read_PLL_CTL())
2036 return;
2037
2038 local_irq_save_hw(flags);
2039 /* Enable the PLL Wakeup bit in SIC IWR */
2040 iwr0 = bfin_read32(SIC_IWR0);
2041 iwr1 = bfin_read32(SIC_IWR1);
2042 /* Only allow PPL Wakeup) */
2043 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2044 bfin_write32(SIC_IWR1, 0);
2045
2046 bfin_write16(PLL_CTL, val);
2047 SSYNC();
2048 asm("IDLE;");
2049
2050 bfin_write32(SIC_IWR0, iwr0);
2051 bfin_write32(SIC_IWR1, iwr1);
2052 local_irq_restore_hw(flags);
2053}
2054
2055/* Writing to VR_CTL initiates a PLL relock sequence. */
2056static __inline__ void bfin_write_VR_CTL(unsigned int val)
2057{
2058 unsigned long flags, iwr0, iwr1;
2059
2060 if (val == bfin_read_VR_CTL())
2061 return;
2062
2063 local_irq_save_hw(flags);
2064 /* Enable the PLL Wakeup bit in SIC IWR */
2065 iwr0 = bfin_read32(SIC_IWR0);
2066 iwr1 = bfin_read32(SIC_IWR1);
2067 /* Only allow PPL Wakeup) */
2068 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2069 bfin_write32(SIC_IWR1, 0);
2070
2071 bfin_write16(VR_CTL, val);
2072 SSYNC();
2073 asm("IDLE;");
2074
2075 bfin_write32(SIC_IWR0, iwr0);
2076 bfin_write32(SIC_IWR1, iwr1);
2077 local_irq_restore_hw(flags);
2078}
2079
2080#endif 2030#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
new file mode 100644
index 000000000000..0e67452df6be
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2008-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
27 bfin_write32(SIC_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SIC_IWR0, iwr0);
34 bfin_write32(SIC_IWR1, iwr1);
35 local_irq_restore_hw(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 local_irq_save_hw(flags);
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SIC_IWR0);
49 iwr1 = bfin_read32(SIC_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
52 bfin_write32(SIC_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SIC_IWR0, iwr0);
59 bfin_write32(SIC_IWR1, iwr1);
60 local_irq_restore_hw(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index ea3ec4ea9e2b..0c16067df4f3 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -2648,61 +2648,5 @@
2648/* These need to be last due to the cdef/linux inter-dependencies */ 2648/* These need to be last due to the cdef/linux inter-dependencies */
2649#include <asm/irq.h> 2649#include <asm/irq.h>
2650 2650
2651/* Writing to PLL_CTL initiates a PLL relock sequence. */
2652static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2653{
2654 unsigned long flags, iwr0, iwr1, iwr2;
2655
2656 if (val == bfin_read_PLL_CTL())
2657 return;
2658
2659 local_irq_save_hw(flags);
2660 /* Enable the PLL Wakeup bit in SIC IWR */
2661 iwr0 = bfin_read32(SIC_IWR0);
2662 iwr1 = bfin_read32(SIC_IWR1);
2663 iwr2 = bfin_read32(SIC_IWR2);
2664 /* Only allow PPL Wakeup) */
2665 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2666 bfin_write32(SIC_IWR1, 0);
2667 bfin_write32(SIC_IWR2, 0);
2668
2669 bfin_write16(PLL_CTL, val);
2670 SSYNC();
2671 asm("IDLE;");
2672
2673 bfin_write32(SIC_IWR0, iwr0);
2674 bfin_write32(SIC_IWR1, iwr1);
2675 bfin_write32(SIC_IWR2, iwr2);
2676 local_irq_restore_hw(flags);
2677}
2678
2679/* Writing to VR_CTL initiates a PLL relock sequence. */
2680static __inline__ void bfin_write_VR_CTL(unsigned int val)
2681{
2682 unsigned long flags, iwr0, iwr1, iwr2;
2683
2684 if (val == bfin_read_VR_CTL())
2685 return;
2686
2687 local_irq_save_hw(flags);
2688 /* Enable the PLL Wakeup bit in SIC IWR */
2689 iwr0 = bfin_read32(SIC_IWR0);
2690 iwr1 = bfin_read32(SIC_IWR1);
2691 iwr2 = bfin_read32(SIC_IWR2);
2692 /* Only allow PPL Wakeup) */
2693 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2694 bfin_write32(SIC_IWR1, 0);
2695 bfin_write32(SIC_IWR2, 0);
2696
2697 bfin_write16(VR_CTL, val);
2698 SSYNC();
2699 asm("IDLE;");
2700
2701 bfin_write32(SIC_IWR0, iwr0);
2702 bfin_write32(SIC_IWR1, iwr1);
2703 bfin_write32(SIC_IWR2, iwr2);
2704 local_irq_restore_hw(flags);
2705}
2706
2707#endif /* _CDEF_BF54X_H */ 2651#endif /* _CDEF_BF54X_H */
2708 2652
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
new file mode 100644
index 000000000000..777fee61fab8
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 local_irq_restore_hw(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 local_irq_save_hw(flags);
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 local_irq_restore_hw(flags);
67}
68
69#endif /* _MACH_PLL_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 81ecdb71c6af..cc0416a5fa02 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1534,54 +1534,4 @@
1534/* These need to be last due to the cdef/linux inter-dependencies */ 1534/* These need to be last due to the cdef/linux inter-dependencies */
1535#include <asm/irq.h> 1535#include <asm/irq.h>
1536 1536
1537/* Writing to PLL_CTL initiates a PLL relock sequence. */
1538static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1539{
1540 unsigned long flags, iwr0, iwr1;
1541
1542 if (val == bfin_read_PLL_CTL())
1543 return;
1544
1545 local_irq_save_hw(flags);
1546 /* Enable the PLL Wakeup bit in SIC IWR */
1547 iwr0 = bfin_read32(SICA_IWR0);
1548 iwr1 = bfin_read32(SICA_IWR1);
1549 /* Only allow PPL Wakeup) */
1550 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1551 bfin_write32(SICA_IWR1, 0);
1552
1553 bfin_write16(PLL_CTL, val);
1554 SSYNC();
1555 asm("IDLE;");
1556
1557 bfin_write32(SICA_IWR0, iwr0);
1558 bfin_write32(SICA_IWR1, iwr1);
1559 local_irq_restore_hw(flags);
1560}
1561
1562/* Writing to VR_CTL initiates a PLL relock sequence. */
1563static __inline__ void bfin_write_VR_CTL(unsigned int val)
1564{
1565 unsigned long flags, iwr0, iwr1;
1566
1567 if (val == bfin_read_VR_CTL())
1568 return;
1569
1570 local_irq_save_hw(flags);
1571 /* Enable the PLL Wakeup bit in SIC IWR */
1572 iwr0 = bfin_read32(SICA_IWR0);
1573 iwr1 = bfin_read32(SICA_IWR1);
1574 /* Only allow PPL Wakeup) */
1575 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1576 bfin_write32(SICA_IWR1, 0);
1577
1578 bfin_write16(VR_CTL, val);
1579 SSYNC();
1580 asm("IDLE;");
1581
1582 bfin_write32(SICA_IWR0, iwr0);
1583 bfin_write32(SICA_IWR1, iwr1);
1584 local_irq_restore_hw(flags);
1585}
1586
1587#endif /* _CDEF_BF561_H */ 1537#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
new file mode 100644
index 000000000000..4baa44fccebd
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2005-2009 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 local_irq_save_hw(flags);
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SICA_IWR0);
24 iwr1 = bfin_read32(SICA_IWR1);
25 /* Only allow PPL Wakeup) */
26 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
27 bfin_write32(SICA_IWR1, 0);
28
29 bfin_write16(PLL_CTL, val);
30 SSYNC();
31 asm("IDLE;");
32
33 bfin_write32(SICA_IWR0, iwr0);
34 bfin_write32(SICA_IWR1, iwr1);
35 local_irq_restore_hw(flags);
36}
37
38/* Writing to VR_CTL initiates a PLL relock sequence. */
39static __inline__ void bfin_write_VR_CTL(unsigned int val)
40{
41 unsigned long flags, iwr0, iwr1;
42
43 if (val == bfin_read_VR_CTL())
44 return;
45
46 local_irq_save_hw(flags);
47 /* Enable the PLL Wakeup bit in SIC IWR */
48 iwr0 = bfin_read32(SICA_IWR0);
49 iwr1 = bfin_read32(SICA_IWR1);
50 /* Only allow PPL Wakeup) */
51 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
52 bfin_write32(SICA_IWR1, 0);
53
54 bfin_write16(VR_CTL, val);
55 SSYNC();
56 asm("IDLE;");
57
58 bfin_write32(SICA_IWR0, iwr0);
59 bfin_write32(SICA_IWR1, iwr1);
60 local_irq_restore_hw(flags);
61}
62
63#endif /* _MACH_PLL_H */
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 012613fde3f4..03d063554b7f 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -38,6 +38,7 @@
38#include <asm/blackfin.h> 38#include <asm/blackfin.h>
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40#include <asm/portmux.h> 40#include <asm/portmux.h>
41#include <mach/pll.h>
41 42
42#include "bfin_mac.h" 43#include "bfin_mac.h"
43 44
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 03:13:20 -0500