diff options
-rw-r--r-- | arch/arm/mach-omap1/fpga.c (renamed from arch/arm/mach-omap/fpga.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-omap1/irq.c (renamed from arch/arm/mach-omap/irq.c) | 17 | ||||
-rw-r--r-- | arch/arm/mach-omap1/time.c (renamed from arch/arm/mach-omap/time.c) | 32 |
3 files changed, 38 insertions, 11 deletions
diff --git a/arch/arm/mach-omap/fpga.c b/arch/arm/mach-omap1/fpga.c index 7c08f6c2e1d0..7c08f6c2e1d0 100644 --- a/arch/arm/mach-omap/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
diff --git a/arch/arm/mach-omap/irq.c b/arch/arm/mach-omap1/irq.c index f01c99266a86..a11b6d807352 100644 --- a/arch/arm/mach-omap/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
@@ -56,6 +56,7 @@ | |||
56 | struct omap_irq_bank { | 56 | struct omap_irq_bank { |
57 | unsigned long base_reg; | 57 | unsigned long base_reg; |
58 | unsigned long trigger_map; | 58 | unsigned long trigger_map; |
59 | unsigned long wake_enable; | ||
59 | }; | 60 | }; |
60 | 61 | ||
61 | static unsigned int irq_bank_count = 0; | 62 | static unsigned int irq_bank_count = 0; |
@@ -105,6 +106,19 @@ static void omap_mask_ack_irq(unsigned int irq) | |||
105 | omap_ack_irq(irq); | 106 | omap_ack_irq(irq); |
106 | } | 107 | } |
107 | 108 | ||
109 | static int omap_wake_irq(unsigned int irq, unsigned int enable) | ||
110 | { | ||
111 | int bank = IRQ_BANK(irq); | ||
112 | |||
113 | if (enable) | ||
114 | irq_banks[bank].wake_enable |= IRQ_BIT(irq); | ||
115 | else | ||
116 | irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); | ||
117 | |||
118 | return 0; | ||
119 | } | ||
120 | |||
121 | |||
108 | /* | 122 | /* |
109 | * Allows tuning the IRQ type and priority | 123 | * Allows tuning the IRQ type and priority |
110 | * | 124 | * |
@@ -145,7 +159,7 @@ static struct omap_irq_bank omap1510_irq_banks[] = { | |||
145 | static struct omap_irq_bank omap1610_irq_banks[] = { | 159 | static struct omap_irq_bank omap1610_irq_banks[] = { |
146 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, | 160 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, |
147 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, | 161 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, |
148 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xfffff7ff }, | 162 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, |
149 | { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, | 163 | { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, |
150 | }; | 164 | }; |
151 | #endif | 165 | #endif |
@@ -154,6 +168,7 @@ static struct irqchip omap_irq_chip = { | |||
154 | .ack = omap_mask_ack_irq, | 168 | .ack = omap_mask_ack_irq, |
155 | .mask = omap_mask_irq, | 169 | .mask = omap_mask_irq, |
156 | .unmask = omap_unmask_irq, | 170 | .unmask = omap_unmask_irq, |
171 | .wake = omap_wake_irq, | ||
157 | }; | 172 | }; |
158 | 173 | ||
159 | void __init omap_init_irq(void) | 174 | void __init omap_init_irq(void) |
diff --git a/arch/arm/mach-omap/time.c b/arch/arm/mach-omap1/time.c index dd34e9f4c413..d540539c9bbb 100644 --- a/arch/arm/mach-omap/time.c +++ b/arch/arm/mach-omap1/time.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap/time.c | 2 | * linux/arch/arm/mach-omap1/time.c |
3 | * | 3 | * |
4 | * OMAP Timers | 4 | * OMAP Timers |
5 | * | 5 | * |
@@ -58,17 +58,9 @@ struct sys_timer omap_timer; | |||
58 | * MPU timer | 58 | * MPU timer |
59 | * --------------------------------------------------------------------------- | 59 | * --------------------------------------------------------------------------- |
60 | */ | 60 | */ |
61 | #define OMAP_MPU_TIMER1_BASE (0xfffec500) | ||
62 | #define OMAP_MPU_TIMER2_BASE (0xfffec600) | ||
63 | #define OMAP_MPU_TIMER3_BASE (0xfffec700) | ||
64 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE | 61 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
65 | #define OMAP_MPU_TIMER_OFFSET 0x100 | 62 | #define OMAP_MPU_TIMER_OFFSET 0x100 |
66 | 63 | ||
67 | #define MPU_TIMER_FREE (1 << 6) | ||
68 | #define MPU_TIMER_CLOCK_ENABLE (1 << 5) | ||
69 | #define MPU_TIMER_AR (1 << 1) | ||
70 | #define MPU_TIMER_ST (1 << 0) | ||
71 | |||
72 | /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c, | 64 | /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c, |
73 | * converted to use kHz by Kevin Hilman */ | 65 | * converted to use kHz by Kevin Hilman */ |
74 | /* convert from cycles(64bits) => nanoseconds (64bits) | 66 | /* convert from cycles(64bits) => nanoseconds (64bits) |
@@ -255,6 +247,13 @@ unsigned long long sched_clock(void) | |||
255 | #define OMAP_32K_TIMER_TCR 0x04 | 247 | #define OMAP_32K_TIMER_TCR 0x04 |
256 | 248 | ||
257 | #define OMAP_32K_TICKS_PER_HZ (32768 / HZ) | 249 | #define OMAP_32K_TICKS_PER_HZ (32768 / HZ) |
250 | #if (32768 % HZ) != 0 | ||
251 | /* We cannot ignore modulo. | ||
252 | * Potential error can be as high as several percent. | ||
253 | */ | ||
254 | #define OMAP_32K_TICK_MODULO (32768 % HZ) | ||
255 | static unsigned modulo_count = 0; /* Counts 1/HZ units */ | ||
256 | #endif | ||
258 | 257 | ||
259 | /* | 258 | /* |
260 | * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 | 259 | * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 |
@@ -331,6 +330,19 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id, | |||
331 | now = omap_32k_sync_timer_read(); | 330 | now = omap_32k_sync_timer_read(); |
332 | 331 | ||
333 | while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) { | 332 | while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) { |
333 | #ifdef OMAP_32K_TICK_MODULO | ||
334 | /* Modulo addition may put omap_32k_last_tick ahead of now | ||
335 | * and cause unwanted repetition of the while loop. | ||
336 | */ | ||
337 | if (unlikely(now - omap_32k_last_tick == ~0)) | ||
338 | break; | ||
339 | |||
340 | modulo_count += OMAP_32K_TICK_MODULO; | ||
341 | if (modulo_count > HZ) { | ||
342 | ++omap_32k_last_tick; | ||
343 | modulo_count -= HZ; | ||
344 | } | ||
345 | #endif | ||
334 | omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ; | 346 | omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ; |
335 | timer_tick(regs); | 347 | timer_tick(regs); |
336 | } | 348 | } |
@@ -407,7 +419,7 @@ static __init void omap_init_32k_timer(void) | |||
407 | * Timer initialization | 419 | * Timer initialization |
408 | * --------------------------------------------------------------------------- | 420 | * --------------------------------------------------------------------------- |
409 | */ | 421 | */ |
410 | void __init omap_timer_init(void) | 422 | static void __init omap_timer_init(void) |
411 | { | 423 | { |
412 | #if defined(CONFIG_OMAP_MPU_TIMER) | 424 | #if defined(CONFIG_OMAP_MPU_TIMER) |
413 | omap_init_mpu_timer(); | 425 | omap_init_mpu_timer(); |