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-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/generic/mem_tx4927.c94
-rw-r--r--arch/mips/txx9/generic/mem_tx4938.c124
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c11
-rw-r--r--include/asm-mips/txx9/tx4927.h48
-rw-r--r--include/asm-mips/txx9/tx4938.h237
8 files changed, 86 insertions, 442 deletions
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 668fdaad6448..ab274ede9a70 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -5,7 +5,7 @@
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 12dfc377bf2f..ef6ea6e97873 100644
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/mips/tx4927/common/tx4927_prom.c 2 * linux/arch/mips/txx9/generic/mem_tx4927.c
3 * 3 *
4 * common tx4927 memory interface 4 * common tx4927 memory interface
5 * 5 *
@@ -32,8 +32,9 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/types.h> 33#include <linux/types.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <asm/txx9/tx4927.h>
35 36
36static unsigned int __init tx4927_process_sdccr(unsigned long addr) 37static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
37{ 38{
38 u64 val; 39 u64 val;
39 unsigned int sdccr_ce; 40 unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
45 unsigned int rs = 0; 46 unsigned int rs = 0;
46 unsigned int cs = 0; 47 unsigned int cs = 0;
47 unsigned int mw = 0; 48 unsigned int mw = 0;
48 unsigned int msize = 0;
49 49
50 val = __raw_readq((void __iomem *)addr); 50 val = __raw_readq(addr);
51 51
52 /* MVMCP -- need #defs for these bits masks */ 52 /* MVMCP -- need #defs for these bits masks */
53 sdccr_ce = ((val & (1 << 10)) >> 10); 53 sdccr_ce = ((val & (1 << 10)) >> 10);
54 sdccr_bs = ((val & (1 << 8)) >> 8); 54 sdccr_bs = ((val & (1 << 8)) >> 8);
55 sdccr_rs = ((val & (3 << 5)) >> 5); 55 sdccr_rs = ((val & (3 << 5)) >> 5);
56 sdccr_cs = ((val & (3 << 2)) >> 2); 56 sdccr_cs = ((val & (7 << 2)) >> 2);
57 sdccr_mw = ((val & (1 << 0)) >> 0); 57 sdccr_mw = ((val & (1 << 0)) >> 0);
58 58
59 if (sdccr_ce) { 59 if (sdccr_ce) {
60 switch (sdccr_bs) { 60 bs = 2 << sdccr_bs;
61 case 0:{ 61 rs = 2048 << sdccr_rs;
62 bs = 2; 62 cs = 256 << sdccr_cs;
63 break; 63 mw = 8 >> sdccr_mw;
64 }
65 case 1:{
66 bs = 4;
67 break;
68 }
69 }
70 switch (sdccr_rs) {
71 case 0:{
72 rs = 2048;
73 break;
74 }
75 case 1:{
76 rs = 4096;
77 break;
78 }
79 case 2:{
80 rs = 8192;
81 break;
82 }
83 case 3:{
84 rs = 0;
85 break;
86 }
87 }
88 switch (sdccr_cs) {
89 case 0:{
90 cs = 256;
91 break;
92 }
93 case 1:{
94 cs = 512;
95 break;
96 }
97 case 2:{
98 cs = 1024;
99 break;
100 }
101 case 3:{
102 cs = 2048;
103 break;
104 }
105 }
106 switch (sdccr_mw) {
107 case 0:{
108 mw = 8;
109 break;
110 } /* 8 bytes = 64 bits */
111 case 1:{
112 mw = 4;
113 break;
114 } /* 4 bytes = 32 bits */
115 }
116 } 64 }
117 65
118 /* bytes per chip MB per chip num chips */ 66 return rs * cs * mw * bs;
119 msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
120
121 return (msize);
122} 67}
123 68
124
125unsigned int __init tx4927_get_mem_size(void) 69unsigned int __init tx4927_get_mem_size(void)
126{ 70{
127 unsigned int c0; 71 unsigned int total = 0;
128 unsigned int c1; 72 int i;
129 unsigned int c2;
130 unsigned int c3;
131 unsigned int total;
132
133 /* MVMCP -- need #defs for these registers */
134 c0 = tx4927_process_sdccr(0xff1f8000);
135 c1 = tx4927_process_sdccr(0xff1f8008);
136 c2 = tx4927_process_sdccr(0xff1f8010);
137 c3 = tx4927_process_sdccr(0xff1f8018);
138 total = c0 + c1 + c2 + c3;
139 73
140 return (total); 74 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
75 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
76 return total;
141} 77}
diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c
deleted file mode 100644
index 20baeaeba4cd..000000000000
--- a/arch/mips/txx9/generic/mem_tx4938.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19static unsigned int __init
20tx4938_process_sdccr(u64 * addr)
21{
22 u64 val;
23 unsigned int sdccr_ce;
24 unsigned int sdccr_rs;
25 unsigned int sdccr_cs;
26 unsigned int sdccr_mw;
27 unsigned int rs = 0;
28 unsigned int cs = 0;
29 unsigned int mw = 0;
30 unsigned int bc = 4;
31 unsigned int msize = 0;
32
33 val = ____raw_readq((void __iomem *)addr);
34
35 /* MVMCP -- need #defs for these bits masks */
36 sdccr_ce = ((val & (1 << 10)) >> 10);
37 sdccr_rs = ((val & (3 << 5)) >> 5);
38 sdccr_cs = ((val & (7 << 2)) >> 2);
39 sdccr_mw = ((val & (1 << 0)) >> 0);
40
41 if (sdccr_ce) {
42 switch (sdccr_rs) {
43 case 0:{
44 rs = 2048;
45 break;
46 }
47 case 1:{
48 rs = 4096;
49 break;
50 }
51 case 2:{
52 rs = 8192;
53 break;
54 }
55 default:{
56 rs = 0;
57 break;
58 }
59 }
60 switch (sdccr_cs) {
61 case 0:{
62 cs = 256;
63 break;
64 }
65 case 1:{
66 cs = 512;
67 break;
68 }
69 case 2:{
70 cs = 1024;
71 break;
72 }
73 case 3:{
74 cs = 2048;
75 break;
76 }
77 case 4:{
78 cs = 4096;
79 break;
80 }
81 default:{
82 cs = 0;
83 break;
84 }
85 }
86 switch (sdccr_mw) {
87 case 0:{
88 mw = 8;
89 break;
90 } /* 8 bytes = 64 bits */
91 case 1:{
92 mw = 4;
93 break;
94 } /* 4 bytes = 32 bits */
95 }
96 }
97
98 /* bytes per chip MB per chip bank count */
99 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
100
101 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
102 /* boad supports bc=2 but no way to detect */
103
104 return (msize);
105}
106
107unsigned int __init
108tx4938_get_mem_size(void)
109{
110 unsigned int c0;
111 unsigned int c1;
112 unsigned int c2;
113 unsigned int c3;
114 unsigned int total;
115
116 /* MVMCP -- need #defs for these registers */
117 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
118 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
119 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
120 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
121 total = c0 + c1 + c2 + c3;
122
123 return (total);
124}
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 942e627d2dc1..5c0de54ebdd2 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,10 +36,6 @@
36 36
37void __init rbtx4927_prom_init(void) 37void __init rbtx4927_prom_init(void)
38{ 38{
39 extern int tx4927_get_mem_size(void);
40 int msize;
41
42 prom_init_cmdline(); 39 prom_init_cmdline();
43 msize = tx4927_get_mem_size(); 40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
44 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
45} 41}
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index fbb37458ddb2..ee189519ce5a 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,12 +18,8 @@
18 18
19void __init rbtx4938_prom_init(void) 19void __init rbtx4938_prom_init(void)
20{ 20{
21 extern int tx4938_get_mem_size(void);
22 int msize;
23#ifndef CONFIG_TX4938_NAND_BOOT 21#ifndef CONFIG_TX4938_NAND_BOOT
24 prom_init_cmdline(); 22 prom_init_cmdline();
25#endif 23#endif
26 24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
27 msize = tx4938_get_mem_size();
28 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
29} 25}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index c2da92396b7a..c1e076c7b2d2 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -310,7 +310,7 @@ void __init tx4938_board_setup(void)
310 310
311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
312 for (i = 0; i < 4; i++) { 312 for (i = 0; i < 4; i++) {
313 unsigned long long cr = tx4938_sdramcptr->cr[i]; 313 u64 cr = TX4938_SDRAMC_CR(i);
314 unsigned long ram_base, ram_size; 314 unsigned long ram_base, ram_size;
315 if (!((unsigned long)cr & 0x00000400)) 315 if (!((unsigned long)cr & 0x00000400))
316 continue; /* disabled */ 316 continue; /* disabled */
@@ -318,20 +318,21 @@ void __init tx4938_board_setup(void)
318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21; 318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
319 if (ram_base >= 0x20000000) 319 if (ram_base >= 0x20000000)
320 continue; /* high memory (ignore) */ 320 continue; /* high memory (ignore) */
321 printk(" CR%d:%016Lx", i, cr); 321 printk(KERN_CONT " CR%d:%016llx", i, cr);
322 tx4938_sdram_resource[i].name = "SDRAM"; 322 tx4938_sdram_resource[i].name = "SDRAM";
323 tx4938_sdram_resource[i].start = ram_base; 323 tx4938_sdram_resource[i].start = ram_base;
324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1; 324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
327 } 327 }
328 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); 328 printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
329 329
330 /* SRAM */ 330 /* SRAM */
331 if (tx4938_sramcptr->cr & 1) { 331 if (____raw_readq(&tx4938_sramcptr->cr) & 1) {
332 unsigned int size = 0x800; 332 unsigned int size = 0x800;
333 unsigned long base = 333 unsigned long base =
334 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); 334 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
335 & ~(size - 1);
335 tx4938_sram_resource.name = "SRAM"; 336 tx4938_sram_resource.name = "SRAM";
336 tx4938_sram_resource.start = base; 337 tx4938_sram_resource.start = base;
337 tx4938_sram_resource.end = base + size - 1; 338 tx4938_sram_resource.end = base + size - 1;
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index 46d60afc038b..c9212155f686 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -32,13 +32,20 @@
32#include <asm/txx9irq.h> 32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h> 33#include <asm/txx9/tx4927pcic.h>
34 34
35#define TX4927_SDRAMC_REG 0xff1f8000 35#ifdef CONFIG_64BIT
36#define TX4927_EBUSC_REG 0xff1f9000 36#define TX4927_REG_BASE 0xffffffffff1f0000UL
37#define TX4927_PCIC_REG 0xff1fd000 37#else
38#define TX4927_CCFG_REG 0xff1fe000 38#define TX4927_REG_BASE 0xff1f0000UL
39#define TX4927_IRC_REG 0xff1ff600 39#endif
40#define TX4927_REG_SIZE 0x00010000
41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
40#define TX4927_NR_TMR 3 47#define TX4927_NR_TMR 3
41#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) 48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
42 49
43#define TX4927_IR_INT(n) (2 + (n)) 50#define TX4927_IR_INT(n) (2 + (n))
44#define TX4927_IR_SIO(n) (8 + (n)) 51#define TX4927_IR_SIO(n) (8 + (n))
@@ -49,15 +56,15 @@
49#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 56#define TX4927_IRC_INT 2 /* IP[2] in Status register */
50 57
51struct tx4927_sdramc_reg { 58struct tx4927_sdramc_reg {
52 volatile unsigned long long cr[4]; 59 u64 cr[4];
53 volatile unsigned long long unused0[4]; 60 u64 unused0[4];
54 volatile unsigned long long tr; 61 u64 tr;
55 volatile unsigned long long unused1[2]; 62 u64 unused1[2];
56 volatile unsigned long long cmd; 63 u64 cmd;
57}; 64};
58 65
59struct tx4927_ebusc_reg { 66struct tx4927_ebusc_reg {
60 volatile unsigned long long cr[8]; 67 u64 cr[8];
61}; 68};
62 69
63struct tx4927_ccfg_reg { 70struct tx4927_ccfg_reg {
@@ -160,12 +167,24 @@ struct tx4927_ccfg_reg {
160#define TX4927_CLKCTR_SIO0RST 0x00000002 167#define TX4927_CLKCTR_SIO0RST 0x00000002
161#define TX4927_CLKCTR_SIO1RST 0x00000001 168#define TX4927_CLKCTR_SIO1RST 0x00000001
162 169
163#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) 170#define tx4927_sdramcptr \
171 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
164#define tx4927_pcicptr \ 172#define tx4927_pcicptr \
165 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) 173 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
166#define tx4927_ccfgptr \ 174#define tx4927_ccfgptr \
167 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 175 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
168#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 176#define tx4927_ebuscptr \
177 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
178
179#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
180#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
181#define TX4927_SDRAMC_SIZE(ch) \
182 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
183
184#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
185#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
186#define TX4927_EBUSC_SIZE(ch) \
187 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
169 188
170/* utilities */ 189/* utilities */
171static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 190static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
@@ -212,6 +231,7 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
212 &tx4927_ccfgptr->ccfg); 231 &tx4927_ccfgptr->ccfg);
213} 232}
214 233
234unsigned int tx4927_get_mem_size(void);
215int tx4927_report_pciclk(void); 235int tx4927_report_pciclk(void);
216int tx4927_pciclk66_setup(void); 236int tx4927_pciclk66_setup(void);
217void tx4927_irq_init(void); 237void tx4927_irq_init(void);
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 12de68a4c10a..6690246a1149 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -15,20 +15,11 @@
15/* some controllers are compatible with 4927 */ 15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h> 16#include <asm/txx9/tx4927.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#ifdef CONFIG_64BIT
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
20 20#else
21#define TX4938_PCIIO_0 0x10000000 21#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
22#define TX4938_PCIIO_1 0x01010000 22#endif
23#define TX4938_PCIMEM_0 0x08000000
24#define TX4938_PCIMEM_1 0x11000000
25
26#define TX4938_PCIIO_SIZE_0 0x01000000
27#define TX4938_PCIIO_SIZE_1 0x00010000
28#define TX4938_PCIMEM_SIZE_0 0x08000000
29#define TX4938_PCIMEM_SIZE_1 0x00010000
30
31#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
32#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ 23#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
33 24
34/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ 25/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
@@ -49,149 +40,8 @@
49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 40#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 41#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
51 42
52#define _CONST64(c) c##ull
53
54#include <asm/byteorder.h>
55
56#ifdef __BIG_ENDIAN
57#define endian_def_l2(e1, e2) \
58 volatile unsigned long e1, e2
59#define endian_def_s2(e1, e2) \
60 volatile unsigned short e1, e2
61#define endian_def_sb2(e1, e2, e3) \
62 volatile unsigned short e1;volatile unsigned char e2, e3
63#define endian_def_b2s(e1, e2, e3) \
64 volatile unsigned char e1, e2;volatile unsigned short e3
65#define endian_def_b4(e1, e2, e3, e4) \
66 volatile unsigned char e1, e2, e3, e4
67#else
68#define endian_def_l2(e1, e2) \
69 volatile unsigned long e2, e1
70#define endian_def_s2(e1, e2) \
71 volatile unsigned short e2, e1
72#define endian_def_sb2(e1, e2, e3) \
73 volatile unsigned char e3, e2;volatile unsigned short e1
74#define endian_def_b2s(e1, e2, e3) \
75 volatile unsigned short e3;volatile unsigned char e2, e1
76#define endian_def_b4(e1, e2, e3, e4) \
77 volatile unsigned char e4, e3, e2, e1
78#endif
79
80
81struct tx4938_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87 volatile unsigned long long sfcmd;
88};
89
90struct tx4938_ebusc_reg {
91 volatile unsigned long long cr[8];
92};
93
94struct tx4938_dma_reg {
95 struct tx4938_dma_ch_reg {
96 volatile unsigned long long cha;
97 volatile unsigned long long sar;
98 volatile unsigned long long dar;
99 endian_def_l2(unused0, cntr);
100 endian_def_l2(unused1, sair);
101 endian_def_l2(unused2, dair);
102 endian_def_l2(unused3, ccr);
103 endian_def_l2(unused4, csr);
104 } ch[4];
105 volatile unsigned long long dbr[8];
106 volatile unsigned long long tdhr;
107 volatile unsigned long long midr;
108 endian_def_l2(unused0, mcr);
109};
110
111struct tx4938_aclc_reg {
112 volatile unsigned long acctlen;
113 volatile unsigned long acctldis;
114 volatile unsigned long acregacc;
115 volatile unsigned long unused0;
116 volatile unsigned long acintsts;
117 volatile unsigned long acintmsts;
118 volatile unsigned long acinten;
119 volatile unsigned long acintdis;
120 volatile unsigned long acsemaph;
121 volatile unsigned long unused1[7];
122 volatile unsigned long acgpidat;
123 volatile unsigned long acgpodat;
124 volatile unsigned long acslten;
125 volatile unsigned long acsltdis;
126 volatile unsigned long acfifosts;
127 volatile unsigned long unused2[11];
128 volatile unsigned long acdmasts;
129 volatile unsigned long acdmasel;
130 volatile unsigned long unused3[6];
131 volatile unsigned long acaudodat;
132 volatile unsigned long acsurrdat;
133 volatile unsigned long accentdat;
134 volatile unsigned long aclfedat;
135 volatile unsigned long acaudiat;
136 volatile unsigned long unused4;
137 volatile unsigned long acmodoat;
138 volatile unsigned long acmodidat;
139 volatile unsigned long unused5[15];
140 volatile unsigned long acrevid;
141};
142
143
144struct tx4938_tmr_reg {
145 volatile unsigned long tcr;
146 volatile unsigned long tisr;
147 volatile unsigned long cpra;
148 volatile unsigned long cprb;
149 volatile unsigned long itmr;
150 volatile unsigned long unused0[3];
151 volatile unsigned long ccdr;
152 volatile unsigned long unused1[3];
153 volatile unsigned long pgmr;
154 volatile unsigned long unused2[3];
155 volatile unsigned long wtmr;
156 volatile unsigned long unused3[43];
157 volatile unsigned long trr;
158};
159
160struct tx4938_sio_reg {
161 volatile unsigned long lcr;
162 volatile unsigned long dicr;
163 volatile unsigned long disr;
164 volatile unsigned long cisr;
165 volatile unsigned long fcr;
166 volatile unsigned long flcr;
167 volatile unsigned long bgr;
168 volatile unsigned long tfifo;
169 volatile unsigned long rfifo;
170};
171
172struct tx4938_ndfmc_reg {
173 endian_def_l2(unused0, dtr);
174 endian_def_l2(unused1, mcr);
175 endian_def_l2(unused2, sr);
176 endian_def_l2(unused3, isr);
177 endian_def_l2(unused4, imr);
178 endian_def_l2(unused5, spr);
179 endian_def_l2(unused6, rstr);
180};
181
182struct tx4938_spi_reg {
183 volatile unsigned long mcr;
184 volatile unsigned long cr0;
185 volatile unsigned long cr1;
186 volatile unsigned long fs;
187 volatile unsigned long unused1;
188 volatile unsigned long sr;
189 volatile unsigned long dr;
190 volatile unsigned long unused2;
191};
192
193struct tx4938_sramc_reg { 43struct tx4938_sramc_reg {
194 volatile unsigned long long cr; 44 u64 cr;
195}; 45};
196 46
197struct tx4938_ccfg_reg { 47struct tx4938_ccfg_reg {
@@ -209,34 +59,6 @@ struct tx4938_ccfg_reg {
209 u64 jmpadr; 59 u64 jmpadr;
210}; 60};
211 61
212#undef endian_def_l2
213#undef endian_def_s2
214#undef endian_def_sb2
215#undef endian_def_b2s
216#undef endian_def_b4
217
218/*
219 * NDFMC
220 */
221
222/* NDFMCR : NDFMC Mode Control */
223#define TX4938_NDFMCR_WE 0x80
224#define TX4938_NDFMCR_ECC_ALL 0x60
225#define TX4938_NDFMCR_ECC_RESET 0x60
226#define TX4938_NDFMCR_ECC_READ 0x40
227#define TX4938_NDFMCR_ECC_ON 0x20
228#define TX4938_NDFMCR_ECC_OFF 0x00
229#define TX4938_NDFMCR_CE 0x10
230#define TX4938_NDFMCR_BSPRT 0x04
231#define TX4938_NDFMCR_ALE 0x02
232#define TX4938_NDFMCR_CLE 0x01
233
234/* NDFMCR : NDFMC Status */
235#define TX4938_NDFSR_BUSY 0x80
236
237/* NDFMCR : NDFMC Reset */
238#define TX4938_NDFRSTR_RST 0x01
239
240/* 62/*
241 * IRC 63 * IRC
242 */ 64 */
@@ -272,9 +94,9 @@ struct tx4938_ccfg_reg {
272 * CCFG 94 * CCFG
273 */ 95 */
274/* CCFG : Chip Configuration */ 96/* CCFG : Chip Configuration */
275#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) 97#define TX4938_CCFG_WDRST 0x0000020000000000ULL
276#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) 98#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
277#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) 99#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
278#define TX4938_CCFG_TINTDIS 0x01000000 100#define TX4938_CCFG_TINTDIS 0x01000000
279#define TX4938_CCFG_PCI66 0x00800000 101#define TX4938_CCFG_PCI66 0x00800000
280#define TX4938_CCFG_PCIMODE 0x00400000 102#define TX4938_CCFG_PCIMODE 0x00400000
@@ -310,12 +132,12 @@ struct tx4938_ccfg_reg {
310#define TX4938_CCFG_ACEHOLD 0x00000001 132#define TX4938_CCFG_ACEHOLD 0x00000001
311 133
312/* PCFG : Pin Configuration */ 134/* PCFG : Pin Configuration */
313#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) 135#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
314#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) 136#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
315#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) 137#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
316#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) 138#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
317#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) 139#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
318#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) 140#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
319#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 141#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
320#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) 142#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
321#define TX4938_PCFG_SYSCLKEN 0x08000000 143#define TX4938_PCFG_SYSCLKEN 0x08000000
@@ -336,8 +158,8 @@ struct tx4938_ccfg_reg {
336#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 158#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
337 159
338/* CLKCTR : Clock Control */ 160/* CLKCTR : Clock Control */
339#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) 161#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
340#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) 162#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
341#define TX4938_CLKCTR_ETH1CKD 0x80000000 163#define TX4938_CLKCTR_ETH1CKD 0x80000000
342#define TX4938_CLKCTR_ETH0CKD 0x40000000 164#define TX4938_CLKCTR_ETH0CKD 0x40000000
343#define TX4938_CLKCTR_SPICKD 0x20000000 165#define TX4938_CLKCTR_SPICKD 0x20000000
@@ -424,20 +246,16 @@ struct tx4938_ccfg_reg {
424#define TX4938_DMA_CSR_DESERR 0x00000002 246#define TX4938_DMA_CSR_DESERR 0x00000002
425#define TX4938_DMA_CSR_SORERR 0x00000001 247#define TX4938_DMA_CSR_SORERR 0x00000001
426 248
427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 249#define tx4938_sdramcptr tx4927_sdramcptr
428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 250#define tx4938_ebuscptr tx4927_ebuscptr
429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
431#define tx4938_pcicptr tx4927_pcicptr 251#define tx4938_pcicptr tx4927_pcicptr
432#define tx4938_pcic1ptr \ 252#define tx4938_pcic1ptr \
433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) 253 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \ 254#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) 255 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 256#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 257#define tx4938_sramcptr \
439#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) 258 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
441 259
442 260
443#define TX4938_REV_PCODE() \ 261#define TX4938_REV_PCODE() \
@@ -447,14 +265,15 @@ struct tx4938_ccfg_reg {
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) 265#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) 266#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
449 267
450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 268#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 269#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
270#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
452 271
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) 272#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 273#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
455#define TX4938_EBUSC_SIZE(ch) \ 274#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
457 275
276#define tx4938_get_mem_size() tx4927_get_mem_size()
458int tx4938_report_pciclk(void); 277int tx4938_report_pciclk(void);
459void tx4938_report_pci1clk(void); 278void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void); 279int tx4938_pciclk66_setup(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 08:10:34 -0500