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-rw-r--r--arch/x86/kernel/cpu/amd.c5
-rw-r--r--arch/x86/kernel/cpu/amd_64.c5
-rw-r--r--include/asm-x86/msr-index.h4
3 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index a38d54f4ff25..30b5055be355 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -25,7 +25,6 @@ extern void vide(void);
25__asm__(".align 4\nvide: ret"); 25__asm__(".align 4\nvide: ret");
26 26
27#ifdef CONFIG_X86_LOCAL_APIC 27#ifdef CONFIG_X86_LOCAL_APIC
28#define ENABLE_C1E_MASK 0x18000000
29#define CPUID_PROCESSOR_SIGNATURE 1 28#define CPUID_PROCESSOR_SIGNATURE 1
30#define CPUID_XFAM 0x0ff00000 29#define CPUID_XFAM 0x0ff00000
31#define CPUID_XFAM_K8 0x00000000 30#define CPUID_XFAM_K8 0x00000000
@@ -45,8 +44,8 @@ static __cpuinit int amd_apic_timer_broken(void)
45 break; 44 break;
46 case CPUID_XFAM_10H: 45 case CPUID_XFAM_10H:
47 case CPUID_XFAM_11H: 46 case CPUID_XFAM_11H:
48 rdmsr(MSR_K8_ENABLE_C1E, lo, hi); 47 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
49 if (lo & ENABLE_C1E_MASK) { 48 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
50 if (smp_processor_id() != boot_cpu_physical_apicid) 49 if (smp_processor_id() != boot_cpu_physical_apicid)
51 printk(KERN_INFO "AMD C1E detected late. " 50 printk(KERN_INFO "AMD C1E detected late. "
52 " Force timer broadcast.\n"); 51 " Force timer broadcast.\n");
diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
index 626fc21f027d..6eef3c79d151 100644
--- a/arch/x86/kernel/cpu/amd_64.c
+++ b/arch/x86/kernel/cpu/amd_64.c
@@ -110,7 +110,6 @@ static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
110#endif 110#endif
111} 111}
112 112
113#define ENABLE_C1E_MASK 0x18000000
114#define CPUID_PROCESSOR_SIGNATURE 1 113#define CPUID_PROCESSOR_SIGNATURE 1
115#define CPUID_XFAM 0x0ff00000 114#define CPUID_XFAM 0x0ff00000
116#define CPUID_XFAM_K8 0x00000000 115#define CPUID_XFAM_K8 0x00000000
@@ -130,8 +129,8 @@ static __cpuinit int amd_apic_timer_broken(void)
130 break; 129 break;
131 case CPUID_XFAM_10H: 130 case CPUID_XFAM_10H:
132 case CPUID_XFAM_11H: 131 case CPUID_XFAM_11H:
133 rdmsr(MSR_K8_ENABLE_C1E, lo, hi); 132 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
134 if (lo & ENABLE_C1E_MASK) 133 if (lo & K8_INTP_C1E_ACTIVE_MASK)
135 return 1; 134 return 1;
136 break; 135 break;
137 default: 136 default:
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 09413ad39d3c..44bce773012e 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -111,7 +111,9 @@
111#define MSR_K8_TOP_MEM2 0xc001001d 111#define MSR_K8_TOP_MEM2 0xc001001d
112#define MSR_K8_SYSCFG 0xc0010010 112#define MSR_K8_SYSCFG 0xc0010010
113#define MSR_K8_HWCR 0xc0010015 113#define MSR_K8_HWCR 0xc0010015
114#define MSR_K8_ENABLE_C1E 0xc0010055 114#define MSR_K8_INT_PENDING_MSG 0xc0010055
115/* C1E active bits in int pending message */
116#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
115#define MSR_K8_TSEG_ADDR 0xc0010112 117#define MSR_K8_TSEG_ADDR 0xc0010112
116#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 118#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
117#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 119#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */