diff options
-rw-r--r-- | drivers/net/bnx2x_hsi.h | 1 | ||||
-rw-r--r-- | drivers/net/bnx2x_link.c | 44 |
2 files changed, 42 insertions, 3 deletions
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h index dc2f8ed5fd07..52585338ada8 100644 --- a/drivers/net/bnx2x_hsi.h +++ b/drivers/net/bnx2x_hsi.h | |||
@@ -264,6 +264,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ | |||
264 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 | 264 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 |
265 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 | 265 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 |
266 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | 266 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 |
267 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | ||
267 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | 268 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
268 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | 269 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
269 | 270 | ||
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index b08ff77f1f96..7897fe13e61a 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c | |||
@@ -2200,6 +2200,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params, | |||
2200 | MDIO_PMA_REG_CTRL, | 2200 | MDIO_PMA_REG_CTRL, |
2201 | 1<<15); | 2201 | 1<<15); |
2202 | break; | 2202 | break; |
2203 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
2204 | break; | ||
2203 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | 2205 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
2204 | DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); | 2206 | DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n"); |
2205 | break; | 2207 | break; |
@@ -4373,6 +4375,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) | |||
4373 | break; | 4375 | break; |
4374 | } | 4376 | } |
4375 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | 4377 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: |
4378 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
4376 | /* This phy uses the NIG latch mechanism since link | 4379 | /* This phy uses the NIG latch mechanism since link |
4377 | indication arrives through its LED4 and not via | 4380 | indication arrives through its LED4 and not via |
4378 | its LASI signal, so we get steady signal | 4381 | its LASI signal, so we get steady signal |
@@ -4380,6 +4383,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) | |||
4380 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, | 4383 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
4381 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | 4384 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); |
4382 | 4385 | ||
4386 | bnx2x_cl45_write(bp, params->port, | ||
4387 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | ||
4388 | ext_phy_addr, | ||
4389 | MDIO_PMA_DEVAD, | ||
4390 | MDIO_PMA_REG_CTRL, 0x0000); | ||
4391 | |||
4383 | bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); | 4392 | bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr); |
4384 | if (params->req_line_speed == SPEED_AUTO_NEG) { | 4393 | if (params->req_line_speed == SPEED_AUTO_NEG) { |
4385 | 4394 | ||
@@ -5230,6 +5239,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, | |||
5230 | } | 5239 | } |
5231 | break; | 5240 | break; |
5232 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | 5241 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: |
5242 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
5233 | /* Check 10G-BaseT link status */ | 5243 | /* Check 10G-BaseT link status */ |
5234 | /* Check PMD signal ok */ | 5244 | /* Check PMD signal ok */ |
5235 | bnx2x_cl45_read(bp, params->port, ext_phy_type, | 5245 | bnx2x_cl45_read(bp, params->port, ext_phy_type, |
@@ -5445,8 +5455,10 @@ static void bnx2x_link_int_ack(struct link_params *params, | |||
5445 | (NIG_STATUS_XGXS0_LINK10G | | 5455 | (NIG_STATUS_XGXS0_LINK10G | |
5446 | NIG_STATUS_XGXS0_LINK_STATUS | | 5456 | NIG_STATUS_XGXS0_LINK_STATUS | |
5447 | NIG_STATUS_SERDES0_LINK_STATUS)); | 5457 | NIG_STATUS_SERDES0_LINK_STATUS)); |
5448 | if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) | 5458 | if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) |
5449 | == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) { | 5459 | == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) || |
5460 | (XGXS_EXT_PHY_TYPE(params->ext_phy_config) | ||
5461 | == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) { | ||
5450 | bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); | 5462 | bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int); |
5451 | } | 5463 | } |
5452 | if (vars->phy_link_up) { | 5464 | if (vars->phy_link_up) { |
@@ -5559,6 +5571,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, | |||
5559 | status = bnx2x_format_ver(spirom_ver, version, len); | 5571 | status = bnx2x_format_ver(spirom_ver, version, len); |
5560 | break; | 5572 | break; |
5561 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | 5573 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: |
5574 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
5562 | spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 | | 5575 | spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 | |
5563 | (spirom_ver & 0x7F); | 5576 | (spirom_ver & 0x7F); |
5564 | status = bnx2x_format_ver(spirom_ver, version, len); | 5577 | status = bnx2x_format_ver(spirom_ver, version, len); |
@@ -6250,6 +6263,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |||
6250 | bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); | 6263 | bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr); |
6251 | break; | 6264 | break; |
6252 | } | 6265 | } |
6266 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
6267 | { | ||
6268 | u8 ext_phy_addr = | ||
6269 | XGXS_EXT_PHY_ADDR(params->ext_phy_config); | ||
6270 | bnx2x_cl45_write(bp, port, | ||
6271 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | ||
6272 | ext_phy_addr, | ||
6273 | MDIO_AN_DEVAD, | ||
6274 | MDIO_AN_REG_CTRL, 0x0000); | ||
6275 | bnx2x_cl45_write(bp, port, | ||
6276 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | ||
6277 | ext_phy_addr, | ||
6278 | MDIO_PMA_DEVAD, | ||
6279 | MDIO_PMA_REG_CTRL, 1); | ||
6280 | break; | ||
6281 | } | ||
6253 | default: | 6282 | default: |
6254 | /* HW reset */ | 6283 | /* HW reset */ |
6255 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | 6284 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
@@ -6661,6 +6690,13 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base) | |||
6661 | return 0; | 6690 | return 0; |
6662 | } | 6691 | } |
6663 | 6692 | ||
6693 | |||
6694 | static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base) | ||
6695 | { | ||
6696 | /* HW reset */ | ||
6697 | bnx2x_ext_phy_hw_reset(bp, 1); | ||
6698 | return 0; | ||
6699 | } | ||
6664 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) | 6700 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) |
6665 | { | 6701 | { |
6666 | u8 rc = 0; | 6702 | u8 rc = 0; |
@@ -6690,7 +6726,9 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) | |||
6690 | /* GPIO1 affects both ports, so there's need to pull | 6726 | /* GPIO1 affects both ports, so there's need to pull |
6691 | it for single port alone */ | 6727 | it for single port alone */ |
6692 | rc = bnx2x_8726_common_init_phy(bp, shmem_base); | 6728 | rc = bnx2x_8726_common_init_phy(bp, shmem_base); |
6693 | 6729 | break; | |
6730 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | ||
6731 | rc = bnx2x_84823_common_init_phy(bp, shmem_base); | ||
6694 | break; | 6732 | break; |
6695 | default: | 6733 | default: |
6696 | DP(NETIF_MSG_LINK, | 6734 | DP(NETIF_MSG_LINK, |