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-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c289
1 files changed, 122 insertions, 167 deletions
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index 52e734042b8e..466c730e6297 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -757,6 +757,10 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
757 ((port_count > 2) && 757 ((port_count > 2) &&
758 (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) { 758 (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) {
759 /* init serdes 1 */ 759 /* init serdes 1 */
760 if (nesadapter->phy_type[0] == NES_PHY_TYPE_ARGUS) {
761 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
762 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
763 }
760 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF); 764 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
761 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { 765 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
762 serdes_common_control = nes_read_indexed(nesdev, 766 serdes_common_control = nes_read_indexed(nesdev,
@@ -1259,203 +1263,155 @@ int nes_init_phy(struct nes_device *nesdev)
1259{ 1263{
1260 struct nes_adapter *nesadapter = nesdev->nesadapter; 1264 struct nes_adapter *nesadapter = nesdev->nesadapter;
1261 u32 counter = 0; 1265 u32 counter = 0;
1262 u32 sds_common_control0; 1266 u32 sds;
1263 u32 mac_index = nesdev->mac_index; 1267 u32 mac_index = nesdev->mac_index;
1264 u32 tx_config = 0; 1268 u32 tx_config = 0;
1265 u16 phy_data; 1269 u16 phy_data;
1266 u32 temp_phy_data = 0; 1270 u32 temp_phy_data = 0;
1267 u32 temp_phy_data2 = 0; 1271 u32 temp_phy_data2 = 0;
1268 u32 i = 0; 1272 u8 phy_type = nesadapter->phy_type[mac_index];
1273 u8 phy_index = nesadapter->phy_index[mac_index];
1269 1274
1270 if ((nesadapter->OneG_Mode) && 1275 if ((nesadapter->OneG_Mode) &&
1271 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) { 1276 (phy_type != NES_PHY_TYPE_PUMA_1G)) {
1272 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); 1277 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
1273 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) { 1278 if (phy_type == NES_PHY_TYPE_1G) {
1274 printk(PFX "%s: Programming mdc config for 1G\n", __func__);
1275 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); 1279 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1276 tx_config &= 0xFFFFFFE3; 1280 tx_config &= 0xFFFFFFE3;
1277 tx_config |= 0x04; 1281 tx_config |= 0x04;
1278 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); 1282 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1279 } 1283 }
1280 1284
1281 nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data); 1285 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1282 nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n", 1286 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
1283 nesadapter->phy_index[mac_index], phy_data);
1284 nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
1285 1287
1286 /* Reset the PHY */ 1288 /* Reset the PHY */
1287 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], 0x8000); 1289 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1288 udelay(100); 1290 udelay(100);
1289 counter = 0; 1291 counter = 0;
1290 do { 1292 do {
1291 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1293 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1292 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1294 if (counter++ > 100)
1293 if (counter++ > 100) break; 1295 break;
1294 } while (phy_data & 0x8000); 1296 } while (phy_data & 0x8000);
1295 1297
1296 /* Setting no phy loopback */ 1298 /* Setting no phy loopback */
1297 phy_data &= 0xbfff; 1299 phy_data &= 0xbfff;
1298 phy_data |= 0x1140; 1300 phy_data |= 0x1140;
1299 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data); 1301 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1300 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1302 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1301 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1303 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1302 1304 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1303 nes_read_1G_phy_reg(nesdev, 0x17, nesadapter->phy_index[mac_index], &phy_data);
1304 nes_debug(NES_DBG_PHY, "Phy data from register 0x17 = 0x%X.\n", phy_data);
1305
1306 nes_read_1G_phy_reg(nesdev, 0x1e, nesadapter->phy_index[mac_index], &phy_data);
1307 nes_debug(NES_DBG_PHY, "Phy data from register 0x1e = 0x%X.\n", phy_data);
1308 1305
1309 /* Setting the interrupt mask */ 1306 /* Setting the interrupt mask */
1310 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data); 1307 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1311 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data); 1308 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1312 nes_write_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], 0xffee); 1309 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1313
1314 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
1315 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
1316 1310
1317 /* turning on flow control */ 1311 /* turning on flow control */
1318 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data); 1312 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1319 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data); 1313 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1320 nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], 1314 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1321 (phy_data & ~(0x03E0)) | 0xc00);
1322 /* nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
1323 phy_data | 0xc00); */
1324 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
1325 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
1326
1327 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1328 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1329 /* Clear Half duplex */
1330 nes_write_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index],
1331 phy_data & ~(0x0100));
1332 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1333 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1334 1315
1335 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1316 /* Clear Half duplex */
1336 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300); 1317 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1337 } else { 1318 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1338 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) || 1319 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1339 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1340 /* setup 10G MDIO operation */
1341 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1342 tx_config &= 0xFFFFFFE3;
1343 tx_config |= 0x15;
1344 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1345 }
1346 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1347 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1348 1320
1349 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1321 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1350 mdelay(10); 1322 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1351 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1352 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1353 1323
1354 /* 1324 return 0;
1355 * if firmware is already running (like from a 1325 }
1356 * driver un-load/load, don't do anything.
1357 */
1358 if (temp_phy_data == temp_phy_data2) {
1359 /* configure QT2505 AMCC PHY */
1360 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0x0000, 0x8000);
1361 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0000);
1362 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc302, 0x0044);
1363 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc318, 0x0052);
1364 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc319, 0x0008);
1365 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc31a, 0x0098);
1366 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0026, 0x0E00);
1367 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0027, 0x0001);
1368 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0028, 0xA528);
1369 1326
1370 /* 1327 if ((phy_type == NES_PHY_TYPE_IRIS) ||
1371 * remove micro from reset; chip boots from ROM, 1328 (phy_type == NES_PHY_TYPE_ARGUS)) {
1372 * uploads EEPROM f/w image, uC executes f/w 1329 /* setup 10G MDIO operation */
1373 */ 1330 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1374 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0002); 1331 tx_config &= 0xFFFFFFE3;
1332 tx_config |= 0x15;
1333 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1334 }
1335 if ((phy_type == NES_PHY_TYPE_ARGUS)) {
1336 /* Check firmware heartbeat */
1337 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1338 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1339 udelay(1500);
1340 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1341 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1375 1342
1376 /* 1343 if (temp_phy_data != temp_phy_data2)
1377 * wait for heart beat to start to 1344 return 0;
1378 * know loading is done
1379 */
1380 counter = 0;
1381 do {
1382 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1383 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1384 if (counter++ > 1000) {
1385 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from heartbeat check <this is bad!!!> \n");
1386 break;
1387 }
1388 mdelay(100);
1389 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1390 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1391 } while ((temp_phy_data2 == temp_phy_data));
1392 1345
1393 /* 1346 /* no heartbeat, configure the PHY */
1394 * wait for tracking to start to know 1347 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1395 * f/w is good to go 1348 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1396 */ 1349 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1397 counter = 0; 1350 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1398 do { 1351 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1399 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7fd); 1352 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1400 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1353 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1401 if (counter++ > 1000) { 1354 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1402 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from status check <this is bad!!!> \n"); 1355 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1403 break;
1404 }
1405 mdelay(1000);
1406 /*
1407 * nes_debug(NES_DBG_PHY, "AMCC PHY- phy_status not ready yet = 0x%02X\n",
1408 * temp_phy_data);
1409 */
1410 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1411
1412 /* set LOS Control invert RXLOSB_I_PADINV */
1413 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd003, 0x0000);
1414 /* set LOS Control to mask of RXLOSB_I */
1415 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc314, 0x0042);
1416 /* set LED1 to input mode (LED1 and LED2 share same LED) */
1417 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd006, 0x0007);
1418 /* set LED2 to RX link_status and activity */
1419 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd007, 0x000A);
1420 /* set LED3 to RX link_status */
1421 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd008, 0x0009);
1422 1356
1423 /* 1357 /* setup LEDs */
1424 * reset the res-calibration on t2 1358 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1425 * serdes; ensures it is stable after 1359 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1426 * the amcc phy is stable 1360 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1427 */
1428 1361
1429 sds_common_control0 = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); 1362 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
1430 sds_common_control0 |= 0x1;
1431 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1432 1363
1433 /* release the res-calibration reset */ 1364 /* Bring PHY out of reset */
1434 sds_common_control0 &= 0xfffffffe; 1365 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
1435 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1436 1366
1437 i = 0; 1367 /* Check for heartbeat */
1438 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) 1368 counter = 0;
1439 && (i++ < 5000)) { 1369 mdelay(690);
1440 /* mdelay(1); */ 1370 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1441 } 1371 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1372 do {
1373 if (counter++ > 150) {
1374 nes_debug(NES_DBG_PHY, "No PHY heartbeat\n");
1375 break;
1376 }
1377 mdelay(1);
1378 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1379 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1380 } while ((temp_phy_data2 == temp_phy_data));
1442 1381
1443 /* 1382 /* wait for tracking */
1444 * wait for link train done before moving on, 1383 counter = 0;
1445 * or will get an interupt storm 1384 do {
1446 */ 1385 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1447 counter = 0; 1386 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1448 do { 1387 if (counter++ > 300) {
1449 temp_phy_data = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 1388 nes_debug(NES_DBG_PHY, "PHY did not track\n");
1450 (0x200 * (nesdev->mac_index & 1))); 1389 break;
1451 if (counter++ > 1000) {
1452 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from link train wait <this is bad, link didnt train!!!>\n");
1453 break;
1454 }
1455 mdelay(1);
1456 } while (((temp_phy_data & 0x0f1f0000) != 0x0f0f0000));
1457 } 1390 }
1458 } 1391 mdelay(10);
1392 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1393
1394 /* setup signal integrity */
1395 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1396 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1397 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1398 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1399 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
1400
1401 /* reset serdes */
1402 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1403 mac_index * 0x200);
1404 sds |= 0x1;
1405 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1406 mac_index * 0x200, sds);
1407 sds &= 0xfffffffe;
1408 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1409 mac_index * 0x200, sds);
1410
1411 counter = 0;
1412 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1413 && (counter++ < 5000))
1414 ;
1459 } 1415 }
1460 return 0; 1416 return 0;
1461} 1417}
@@ -2483,19 +2439,18 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2483 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004); 2439 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2484 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005); 2440 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2485 /* check link status */ 2441 /* check link status */
2486 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); 2442 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2487 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2443 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2488 u32temp = 100;
2489 do {
2490 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1);
2491 2444
2492 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2445 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2493 if ((phy_data == temp_phy_data) || (!(--u32temp))) 2446 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2494 break; 2447 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2495 temp_phy_data = phy_data; 2448 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2496 } while (1); 2449
2450 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2451
2497 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n", 2452 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2498 __func__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP"); 2453 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2499 break; 2454 break;
2500 2455
2501 case NES_PHY_TYPE_PUMA_1G: 2456 case NES_PHY_TYPE_PUMA_1G:
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-13 19:02:31 -0500