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-rw-r--r--drivers/net/tg3.c1299
-rw-r--r--drivers/net/tg3.h168
2 files changed, 728 insertions, 739 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b20538a34fd1..fa57e3d699de 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -62,6 +62,30 @@
62 62
63#include "tg3.h" 63#include "tg3.h"
64 64
65/* Functions & macros to verify TG3_FLAGS types */
66
67static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
68{
69 return test_bit(flag, bits);
70}
71
72static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
73{
74 set_bit(flag, bits);
75}
76
77static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
78{
79 clear_bit(flag, bits);
80}
81
82#define tg3_flag(tp, flag) \
83 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
84#define tg3_flag_set(tp, flag) \
85 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
86#define tg3_flag_clear(tp, flag) \
87 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
88
65#define DRV_MODULE_NAME "tg3" 89#define DRV_MODULE_NAME "tg3"
66#define TG3_MAJ_NUM 3 90#define TG3_MAJ_NUM 3
67#define TG3_MIN_NUM 118 91#define TG3_MIN_NUM 118
@@ -85,23 +109,24 @@
85/* length of time before we decide the hardware is borked, 109/* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem 110 * and dev->tx_timeout() should be called to fix the problem
87 */ 111 */
112
88#define TG3_TX_TIMEOUT (5 * HZ) 113#define TG3_TX_TIMEOUT (5 * HZ)
89 114
90/* hardware minimum and maximum for a single frame's data payload */ 115/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60 116#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \ 117#define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) 118 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
94 119
95/* These numbers seem to be hard coded in the NIC firmware somehow. 120/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place 121 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory. 122 * them in the NIC onboard memory.
98 */ 123 */
99#define TG3_RX_STD_RING_SIZE(tp) \ 124#define TG3_RX_STD_RING_SIZE(tp) \
100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ 125 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) 126 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102#define TG3_DEF_RX_RING_PENDING 200 127#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JMB_RING_SIZE(tp) \ 128#define TG3_RX_JMB_RING_SIZE(tp) \
104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \ 129 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) 130 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106#define TG3_DEF_RX_JUMBO_RING_PENDING 100 131#define TG3_DEF_RX_JUMBO_RING_PENDING 100
107#define TG3_RSS_INDIR_TBL_SIZE 128 132#define TG3_RSS_INDIR_TBL_SIZE 128
@@ -468,8 +493,7 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
468 */ 493 */
469static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) 494static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
470{ 495{
471 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || 496 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
472 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
473 /* Non-posted methods */ 497 /* Non-posted methods */
474 tp->write32(tp, off, val); 498 tp->write32(tp, off, val);
475 else { 499 else {
@@ -489,8 +513,7 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
489static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) 513static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
490{ 514{
491 tp->write32_mbox(tp, off, val); 515 tp->write32_mbox(tp, off, val);
492 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && 516 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
493 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
494 tp->read32_mbox(tp, off); 517 tp->read32_mbox(tp, off);
495} 518}
496 519
@@ -498,9 +521,9 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
498{ 521{
499 void __iomem *mbox = tp->regs + off; 522 void __iomem *mbox = tp->regs + off;
500 writel(val, mbox); 523 writel(val, mbox);
501 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) 524 if (tg3_flag(tp, TXD_MBOX_HWBUG))
502 writel(val, mbox); 525 writel(val, mbox);
503 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) 526 if (tg3_flag(tp, MBOX_WRITE_REORDER))
504 readl(mbox); 527 readl(mbox);
505} 528}
506 529
@@ -534,7 +557,7 @@ static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
534 return; 557 return;
535 558
536 spin_lock_irqsave(&tp->indirect_lock, flags); 559 spin_lock_irqsave(&tp->indirect_lock, flags);
537 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { 560 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
538 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 561 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
539 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 562 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
540 563
@@ -561,7 +584,7 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 } 584 }
562 585
563 spin_lock_irqsave(&tp->indirect_lock, flags); 586 spin_lock_irqsave(&tp->indirect_lock, flags);
564 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { 587 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
565 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 588 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
566 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 589 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
567 590
@@ -598,7 +621,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
598 int ret = 0; 621 int ret = 0;
599 u32 status, req, gnt; 622 u32 status, req, gnt;
600 623
601 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 624 if (!tg3_flag(tp, ENABLE_APE))
602 return 0; 625 return 0;
603 626
604 switch (locknum) { 627 switch (locknum) {
@@ -644,7 +667,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
644{ 667{
645 u32 gnt; 668 u32 gnt;
646 669
647 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 670 if (!tg3_flag(tp, ENABLE_APE))
648 return; 671 return;
649 672
650 switch (locknum) { 673 switch (locknum) {
@@ -688,14 +711,14 @@ static void tg3_enable_ints(struct tg3 *tp)
688 struct tg3_napi *tnapi = &tp->napi[i]; 711 struct tg3_napi *tnapi = &tp->napi[i];
689 712
690 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 713 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
691 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) 714 if (tg3_flag(tp, 1SHOT_MSI))
692 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 715 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
693 716
694 tp->coal_now |= tnapi->coal_now; 717 tp->coal_now |= tnapi->coal_now;
695 } 718 }
696 719
697 /* Force an initial interrupt */ 720 /* Force an initial interrupt */
698 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && 721 if (!tg3_flag(tp, TAGGED_STATUS) &&
699 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) 722 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
700 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); 723 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
701 else 724 else
@@ -711,9 +734,7 @@ static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
711 unsigned int work_exists = 0; 734 unsigned int work_exists = 0;
712 735
713 /* check for phy events */ 736 /* check for phy events */
714 if (!(tp->tg3_flags & 737 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
715 (TG3_FLAG_USE_LINKCHG_REG |
716 TG3_FLAG_POLL_SERDES))) {
717 if (sblk->status & SD_STATUS_LINK_CHG) 738 if (sblk->status & SD_STATUS_LINK_CHG)
718 work_exists = 1; 739 work_exists = 1;
719 } 740 }
@@ -741,8 +762,7 @@ static void tg3_int_reenable(struct tg3_napi *tnapi)
741 * The last_tag we write above tells the chip which piece of 762 * The last_tag we write above tells the chip which piece of
742 * work we've completed. 763 * work we've completed.
743 */ 764 */
744 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && 765 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
745 tg3_has_work(tnapi))
746 tw32(HOSTCC_MODE, tp->coalesce_mode | 766 tw32(HOSTCC_MODE, tp->coalesce_mode |
747 HOSTCC_MODE_ENABLE | tnapi->coal_now); 767 HOSTCC_MODE_ENABLE | tnapi->coal_now);
748} 768}
@@ -752,8 +772,7 @@ static void tg3_switch_clocks(struct tg3 *tp)
752 u32 clock_ctrl; 772 u32 clock_ctrl;
753 u32 orig_clock_ctrl; 773 u32 orig_clock_ctrl;
754 774
755 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || 775 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
756 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757 return; 776 return;
758 777
759 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); 778 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
@@ -764,7 +783,7 @@ static void tg3_switch_clocks(struct tg3 *tp)
764 0x1f); 783 0x1f);
765 tp->pci_clock_ctrl = clock_ctrl; 784 tp->pci_clock_ctrl = clock_ctrl;
766 785
767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 786 if (tg3_flag(tp, 5705_PLUS)) {
768 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { 787 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
769 tw32_wait_f(TG3PCI_CLOCK_CTRL, 788 tw32_wait_f(TG3PCI_CLOCK_CTRL,
770 clock_ctrl | CLOCK_CTRL_625_CORE, 40); 789 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
@@ -1081,7 +1100,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
1081 return; 1100 return;
1082 } 1101 }
1083 1102
1084 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) 1103 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1085 val |= MAC_PHYCFG2_EMODE_MASK_MASK | 1104 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1086 MAC_PHYCFG2_FMODE_MASK_MASK | 1105 MAC_PHYCFG2_FMODE_MASK_MASK |
1087 MAC_PHYCFG2_GMODE_MASK_MASK | 1106 MAC_PHYCFG2_GMODE_MASK_MASK |
@@ -1094,10 +1113,10 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
1094 val = tr32(MAC_PHYCFG1); 1113 val = tr32(MAC_PHYCFG1);
1095 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | 1114 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1096 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); 1115 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1097 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { 1116 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1098 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) 1117 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1099 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; 1118 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1100 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) 1119 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1101 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; 1120 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1102 } 1121 }
1103 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | 1122 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
@@ -1112,13 +1131,13 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
1112 MAC_RGMII_MODE_TX_ENABLE | 1131 MAC_RGMII_MODE_TX_ENABLE |
1113 MAC_RGMII_MODE_TX_LOWPWR | 1132 MAC_RGMII_MODE_TX_LOWPWR |
1114 MAC_RGMII_MODE_TX_RESET); 1133 MAC_RGMII_MODE_TX_RESET);
1115 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { 1134 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1116 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) 1135 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1117 val |= MAC_RGMII_MODE_RX_INT_B | 1136 val |= MAC_RGMII_MODE_RX_INT_B |
1118 MAC_RGMII_MODE_RX_QUALITY | 1137 MAC_RGMII_MODE_RX_QUALITY |
1119 MAC_RGMII_MODE_RX_ACTIVITY | 1138 MAC_RGMII_MODE_RX_ACTIVITY |
1120 MAC_RGMII_MODE_RX_ENG_DET; 1139 MAC_RGMII_MODE_RX_ENG_DET;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) 1140 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1122 val |= MAC_RGMII_MODE_TX_ENABLE | 1141 val |= MAC_RGMII_MODE_TX_ENABLE |
1123 MAC_RGMII_MODE_TX_LOWPWR | 1142 MAC_RGMII_MODE_TX_LOWPWR |
1124 MAC_RGMII_MODE_TX_RESET; 1143 MAC_RGMII_MODE_TX_RESET;
@@ -1132,7 +1151,7 @@ static void tg3_mdio_start(struct tg3 *tp)
1132 tw32_f(MAC_MI_MODE, tp->mi_mode); 1151 tw32_f(MAC_MI_MODE, tp->mi_mode);
1133 udelay(80); 1152 udelay(80);
1134 1153
1135 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && 1154 if (tg3_flag(tp, MDIOBUS_INITED) &&
1136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 1155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1137 tg3_mdio_config_5785(tp); 1156 tg3_mdio_config_5785(tp);
1138} 1157}
@@ -1143,7 +1162,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1143 u32 reg; 1162 u32 reg;
1144 struct phy_device *phydev; 1163 struct phy_device *phydev;
1145 1164
1146 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { 1165 if (tg3_flag(tp, 5717_PLUS)) {
1147 u32 is_serdes; 1166 u32 is_serdes;
1148 1167
1149 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1; 1168 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
@@ -1160,8 +1179,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1160 1179
1161 tg3_mdio_start(tp); 1180 tg3_mdio_start(tp);
1162 1181
1163 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || 1182 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1164 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1165 return 0; 1183 return 0;
1166 1184
1167 tp->mdio_bus = mdiobus_alloc(); 1185 tp->mdio_bus = mdiobus_alloc();
@@ -1217,11 +1235,11 @@ static int tg3_mdio_init(struct tg3 *tp)
1217 PHY_BRCM_RX_REFCLK_UNUSED | 1235 PHY_BRCM_RX_REFCLK_UNUSED |
1218 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1236 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1219 PHY_BRCM_AUTO_PWRDWN_ENABLE; 1237 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1220 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) 1238 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1221 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; 1239 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1222 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) 1240 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1223 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; 1241 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1224 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) 1242 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1225 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; 1243 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1226 /* fallthru */ 1244 /* fallthru */
1227 case PHY_ID_RTL8211C: 1245 case PHY_ID_RTL8211C:
@@ -1235,7 +1253,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1235 break; 1253 break;
1236 } 1254 }
1237 1255
1238 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; 1256 tg3_flag_set(tp, MDIOBUS_INITED);
1239 1257
1240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 1258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1241 tg3_mdio_config_5785(tp); 1259 tg3_mdio_config_5785(tp);
@@ -1245,8 +1263,8 @@ static int tg3_mdio_init(struct tg3 *tp)
1245 1263
1246static void tg3_mdio_fini(struct tg3 *tp) 1264static void tg3_mdio_fini(struct tg3 *tp)
1247{ 1265{
1248 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { 1266 if (tg3_flag(tp, MDIOBUS_INITED)) {
1249 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; 1267 tg3_flag_clear(tp, MDIOBUS_INITED);
1250 mdiobus_unregister(tp->mdio_bus); 1268 mdiobus_unregister(tp->mdio_bus);
1251 mdiobus_free(tp->mdio_bus); 1269 mdiobus_free(tp->mdio_bus);
1252 } 1270 }
@@ -1299,8 +1317,7 @@ static void tg3_ump_link_report(struct tg3 *tp)
1299 u32 reg; 1317 u32 reg;
1300 u32 val; 1318 u32 val;
1301 1319
1302 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 1320 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1303 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1304 return; 1321 return;
1305 1322
1306 tg3_wait_for_event_ack(tp); 1323 tg3_wait_for_event_ack(tp);
@@ -1430,13 +1447,12 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1430 u32 old_rx_mode = tp->rx_mode; 1447 u32 old_rx_mode = tp->rx_mode;
1431 u32 old_tx_mode = tp->tx_mode; 1448 u32 old_tx_mode = tp->tx_mode;
1432 1449
1433 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) 1450 if (tg3_flag(tp, USE_PHYLIB))
1434 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; 1451 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1435 else 1452 else
1436 autoneg = tp->link_config.autoneg; 1453 autoneg = tp->link_config.autoneg;
1437 1454
1438 if (autoneg == AUTONEG_ENABLE && 1455 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1439 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1440 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) 1456 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1441 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); 1457 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1442 else 1458 else
@@ -1657,8 +1673,8 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1657{ 1673{
1658 u32 reg; 1674 u32 reg;
1659 1675
1660 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 1676 if (!tg3_flag(tp, 5705_PLUS) ||
1661 ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && 1677 (tg3_flag(tp, 5717_PLUS) &&
1662 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) 1678 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1663 return; 1679 return;
1664 1680
@@ -1692,7 +1708,7 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1692{ 1708{
1693 u32 phy; 1709 u32 phy;
1694 1710
1695 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 1711 if (!tg3_flag(tp, 5705_PLUS) ||
1696 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) 1712 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1697 return; 1713 return;
1698 1714
@@ -2065,7 +2081,7 @@ static int tg3_phy_reset(struct tg3 *tp)
2065 } 2081 }
2066 } 2082 }
2067 2083
2068 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && 2084 if (tg3_flag(tp, 5717_PLUS) &&
2069 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) 2085 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2070 return 0; 2086 return 0;
2071 2087
@@ -2115,7 +2131,7 @@ out:
2115 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { 2131 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2116 /* Cannot do read-modify-write on 5401 */ 2132 /* Cannot do read-modify-write on 5401 */
2117 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); 2133 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2118 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { 2134 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2119 /* Set bit 14 with read-modify-write to preserve other bits */ 2135 /* Set bit 14 with read-modify-write to preserve other bits */
2120 err = tg3_phy_auxctl_read(tp, 2136 err = tg3_phy_auxctl_read(tp,
2121 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); 2137 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
@@ -2127,7 +2143,7 @@ out:
2127 /* Set phy register 0x10 bit 0 to high fifo elasticity to support 2143 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2128 * jumbo frames transmission. 2144 * jumbo frames transmission.
2129 */ 2145 */
2130 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { 2146 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2131 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) 2147 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2132 tg3_writephy(tp, MII_TG3_EXT_CTRL, 2148 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2133 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); 2149 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
@@ -2148,7 +2164,7 @@ static void tg3_frob_aux_power(struct tg3 *tp)
2148 bool need_vaux = false; 2164 bool need_vaux = false;
2149 2165
2150 /* The GPIOs do something completely different on 57765. */ 2166 /* The GPIOs do something completely different on 57765. */
2151 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || 2167 if (!tg3_flag(tp, IS_NIC) ||
2152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 2168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 2169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2154 return; 2170 return;
@@ -2166,17 +2182,16 @@ static void tg3_frob_aux_power(struct tg3 *tp)
2166 if (dev_peer) { 2182 if (dev_peer) {
2167 struct tg3 *tp_peer = netdev_priv(dev_peer); 2183 struct tg3 *tp_peer = netdev_priv(dev_peer);
2168 2184
2169 if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) 2185 if (tg3_flag(tp_peer, INIT_COMPLETE))
2170 return; 2186 return;
2171 2187
2172 if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) || 2188 if (tg3_flag(tp_peer, WOL_ENABLE) ||
2173 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF)) 2189 tg3_flag(tp_peer, ENABLE_ASF))
2174 need_vaux = true; 2190 need_vaux = true;
2175 } 2191 }
2176 } 2192 }
2177 2193
2178 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) || 2194 if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF))
2179 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2180 need_vaux = true; 2195 need_vaux = true;
2181 2196
2182 if (need_vaux) { 2197 if (need_vaux) {
@@ -2359,7 +2374,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2359/* tp->lock is held. */ 2374/* tp->lock is held. */
2360static int tg3_nvram_lock(struct tg3 *tp) 2375static int tg3_nvram_lock(struct tg3 *tp)
2361{ 2376{
2362 if (tp->tg3_flags & TG3_FLAG_NVRAM) { 2377 if (tg3_flag(tp, NVRAM)) {
2363 int i; 2378 int i;
2364 2379
2365 if (tp->nvram_lock_cnt == 0) { 2380 if (tp->nvram_lock_cnt == 0) {
@@ -2382,7 +2397,7 @@ static int tg3_nvram_lock(struct tg3 *tp)
2382/* tp->lock is held. */ 2397/* tp->lock is held. */
2383static void tg3_nvram_unlock(struct tg3 *tp) 2398static void tg3_nvram_unlock(struct tg3 *tp)
2384{ 2399{
2385 if (tp->tg3_flags & TG3_FLAG_NVRAM) { 2400 if (tg3_flag(tp, NVRAM)) {
2386 if (tp->nvram_lock_cnt > 0) 2401 if (tp->nvram_lock_cnt > 0)
2387 tp->nvram_lock_cnt--; 2402 tp->nvram_lock_cnt--;
2388 if (tp->nvram_lock_cnt == 0) 2403 if (tp->nvram_lock_cnt == 0)
@@ -2393,8 +2408,7 @@ static void tg3_nvram_unlock(struct tg3 *tp)
2393/* tp->lock is held. */ 2408/* tp->lock is held. */
2394static void tg3_enable_nvram_access(struct tg3 *tp) 2409static void tg3_enable_nvram_access(struct tg3 *tp)
2395{ 2410{
2396 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 2411 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2397 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2398 u32 nvaccess = tr32(NVRAM_ACCESS); 2412 u32 nvaccess = tr32(NVRAM_ACCESS);
2399 2413
2400 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 2414 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -2404,8 +2418,7 @@ static void tg3_enable_nvram_access(struct tg3 *tp)
2404/* tp->lock is held. */ 2418/* tp->lock is held. */
2405static void tg3_disable_nvram_access(struct tg3 *tp) 2419static void tg3_disable_nvram_access(struct tg3 *tp)
2406{ 2420{
2407 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 2421 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2408 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2409 u32 nvaccess = tr32(NVRAM_ACCESS); 2422 u32 nvaccess = tr32(NVRAM_ACCESS);
2410 2423
2411 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 2424 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -2475,10 +2488,10 @@ static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2475 2488
2476static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) 2489static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2477{ 2490{
2478 if ((tp->tg3_flags & TG3_FLAG_NVRAM) && 2491 if (tg3_flag(tp, NVRAM) &&
2479 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && 2492 tg3_flag(tp, NVRAM_BUFFERED) &&
2480 (tp->tg3_flags2 & TG3_FLG2_FLASH) && 2493 tg3_flag(tp, FLASH) &&
2481 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && 2494 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2482 (tp->nvram_jedecnum == JEDEC_ATMEL)) 2495 (tp->nvram_jedecnum == JEDEC_ATMEL))
2483 2496
2484 addr = ((addr / tp->nvram_pagesize) << 2497 addr = ((addr / tp->nvram_pagesize) <<
@@ -2490,10 +2503,10 @@ static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2490 2503
2491static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) 2504static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2492{ 2505{
2493 if ((tp->tg3_flags & TG3_FLAG_NVRAM) && 2506 if (tg3_flag(tp, NVRAM) &&
2494 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && 2507 tg3_flag(tp, NVRAM_BUFFERED) &&
2495 (tp->tg3_flags2 & TG3_FLG2_FLASH) && 2508 tg3_flag(tp, FLASH) &&
2496 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && 2509 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2497 (tp->nvram_jedecnum == JEDEC_ATMEL)) 2510 (tp->nvram_jedecnum == JEDEC_ATMEL))
2498 2511
2499 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * 2512 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
@@ -2513,7 +2526,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2513{ 2526{
2514 int ret; 2527 int ret;
2515 2528
2516 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) 2529 if (!tg3_flag(tp, NVRAM))
2517 return tg3_nvram_read_using_eeprom(tp, offset, val); 2530 return tg3_nvram_read_using_eeprom(tp, offset, val);
2518 2531
2519 offset = tg3_nvram_phys_addr(tp, offset); 2532 offset = tg3_nvram_phys_addr(tp, offset);
@@ -2605,7 +2618,7 @@ static int tg3_power_up(struct tg3 *tp)
2605 pci_set_power_state(tp->pdev, PCI_D0); 2618 pci_set_power_state(tp->pdev, PCI_D0);
2606 2619
2607 /* Switch out of Vaux if it is a NIC */ 2620 /* Switch out of Vaux if it is a NIC */
2608 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) 2621 if (tg3_flag(tp, IS_NIC))
2609 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); 2622 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2610 2623
2611 return 0; 2624 return 0;
@@ -2619,7 +2632,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2619 tg3_enable_register_access(tp); 2632 tg3_enable_register_access(tp);
2620 2633
2621 /* Restore the CLKREQ setting. */ 2634 /* Restore the CLKREQ setting. */
2622 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { 2635 if (tg3_flag(tp, CLKREQ_BUG)) {
2623 u16 lnkctl; 2636 u16 lnkctl;
2624 2637
2625 pci_read_config_word(tp->pdev, 2638 pci_read_config_word(tp->pdev,
@@ -2636,9 +2649,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2636 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 2649 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2637 2650
2638 device_should_wake = device_may_wakeup(&tp->pdev->dev) && 2651 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2639 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); 2652 tg3_flag(tp, WOL_ENABLE);
2640 2653
2641 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 2654 if (tg3_flag(tp, USE_PHYLIB)) {
2642 do_low_power = false; 2655 do_low_power = false;
2643 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && 2656 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2644 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { 2657 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
@@ -2659,9 +2672,8 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2659 ADVERTISED_Autoneg | 2672 ADVERTISED_Autoneg |
2660 ADVERTISED_10baseT_Half; 2673 ADVERTISED_10baseT_Half;
2661 2674
2662 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 2675 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
2663 device_should_wake) { 2676 if (tg3_flag(tp, WOL_SPEED_100MB))
2664 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2665 advertising |= 2677 advertising |=
2666 ADVERTISED_100baseT_Half | 2678 ADVERTISED_100baseT_Half |
2667 ADVERTISED_100baseT_Full | 2679 ADVERTISED_100baseT_Full |
@@ -2706,7 +2718,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2706 2718
2707 val = tr32(GRC_VCPU_EXT_CTRL); 2719 val = tr32(GRC_VCPU_EXT_CTRL);
2708 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); 2720 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2709 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 2721 } else if (!tg3_flag(tp, ENABLE_ASF)) {
2710 int i; 2722 int i;
2711 u32 val; 2723 u32 val;
2712 2724
@@ -2717,7 +2729,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2717 msleep(1); 2729 msleep(1);
2718 } 2730 }
2719 } 2731 }
2720 if (tp->tg3_flags & TG3_FLAG_WOL_CAP) 2732 if (tg3_flag(tp, WOL_CAP))
2721 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | 2733 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2722 WOL_DRV_STATE_SHUTDOWN | 2734 WOL_DRV_STATE_SHUTDOWN |
2723 WOL_DRV_WOL | 2735 WOL_DRV_WOL |
@@ -2745,8 +2757,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2745 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; 2757 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == 2758 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2747 ASIC_REV_5700) { 2759 ASIC_REV_5700) {
2748 u32 speed = (tp->tg3_flags & 2760 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
2749 TG3_FLAG_WOL_SPEED_100MB) ?
2750 SPEED_100 : SPEED_10; 2761 SPEED_100 : SPEED_10;
2751 if (tg3_5700_link_polarity(tp, speed)) 2762 if (tg3_5700_link_polarity(tp, speed))
2752 mac_mode |= MAC_MODE_LINK_POLARITY; 2763 mac_mode |= MAC_MODE_LINK_POLARITY;
@@ -2757,17 +2768,15 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2757 mac_mode = MAC_MODE_PORT_MODE_TBI; 2768 mac_mode = MAC_MODE_PORT_MODE_TBI;
2758 } 2769 }
2759 2770
2760 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) 2771 if (!tg3_flag(tp, 5750_PLUS))
2761 tw32(MAC_LED_CTRL, tp->led_ctrl); 2772 tw32(MAC_LED_CTRL, tp->led_ctrl);
2762 2773
2763 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; 2774 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2764 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 2775 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
2765 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && 2776 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
2766 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2767 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2768 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; 2777 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2769 2778
2770 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 2779 if (tg3_flag(tp, ENABLE_APE))
2771 mac_mode |= MAC_MODE_APE_TX_EN | 2780 mac_mode |= MAC_MODE_APE_TX_EN |
2772 MAC_MODE_APE_RX_EN | 2781 MAC_MODE_APE_RX_EN |
2773 MAC_MODE_TDE_ENABLE; 2782 MAC_MODE_TDE_ENABLE;
@@ -2779,7 +2788,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2779 udelay(10); 2788 udelay(10);
2780 } 2789 }
2781 2790
2782 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && 2791 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
2783 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 2792 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2784 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { 2793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2785 u32 base_val; 2794 u32 base_val;
@@ -2790,12 +2799,11 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2790 2799
2791 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | 2800 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2792 CLOCK_CTRL_PWRDOWN_PLL133, 40); 2801 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2793 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 2802 } else if (tg3_flag(tp, 5780_CLASS) ||
2794 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || 2803 tg3_flag(tp, CPMU_PRESENT) ||
2795 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { 2804 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2796 /* do nothing */ 2805 /* do nothing */
2797 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 2806 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
2798 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2799 u32 newbits1, newbits2; 2807 u32 newbits1, newbits2;
2800 2808
2801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 2809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -2804,7 +2812,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2804 CLOCK_CTRL_TXCLK_DISABLE | 2812 CLOCK_CTRL_TXCLK_DISABLE |
2805 CLOCK_CTRL_ALTCLK); 2813 CLOCK_CTRL_ALTCLK);
2806 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; 2814 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2807 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 2815 } else if (tg3_flag(tp, 5705_PLUS)) {
2808 newbits1 = CLOCK_CTRL_625_CORE; 2816 newbits1 = CLOCK_CTRL_625_CORE;
2809 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; 2817 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2810 } else { 2818 } else {
@@ -2818,7 +2826,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2818 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, 2826 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2819 40); 2827 40);
2820 2828
2821 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 2829 if (!tg3_flag(tp, 5705_PLUS)) {
2822 u32 newbits3; 2830 u32 newbits3;
2823 2831
2824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 2832 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -2835,8 +2843,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2835 } 2843 }
2836 } 2844 }
2837 2845
2838 if (!(device_should_wake) && 2846 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
2839 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2840 tg3_power_down_phy(tp, do_low_power); 2847 tg3_power_down_phy(tp, do_low_power);
2841 2848
2842 tg3_frob_aux_power(tp); 2849 tg3_frob_aux_power(tp);
@@ -2848,7 +2855,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
2848 2855
2849 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); 2856 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2850 tw32(0x7d00, val); 2857 tw32(0x7d00, val);
2851 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 2858 if (!tg3_flag(tp, ENABLE_ASF)) {
2852 int err; 2859 int err;
2853 2860
2854 err = tg3_nvram_lock(tp); 2861 err = tg3_nvram_lock(tp);
@@ -2867,7 +2874,7 @@ static void tg3_power_down(struct tg3 *tp)
2867{ 2874{
2868 tg3_power_down_prepare(tp); 2875 tg3_power_down_prepare(tp);
2869 2876
2870 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE); 2877 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
2871 pci_set_power_state(tp->pdev, PCI_D3hot); 2878 pci_set_power_state(tp->pdev, PCI_D3hot);
2872} 2879}
2873 2880
@@ -2931,7 +2938,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
2931 2938
2932 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | 2939 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2933 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 2940 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2934 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) 2941 if (tg3_flag(tp, WOL_SPEED_100MB))
2935 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); 2942 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2936 2943
2937 tg3_writephy(tp, MII_ADVERTISE, new_adv); 2944 tg3_writephy(tp, MII_ADVERTISE, new_adv);
@@ -3163,7 +3170,7 @@ static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3163 if (curadv != reqadv) 3170 if (curadv != reqadv)
3164 return 0; 3171 return 0;
3165 3172
3166 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) 3173 if (tg3_flag(tp, PAUSE_AUTONEG))
3167 tg3_readphy(tp, MII_LPA, rmtadv); 3174 tg3_readphy(tp, MII_LPA, rmtadv);
3168 } else { 3175 } else {
3169 /* Reprogram the advertisement register, even if it 3176 /* Reprogram the advertisement register, even if it
@@ -3226,7 +3233,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3226 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { 3233 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3227 tg3_readphy(tp, MII_BMSR, &bmsr); 3234 tg3_readphy(tp, MII_BMSR, &bmsr);
3228 if (tg3_readphy(tp, MII_BMSR, &bmsr) || 3235 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3229 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) 3236 !tg3_flag(tp, INIT_COMPLETE))
3230 bmsr = 0; 3237 bmsr = 0;
3231 3238
3232 if (!(bmsr & BMSR_LSTATUS)) { 3239 if (!(bmsr & BMSR_LSTATUS)) {
@@ -3410,7 +3417,7 @@ relink:
3410 3417
3411 tg3_phy_eee_adjust(tp, current_link_up); 3418 tg3_phy_eee_adjust(tp, current_link_up);
3412 3419
3413 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { 3420 if (tg3_flag(tp, USE_LINKCHG_REG)) {
3414 /* Polled via timer. */ 3421 /* Polled via timer. */
3415 tw32_f(MAC_EVENT, 0); 3422 tw32_f(MAC_EVENT, 0);
3416 } else { 3423 } else {
@@ -3421,8 +3428,7 @@ relink:
3421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && 3428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3422 current_link_up == 1 && 3429 current_link_up == 1 &&
3423 tp->link_config.active_speed == SPEED_1000 && 3430 tp->link_config.active_speed == SPEED_1000 &&
3424 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || 3431 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
3425 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3426 udelay(120); 3432 udelay(120);
3427 tw32_f(MAC_STATUS, 3433 tw32_f(MAC_STATUS,
3428 (MAC_STATUS_SYNC_CHANGED | 3434 (MAC_STATUS_SYNC_CHANGED |
@@ -3434,7 +3440,7 @@ relink:
3434 } 3440 }
3435 3441
3436 /* Prevent send BD corruption. */ 3442 /* Prevent send BD corruption. */
3437 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { 3443 if (tg3_flag(tp, CLKREQ_BUG)) {
3438 u16 oldlnkctl, newlnkctl; 3444 u16 oldlnkctl, newlnkctl;
3439 3445
3440 pci_read_config_word(tp->pdev, 3446 pci_read_config_word(tp->pdev,
@@ -3829,7 +3835,7 @@ static void tg3_init_bcm8002(struct tg3 *tp)
3829 int i; 3835 int i;
3830 3836
3831 /* Reset when initting first time or we have a link. */ 3837 /* Reset when initting first time or we have a link. */
3832 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && 3838 if (tg3_flag(tp, INIT_COMPLETE) &&
3833 !(mac_status & MAC_STATUS_PCS_SYNCED)) 3839 !(mac_status & MAC_STATUS_PCS_SYNCED))
3834 return; 3840 return;
3835 3841
@@ -4090,9 +4096,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4090 orig_active_speed = tp->link_config.active_speed; 4096 orig_active_speed = tp->link_config.active_speed;
4091 orig_active_duplex = tp->link_config.active_duplex; 4097 orig_active_duplex = tp->link_config.active_duplex;
4092 4098
4093 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && 4099 if (!tg3_flag(tp, HW_AUTONEG) &&
4094 netif_carrier_ok(tp->dev) && 4100 netif_carrier_ok(tp->dev) &&
4095 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { 4101 tg3_flag(tp, INIT_COMPLETE)) {
4096 mac_status = tr32(MAC_STATUS); 4102 mac_status = tr32(MAC_STATUS);
4097 mac_status &= (MAC_STATUS_PCS_SYNCED | 4103 mac_status &= (MAC_STATUS_PCS_SYNCED |
4098 MAC_STATUS_SIGNAL_DET | 4104 MAC_STATUS_SIGNAL_DET |
@@ -4123,7 +4129,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4123 current_link_up = 0; 4129 current_link_up = 0;
4124 mac_status = tr32(MAC_STATUS); 4130 mac_status = tr32(MAC_STATUS);
4125 4131
4126 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) 4132 if (tg3_flag(tp, HW_AUTONEG))
4127 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); 4133 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4128 else 4134 else
4129 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); 4135 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
@@ -4322,7 +4328,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4322 current_duplex = DUPLEX_FULL; 4328 current_duplex = DUPLEX_FULL;
4323 else 4329 else
4324 current_duplex = DUPLEX_HALF; 4330 current_duplex = DUPLEX_HALF;
4325 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 4331 } else if (!tg3_flag(tp, 5780_CLASS)) {
4326 /* Link is up via parallel detect */ 4332 /* Link is up via parallel detect */
4327 } else { 4333 } else {
4328 current_link_up = 0; 4334 current_link_up = 0;
@@ -4460,7 +4466,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4460 tw32(MAC_TX_LENGTHS, val | 4466 tw32(MAC_TX_LENGTHS, val |
4461 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); 4467 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4462 4468
4463 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 4469 if (!tg3_flag(tp, 5705_PLUS)) {
4464 if (netif_carrier_ok(tp->dev)) { 4470 if (netif_carrier_ok(tp->dev)) {
4465 tw32(HOSTCC_STAT_COAL_TICKS, 4471 tw32(HOSTCC_STAT_COAL_TICKS,
4466 tp->coal.stats_block_coalesce_usecs); 4472 tp->coal.stats_block_coalesce_usecs);
@@ -4469,7 +4475,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4469 } 4475 }
4470 } 4476 }
4471 4477
4472 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { 4478 if (tg3_flag(tp, ASPM_WORKAROUND)) {
4473 val = tr32(PCIE_PWR_MGMT_THRESH); 4479 val = tr32(PCIE_PWR_MGMT_THRESH);
4474 if (!netif_carrier_ok(tp->dev)) 4480 if (!netif_carrier_ok(tp->dev))
4475 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | 4481 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
@@ -4518,7 +4524,7 @@ static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4518 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); 4524 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4519 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); 4525 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4520 4526
4521 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) 4527 if (tg3_flag(tp, SUPPORT_MSIX))
4522 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); 4528 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4523 4529
4524 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); 4530 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
@@ -4530,7 +4536,7 @@ static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4530 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); 4536 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4531 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); 4537 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4532 4538
4533 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 4539 if (!tg3_flag(tp, 5705_PLUS)) {
4534 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); 4540 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4535 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); 4541 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4536 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); 4542 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
@@ -4542,7 +4548,7 @@ static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4542 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); 4548 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4543 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); 4549 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4544 4550
4545 if (tp->tg3_flags & TG3_FLAG_NVRAM) 4551 if (tg3_flag(tp, NVRAM))
4546 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); 4552 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4547} 4553}
4548 4554
@@ -4557,7 +4563,7 @@ static void tg3_dump_state(struct tg3 *tp)
4557 return; 4563 return;
4558 } 4564 }
4559 4565
4560 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 4566 if (tg3_flag(tp, PCI_EXPRESS)) {
4561 /* Read up to but not including private PCI registers */ 4567 /* Read up to but not including private PCI registers */
4562 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) 4568 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4563 regs[i / sizeof(u32)] = tr32(i); 4569 regs[i / sizeof(u32)] = tr32(i);
@@ -4612,7 +4618,7 @@ static void tg3_dump_state(struct tg3 *tp)
4612 */ 4618 */
4613static void tg3_tx_recover(struct tg3 *tp) 4619static void tg3_tx_recover(struct tg3 *tp)
4614{ 4620{
4615 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || 4621 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
4616 tp->write32_tx_mbox == tg3_write_indirect_mbox); 4622 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4617 4623
4618 netdev_warn(tp->dev, 4624 netdev_warn(tp->dev,
@@ -4622,7 +4628,7 @@ static void tg3_tx_recover(struct tg3 *tp)
4622 "and include system chipset information.\n"); 4628 "and include system chipset information.\n");
4623 4629
4624 spin_lock(&tp->lock); 4630 spin_lock(&tp->lock);
4625 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; 4631 tg3_flag_set(tp, TX_RECOVERY_PENDING);
4626 spin_unlock(&tp->lock); 4632 spin_unlock(&tp->lock);
4627} 4633}
4628 4634
@@ -4646,7 +4652,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
4646 struct netdev_queue *txq; 4652 struct netdev_queue *txq;
4647 int index = tnapi - tp->napi; 4653 int index = tnapi - tp->napi;
4648 4654
4649 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 4655 if (tg3_flag(tp, ENABLE_TSS))
4650 index--; 4656 index--;
4651 4657
4652 txq = netdev_get_tx_queue(tp->dev, index); 4658 txq = netdev_get_tx_queue(tp->dev, index);
@@ -5014,7 +5020,7 @@ next_pkt_nopost:
5014 tw32_rx_mbox(tnapi->consmbox, sw_idx); 5020 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5015 5021
5016 /* Refill RX ring(s). */ 5022 /* Refill RX ring(s). */
5017 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { 5023 if (!tg3_flag(tp, ENABLE_RSS)) {
5018 if (work_mask & RXD_OPAQUE_RING_STD) { 5024 if (work_mask & RXD_OPAQUE_RING_STD) {
5019 tpr->rx_std_prod_idx = std_prod_idx & 5025 tpr->rx_std_prod_idx = std_prod_idx &
5020 tp->rx_std_ring_mask; 5026 tp->rx_std_ring_mask;
@@ -5047,16 +5053,14 @@ next_pkt_nopost:
5047static void tg3_poll_link(struct tg3 *tp) 5053static void tg3_poll_link(struct tg3 *tp)
5048{ 5054{
5049 /* handle link change and other phy events */ 5055 /* handle link change and other phy events */
5050 if (!(tp->tg3_flags & 5056 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5051 (TG3_FLAG_USE_LINKCHG_REG |
5052 TG3_FLAG_POLL_SERDES))) {
5053 struct tg3_hw_status *sblk = tp->napi[0].hw_status; 5057 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5054 5058
5055 if (sblk->status & SD_STATUS_LINK_CHG) { 5059 if (sblk->status & SD_STATUS_LINK_CHG) {
5056 sblk->status = SD_STATUS_UPDATED | 5060 sblk->status = SD_STATUS_UPDATED |
5057 (sblk->status & ~SD_STATUS_LINK_CHG); 5061 (sblk->status & ~SD_STATUS_LINK_CHG);
5058 spin_lock(&tp->lock); 5062 spin_lock(&tp->lock);
5059 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 5063 if (tg3_flag(tp, USE_PHYLIB)) {
5060 tw32_f(MAC_STATUS, 5064 tw32_f(MAC_STATUS,
5061 (MAC_STATUS_SYNC_CHANGED | 5065 (MAC_STATUS_SYNC_CHANGED |
5062 MAC_STATUS_CFG_CHANGED | 5066 MAC_STATUS_CFG_CHANGED |
@@ -5203,7 +5207,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5203 /* run TX completion thread */ 5207 /* run TX completion thread */
5204 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { 5208 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5205 tg3_tx(tnapi); 5209 tg3_tx(tnapi);
5206 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) 5210 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5207 return work_done; 5211 return work_done;
5208 } 5212 }
5209 5213
@@ -5214,7 +5218,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5214 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) 5218 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5215 work_done += tg3_rx(tnapi, budget - work_done); 5219 work_done += tg3_rx(tnapi, budget - work_done);
5216 5220
5217 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { 5221 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5218 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; 5222 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5219 int i, err = 0; 5223 int i, err = 0;
5220 u32 std_prod_idx = dpr->rx_std_prod_idx; 5224 u32 std_prod_idx = dpr->rx_std_prod_idx;
@@ -5253,7 +5257,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
5253 while (1) { 5257 while (1) {
5254 work_done = tg3_poll_work(tnapi, work_done, budget); 5258 work_done = tg3_poll_work(tnapi, work_done, budget);
5255 5259
5256 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) 5260 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5257 goto tx_recovery; 5261 goto tx_recovery;
5258 5262
5259 if (unlikely(work_done >= budget)) 5263 if (unlikely(work_done >= budget))
@@ -5292,7 +5296,7 @@ static void tg3_process_error(struct tg3 *tp)
5292 u32 val; 5296 u32 val;
5293 bool real_error = false; 5297 bool real_error = false;
5294 5298
5295 if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED) 5299 if (tg3_flag(tp, ERROR_PROCESSED))
5296 return; 5300 return;
5297 5301
5298 /* Check Flow Attention register */ 5302 /* Check Flow Attention register */
@@ -5317,7 +5321,7 @@ static void tg3_process_error(struct tg3 *tp)
5317 5321
5318 tg3_dump_state(tp); 5322 tg3_dump_state(tp);
5319 5323
5320 tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED; 5324 tg3_flag_set(tp, ERROR_PROCESSED);
5321 schedule_work(&tp->reset_task); 5325 schedule_work(&tp->reset_task);
5322} 5326}
5323 5327
@@ -5336,13 +5340,13 @@ static int tg3_poll(struct napi_struct *napi, int budget)
5336 5340
5337 work_done = tg3_poll_work(tnapi, work_done, budget); 5341 work_done = tg3_poll_work(tnapi, work_done, budget);
5338 5342
5339 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) 5343 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5340 goto tx_recovery; 5344 goto tx_recovery;
5341 5345
5342 if (unlikely(work_done >= budget)) 5346 if (unlikely(work_done >= budget))
5343 break; 5347 break;
5344 5348
5345 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { 5349 if (tg3_flag(tp, TAGGED_STATUS)) {
5346 /* tp->last_tag is used in tg3_int_reenable() below 5350 /* tp->last_tag is used in tg3_int_reenable() below
5347 * to tell the hw how much work has been processed, 5351 * to tell the hw how much work has been processed,
5348 * so we must read it before checking for more work. 5352 * so we must read it before checking for more work.
@@ -5509,7 +5513,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5509 * interrupt is ours and will flush the status block. 5513 * interrupt is ours and will flush the status block.
5510 */ 5514 */
5511 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { 5515 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5512 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || 5516 if (tg3_flag(tp, CHIP_RESETTING) ||
5513 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { 5517 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5514 handled = 0; 5518 handled = 0;
5515 goto out; 5519 goto out;
@@ -5558,7 +5562,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5558 * interrupt is ours and will flush the status block. 5562 * interrupt is ours and will flush the status block.
5559 */ 5563 */
5560 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { 5564 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5561 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || 5565 if (tg3_flag(tp, CHIP_RESETTING) ||
5562 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { 5566 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5563 handled = 0; 5567 handled = 0;
5564 goto out; 5568 goto out;
@@ -5671,14 +5675,14 @@ static void tg3_reset_task(struct work_struct *work)
5671 5675
5672 tg3_full_lock(tp, 1); 5676 tg3_full_lock(tp, 1);
5673 5677
5674 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; 5678 restart_timer = tg3_flag(tp, RESTART_TIMER);
5675 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 5679 tg3_flag_clear(tp, RESTART_TIMER);
5676 5680
5677 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { 5681 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
5678 tp->write32_tx_mbox = tg3_write32_tx_mbox; 5682 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5679 tp->write32_rx_mbox = tg3_write_flush_reg32; 5683 tp->write32_rx_mbox = tg3_write_flush_reg32;
5680 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; 5684 tg3_flag_set(tp, MBOX_WRITE_REORDER);
5681 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; 5685 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
5682 } 5686 }
5683 5687
5684 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 5688 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
@@ -5723,7 +5727,7 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5723 int len) 5727 int len)
5724{ 5728{
5725#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) 5729#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5726 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) 5730 if (tg3_flag(tp, 40BIT_DMA_BUG))
5727 return ((u64) mapping + len) > DMA_BIT_MASK(40); 5731 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5728 return 0; 5732 return 0;
5729#else 5733#else
@@ -5770,8 +5774,8 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5770 /* Make sure new skb does not cross any 4G boundaries. 5774 /* Make sure new skb does not cross any 4G boundaries.
5771 * Drop the packet if it does. 5775 * Drop the packet if it does.
5772 */ 5776 */
5773 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && 5777 } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
5774 tg3_4g_overflow_test(new_addr, new_skb->len)) { 5778 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5775 pci_unmap_single(tp->pdev, new_addr, new_skb->len, 5779 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5776 PCI_DMA_TODEVICE); 5780 PCI_DMA_TODEVICE);
5777 ret = -1; 5781 ret = -1;
@@ -5838,7 +5842,7 @@ static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5838} 5842}
5839 5843
5840/* hard_start_xmit for devices that don't have any bugs and 5844/* hard_start_xmit for devices that don't have any bugs and
5841 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. 5845 * support TG3_FLAG_HW_TSO_2 and TG3_FLAG_HW_TSO_3 only.
5842 */ 5846 */
5843static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, 5847static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5844 struct net_device *dev) 5848 struct net_device *dev)
@@ -5852,7 +5856,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5852 5856
5853 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5857 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5854 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5858 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5855 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 5859 if (tg3_flag(tp, ENABLE_TSS))
5856 tnapi++; 5860 tnapi++;
5857 5861
5858 /* We are running in BH disabled context with netif_tx_lock 5862 /* We are running in BH disabled context with netif_tx_lock
@@ -5897,7 +5901,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5897 hdrlen = ip_tcp_len + tcp_opt_len; 5901 hdrlen = ip_tcp_len + tcp_opt_len;
5898 } 5902 }
5899 5903
5900 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { 5904 if (tg3_flag(tp, HW_TSO_3)) {
5901 mss |= (hdrlen & 0xc) << 12; 5905 mss |= (hdrlen & 0xc) << 12;
5902 if (hdrlen & 0x10) 5906 if (hdrlen & 0x10)
5903 base_flags |= 0x00000010; 5907 base_flags |= 0x00000010;
@@ -5930,7 +5934,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5930 tnapi->tx_buffers[entry].skb = skb; 5934 tnapi->tx_buffers[entry].skb = skb;
5931 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); 5935 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5932 5936
5933 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && 5937 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
5934 !mss && skb->len > VLAN_ETH_FRAME_LEN) 5938 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5935 base_flags |= TXD_FLAG_JMB_PKT; 5939 base_flags |= TXD_FLAG_JMB_PKT;
5936 5940
@@ -6053,7 +6057,7 @@ tg3_tso_bug_end:
6053} 6057}
6054 6058
6055/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and 6059/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6056 * support TG3_FLG2_HW_TSO_1 or firmware TSO only. 6060 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6057 */ 6061 */
6058static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, 6062static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6059 struct net_device *dev) 6063 struct net_device *dev)
@@ -6068,7 +6072,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6068 6072
6069 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 6073 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6070 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 6074 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6071 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 6075 if (tg3_flag(tp, ENABLE_TSS))
6072 tnapi++; 6076 tnapi++;
6073 6077
6074 /* We are running in BH disabled context with netif_tx_lock 6078 /* We are running in BH disabled context with netif_tx_lock
@@ -6119,13 +6123,15 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6119 } 6123 }
6120 6124
6121 if (unlikely((ETH_HLEN + hdr_len) > 80) && 6125 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6122 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) 6126 tg3_flag(tp, TSO_BUG))
6123 return tg3_tso_bug(tp, skb); 6127 return tg3_tso_bug(tp, skb);
6124 6128
6125 base_flags |= (TXD_FLAG_CPU_PRE_DMA | 6129 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6126 TXD_FLAG_CPU_POST_DMA); 6130 TXD_FLAG_CPU_POST_DMA);
6127 6131
6128 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { 6132 if (tg3_flag(tp, HW_TSO_1) ||
6133 tg3_flag(tp, HW_TSO_2) ||
6134 tg3_flag(tp, HW_TSO_3)) {
6129 tcp_hdr(skb)->check = 0; 6135 tcp_hdr(skb)->check = 0;
6130 base_flags &= ~TXD_FLAG_TCPUDP_CSUM; 6136 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6131 } else 6137 } else
@@ -6134,14 +6140,14 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6134 IPPROTO_TCP, 6140 IPPROTO_TCP,
6135 0); 6141 0);
6136 6142
6137 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { 6143 if (tg3_flag(tp, HW_TSO_3)) {
6138 mss |= (hdr_len & 0xc) << 12; 6144 mss |= (hdr_len & 0xc) << 12;
6139 if (hdr_len & 0x10) 6145 if (hdr_len & 0x10)
6140 base_flags |= 0x00000010; 6146 base_flags |= 0x00000010;
6141 base_flags |= (hdr_len & 0x3e0) << 5; 6147 base_flags |= (hdr_len & 0x3e0) << 5;
6142 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) 6148 } else if (tg3_flag(tp, HW_TSO_2))
6143 mss |= hdr_len << 9; 6149 mss |= hdr_len << 9;
6144 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || 6150 else if (tg3_flag(tp, HW_TSO_1) ||
6145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 6151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6146 if (tcp_opt_len || iph->ihl > 5) { 6152 if (tcp_opt_len || iph->ihl > 5) {
6147 int tsflags; 6153 int tsflags;
@@ -6163,7 +6169,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6163 base_flags |= (TXD_FLAG_VLAN | 6169 base_flags |= (TXD_FLAG_VLAN |
6164 (vlan_tx_tag_get(skb) << 16)); 6170 (vlan_tx_tag_get(skb) << 16));
6165 6171
6166 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && 6172 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6167 !mss && skb->len > VLAN_ETH_FRAME_LEN) 6173 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6168 base_flags |= TXD_FLAG_JMB_PKT; 6174 base_flags |= TXD_FLAG_JMB_PKT;
6169 6175
@@ -6180,18 +6186,18 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6180 6186
6181 would_hit_hwbug = 0; 6187 would_hit_hwbug = 0;
6182 6188
6183 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) 6189 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6184 would_hit_hwbug = 1; 6190 would_hit_hwbug = 1;
6185 6191
6186 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && 6192 if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6187 tg3_4g_overflow_test(mapping, len)) 6193 tg3_4g_overflow_test(mapping, len))
6188 would_hit_hwbug = 1; 6194 would_hit_hwbug = 1;
6189 6195
6190 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && 6196 if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6191 tg3_40bit_overflow_test(tp, mapping, len)) 6197 tg3_40bit_overflow_test(tp, mapping, len))
6192 would_hit_hwbug = 1; 6198 would_hit_hwbug = 1;
6193 6199
6194 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) 6200 if (tg3_flag(tp, 5701_DMA_BUG))
6195 would_hit_hwbug = 1; 6201 would_hit_hwbug = 1;
6196 6202
6197 tg3_set_txd(tnapi, entry, mapping, len, base_flags, 6203 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
@@ -6217,19 +6223,21 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6217 if (pci_dma_mapping_error(tp->pdev, mapping)) 6223 if (pci_dma_mapping_error(tp->pdev, mapping))
6218 goto dma_error; 6224 goto dma_error;
6219 6225
6220 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && 6226 if (tg3_flag(tp, SHORT_DMA_BUG) &&
6221 len <= 8) 6227 len <= 8)
6222 would_hit_hwbug = 1; 6228 would_hit_hwbug = 1;
6223 6229
6224 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && 6230 if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6225 tg3_4g_overflow_test(mapping, len)) 6231 tg3_4g_overflow_test(mapping, len))
6226 would_hit_hwbug = 1; 6232 would_hit_hwbug = 1;
6227 6233
6228 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && 6234 if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6229 tg3_40bit_overflow_test(tp, mapping, len)) 6235 tg3_40bit_overflow_test(tp, mapping, len))
6230 would_hit_hwbug = 1; 6236 would_hit_hwbug = 1;
6231 6237
6232 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 6238 if (tg3_flag(tp, HW_TSO_1) ||
6239 tg3_flag(tp, HW_TSO_2) ||
6240 tg3_flag(tp, HW_TSO_3))
6233 tg3_set_txd(tnapi, entry, mapping, len, 6241 tg3_set_txd(tnapi, entry, mapping, len,
6234 base_flags, (i == last)|(mss << 1)); 6242 base_flags, (i == last)|(mss << 1));
6235 else 6243 else
@@ -6305,7 +6313,7 @@ static u32 tg3_fix_features(struct net_device *dev, u32 features)
6305{ 6313{
6306 struct tg3 *tp = netdev_priv(dev); 6314 struct tg3 *tp = netdev_priv(dev);
6307 6315
6308 if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 6316 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6309 features &= ~NETIF_F_ALL_TSO; 6317 features &= ~NETIF_F_ALL_TSO;
6310 6318
6311 return features; 6319 return features;
@@ -6317,18 +6325,18 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6317 dev->mtu = new_mtu; 6325 dev->mtu = new_mtu;
6318 6326
6319 if (new_mtu > ETH_DATA_LEN) { 6327 if (new_mtu > ETH_DATA_LEN) {
6320 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 6328 if (tg3_flag(tp, 5780_CLASS)) {
6321 netdev_update_features(dev); 6329 netdev_update_features(dev);
6322 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 6330 tg3_flag_clear(tp, TSO_CAPABLE);
6323 } else { 6331 } else {
6324 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; 6332 tg3_flag_set(tp, JUMBO_RING_ENABLE);
6325 } 6333 }
6326 } else { 6334 } else {
6327 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 6335 if (tg3_flag(tp, 5780_CLASS)) {
6328 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 6336 tg3_flag_set(tp, TSO_CAPABLE);
6329 netdev_update_features(dev); 6337 netdev_update_features(dev);
6330 } 6338 }
6331 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; 6339 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
6332 } 6340 }
6333} 6341}
6334 6342
@@ -6382,7 +6390,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
6382 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], 6390 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6383 tp->rx_pkt_map_sz); 6391 tp->rx_pkt_map_sz);
6384 6392
6385 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { 6393 if (tg3_flag(tp, JUMBO_CAPABLE)) {
6386 for (i = tpr->rx_jmb_cons_idx; 6394 for (i = tpr->rx_jmb_cons_idx;
6387 i != tpr->rx_jmb_prod_idx; 6395 i != tpr->rx_jmb_prod_idx;
6388 i = (i + 1) & tp->rx_jmb_ring_mask) { 6396 i = (i + 1) & tp->rx_jmb_ring_mask) {
@@ -6398,8 +6406,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
6398 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], 6406 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6399 tp->rx_pkt_map_sz); 6407 tp->rx_pkt_map_sz);
6400 6408
6401 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && 6409 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6402 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6403 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) 6410 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6404 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], 6411 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6405 TG3_RX_JMB_MAP_SZ); 6412 TG3_RX_JMB_MAP_SZ);
@@ -6436,7 +6443,7 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6436 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); 6443 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6437 6444
6438 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; 6445 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6439 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && 6446 if (tg3_flag(tp, 5780_CLASS) &&
6440 tp->dev->mtu > ETH_DATA_LEN) 6447 tp->dev->mtu > ETH_DATA_LEN)
6441 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; 6448 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6442 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); 6449 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
@@ -6469,13 +6476,12 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6469 } 6476 }
6470 } 6477 }
6471 6478
6472 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || 6479 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
6473 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6474 goto done; 6480 goto done;
6475 6481
6476 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); 6482 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6477 6483
6478 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) 6484 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
6479 goto done; 6485 goto done;
6480 6486
6481 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { 6487 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
@@ -6544,8 +6550,7 @@ static int tg3_rx_prodring_init(struct tg3 *tp,
6544 if (!tpr->rx_std) 6550 if (!tpr->rx_std)
6545 goto err_out; 6551 goto err_out;
6546 6552
6547 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && 6553 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6548 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6549 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), 6554 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6550 GFP_KERNEL); 6555 GFP_KERNEL);
6551 if (!tpr->rx_jmb_buffers) 6556 if (!tpr->rx_jmb_buffers)
@@ -6743,8 +6748,8 @@ static int tg3_alloc_consistent(struct tg3 *tp)
6743 /* If multivector TSS is enabled, vector 0 does not handle 6748 /* If multivector TSS is enabled, vector 0 does not handle
6744 * tx interrupts. Don't allocate any resources for it. 6749 * tx interrupts. Don't allocate any resources for it.
6745 */ 6750 */
6746 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || 6751 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
6747 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { 6752 (i && tg3_flag(tp, ENABLE_TSS))) {
6748 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * 6753 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6749 TG3_TX_RING_SIZE, 6754 TG3_TX_RING_SIZE,
6750 GFP_KERNEL); 6755 GFP_KERNEL);
@@ -6784,7 +6789,7 @@ static int tg3_alloc_consistent(struct tg3 *tp)
6784 * If multivector RSS is enabled, vector 0 does not handle 6789 * If multivector RSS is enabled, vector 0 does not handle
6785 * rx or tx interrupts. Don't allocate any resources for it. 6790 * rx or tx interrupts. Don't allocate any resources for it.
6786 */ 6791 */
6787 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) 6792 if (!i && tg3_flag(tp, ENABLE_RSS))
6788 continue; 6793 continue;
6789 6794
6790 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, 6795 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
@@ -6814,7 +6819,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
6814 unsigned int i; 6819 unsigned int i;
6815 u32 val; 6820 u32 val;
6816 6821
6817 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 6822 if (tg3_flag(tp, 5705_PLUS)) {
6818 switch (ofs) { 6823 switch (ofs) {
6819 case RCVLSC_MODE: 6824 case RCVLSC_MODE:
6820 case DMAC_MODE: 6825 case DMAC_MODE:
@@ -6924,7 +6929,7 @@ static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6924 u32 apedata; 6929 u32 apedata;
6925 6930
6926 /* NCSI does not support APE events */ 6931 /* NCSI does not support APE events */
6927 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI) 6932 if (tg3_flag(tp, APE_HAS_NCSI))
6928 return; 6933 return;
6929 6934
6930 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); 6935 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
@@ -6963,7 +6968,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6963 u32 event; 6968 u32 event;
6964 u32 apedata; 6969 u32 apedata;
6965 6970
6966 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 6971 if (!tg3_flag(tp, ENABLE_APE))
6967 return; 6972 return;
6968 6973
6969 switch (kind) { 6974 switch (kind) {
@@ -6992,7 +6997,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6992 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); 6997 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6993 6998
6994 if (device_may_wakeup(&tp->pdev->dev) && 6999 if (device_may_wakeup(&tp->pdev->dev) &&
6995 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) { 7000 tg3_flag(tp, WOL_ENABLE)) {
6996 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, 7001 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6997 TG3_APE_HOST_WOL_SPEED_AUTO); 7002 TG3_APE_HOST_WOL_SPEED_AUTO);
6998 apedata = TG3_APE_HOST_DRVR_STATE_WOL; 7003 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
@@ -7021,7 +7026,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
7021 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, 7026 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
7022 NIC_SRAM_FIRMWARE_MBOX_MAGIC1); 7027 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
7023 7028
7024 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { 7029 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
7025 switch (kind) { 7030 switch (kind) {
7026 case RESET_KIND_INIT: 7031 case RESET_KIND_INIT:
7027 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, 7032 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -7051,7 +7056,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
7051/* tp->lock is held. */ 7056/* tp->lock is held. */
7052static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) 7057static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7053{ 7058{
7054 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { 7059 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
7055 switch (kind) { 7060 switch (kind) {
7056 case RESET_KIND_INIT: 7061 case RESET_KIND_INIT:
7057 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, 7062 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -7075,7 +7080,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7075/* tp->lock is held. */ 7080/* tp->lock is held. */
7076static void tg3_write_sig_legacy(struct tg3 *tp, int kind) 7081static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7077{ 7082{
7078 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 7083 if (tg3_flag(tp, ENABLE_ASF)) {
7079 switch (kind) { 7084 switch (kind) {
7080 case RESET_KIND_INIT: 7085 case RESET_KIND_INIT:
7081 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, 7086 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -7126,9 +7131,8 @@ static int tg3_poll_fw(struct tg3 *tp)
7126 * of the above loop as an error, but do report the lack of 7131 * of the above loop as an error, but do report the lack of
7127 * running firmware once. 7132 * running firmware once.
7128 */ 7133 */
7129 if (i >= 100000 && 7134 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
7130 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { 7135 tg3_flag_set(tp, NO_FWARE_REPORTED);
7131 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
7132 7136
7133 netdev_info(tp->dev, "No firmware running\n"); 7137 netdev_info(tp->dev, "No firmware running\n");
7134 } 7138 }
@@ -7161,10 +7165,10 @@ static void tg3_restore_pci_state(struct tg3 *tp)
7161 /* Set MAX PCI retry to zero. */ 7165 /* Set MAX PCI retry to zero. */
7162 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); 7166 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7163 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && 7167 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7164 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) 7168 tg3_flag(tp, PCIX_MODE))
7165 val |= PCISTATE_RETRY_SAME_DMA; 7169 val |= PCISTATE_RETRY_SAME_DMA;
7166 /* Allow reads and writes to the APE register and memory space. */ 7170 /* Allow reads and writes to the APE register and memory space. */
7167 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 7171 if (tg3_flag(tp, ENABLE_APE))
7168 val |= PCISTATE_ALLOW_APE_CTLSPC_WR | 7172 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7169 PCISTATE_ALLOW_APE_SHMEM_WR | 7173 PCISTATE_ALLOW_APE_SHMEM_WR |
7170 PCISTATE_ALLOW_APE_PSPACE_WR; 7174 PCISTATE_ALLOW_APE_PSPACE_WR;
@@ -7173,7 +7177,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
7173 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); 7177 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7174 7178
7175 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { 7179 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7176 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) 7180 if (tg3_flag(tp, PCI_EXPRESS))
7177 pcie_set_readrq(tp->pdev, tp->pcie_readrq); 7181 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7178 else { 7182 else {
7179 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, 7183 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
@@ -7184,7 +7188,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
7184 } 7188 }
7185 7189
7186 /* Make sure PCI-X relaxed ordering bit is clear. */ 7190 /* Make sure PCI-X relaxed ordering bit is clear. */
7187 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { 7191 if (tg3_flag(tp, PCIX_MODE)) {
7188 u16 pcix_cmd; 7192 u16 pcix_cmd;
7189 7193
7190 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, 7194 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
@@ -7194,12 +7198,12 @@ static void tg3_restore_pci_state(struct tg3 *tp)
7194 pcix_cmd); 7198 pcix_cmd);
7195 } 7199 }
7196 7200
7197 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 7201 if (tg3_flag(tp, 5780_CLASS)) {
7198 7202
7199 /* Chip reset on 5780 will reset MSI enable bit, 7203 /* Chip reset on 5780 will reset MSI enable bit,
7200 * so need to restore it. 7204 * so need to restore it.
7201 */ 7205 */
7202 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 7206 if (tg3_flag(tp, USING_MSI)) {
7203 u16 ctrl; 7207 u16 ctrl;
7204 7208
7205 pci_read_config_word(tp->pdev, 7209 pci_read_config_word(tp->pdev,
@@ -7239,7 +7243,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7239 tg3_save_pci_state(tp); 7243 tg3_save_pci_state(tp);
7240 7244
7241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || 7245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7242 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) 7246 tg3_flag(tp, 5755_PLUS))
7243 tw32(GRC_FASTBOOT_PC, 0); 7247 tw32(GRC_FASTBOOT_PC, 0);
7244 7248
7245 /* 7249 /*
@@ -7258,7 +7262,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7258 * at this time, but the irq handler may still be called due to irq 7262 * at this time, but the irq handler may still be called due to irq
7259 * sharing or irqpoll. 7263 * sharing or irqpoll.
7260 */ 7264 */
7261 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; 7265 tg3_flag_set(tp, CHIP_RESETTING);
7262 for (i = 0; i < tp->irq_cnt; i++) { 7266 for (i = 0; i < tp->irq_cnt; i++) {
7263 struct tg3_napi *tnapi = &tp->napi[i]; 7267 struct tg3_napi *tnapi = &tp->napi[i];
7264 if (tnapi->hw_status) { 7268 if (tnapi->hw_status) {
@@ -7281,10 +7285,10 @@ static int tg3_chip_reset(struct tg3 *tp)
7281 /* do the reset */ 7285 /* do the reset */
7282 val = GRC_MISC_CFG_CORECLK_RESET; 7286 val = GRC_MISC_CFG_CORECLK_RESET;
7283 7287
7284 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 7288 if (tg3_flag(tp, PCI_EXPRESS)) {
7285 /* Force PCIe 1.0a mode */ 7289 /* Force PCIe 1.0a mode */
7286 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && 7290 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7287 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && 7291 !tg3_flag(tp, 57765_PLUS) &&
7288 tr32(TG3_PCIE_PHY_TSTCTL) == 7292 tr32(TG3_PCIE_PHY_TSTCTL) ==
7289 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) 7293 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7290 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); 7294 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
@@ -7302,8 +7306,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7302 } 7306 }
7303 7307
7304 /* Manage gphy power for all CPMU absent PCIe devices. */ 7308 /* Manage gphy power for all CPMU absent PCIe devices. */
7305 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 7309 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7306 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7307 val |= GRC_MISC_CFG_KEEP_GPHY_POWER; 7310 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7308 7311
7309 tw32(GRC_MISC_CFG, val); 7312 tw32(GRC_MISC_CFG, val);
@@ -7336,7 +7339,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7336 7339
7337 udelay(120); 7340 udelay(120);
7338 7341
7339 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { 7342 if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
7340 u16 val16; 7343 u16 val16;
7341 7344
7342 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { 7345 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
@@ -7362,7 +7365,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7362 * Older PCIe devices only support the 128 byte 7365 * Older PCIe devices only support the 128 byte
7363 * MPS setting. Enforce the restriction. 7366 * MPS setting. Enforce the restriction.
7364 */ 7367 */
7365 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) 7368 if (!tg3_flag(tp, CPMU_PRESENT))
7366 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; 7369 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7367 pci_write_config_word(tp->pdev, 7370 pci_write_config_word(tp->pdev,
7368 tp->pcie_cap + PCI_EXP_DEVCTL, 7371 tp->pcie_cap + PCI_EXP_DEVCTL,
@@ -7381,11 +7384,11 @@ static int tg3_chip_reset(struct tg3 *tp)
7381 7384
7382 tg3_restore_pci_state(tp); 7385 tg3_restore_pci_state(tp);
7383 7386
7384 tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING | 7387 tg3_flag_clear(tp, CHIP_RESETTING);
7385 TG3_FLAG_ERROR_PROCESSED); 7388 tg3_flag_clear(tp, ERROR_PROCESSED);
7386 7389
7387 val = 0; 7390 val = 0;
7388 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 7391 if (tg3_flag(tp, 5780_CLASS))
7389 val = tr32(MEMARB_MODE); 7392 val = tr32(MEMARB_MODE);
7390 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); 7393 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7391 7394
@@ -7410,7 +7413,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7410 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); 7413 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7411 } 7414 }
7412 7415
7413 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 7416 if (tg3_flag(tp, ENABLE_APE))
7414 tp->mac_mode = MAC_MODE_APE_TX_EN | 7417 tp->mac_mode = MAC_MODE_APE_TX_EN |
7415 MAC_MODE_APE_RX_EN | 7418 MAC_MODE_APE_RX_EN |
7416 MAC_MODE_TDE_ENABLE; 7419 MAC_MODE_TDE_ENABLE;
@@ -7435,10 +7438,10 @@ static int tg3_chip_reset(struct tg3 *tp)
7435 7438
7436 tg3_mdio_start(tp); 7439 tg3_mdio_start(tp);
7437 7440
7438 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 7441 if (tg3_flag(tp, PCI_EXPRESS) &&
7439 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && 7442 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7440 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && 7443 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7441 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { 7444 !tg3_flag(tp, 57765_PLUS)) {
7442 val = tr32(0x7c00); 7445 val = tr32(0x7c00);
7443 7446
7444 tw32(0x7c00, val | (1 << 25)); 7447 tw32(0x7c00, val | (1 << 25));
@@ -7450,18 +7453,18 @@ static int tg3_chip_reset(struct tg3 *tp)
7450 } 7453 }
7451 7454
7452 /* Reprobe ASF enable state. */ 7455 /* Reprobe ASF enable state. */
7453 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; 7456 tg3_flag_clear(tp, ENABLE_ASF);
7454 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; 7457 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7455 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 7458 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7456 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 7459 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7457 u32 nic_cfg; 7460 u32 nic_cfg;
7458 7461
7459 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 7462 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7460 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 7463 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7461 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 7464 tg3_flag_set(tp, ENABLE_ASF);
7462 tp->last_event_jiffies = jiffies; 7465 tp->last_event_jiffies = jiffies;
7463 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 7466 if (tg3_flag(tp, 5750_PLUS))
7464 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 7467 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7465 } 7468 }
7466 } 7469 }
7467 7470
@@ -7471,8 +7474,7 @@ static int tg3_chip_reset(struct tg3 *tp)
7471/* tp->lock is held. */ 7474/* tp->lock is held. */
7472static void tg3_stop_fw(struct tg3 *tp) 7475static void tg3_stop_fw(struct tg3 *tp)
7473{ 7476{
7474 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && 7477 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7475 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7476 /* Wait for RX cpu to ACK the previous event. */ 7478 /* Wait for RX cpu to ACK the previous event. */
7477 tg3_wait_for_event_ack(tp); 7479 tg3_wait_for_event_ack(tp);
7478 7480
@@ -7518,8 +7520,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7518{ 7520{
7519 int i; 7521 int i;
7520 7522
7521 BUG_ON(offset == TX_CPU_BASE && 7523 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
7522 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7523 7524
7524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 7525 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7525 u32 val = tr32(GRC_VCPU_EXT_CTRL); 7526 u32 val = tr32(GRC_VCPU_EXT_CTRL);
@@ -7554,7 +7555,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7554 } 7555 }
7555 7556
7556 /* Clear firmware's nvram arbitration. */ 7557 /* Clear firmware's nvram arbitration. */
7557 if (tp->tg3_flags & TG3_FLAG_NVRAM) 7558 if (tg3_flag(tp, NVRAM))
7558 tw32(NVRAM_SWARB, SWARB_REQ_CLR0); 7559 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7559 return 0; 7560 return 0;
7560} 7561}
@@ -7572,15 +7573,14 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
7572 int err, lock_err, i; 7573 int err, lock_err, i;
7573 void (*write_op)(struct tg3 *, u32, u32); 7574 void (*write_op)(struct tg3 *, u32, u32);
7574 7575
7575 if (cpu_base == TX_CPU_BASE && 7576 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
7576 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7577 netdev_err(tp->dev, 7577 netdev_err(tp->dev,
7578 "%s: Trying to load TX cpu firmware which is 5705\n", 7578 "%s: Trying to load TX cpu firmware which is 5705\n",
7579 __func__); 7579 __func__);
7580 return -EINVAL; 7580 return -EINVAL;
7581 } 7581 }
7582 7582
7583 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 7583 if (tg3_flag(tp, 5705_PLUS))
7584 write_op = tg3_write_mem; 7584 write_op = tg3_write_mem;
7585 else 7585 else
7586 write_op = tg3_write_indirect_reg32; 7586 write_op = tg3_write_indirect_reg32;
@@ -7674,7 +7674,9 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
7674 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; 7674 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7675 int err, i; 7675 int err, i;
7676 7676
7677 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 7677 if (tg3_flag(tp, HW_TSO_1) ||
7678 tg3_flag(tp, HW_TSO_2) ||
7679 tg3_flag(tp, HW_TSO_3))
7678 return 0; 7680 return 0;
7679 7681
7680 fw_data = (void *)tp->fw->data; 7682 fw_data = (void *)tp->fw->data;
@@ -7743,7 +7745,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
7743 if (!netif_running(dev)) 7745 if (!netif_running(dev))
7744 return 0; 7746 return 0;
7745 7747
7746 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 7748 if (tg3_flag(tp, ENABLE_ASF)) {
7747 u32 addr0_high, addr0_low, addr1_high, addr1_low; 7749 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7748 7750
7749 addr0_high = tr32(MAC_ADDR_0_HIGH); 7751 addr0_high = tr32(MAC_ADDR_0_HIGH);
@@ -7778,7 +7780,7 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7778 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), 7780 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7779 maxlen_flags); 7781 maxlen_flags);
7780 7782
7781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 7783 if (!tg3_flag(tp, 5705_PLUS))
7782 tg3_write_mem(tp, 7784 tg3_write_mem(tp,
7783 (bdinfo_addr + TG3_BDINFO_NIC_ADDR), 7785 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7784 nic_addr); 7786 nic_addr);
@@ -7789,7 +7791,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7789{ 7791{
7790 int i; 7792 int i;
7791 7793
7792 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { 7794 if (!tg3_flag(tp, ENABLE_TSS)) {
7793 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); 7795 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7794 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); 7796 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7795 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); 7797 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
@@ -7799,7 +7801,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7799 tw32(HOSTCC_TXCOAL_MAXF_INT, 0); 7801 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7800 } 7802 }
7801 7803
7802 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { 7804 if (!tg3_flag(tp, ENABLE_RSS)) {
7803 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); 7805 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7804 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); 7806 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7805 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); 7807 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
@@ -7809,7 +7811,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7809 tw32(HOSTCC_RXCOAL_MAXF_INT, 0); 7811 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7810 } 7812 }
7811 7813
7812 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7814 if (!tg3_flag(tp, 5705_PLUS)) {
7813 u32 val = ec->stats_block_coalesce_usecs; 7815 u32 val = ec->stats_block_coalesce_usecs;
7814 7816
7815 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); 7817 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
@@ -7831,7 +7833,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7831 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; 7833 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7832 tw32(reg, ec->rx_max_coalesced_frames_irq); 7834 tw32(reg, ec->rx_max_coalesced_frames_irq);
7833 7835
7834 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { 7836 if (tg3_flag(tp, ENABLE_TSS)) {
7835 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; 7837 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7836 tw32(reg, ec->tx_coalesce_usecs); 7838 tw32(reg, ec->tx_coalesce_usecs);
7837 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; 7839 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
@@ -7846,7 +7848,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7846 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); 7848 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7847 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 7849 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7848 7850
7849 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { 7851 if (tg3_flag(tp, ENABLE_TSS)) {
7850 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); 7852 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7851 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); 7853 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7852 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); 7854 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
@@ -7862,9 +7864,9 @@ static void tg3_rings_reset(struct tg3 *tp)
7862 struct tg3_napi *tnapi = &tp->napi[0]; 7864 struct tg3_napi *tnapi = &tp->napi[0];
7863 7865
7864 /* Disable all transmit rings but the first. */ 7866 /* Disable all transmit rings but the first. */
7865 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 7867 if (!tg3_flag(tp, 5705_PLUS))
7866 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; 7868 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7867 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) 7869 else if (tg3_flag(tp, 5717_PLUS))
7868 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; 7870 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7869 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 7871 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7870 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; 7872 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
@@ -7878,9 +7880,9 @@ static void tg3_rings_reset(struct tg3 *tp)
7878 7880
7879 7881
7880 /* Disable all receive return rings but the first. */ 7882 /* Disable all receive return rings but the first. */
7881 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) 7883 if (tg3_flag(tp, 5717_PLUS))
7882 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; 7884 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7883 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 7885 else if (!tg3_flag(tp, 5705_PLUS))
7884 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; 7886 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7885 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 7887 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 7888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
@@ -7897,16 +7899,16 @@ static void tg3_rings_reset(struct tg3 *tp)
7897 tw32_mailbox_f(tp->napi[0].int_mbox, 1); 7899 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7898 7900
7899 /* Zero mailbox registers. */ 7901 /* Zero mailbox registers. */
7900 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { 7902 if (tg3_flag(tp, SUPPORT_MSIX)) {
7901 for (i = 1; i < tp->irq_max; i++) { 7903 for (i = 1; i < tp->irq_max; i++) {
7902 tp->napi[i].tx_prod = 0; 7904 tp->napi[i].tx_prod = 0;
7903 tp->napi[i].tx_cons = 0; 7905 tp->napi[i].tx_cons = 0;
7904 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 7906 if (tg3_flag(tp, ENABLE_TSS))
7905 tw32_mailbox(tp->napi[i].prodmbox, 0); 7907 tw32_mailbox(tp->napi[i].prodmbox, 0);
7906 tw32_rx_mbox(tp->napi[i].consmbox, 0); 7908 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7907 tw32_mailbox_f(tp->napi[i].int_mbox, 1); 7909 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7908 } 7910 }
7909 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) 7911 if (!tg3_flag(tp, ENABLE_TSS))
7910 tw32_mailbox(tp->napi[0].prodmbox, 0); 7912 tw32_mailbox(tp->napi[0].prodmbox, 0);
7911 } else { 7913 } else {
7912 tp->napi[0].tx_prod = 0; 7914 tp->napi[0].tx_prod = 0;
@@ -7916,7 +7918,7 @@ static void tg3_rings_reset(struct tg3 *tp)
7916 } 7918 }
7917 7919
7918 /* Make sure the NIC-based send BD rings are disabled. */ 7920 /* Make sure the NIC-based send BD rings are disabled. */
7919 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7921 if (!tg3_flag(tp, 5705_PLUS)) {
7920 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; 7922 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7921 for (i = 0; i < 16; i++) 7923 for (i = 0; i < 16; i++)
7922 tw32_tx_mbox(mbox + i * 8, 0); 7924 tw32_tx_mbox(mbox + i * 8, 0);
@@ -7980,8 +7982,8 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7980{ 7982{
7981 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; 7983 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
7982 7984
7983 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS) || 7985 if (!tg3_flag(tp, 5750_PLUS) ||
7984 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 7986 tg3_flag(tp, 5780_CLASS) ||
7985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 7988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7987 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; 7989 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
@@ -7997,14 +7999,13 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7997 val = min(nic_rep_thresh, host_rep_thresh); 7999 val = min(nic_rep_thresh, host_rep_thresh);
7998 tw32(RCVBDI_STD_THRESH, val); 8000 tw32(RCVBDI_STD_THRESH, val);
7999 8001
8000 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) 8002 if (tg3_flag(tp, 57765_PLUS))
8001 tw32(STD_REPLENISH_LWM, bdcache_maxcnt); 8003 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8002 8004
8003 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) || 8005 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8004 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8005 return; 8006 return;
8006 8007
8007 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 8008 if (!tg3_flag(tp, 5705_PLUS))
8008 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; 8009 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8009 else 8010 else
8010 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717; 8011 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
@@ -8014,7 +8015,7 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8014 val = min(bdcache_maxcnt / 2, host_rep_thresh); 8015 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8015 tw32(RCVBDI_JUMBO_THRESH, val); 8016 tw32(RCVBDI_JUMBO_THRESH, val);
8016 8017
8017 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) 8018 if (tg3_flag(tp, 57765_PLUS))
8018 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); 8019 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8019} 8020}
8020 8021
@@ -8031,7 +8032,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8031 8032
8032 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); 8033 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8033 8034
8034 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) 8035 if (tg3_flag(tp, INIT_COMPLETE))
8035 tg3_abort_hw(tp, 1); 8036 tg3_abort_hw(tp, 1);
8036 8037
8037 /* Enable MAC control of LPI */ 8038 /* Enable MAC control of LPI */
@@ -8051,7 +8052,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8051 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) 8052 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8052 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; 8053 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8053 8054
8054 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 8055 if (tg3_flag(tp, ENABLE_APE))
8055 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; 8056 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8056 8057
8057 tw32_f(TG3_CPMU_EEE_MODE, val); 8058 tw32_f(TG3_CPMU_EEE_MODE, val);
@@ -8110,7 +8111,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8110 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); 8111 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8111 } 8112 }
8112 8113
8113 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { 8114 if (tg3_flag(tp, L1PLLPD_EN)) {
8114 u32 grc_mode = tr32(GRC_MODE); 8115 u32 grc_mode = tr32(GRC_MODE);
8115 8116
8116 /* Access the lower 1K of PL PCIE block registers. */ 8117 /* Access the lower 1K of PL PCIE block registers. */
@@ -8151,20 +8152,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8151 * other revision. But do not set this on PCI Express 8152 * other revision. But do not set this on PCI Express
8152 * chips and don't even touch the clocks if the CPMU is present. 8153 * chips and don't even touch the clocks if the CPMU is present.
8153 */ 8154 */
8154 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { 8155 if (!tg3_flag(tp, CPMU_PRESENT)) {
8155 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) 8156 if (!tg3_flag(tp, PCI_EXPRESS))
8156 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; 8157 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8157 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); 8158 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8158 } 8159 }
8159 8160
8160 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && 8161 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8161 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { 8162 tg3_flag(tp, PCIX_MODE)) {
8162 val = tr32(TG3PCI_PCISTATE); 8163 val = tr32(TG3PCI_PCISTATE);
8163 val |= PCISTATE_RETRY_SAME_DMA; 8164 val |= PCISTATE_RETRY_SAME_DMA;
8164 tw32(TG3PCI_PCISTATE, val); 8165 tw32(TG3PCI_PCISTATE, val);
8165 } 8166 }
8166 8167
8167 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 8168 if (tg3_flag(tp, ENABLE_APE)) {
8168 /* Allow reads and writes to the 8169 /* Allow reads and writes to the
8169 * APE register and memory space. 8170 * APE register and memory space.
8170 */ 8171 */
@@ -8191,7 +8192,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8191 if (err) 8192 if (err)
8192 return err; 8193 return err;
8193 8194
8194 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { 8195 if (tg3_flag(tp, 57765_PLUS)) {
8195 val = tr32(TG3PCI_DMA_RW_CTRL) & 8196 val = tr32(TG3PCI_DMA_RW_CTRL) &
8196 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; 8197 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8197 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) 8198 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
@@ -8233,7 +8234,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8233 tw32(GRC_MISC_CFG, val); 8234 tw32(GRC_MISC_CFG, val);
8234 8235
8235 /* Initialize MBUF/DESC pool. */ 8236 /* Initialize MBUF/DESC pool. */
8236 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 8237 if (tg3_flag(tp, 5750_PLUS)) {
8237 /* Do nothing. */ 8238 /* Do nothing. */
8238 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 8239 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8239 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); 8240 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -8243,7 +8244,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8243 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); 8244 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8244 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); 8245 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8245 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); 8246 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8246 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { 8247 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8247 int fw_len; 8248 int fw_len;
8248 8249
8249 fw_len = tp->fw_len; 8250 fw_len = tp->fw_len;
@@ -8318,12 +8319,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8318 ((u64) tpr->rx_std_mapping >> 32)); 8319 ((u64) tpr->rx_std_mapping >> 32));
8319 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 8320 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8320 ((u64) tpr->rx_std_mapping & 0xffffffff)); 8321 ((u64) tpr->rx_std_mapping & 0xffffffff));
8321 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) 8322 if (!tg3_flag(tp, 5717_PLUS))
8322 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, 8323 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8323 NIC_SRAM_RX_BUFFER_DESC); 8324 NIC_SRAM_RX_BUFFER_DESC);
8324 8325
8325 /* Disable the mini ring */ 8326 /* Disable the mini ring */
8326 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 8327 if (!tg3_flag(tp, 5705_PLUS))
8327 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, 8328 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8328 BDINFO_FLAGS_DISABLED); 8329 BDINFO_FLAGS_DISABLED);
8329 8330
@@ -8331,10 +8332,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8331 * blocks on those devices that have them. 8332 * blocks on those devices that have them.
8332 */ 8333 */
8333 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 8334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8334 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && 8335 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8335 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8336 8336
8337 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { 8337 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8338 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 8338 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8339 ((u64) tpr->rx_jmb_mapping >> 32)); 8339 ((u64) tpr->rx_jmb_mapping >> 32));
8340 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 8340 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -8343,7 +8343,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8343 BDINFO_FLAGS_MAXLEN_SHIFT; 8343 BDINFO_FLAGS_MAXLEN_SHIFT;
8344 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, 8344 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8345 val | BDINFO_FLAGS_USE_EXT_RECV); 8345 val | BDINFO_FLAGS_USE_EXT_RECV);
8346 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) || 8346 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 8347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8348 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, 8348 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8349 NIC_SRAM_RX_JUMBO_BUFFER_DESC); 8349 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
@@ -8352,7 +8352,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8352 BDINFO_FLAGS_DISABLED); 8352 BDINFO_FLAGS_DISABLED);
8353 } 8353 }
8354 8354
8355 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { 8355 if (tg3_flag(tp, 57765_PLUS)) {
8356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 8356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8357 val = TG3_RX_STD_MAX_SIZE_5700; 8357 val = TG3_RX_STD_MAX_SIZE_5700;
8358 else 8358 else
@@ -8369,8 +8369,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8369 tpr->rx_std_prod_idx = tp->rx_pending; 8369 tpr->rx_std_prod_idx = tp->rx_pending;
8370 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); 8370 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8371 8371
8372 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? 8372 tpr->rx_jmb_prod_idx =
8373 tp->rx_jumbo_pending : 0; 8373 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8374 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); 8374 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8375 8375
8376 tg3_rings_reset(tp); 8376 tg3_rings_reset(tp);
@@ -8421,22 +8421,24 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8421 8421
8422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 8422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8423 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { 8423 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8424 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && 8424 if (tg3_flag(tp, TSO_CAPABLE) &&
8425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 8425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8426 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; 8426 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8427 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && 8427 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8428 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { 8428 !tg3_flag(tp, IS_5788)) {
8429 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; 8429 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8430 } 8430 }
8431 } 8431 }
8432 8432
8433 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) 8433 if (tg3_flag(tp, PCI_EXPRESS))
8434 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; 8434 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8435 8435
8436 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 8436 if (tg3_flag(tp, HW_TSO_1) ||
8437 tg3_flag(tp, HW_TSO_2) ||
8438 tg3_flag(tp, HW_TSO_3))
8437 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; 8439 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8438 8440
8439 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || 8441 if (tg3_flag(tp, HW_TSO_3) ||
8440 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 8442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) 8443 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8442 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; 8444 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
@@ -8448,7 +8450,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8448 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 8450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 8451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 8452 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8451 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { 8453 tg3_flag(tp, 57765_PLUS)) {
8452 val = tr32(TG3_RDMA_RSRVCTRL_REG); 8454 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 8455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { 8456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
@@ -8472,12 +8474,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8472 } 8474 }
8473 8475
8474 /* Receive/send statistics. */ 8476 /* Receive/send statistics. */
8475 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 8477 if (tg3_flag(tp, 5750_PLUS)) {
8476 val = tr32(RCVLPC_STATS_ENABLE); 8478 val = tr32(RCVLPC_STATS_ENABLE);
8477 val &= ~RCVLPC_STATSENAB_DACK_FIX; 8479 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8478 tw32(RCVLPC_STATS_ENABLE, val); 8480 tw32(RCVLPC_STATS_ENABLE, val);
8479 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && 8481 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8480 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { 8482 tg3_flag(tp, TSO_CAPABLE)) {
8481 val = tr32(RCVLPC_STATS_ENABLE); 8483 val = tr32(RCVLPC_STATS_ENABLE);
8482 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; 8484 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8483 tw32(RCVLPC_STATS_ENABLE, val); 8485 tw32(RCVLPC_STATS_ENABLE, val);
@@ -8500,7 +8502,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8500 8502
8501 __tg3_set_coalesce(tp, &tp->coal); 8503 __tg3_set_coalesce(tp, &tp->coal);
8502 8504
8503 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 8505 if (!tg3_flag(tp, 5705_PLUS)) {
8504 /* Status/statistics block address. See tg3_timer, 8506 /* Status/statistics block address. See tg3_timer,
8505 * the tg3_periodic_fetch_stats call there, and 8507 * the tg3_periodic_fetch_stats call there, and
8506 * tg3_get_stats to see how this works for 5705/5750 chips. 8508 * tg3_get_stats to see how this works for 5705/5750 chips.
@@ -8526,7 +8528,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8526 8528
8527 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); 8529 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8528 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); 8530 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8529 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 8531 if (!tg3_flag(tp, 5705_PLUS))
8530 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); 8532 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8531 8533
8532 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { 8534 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
@@ -8536,13 +8538,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8536 udelay(10); 8538 udelay(10);
8537 } 8539 }
8538 8540
8539 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 8541 if (tg3_flag(tp, ENABLE_APE))
8540 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; 8542 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8541 else 8543 else
8542 tp->mac_mode = 0; 8544 tp->mac_mode = 0;
8543 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 8545 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8544 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 8546 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 8547 if (!tg3_flag(tp, 5705_PLUS) &&
8546 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && 8548 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8547 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) 8549 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8548 tp->mac_mode |= MAC_MODE_LINK_POLARITY; 8550 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
@@ -8550,12 +8552,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8550 udelay(40); 8552 udelay(40);
8551 8553
8552 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). 8554 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8553 * If TG3_FLG2_IS_NIC is zero, we should read the 8555 * If TG3_FLAG_IS_NIC is zero, we should read the
8554 * register to preserve the GPIO settings for LOMs. The GPIOs, 8556 * register to preserve the GPIO settings for LOMs. The GPIOs,
8555 * whether used as inputs or outputs, are set by boot code after 8557 * whether used as inputs or outputs, are set by boot code after
8556 * reset. 8558 * reset.
8557 */ 8559 */
8558 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { 8560 if (!tg3_flag(tp, IS_NIC)) {
8559 u32 gpio_mask; 8561 u32 gpio_mask;
8560 8562
8561 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | 8563 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
@@ -8573,21 +8575,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8573 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; 8575 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8574 8576
8575 /* GPIO1 must be driven high for eeprom write protect */ 8577 /* GPIO1 must be driven high for eeprom write protect */
8576 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) 8578 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8577 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | 8579 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8578 GRC_LCLCTRL_GPIO_OUTPUT1); 8580 GRC_LCLCTRL_GPIO_OUTPUT1);
8579 } 8581 }
8580 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 8582 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8581 udelay(100); 8583 udelay(100);
8582 8584
8583 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && 8585 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8584 tp->irq_cnt > 1) {
8585 val = tr32(MSGINT_MODE); 8586 val = tr32(MSGINT_MODE);
8586 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; 8587 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8587 tw32(MSGINT_MODE, val); 8588 tw32(MSGINT_MODE, val);
8588 } 8589 }
8589 8590
8590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 8591 if (!tg3_flag(tp, 5705_PLUS)) {
8591 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); 8592 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8592 udelay(40); 8593 udelay(40);
8593 } 8594 }
@@ -8600,18 +8601,18 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8600 8601
8601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 8602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8602 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { 8603 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8603 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && 8604 if (tg3_flag(tp, TSO_CAPABLE) &&
8604 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || 8605 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8605 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { 8606 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8606 /* nothing */ 8607 /* nothing */
8607 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && 8608 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8608 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { 8609 !tg3_flag(tp, IS_5788)) {
8609 val |= WDMAC_MODE_RX_ACCEL; 8610 val |= WDMAC_MODE_RX_ACCEL;
8610 } 8611 }
8611 } 8612 }
8612 8613
8613 /* Enable host coalescing bug fix */ 8614 /* Enable host coalescing bug fix */
8614 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 8615 if (tg3_flag(tp, 5755_PLUS))
8615 val |= WDMAC_MODE_STATUS_TAG_FIX; 8616 val |= WDMAC_MODE_STATUS_TAG_FIX;
8616 8617
8617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) 8618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
@@ -8620,7 +8621,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8620 tw32_f(WDMAC_MODE, val); 8621 tw32_f(WDMAC_MODE, val);
8621 udelay(40); 8622 udelay(40);
8622 8623
8623 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { 8624 if (tg3_flag(tp, PCIX_MODE)) {
8624 u16 pcix_cmd; 8625 u16 pcix_cmd;
8625 8626
8626 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, 8627 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
@@ -8640,7 +8641,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8640 udelay(40); 8641 udelay(40);
8641 8642
8642 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); 8643 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8643 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 8644 if (!tg3_flag(tp, 5705_PLUS))
8644 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); 8645 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8645 8646
8646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) 8647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
@@ -8652,14 +8653,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8652 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); 8653 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8653 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); 8654 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8654 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; 8655 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8655 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) 8656 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8656 val |= RCVDBDI_MODE_LRG_RING_SZ; 8657 val |= RCVDBDI_MODE_LRG_RING_SZ;
8657 tw32(RCVDBDI_MODE, val); 8658 tw32(RCVDBDI_MODE, val);
8658 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); 8659 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8659 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 8660 if (tg3_flag(tp, HW_TSO_1) ||
8661 tg3_flag(tp, HW_TSO_2) ||
8662 tg3_flag(tp, HW_TSO_3))
8660 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); 8663 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8661 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; 8664 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8662 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 8665 if (tg3_flag(tp, ENABLE_TSS))
8663 val |= SNDBDI_MODE_MULTI_TXQ_EN; 8666 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8664 tw32(SNDBDI_MODE, val); 8667 tw32(SNDBDI_MODE, val);
8665 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); 8668 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
@@ -8670,7 +8673,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8670 return err; 8673 return err;
8671 } 8674 }
8672 8675
8673 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { 8676 if (tg3_flag(tp, TSO_CAPABLE)) {
8674 err = tg3_load_tso_firmware(tp); 8677 err = tg3_load_tso_firmware(tp);
8675 if (err) 8678 if (err)
8676 return err; 8679 return err;
@@ -8678,7 +8681,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8678 8681
8679 tp->tx_mode = TX_MODE_ENABLE; 8682 tp->tx_mode = TX_MODE_ENABLE;
8680 8683
8681 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || 8684 if (tg3_flag(tp, 5755_PLUS) ||
8682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 8685 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8683 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; 8686 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8684 8687
@@ -8691,7 +8694,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8691 tw32_f(MAC_TX_MODE, tp->tx_mode); 8694 tw32_f(MAC_TX_MODE, tp->tx_mode);
8692 udelay(100); 8695 udelay(100);
8693 8696
8694 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { 8697 if (tg3_flag(tp, ENABLE_RSS)) {
8695 u32 reg = MAC_RSS_INDIR_TBL_0; 8698 u32 reg = MAC_RSS_INDIR_TBL_0;
8696 u8 *ent = (u8 *)&val; 8699 u8 *ent = (u8 *)&val;
8697 8700
@@ -8720,10 +8723,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8720 } 8723 }
8721 8724
8722 tp->rx_mode = RX_MODE_ENABLE; 8725 tp->rx_mode = RX_MODE_ENABLE;
8723 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 8726 if (tg3_flag(tp, 5755_PLUS))
8724 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; 8727 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8725 8728
8726 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) 8729 if (tg3_flag(tp, ENABLE_RSS))
8727 tp->rx_mode |= RX_MODE_RSS_ENABLE | 8730 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8728 RX_MODE_RSS_ITBL_HASH_BITS_7 | 8731 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8729 RX_MODE_RSS_IPV6_HASH_EN | 8732 RX_MODE_RSS_IPV6_HASH_EN |
@@ -8770,7 +8773,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && 8773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8771 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { 8774 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8772 /* Use hardware link auto-negotiation */ 8775 /* Use hardware link auto-negotiation */
8773 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; 8776 tg3_flag_set(tp, HW_AUTONEG);
8774 } 8777 }
8775 8778
8776 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && 8779 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
@@ -8784,7 +8787,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8784 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 8787 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8785 } 8788 }
8786 8789
8787 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 8790 if (!tg3_flag(tp, USE_PHYLIB)) {
8788 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { 8791 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8789 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; 8792 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8790 tp->link_config.speed = tp->link_config.orig_speed; 8793 tp->link_config.speed = tp->link_config.orig_speed;
@@ -8817,12 +8820,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8817 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); 8820 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8818 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); 8821 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8819 8822
8820 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 8823 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
8821 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8822 limit = 8; 8824 limit = 8;
8823 else 8825 else
8824 limit = 16; 8826 limit = 16;
8825 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) 8827 if (tg3_flag(tp, ENABLE_ASF))
8826 limit -= 4; 8828 limit -= 4;
8827 switch (limit) { 8829 switch (limit) {
8828 case 16: 8830 case 16:
@@ -8860,7 +8862,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8860 break; 8862 break;
8861 } 8863 }
8862 8864
8863 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 8865 if (tg3_flag(tp, ENABLE_APE))
8864 /* Write our heartbeat update interval to APE. */ 8866 /* Write our heartbeat update interval to APE. */
8865 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, 8867 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8866 APE_HOST_HEARTBEAT_INT_DISABLE); 8868 APE_HOST_HEARTBEAT_INT_DISABLE);
@@ -8951,7 +8953,7 @@ static void tg3_timer(unsigned long __opaque)
8951 8953
8952 spin_lock(&tp->lock); 8954 spin_lock(&tp->lock);
8953 8955
8954 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { 8956 if (!tg3_flag(tp, TAGGED_STATUS)) {
8955 /* All of this garbage is because when using non-tagged 8957 /* All of this garbage is because when using non-tagged
8956 * IRQ status the mailbox/status_block protocol the chip 8958 * IRQ status the mailbox/status_block protocol the chip
8957 * uses with the cpu is race prone. 8959 * uses with the cpu is race prone.
@@ -8965,7 +8967,7 @@ static void tg3_timer(unsigned long __opaque)
8965 } 8967 }
8966 8968
8967 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { 8969 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8968 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; 8970 tg3_flag_set(tp, RESTART_TIMER);
8969 spin_unlock(&tp->lock); 8971 spin_unlock(&tp->lock);
8970 schedule_work(&tp->reset_task); 8972 schedule_work(&tp->reset_task);
8971 return; 8973 return;
@@ -8974,7 +8976,7 @@ static void tg3_timer(unsigned long __opaque)
8974 8976
8975 /* This part only runs once per second. */ 8977 /* This part only runs once per second. */
8976 if (!--tp->timer_counter) { 8978 if (!--tp->timer_counter) {
8977 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 8979 if (tg3_flag(tp, 5705_PLUS))
8978 tg3_periodic_fetch_stats(tp); 8980 tg3_periodic_fetch_stats(tp);
8979 8981
8980 if (tp->setlpicnt && !--tp->setlpicnt) { 8982 if (tp->setlpicnt && !--tp->setlpicnt) {
@@ -8983,7 +8985,7 @@ static void tg3_timer(unsigned long __opaque)
8983 val | TG3_CPMU_EEEMD_LPI_ENABLE); 8985 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8984 } 8986 }
8985 8987
8986 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { 8988 if (tg3_flag(tp, USE_LINKCHG_REG)) {
8987 u32 mac_stat; 8989 u32 mac_stat;
8988 int phy_event; 8990 int phy_event;
8989 8991
@@ -8998,7 +9000,7 @@ static void tg3_timer(unsigned long __opaque)
8998 9000
8999 if (phy_event) 9001 if (phy_event)
9000 tg3_setup_phy(tp, 0); 9002 tg3_setup_phy(tp, 0);
9001 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { 9003 } else if (tg3_flag(tp, POLL_SERDES)) {
9002 u32 mac_stat = tr32(MAC_STATUS); 9004 u32 mac_stat = tr32(MAC_STATUS);
9003 int need_setup = 0; 9005 int need_setup = 0;
9004 9006
@@ -9023,7 +9025,7 @@ static void tg3_timer(unsigned long __opaque)
9023 tg3_setup_phy(tp, 0); 9025 tg3_setup_phy(tp, 0);
9024 } 9026 }
9025 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && 9027 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9026 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 9028 tg3_flag(tp, 5780_CLASS)) {
9027 tg3_serdes_parallel_detect(tp); 9029 tg3_serdes_parallel_detect(tp);
9028 } 9030 }
9029 9031
@@ -9048,8 +9050,7 @@ static void tg3_timer(unsigned long __opaque)
9048 * resets. 9050 * resets.
9049 */ 9051 */
9050 if (!--tp->asf_counter) { 9052 if (!--tp->asf_counter) {
9051 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && 9053 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9052 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
9053 tg3_wait_for_event_ack(tp); 9054 tg3_wait_for_event_ack(tp);
9054 9055
9055 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, 9056 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
@@ -9085,14 +9086,14 @@ static int tg3_request_irq(struct tg3 *tp, int irq_num)
9085 name[IFNAMSIZ-1] = 0; 9086 name[IFNAMSIZ-1] = 0;
9086 } 9087 }
9087 9088
9088 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { 9089 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9089 fn = tg3_msi; 9090 fn = tg3_msi;
9090 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) 9091 if (tg3_flag(tp, 1SHOT_MSI))
9091 fn = tg3_msi_1shot; 9092 fn = tg3_msi_1shot;
9092 flags = 0; 9093 flags = 0;
9093 } else { 9094 } else {
9094 fn = tg3_interrupt; 9095 fn = tg3_interrupt;
9095 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) 9096 if (tg3_flag(tp, TAGGED_STATUS))
9096 fn = tg3_interrupt_tagged; 9097 fn = tg3_interrupt_tagged;
9097 flags = IRQF_SHARED; 9098 flags = IRQF_SHARED;
9098 } 9099 }
@@ -9118,8 +9119,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
9118 * Turn off MSI one shot mode. Otherwise this test has no 9119 * Turn off MSI one shot mode. Otherwise this test has no
9119 * observable way to know whether the interrupt was delivered. 9120 * observable way to know whether the interrupt was delivered.
9120 */ 9121 */
9121 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && 9122 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9122 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9123 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; 9123 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9124 tw32(MSGINT_MODE, val); 9124 tw32(MSGINT_MODE, val);
9125 } 9125 }
@@ -9161,8 +9161,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
9161 9161
9162 if (intr_ok) { 9162 if (intr_ok) {
9163 /* Reenable MSI one shot mode. */ 9163 /* Reenable MSI one shot mode. */
9164 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && 9164 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9165 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9166 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; 9165 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9167 tw32(MSGINT_MODE, val); 9166 tw32(MSGINT_MODE, val);
9168 } 9167 }
@@ -9180,7 +9179,7 @@ static int tg3_test_msi(struct tg3 *tp)
9180 int err; 9179 int err;
9181 u16 pci_cmd; 9180 u16 pci_cmd;
9182 9181
9183 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) 9182 if (!tg3_flag(tp, USING_MSI))
9184 return 0; 9183 return 0;
9185 9184
9186 /* Turn off SERR reporting in case MSI terminates with Master 9185 /* Turn off SERR reporting in case MSI terminates with Master
@@ -9210,7 +9209,7 @@ static int tg3_test_msi(struct tg3 *tp)
9210 9209
9211 pci_disable_msi(tp->pdev); 9210 pci_disable_msi(tp->pdev);
9212 9211
9213 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; 9212 tg3_flag_clear(tp, USING_MSI);
9214 tp->napi[0].irq_vec = tp->pdev->irq; 9213 tp->napi[0].irq_vec = tp->pdev->irq;
9215 9214
9216 err = tg3_request_irq(tp, 0); 9215 err = tg3_request_irq(tp, 0);
@@ -9307,11 +9306,11 @@ static bool tg3_enable_msix(struct tg3 *tp)
9307 } 9306 }
9308 9307
9309 if (tp->irq_cnt > 1) { 9308 if (tp->irq_cnt > 1) {
9310 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; 9309 tg3_flag_set(tp, ENABLE_RSS);
9311 9310
9312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 9311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { 9312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9314 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; 9313 tg3_flag_set(tp, ENABLE_TSS);
9315 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); 9314 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9316 } 9315 }
9317 } 9316 }
@@ -9321,8 +9320,8 @@ static bool tg3_enable_msix(struct tg3 *tp)
9321 9320
9322static void tg3_ints_init(struct tg3 *tp) 9321static void tg3_ints_init(struct tg3 *tp)
9323{ 9322{
9324 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && 9323 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9325 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { 9324 !tg3_flag(tp, TAGGED_STATUS)) {
9326 /* All MSI supporting chips should support tagged 9325 /* All MSI supporting chips should support tagged
9327 * status. Assert that this is the case. 9326 * status. Assert that this is the case.
9328 */ 9327 */
@@ -9331,21 +9330,19 @@ static void tg3_ints_init(struct tg3 *tp)
9331 goto defcfg; 9330 goto defcfg;
9332 } 9331 }
9333 9332
9334 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) 9333 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9335 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; 9334 tg3_flag_set(tp, USING_MSIX);
9336 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && 9335 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9337 pci_enable_msi(tp->pdev) == 0) 9336 tg3_flag_set(tp, USING_MSI);
9338 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9339 9337
9340 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { 9338 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9341 u32 msi_mode = tr32(MSGINT_MODE); 9339 u32 msi_mode = tr32(MSGINT_MODE);
9342 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) && 9340 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9343 tp->irq_cnt > 1)
9344 msi_mode |= MSGINT_MODE_MULTIVEC_EN; 9341 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9345 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); 9342 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9346 } 9343 }
9347defcfg: 9344defcfg:
9348 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { 9345 if (!tg3_flag(tp, USING_MSIX)) {
9349 tp->irq_cnt = 1; 9346 tp->irq_cnt = 1;
9350 tp->napi[0].irq_vec = tp->pdev->irq; 9347 tp->napi[0].irq_vec = tp->pdev->irq;
9351 netif_set_real_num_tx_queues(tp->dev, 1); 9348 netif_set_real_num_tx_queues(tp->dev, 1);
@@ -9355,12 +9352,14 @@ defcfg:
9355 9352
9356static void tg3_ints_fini(struct tg3 *tp) 9353static void tg3_ints_fini(struct tg3 *tp)
9357{ 9354{
9358 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) 9355 if (tg3_flag(tp, USING_MSIX))
9359 pci_disable_msix(tp->pdev); 9356 pci_disable_msix(tp->pdev);
9360 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) 9357 else if (tg3_flag(tp, USING_MSI))
9361 pci_disable_msi(tp->pdev); 9358 pci_disable_msi(tp->pdev);
9362 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; 9359 tg3_flag_clear(tp, USING_MSI);
9363 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS); 9360 tg3_flag_clear(tp, USING_MSIX);
9361 tg3_flag_clear(tp, ENABLE_RSS);
9362 tg3_flag_clear(tp, ENABLE_TSS);
9364} 9363}
9365 9364
9366static int tg3_open(struct net_device *dev) 9365static int tg3_open(struct net_device *dev)
@@ -9375,10 +9374,10 @@ static int tg3_open(struct net_device *dev)
9375 return err; 9374 return err;
9376 } else if (err) { 9375 } else if (err) {
9377 netdev_warn(tp->dev, "TSO capability disabled\n"); 9376 netdev_warn(tp->dev, "TSO capability disabled\n");
9378 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 9377 tg3_flag_clear(tp, TSO_CAPABLE);
9379 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { 9378 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9380 netdev_notice(tp->dev, "TSO capability restored\n"); 9379 netdev_notice(tp->dev, "TSO capability restored\n");
9381 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 9380 tg3_flag_set(tp, TSO_CAPABLE);
9382 } 9381 }
9383 } 9382 }
9384 9383
@@ -9391,7 +9390,7 @@ static int tg3_open(struct net_device *dev)
9391 tg3_full_lock(tp, 0); 9390 tg3_full_lock(tp, 0);
9392 9391
9393 tg3_disable_ints(tp); 9392 tg3_disable_ints(tp);
9394 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 9393 tg3_flag_clear(tp, INIT_COMPLETE);
9395 9394
9396 tg3_full_unlock(tp); 9395 tg3_full_unlock(tp);
9397 9396
@@ -9432,7 +9431,7 @@ static int tg3_open(struct net_device *dev)
9432 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 9431 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9433 tg3_free_rings(tp); 9432 tg3_free_rings(tp);
9434 } else { 9433 } else {
9435 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) 9434 if (tg3_flag(tp, TAGGED_STATUS))
9436 tp->timer_offset = HZ; 9435 tp->timer_offset = HZ;
9437 else 9436 else
9438 tp->timer_offset = HZ / 10; 9437 tp->timer_offset = HZ / 10;
@@ -9454,7 +9453,7 @@ static int tg3_open(struct net_device *dev)
9454 if (err) 9453 if (err)
9455 goto err_out3; 9454 goto err_out3;
9456 9455
9457 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 9456 if (tg3_flag(tp, USING_MSI)) {
9458 err = tg3_test_msi(tp); 9457 err = tg3_test_msi(tp);
9459 9458
9460 if (err) { 9459 if (err) {
@@ -9466,8 +9465,7 @@ static int tg3_open(struct net_device *dev)
9466 goto err_out2; 9465 goto err_out2;
9467 } 9466 }
9468 9467
9469 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && 9468 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9470 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9471 u32 val = tr32(PCIE_TRANSACTION_CFG); 9469 u32 val = tr32(PCIE_TRANSACTION_CFG);
9472 9470
9473 tw32(PCIE_TRANSACTION_CFG, 9471 tw32(PCIE_TRANSACTION_CFG,
@@ -9480,7 +9478,7 @@ static int tg3_open(struct net_device *dev)
9480 tg3_full_lock(tp, 0); 9478 tg3_full_lock(tp, 0);
9481 9479
9482 add_timer(&tp->timer); 9480 add_timer(&tp->timer);
9483 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 9481 tg3_flag_set(tp, INIT_COMPLETE);
9484 tg3_enable_ints(tp); 9482 tg3_enable_ints(tp);
9485 9483
9486 tg3_full_unlock(tp); 9484 tg3_full_unlock(tp);
@@ -9529,7 +9527,7 @@ static int tg3_close(struct net_device *dev)
9529 9527
9530 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 9528 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9531 tg3_free_rings(tp); 9529 tg3_free_rings(tp);
9532 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 9530 tg3_flag_clear(tp, INIT_COMPLETE);
9533 9531
9534 tg3_full_unlock(tp); 9532 tg3_full_unlock(tp);
9535 9533
@@ -9786,7 +9784,7 @@ static void __tg3_set_rx_mode(struct net_device *dev)
9786 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG 9784 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9787 * flag clear. 9785 * flag clear.
9788 */ 9786 */
9789 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) 9787 if (!tg3_flag(tp, ENABLE_ASF))
9790 rx_mode |= RX_MODE_KEEP_VLAN_TAG; 9788 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9791#endif 9789#endif
9792 9790
@@ -9879,7 +9877,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
9879 u32 i, offset, len, b_offset, b_count; 9877 u32 i, offset, len, b_offset, b_count;
9880 __be32 val; 9878 __be32 val;
9881 9879
9882 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) 9880 if (tg3_flag(tp, NO_NVRAM))
9883 return -EINVAL; 9881 return -EINVAL;
9884 9882
9885 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) 9883 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
@@ -9947,7 +9945,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
9947 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) 9945 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9948 return -EAGAIN; 9946 return -EAGAIN;
9949 9947
9950 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || 9948 if (tg3_flag(tp, NO_NVRAM) ||
9951 eeprom->magic != TG3_EEPROM_MAGIC) 9949 eeprom->magic != TG3_EEPROM_MAGIC)
9952 return -EINVAL; 9950 return -EINVAL;
9953 9951
@@ -9999,7 +9997,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9999{ 9997{
10000 struct tg3 *tp = netdev_priv(dev); 9998 struct tg3 *tp = netdev_priv(dev);
10001 9999
10002 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 10000 if (tg3_flag(tp, USE_PHYLIB)) {
10003 struct phy_device *phydev; 10001 struct phy_device *phydev;
10004 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) 10002 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10005 return -EAGAIN; 10003 return -EAGAIN;
@@ -10045,7 +10043,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10045{ 10043{
10046 struct tg3 *tp = netdev_priv(dev); 10044 struct tg3 *tp = netdev_priv(dev);
10047 10045
10048 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 10046 if (tg3_flag(tp, USE_PHYLIB)) {
10049 struct phy_device *phydev; 10047 struct phy_device *phydev;
10050 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) 10048 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10051 return -EAGAIN; 10049 return -EAGAIN;
@@ -10145,14 +10143,12 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10145{ 10143{
10146 struct tg3 *tp = netdev_priv(dev); 10144 struct tg3 *tp = netdev_priv(dev);
10147 10145
10148 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && 10146 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10149 device_can_wakeup(&tp->pdev->dev))
10150 wol->supported = WAKE_MAGIC; 10147 wol->supported = WAKE_MAGIC;
10151 else 10148 else
10152 wol->supported = 0; 10149 wol->supported = 0;
10153 wol->wolopts = 0; 10150 wol->wolopts = 0;
10154 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && 10151 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10155 device_can_wakeup(&tp->pdev->dev))
10156 wol->wolopts = WAKE_MAGIC; 10152 wol->wolopts = WAKE_MAGIC;
10157 memset(&wol->sopass, 0, sizeof(wol->sopass)); 10153 memset(&wol->sopass, 0, sizeof(wol->sopass));
10158} 10154}
@@ -10165,16 +10161,16 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10165 if (wol->wolopts & ~WAKE_MAGIC) 10161 if (wol->wolopts & ~WAKE_MAGIC)
10166 return -EINVAL; 10162 return -EINVAL;
10167 if ((wol->wolopts & WAKE_MAGIC) && 10163 if ((wol->wolopts & WAKE_MAGIC) &&
10168 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) 10164 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10169 return -EINVAL; 10165 return -EINVAL;
10170 10166
10171 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); 10167 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10172 10168
10173 spin_lock_bh(&tp->lock); 10169 spin_lock_bh(&tp->lock);
10174 if (device_may_wakeup(dp)) 10170 if (device_may_wakeup(dp))
10175 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 10171 tg3_flag_set(tp, WOL_ENABLE);
10176 else 10172 else
10177 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; 10173 tg3_flag_clear(tp, WOL_ENABLE);
10178 spin_unlock_bh(&tp->lock); 10174 spin_unlock_bh(&tp->lock);
10179 10175
10180 return 0; 10176 return 0;
@@ -10203,7 +10199,7 @@ static int tg3_nway_reset(struct net_device *dev)
10203 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) 10199 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10204 return -EINVAL; 10200 return -EINVAL;
10205 10201
10206 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 10202 if (tg3_flag(tp, USE_PHYLIB)) {
10207 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) 10203 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10208 return -EAGAIN; 10204 return -EAGAIN;
10209 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); 10205 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
@@ -10232,7 +10228,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
10232 10228
10233 ering->rx_max_pending = tp->rx_std_ring_mask; 10229 ering->rx_max_pending = tp->rx_std_ring_mask;
10234 ering->rx_mini_max_pending = 0; 10230 ering->rx_mini_max_pending = 0;
10235 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) 10231 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10236 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; 10232 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10237 else 10233 else
10238 ering->rx_jumbo_max_pending = 0; 10234 ering->rx_jumbo_max_pending = 0;
@@ -10241,7 +10237,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
10241 10237
10242 ering->rx_pending = tp->rx_pending; 10238 ering->rx_pending = tp->rx_pending;
10243 ering->rx_mini_pending = 0; 10239 ering->rx_mini_pending = 0;
10244 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) 10240 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10245 ering->rx_jumbo_pending = tp->rx_jumbo_pending; 10241 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10246 else 10242 else
10247 ering->rx_jumbo_pending = 0; 10243 ering->rx_jumbo_pending = 0;
@@ -10258,7 +10254,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
10258 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || 10254 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10259 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || 10255 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10260 (ering->tx_pending <= MAX_SKB_FRAGS) || 10256 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10261 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && 10257 (tg3_flag(tp, TSO_BUG) &&
10262 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) 10258 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10263 return -EINVAL; 10259 return -EINVAL;
10264 10260
@@ -10272,7 +10268,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
10272 10268
10273 tp->rx_pending = ering->rx_pending; 10269 tp->rx_pending = ering->rx_pending;
10274 10270
10275 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && 10271 if (tg3_flag(tp, MAX_RXPEND_64) &&
10276 tp->rx_pending > 63) 10272 tp->rx_pending > 63)
10277 tp->rx_pending = 63; 10273 tp->rx_pending = 63;
10278 tp->rx_jumbo_pending = ering->rx_jumbo_pending; 10274 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
@@ -10299,7 +10295,7 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
10299{ 10295{
10300 struct tg3 *tp = netdev_priv(dev); 10296 struct tg3 *tp = netdev_priv(dev);
10301 10297
10302 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; 10298 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10303 10299
10304 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) 10300 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10305 epause->rx_pause = 1; 10301 epause->rx_pause = 1;
@@ -10317,7 +10313,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
10317 struct tg3 *tp = netdev_priv(dev); 10313 struct tg3 *tp = netdev_priv(dev);
10318 int err = 0; 10314 int err = 0;
10319 10315
10320 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 10316 if (tg3_flag(tp, USE_PHYLIB)) {
10321 u32 newadv; 10317 u32 newadv;
10322 struct phy_device *phydev; 10318 struct phy_device *phydev;
10323 10319
@@ -10345,9 +10341,9 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
10345 newadv = 0; 10341 newadv = 0;
10346 10342
10347 if (epause->autoneg) 10343 if (epause->autoneg)
10348 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 10344 tg3_flag_set(tp, PAUSE_AUTONEG);
10349 else 10345 else
10350 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; 10346 tg3_flag_clear(tp, PAUSE_AUTONEG);
10351 10347
10352 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { 10348 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10353 u32 oldadv = phydev->advertising & 10349 u32 oldadv = phydev->advertising &
@@ -10389,9 +10385,9 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
10389 tg3_full_lock(tp, irq_sync); 10385 tg3_full_lock(tp, irq_sync);
10390 10386
10391 if (epause->autoneg) 10387 if (epause->autoneg)
10392 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 10388 tg3_flag_set(tp, PAUSE_AUTONEG);
10393 else 10389 else
10394 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; 10390 tg3_flag_clear(tp, PAUSE_AUTONEG);
10395 if (epause->rx_pause) 10391 if (epause->rx_pause)
10396 tp->link_config.flowctrl |= FLOW_CTRL_RX; 10392 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10397 else 10393 else
@@ -10490,8 +10486,7 @@ static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10490 u32 offset = 0, len = 0; 10486 u32 offset = 0, len = 0;
10491 u32 magic, val; 10487 u32 magic, val;
10492 10488
10493 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || 10489 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10494 tg3_nvram_read(tp, 0, &magic))
10495 return NULL; 10490 return NULL;
10496 10491
10497 if (magic == TG3_EEPROM_MAGIC) { 10492 if (magic == TG3_EEPROM_MAGIC) {
@@ -10571,7 +10566,7 @@ static int tg3_test_nvram(struct tg3 *tp)
10571 __be32 *buf; 10566 __be32 *buf;
10572 int i, j, k, err = 0, size; 10567 int i, j, k, err = 0, size;
10573 10568
10574 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) 10569 if (tg3_flag(tp, NO_NVRAM))
10575 return 0; 10570 return 0;
10576 10571
10577 if (tg3_nvram_read(tp, 0, &magic) != 0) 10572 if (tg3_nvram_read(tp, 0, &magic) != 0)
@@ -10913,9 +10908,9 @@ static int tg3_test_registers(struct tg3 *tp)
10913 }; 10908 };
10914 10909
10915 is_5705 = is_5750 = 0; 10910 is_5705 = is_5750 = 0;
10916 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10911 if (tg3_flag(tp, 5705_PLUS)) {
10917 is_5705 = 1; 10912 is_5705 = 1;
10918 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 10913 if (tg3_flag(tp, 5750_PLUS))
10919 is_5750 = 1; 10914 is_5750 = 1;
10920 } 10915 }
10921 10916
@@ -10926,7 +10921,7 @@ static int tg3_test_registers(struct tg3 *tp)
10926 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) 10921 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10927 continue; 10922 continue;
10928 10923
10929 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && 10924 if (tg3_flag(tp, IS_5788) &&
10930 (reg_tbl[i].flags & TG3_FL_NOT_5788)) 10925 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10931 continue; 10926 continue;
10932 10927
@@ -11049,15 +11044,15 @@ static int tg3_test_memory(struct tg3 *tp)
11049 int err = 0; 11044 int err = 0;
11050 int i; 11045 int i;
11051 11046
11052 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) 11047 if (tg3_flag(tp, 5717_PLUS))
11053 mem_tbl = mem_tbl_5717; 11048 mem_tbl = mem_tbl_5717;
11054 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 11049 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11055 mem_tbl = mem_tbl_57765; 11050 mem_tbl = mem_tbl_57765;
11056 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 11051 else if (tg3_flag(tp, 5755_PLUS))
11057 mem_tbl = mem_tbl_5755; 11052 mem_tbl = mem_tbl_5755;
11058 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 11053 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11059 mem_tbl = mem_tbl_5906; 11054 mem_tbl = mem_tbl_5906;
11060 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 11055 else if (tg3_flag(tp, 5705_PLUS))
11061 mem_tbl = mem_tbl_5705; 11056 mem_tbl = mem_tbl_5705;
11062 else 11057 else
11063 mem_tbl = mem_tbl_570x; 11058 mem_tbl = mem_tbl_570x;
@@ -11113,9 +11108,9 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11113 tnapi = &tp->napi[0]; 11108 tnapi = &tp->napi[0];
11114 rnapi = &tp->napi[0]; 11109 rnapi = &tp->napi[0];
11115 if (tp->irq_cnt > 1) { 11110 if (tp->irq_cnt > 1) {
11116 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) 11111 if (tg3_flag(tp, ENABLE_RSS))
11117 rnapi = &tp->napi[1]; 11112 rnapi = &tp->napi[1];
11118 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 11113 if (tg3_flag(tp, ENABLE_TSS))
11119 tnapi = &tp->napi[1]; 11114 tnapi = &tp->napi[1];
11120 } 11115 }
11121 coal_now = tnapi->coal_now | rnapi->coal_now; 11116 coal_now = tnapi->coal_now | rnapi->coal_now;
@@ -11127,13 +11122,13 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11127 * all newer ASIC revisions. 11122 * all newer ASIC revisions.
11128 */ 11123 */
11129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || 11124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11130 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) 11125 tg3_flag(tp, CPMU_PRESENT))
11131 return 0; 11126 return 0;
11132 11127
11133 mac_mode = tp->mac_mode & 11128 mac_mode = tp->mac_mode &
11134 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); 11129 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11135 mac_mode |= MAC_MODE_PORT_INT_LPBACK; 11130 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
11136 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 11131 if (!tg3_flag(tp, 5705_PLUS))
11137 mac_mode |= MAC_MODE_LINK_POLARITY; 11132 mac_mode |= MAC_MODE_LINK_POLARITY;
11138 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) 11133 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
11139 mac_mode |= MAC_MODE_PORT_MODE_MII; 11134 mac_mode |= MAC_MODE_PORT_MODE_MII;
@@ -11222,7 +11217,9 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11222 base_flags = (TXD_FLAG_CPU_PRE_DMA | 11217 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11223 TXD_FLAG_CPU_POST_DMA); 11218 TXD_FLAG_CPU_POST_DMA);
11224 11219
11225 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { 11220 if (tg3_flag(tp, HW_TSO_1) ||
11221 tg3_flag(tp, HW_TSO_2) ||
11222 tg3_flag(tp, HW_TSO_3)) {
11226 struct tcphdr *th; 11223 struct tcphdr *th;
11227 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; 11224 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11228 th = (struct tcphdr *)&tx_data[val]; 11225 th = (struct tcphdr *)&tx_data[val];
@@ -11230,14 +11227,14 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11230 } else 11227 } else
11231 base_flags |= TXD_FLAG_TCPUDP_CSUM; 11228 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11232 11229
11233 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { 11230 if (tg3_flag(tp, HW_TSO_3)) {
11234 mss |= (hdr_len & 0xc) << 12; 11231 mss |= (hdr_len & 0xc) << 12;
11235 if (hdr_len & 0x10) 11232 if (hdr_len & 0x10)
11236 base_flags |= 0x00000010; 11233 base_flags |= 0x00000010;
11237 base_flags |= (hdr_len & 0x3e0) << 5; 11234 base_flags |= (hdr_len & 0x3e0) << 5;
11238 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) 11235 } else if (tg3_flag(tp, HW_TSO_2))
11239 mss |= hdr_len << 9; 11236 mss |= hdr_len << 9;
11240 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || 11237 else if (tg3_flag(tp, HW_TSO_1) ||
11241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 11238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11242 mss |= (TG3_TSO_TCP_OPT_LEN << 9); 11239 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11243 } else { 11240 } else {
@@ -11381,7 +11378,7 @@ static int tg3_test_loopback(struct tg3 *tp)
11381 goto done; 11378 goto done;
11382 } 11379 }
11383 11380
11384 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { 11381 if (tg3_flag(tp, ENABLE_RSS)) {
11385 int i; 11382 int i;
11386 11383
11387 /* Reroute all rx packets to the 1st queue */ 11384 /* Reroute all rx packets to the 1st queue */
@@ -11394,7 +11391,7 @@ static int tg3_test_loopback(struct tg3 *tp)
11394 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) 11391 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11395 tg3_phy_toggle_apd(tp, false); 11392 tg3_phy_toggle_apd(tp, false);
11396 11393
11397 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { 11394 if (tg3_flag(tp, CPMU_PRESENT)) {
11398 int i; 11395 int i;
11399 u32 status; 11396 u32 status;
11400 11397
@@ -11423,11 +11420,11 @@ static int tg3_test_loopback(struct tg3 *tp)
11423 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK)) 11420 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
11424 err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; 11421 err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11425 11422
11426 if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && 11423 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11427 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK)) 11424 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11428 err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT; 11425 err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11429 11426
11430 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { 11427 if (tg3_flag(tp, CPMU_PRESENT)) {
11431 tw32(TG3_CPMU_CTRL, cpmuctrl); 11428 tw32(TG3_CPMU_CTRL, cpmuctrl);
11432 11429
11433 /* Release the mutex */ 11430 /* Release the mutex */
@@ -11435,15 +11432,15 @@ static int tg3_test_loopback(struct tg3 *tp)
11435 } 11432 }
11436 11433
11437 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && 11434 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11438 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 11435 !tg3_flag(tp, USE_PHYLIB)) {
11439 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK)) 11436 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
11440 err |= TG3_STD_LOOPBACK_FAILED << 11437 err |= TG3_STD_LOOPBACK_FAILED <<
11441 TG3_PHY_LOOPBACK_SHIFT; 11438 TG3_PHY_LOOPBACK_SHIFT;
11442 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && 11439 if (tg3_flag(tp, TSO_CAPABLE) &&
11443 tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK)) 11440 tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK))
11444 err |= TG3_TSO_LOOPBACK_FAILED << 11441 err |= TG3_TSO_LOOPBACK_FAILED <<
11445 TG3_PHY_LOOPBACK_SHIFT; 11442 TG3_PHY_LOOPBACK_SHIFT;
11446 if ((tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) && 11443 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11447 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK)) 11444 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11448 err |= TG3_JMB_LOOPBACK_FAILED << 11445 err |= TG3_JMB_LOOPBACK_FAILED <<
11449 TG3_PHY_LOOPBACK_SHIFT; 11446 TG3_PHY_LOOPBACK_SHIFT;
@@ -11491,7 +11488,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11491 tg3_halt(tp, RESET_KIND_SUSPEND, 1); 11488 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11492 err = tg3_nvram_lock(tp); 11489 err = tg3_nvram_lock(tp);
11493 tg3_halt_cpu(tp, RX_CPU_BASE); 11490 tg3_halt_cpu(tp, RX_CPU_BASE);
11494 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 11491 if (!tg3_flag(tp, 5705_PLUS))
11495 tg3_halt_cpu(tp, TX_CPU_BASE); 11492 tg3_halt_cpu(tp, TX_CPU_BASE);
11496 if (!err) 11493 if (!err)
11497 tg3_nvram_unlock(tp); 11494 tg3_nvram_unlock(tp);
@@ -11521,7 +11518,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11521 11518
11522 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 11519 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11523 if (netif_running(dev)) { 11520 if (netif_running(dev)) {
11524 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11521 tg3_flag_set(tp, INIT_COMPLETE);
11525 err2 = tg3_restart_hw(tp, 1); 11522 err2 = tg3_restart_hw(tp, 1);
11526 if (!err2) 11523 if (!err2)
11527 tg3_netif_start(tp); 11524 tg3_netif_start(tp);
@@ -11543,7 +11540,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11543 struct tg3 *tp = netdev_priv(dev); 11540 struct tg3 *tp = netdev_priv(dev);
11544 int err; 11541 int err;
11545 11542
11546 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 11543 if (tg3_flag(tp, USE_PHYLIB)) {
11547 struct phy_device *phydev; 11544 struct phy_device *phydev;
11548 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) 11545 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11549 return -EAGAIN; 11546 return -EAGAIN;
@@ -11608,7 +11605,7 @@ static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11608 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; 11605 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11609 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; 11606 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11610 11607
11611 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 11608 if (!tg3_flag(tp, 5705_PLUS)) {
11612 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; 11609 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11613 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; 11610 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11614 max_stat_coal_ticks = MAX_STAT_COAL_TICKS; 11611 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
@@ -11722,8 +11719,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11722{ 11719{
11723 u32 val; 11720 u32 val;
11724 11721
11725 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || 11722 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11726 tg3_nvram_read(tp, 0, &val) != 0)
11727 return; 11723 return;
11728 11724
11729 /* Selfboot format */ 11725 /* Selfboot format */
@@ -11758,19 +11754,19 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11758 11754
11759 nvcfg1 = tr32(NVRAM_CFG1); 11755 nvcfg1 = tr32(NVRAM_CFG1);
11760 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { 11756 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11761 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11757 tg3_flag_set(tp, FLASH);
11762 } else { 11758 } else {
11763 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 11759 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11764 tw32(NVRAM_CFG1, nvcfg1); 11760 tw32(NVRAM_CFG1, nvcfg1);
11765 } 11761 }
11766 11762
11767 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || 11763 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11768 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 11764 tg3_flag(tp, 5780_CLASS)) {
11769 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { 11765 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11770 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: 11766 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11771 tp->nvram_jedecnum = JEDEC_ATMEL; 11767 tp->nvram_jedecnum = JEDEC_ATMEL;
11772 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; 11768 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11773 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11769 tg3_flag_set(tp, NVRAM_BUFFERED);
11774 break; 11770 break;
11775 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: 11771 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11776 tp->nvram_jedecnum = JEDEC_ATMEL; 11772 tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -11779,12 +11775,12 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11779 case FLASH_VENDOR_ATMEL_EEPROM: 11775 case FLASH_VENDOR_ATMEL_EEPROM:
11780 tp->nvram_jedecnum = JEDEC_ATMEL; 11776 tp->nvram_jedecnum = JEDEC_ATMEL;
11781 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 11777 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11782 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11778 tg3_flag_set(tp, NVRAM_BUFFERED);
11783 break; 11779 break;
11784 case FLASH_VENDOR_ST: 11780 case FLASH_VENDOR_ST:
11785 tp->nvram_jedecnum = JEDEC_ST; 11781 tp->nvram_jedecnum = JEDEC_ST;
11786 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; 11782 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11787 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11783 tg3_flag_set(tp, NVRAM_BUFFERED);
11788 break; 11784 break;
11789 case FLASH_VENDOR_SAIFUN: 11785 case FLASH_VENDOR_SAIFUN:
11790 tp->nvram_jedecnum = JEDEC_SAIFUN; 11786 tp->nvram_jedecnum = JEDEC_SAIFUN;
@@ -11799,7 +11795,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11799 } else { 11795 } else {
11800 tp->nvram_jedecnum = JEDEC_ATMEL; 11796 tp->nvram_jedecnum = JEDEC_ATMEL;
11801 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; 11797 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11802 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11798 tg3_flag_set(tp, NVRAM_BUFFERED);
11803 } 11799 }
11804} 11800}
11805 11801
@@ -11838,29 +11834,29 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11838 11834
11839 /* NVRAM protection for TPM */ 11835 /* NVRAM protection for TPM */
11840 if (nvcfg1 & (1 << 27)) 11836 if (nvcfg1 & (1 << 27))
11841 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; 11837 tg3_flag_set(tp, PROTECTED_NVRAM);
11842 11838
11843 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 11839 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11844 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: 11840 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11845 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: 11841 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11846 tp->nvram_jedecnum = JEDEC_ATMEL; 11842 tp->nvram_jedecnum = JEDEC_ATMEL;
11847 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11843 tg3_flag_set(tp, NVRAM_BUFFERED);
11848 break; 11844 break;
11849 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: 11845 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11850 tp->nvram_jedecnum = JEDEC_ATMEL; 11846 tp->nvram_jedecnum = JEDEC_ATMEL;
11851 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11847 tg3_flag_set(tp, NVRAM_BUFFERED);
11852 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11848 tg3_flag_set(tp, FLASH);
11853 break; 11849 break;
11854 case FLASH_5752VENDOR_ST_M45PE10: 11850 case FLASH_5752VENDOR_ST_M45PE10:
11855 case FLASH_5752VENDOR_ST_M45PE20: 11851 case FLASH_5752VENDOR_ST_M45PE20:
11856 case FLASH_5752VENDOR_ST_M45PE40: 11852 case FLASH_5752VENDOR_ST_M45PE40:
11857 tp->nvram_jedecnum = JEDEC_ST; 11853 tp->nvram_jedecnum = JEDEC_ST;
11858 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11854 tg3_flag_set(tp, NVRAM_BUFFERED);
11859 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11855 tg3_flag_set(tp, FLASH);
11860 break; 11856 break;
11861 } 11857 }
11862 11858
11863 if (tp->tg3_flags2 & TG3_FLG2_FLASH) { 11859 if (tg3_flag(tp, FLASH)) {
11864 tg3_nvram_get_pagesize(tp, nvcfg1); 11860 tg3_nvram_get_pagesize(tp, nvcfg1);
11865 } else { 11861 } else {
11866 /* For eeprom, set pagesize to maximum eeprom size */ 11862 /* For eeprom, set pagesize to maximum eeprom size */
@@ -11879,7 +11875,7 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11879 11875
11880 /* NVRAM protection for TPM */ 11876 /* NVRAM protection for TPM */
11881 if (nvcfg1 & (1 << 27)) { 11877 if (nvcfg1 & (1 << 27)) {
11882 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; 11878 tg3_flag_set(tp, PROTECTED_NVRAM);
11883 protect = 1; 11879 protect = 1;
11884 } 11880 }
11885 11881
@@ -11890,8 +11886,8 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11890 case FLASH_5755VENDOR_ATMEL_FLASH_3: 11886 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11891 case FLASH_5755VENDOR_ATMEL_FLASH_5: 11887 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11892 tp->nvram_jedecnum = JEDEC_ATMEL; 11888 tp->nvram_jedecnum = JEDEC_ATMEL;
11893 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11889 tg3_flag_set(tp, NVRAM_BUFFERED);
11894 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11890 tg3_flag_set(tp, FLASH);
11895 tp->nvram_pagesize = 264; 11891 tp->nvram_pagesize = 264;
11896 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || 11892 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11897 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) 11893 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
@@ -11908,8 +11904,8 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11908 case FLASH_5752VENDOR_ST_M45PE20: 11904 case FLASH_5752VENDOR_ST_M45PE20:
11909 case FLASH_5752VENDOR_ST_M45PE40: 11905 case FLASH_5752VENDOR_ST_M45PE40:
11910 tp->nvram_jedecnum = JEDEC_ST; 11906 tp->nvram_jedecnum = JEDEC_ST;
11911 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11907 tg3_flag_set(tp, NVRAM_BUFFERED);
11912 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11908 tg3_flag_set(tp, FLASH);
11913 tp->nvram_pagesize = 256; 11909 tp->nvram_pagesize = 256;
11914 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) 11910 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11915 tp->nvram_size = (protect ? 11911 tp->nvram_size = (protect ?
@@ -11939,7 +11935,7 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11939 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: 11935 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11940 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: 11936 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11941 tp->nvram_jedecnum = JEDEC_ATMEL; 11937 tp->nvram_jedecnum = JEDEC_ATMEL;
11942 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11938 tg3_flag_set(tp, NVRAM_BUFFERED);
11943 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 11939 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11944 11940
11945 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 11941 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -11950,16 +11946,16 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11950 case FLASH_5755VENDOR_ATMEL_FLASH_2: 11946 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11951 case FLASH_5755VENDOR_ATMEL_FLASH_3: 11947 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11952 tp->nvram_jedecnum = JEDEC_ATMEL; 11948 tp->nvram_jedecnum = JEDEC_ATMEL;
11953 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11949 tg3_flag_set(tp, NVRAM_BUFFERED);
11954 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11950 tg3_flag_set(tp, FLASH);
11955 tp->nvram_pagesize = 264; 11951 tp->nvram_pagesize = 264;
11956 break; 11952 break;
11957 case FLASH_5752VENDOR_ST_M45PE10: 11953 case FLASH_5752VENDOR_ST_M45PE10:
11958 case FLASH_5752VENDOR_ST_M45PE20: 11954 case FLASH_5752VENDOR_ST_M45PE20:
11959 case FLASH_5752VENDOR_ST_M45PE40: 11955 case FLASH_5752VENDOR_ST_M45PE40:
11960 tp->nvram_jedecnum = JEDEC_ST; 11956 tp->nvram_jedecnum = JEDEC_ST;
11961 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11957 tg3_flag_set(tp, NVRAM_BUFFERED);
11962 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11958 tg3_flag_set(tp, FLASH);
11963 tp->nvram_pagesize = 256; 11959 tp->nvram_pagesize = 256;
11964 break; 11960 break;
11965 } 11961 }
@@ -11973,7 +11969,7 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11973 11969
11974 /* NVRAM protection for TPM */ 11970 /* NVRAM protection for TPM */
11975 if (nvcfg1 & (1 << 27)) { 11971 if (nvcfg1 & (1 << 27)) {
11976 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; 11972 tg3_flag_set(tp, PROTECTED_NVRAM);
11977 protect = 1; 11973 protect = 1;
11978 } 11974 }
11979 11975
@@ -11988,9 +11984,9 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11988 case FLASH_5761VENDOR_ATMEL_MDB081D: 11984 case FLASH_5761VENDOR_ATMEL_MDB081D:
11989 case FLASH_5761VENDOR_ATMEL_MDB161D: 11985 case FLASH_5761VENDOR_ATMEL_MDB161D:
11990 tp->nvram_jedecnum = JEDEC_ATMEL; 11986 tp->nvram_jedecnum = JEDEC_ATMEL;
11991 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 11987 tg3_flag_set(tp, NVRAM_BUFFERED);
11992 tp->tg3_flags2 |= TG3_FLG2_FLASH; 11988 tg3_flag_set(tp, FLASH);
11993 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 11989 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
11994 tp->nvram_pagesize = 256; 11990 tp->nvram_pagesize = 256;
11995 break; 11991 break;
11996 case FLASH_5761VENDOR_ST_A_M45PE20: 11992 case FLASH_5761VENDOR_ST_A_M45PE20:
@@ -12002,8 +11998,8 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12002 case FLASH_5761VENDOR_ST_M_M45PE80: 11998 case FLASH_5761VENDOR_ST_M_M45PE80:
12003 case FLASH_5761VENDOR_ST_M_M45PE16: 11999 case FLASH_5761VENDOR_ST_M_M45PE16:
12004 tp->nvram_jedecnum = JEDEC_ST; 12000 tp->nvram_jedecnum = JEDEC_ST;
12005 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12001 tg3_flag_set(tp, NVRAM_BUFFERED);
12006 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12002 tg3_flag_set(tp, FLASH);
12007 tp->nvram_pagesize = 256; 12003 tp->nvram_pagesize = 256;
12008 break; 12004 break;
12009 } 12005 }
@@ -12043,7 +12039,7 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12043static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) 12039static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12044{ 12040{
12045 tp->nvram_jedecnum = JEDEC_ATMEL; 12041 tp->nvram_jedecnum = JEDEC_ATMEL;
12046 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12042 tg3_flag_set(tp, NVRAM_BUFFERED);
12047 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 12043 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12048} 12044}
12049 12045
@@ -12057,7 +12053,7 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12057 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: 12053 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12058 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: 12054 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12059 tp->nvram_jedecnum = JEDEC_ATMEL; 12055 tp->nvram_jedecnum = JEDEC_ATMEL;
12060 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12056 tg3_flag_set(tp, NVRAM_BUFFERED);
12061 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 12057 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12062 12058
12063 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 12059 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -12071,8 +12067,8 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12071 case FLASH_57780VENDOR_ATMEL_AT45DB041D: 12067 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12072 case FLASH_57780VENDOR_ATMEL_AT45DB041B: 12068 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12073 tp->nvram_jedecnum = JEDEC_ATMEL; 12069 tp->nvram_jedecnum = JEDEC_ATMEL;
12074 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12070 tg3_flag_set(tp, NVRAM_BUFFERED);
12075 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12071 tg3_flag_set(tp, FLASH);
12076 12072
12077 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 12073 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12078 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: 12074 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
@@ -12094,8 +12090,8 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12094 case FLASH_5752VENDOR_ST_M45PE20: 12090 case FLASH_5752VENDOR_ST_M45PE20:
12095 case FLASH_5752VENDOR_ST_M45PE40: 12091 case FLASH_5752VENDOR_ST_M45PE40:
12096 tp->nvram_jedecnum = JEDEC_ST; 12092 tp->nvram_jedecnum = JEDEC_ST;
12097 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12093 tg3_flag_set(tp, NVRAM_BUFFERED);
12098 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12094 tg3_flag_set(tp, FLASH);
12099 12095
12100 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 12096 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12101 case FLASH_5752VENDOR_ST_M45PE10: 12097 case FLASH_5752VENDOR_ST_M45PE10:
@@ -12110,13 +12106,13 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12110 } 12106 }
12111 break; 12107 break;
12112 default: 12108 default:
12113 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; 12109 tg3_flag_set(tp, NO_NVRAM);
12114 return; 12110 return;
12115 } 12111 }
12116 12112
12117 tg3_nvram_get_pagesize(tp, nvcfg1); 12113 tg3_nvram_get_pagesize(tp, nvcfg1);
12118 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) 12114 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12119 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 12115 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12120} 12116}
12121 12117
12122 12118
@@ -12130,7 +12126,7 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12130 case FLASH_5717VENDOR_ATMEL_EEPROM: 12126 case FLASH_5717VENDOR_ATMEL_EEPROM:
12131 case FLASH_5717VENDOR_MICRO_EEPROM: 12127 case FLASH_5717VENDOR_MICRO_EEPROM:
12132 tp->nvram_jedecnum = JEDEC_ATMEL; 12128 tp->nvram_jedecnum = JEDEC_ATMEL;
12133 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12129 tg3_flag_set(tp, NVRAM_BUFFERED);
12134 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; 12130 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12135 12131
12136 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 12132 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -12144,8 +12140,8 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12144 case FLASH_5717VENDOR_ATMEL_ADB021D: 12140 case FLASH_5717VENDOR_ATMEL_ADB021D:
12145 case FLASH_5717VENDOR_ATMEL_45USPT: 12141 case FLASH_5717VENDOR_ATMEL_45USPT:
12146 tp->nvram_jedecnum = JEDEC_ATMEL; 12142 tp->nvram_jedecnum = JEDEC_ATMEL;
12147 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12143 tg3_flag_set(tp, NVRAM_BUFFERED);
12148 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12144 tg3_flag_set(tp, FLASH);
12149 12145
12150 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 12146 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12151 case FLASH_5717VENDOR_ATMEL_MDB021D: 12147 case FLASH_5717VENDOR_ATMEL_MDB021D:
@@ -12171,8 +12167,8 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12171 case FLASH_5717VENDOR_ST_25USPT: 12167 case FLASH_5717VENDOR_ST_25USPT:
12172 case FLASH_5717VENDOR_ST_45USPT: 12168 case FLASH_5717VENDOR_ST_45USPT:
12173 tp->nvram_jedecnum = JEDEC_ST; 12169 tp->nvram_jedecnum = JEDEC_ST;
12174 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12170 tg3_flag_set(tp, NVRAM_BUFFERED);
12175 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12171 tg3_flag_set(tp, FLASH);
12176 12172
12177 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 12173 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12178 case FLASH_5717VENDOR_ST_M_M25PE20: 12174 case FLASH_5717VENDOR_ST_M_M25PE20:
@@ -12189,13 +12185,13 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12189 } 12185 }
12190 break; 12186 break;
12191 default: 12187 default:
12192 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; 12188 tg3_flag_set(tp, NO_NVRAM);
12193 return; 12189 return;
12194 } 12190 }
12195 12191
12196 tg3_nvram_get_pagesize(tp, nvcfg1); 12192 tg3_nvram_get_pagesize(tp, nvcfg1);
12197 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) 12193 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12198 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 12194 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12199} 12195}
12200 12196
12201static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) 12197static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
@@ -12209,7 +12205,7 @@ static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12209 case FLASH_5720_EEPROM_HD: 12205 case FLASH_5720_EEPROM_HD:
12210 case FLASH_5720_EEPROM_LD: 12206 case FLASH_5720_EEPROM_LD:
12211 tp->nvram_jedecnum = JEDEC_ATMEL; 12207 tp->nvram_jedecnum = JEDEC_ATMEL;
12212 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12208 tg3_flag_set(tp, NVRAM_BUFFERED);
12213 12209
12214 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 12210 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12215 tw32(NVRAM_CFG1, nvcfg1); 12211 tw32(NVRAM_CFG1, nvcfg1);
@@ -12231,8 +12227,8 @@ static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12231 case FLASH_5720VENDOR_A_ATMEL_DB081D: 12227 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12232 case FLASH_5720VENDOR_ATMEL_45USPT: 12228 case FLASH_5720VENDOR_ATMEL_45USPT:
12233 tp->nvram_jedecnum = JEDEC_ATMEL; 12229 tp->nvram_jedecnum = JEDEC_ATMEL;
12234 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12230 tg3_flag_set(tp, NVRAM_BUFFERED);
12235 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12231 tg3_flag_set(tp, FLASH);
12236 12232
12237 switch (nvmpinstrp) { 12233 switch (nvmpinstrp) {
12238 case FLASH_5720VENDOR_M_ATMEL_DB021D: 12234 case FLASH_5720VENDOR_M_ATMEL_DB021D:
@@ -12273,8 +12269,8 @@ static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12273 case FLASH_5720VENDOR_ST_25USPT: 12269 case FLASH_5720VENDOR_ST_25USPT:
12274 case FLASH_5720VENDOR_ST_45USPT: 12270 case FLASH_5720VENDOR_ST_45USPT:
12275 tp->nvram_jedecnum = JEDEC_ST; 12271 tp->nvram_jedecnum = JEDEC_ST;
12276 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 12272 tg3_flag_set(tp, NVRAM_BUFFERED);
12277 tp->tg3_flags2 |= TG3_FLG2_FLASH; 12273 tg3_flag_set(tp, FLASH);
12278 12274
12279 switch (nvmpinstrp) { 12275 switch (nvmpinstrp) {
12280 case FLASH_5720VENDOR_M_ST_M25PE20: 12276 case FLASH_5720VENDOR_M_ST_M25PE20:
@@ -12301,13 +12297,13 @@ static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12301 } 12297 }
12302 break; 12298 break;
12303 default: 12299 default:
12304 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; 12300 tg3_flag_set(tp, NO_NVRAM);
12305 return; 12301 return;
12306 } 12302 }
12307 12303
12308 tg3_nvram_get_pagesize(tp, nvcfg1); 12304 tg3_nvram_get_pagesize(tp, nvcfg1);
12309 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) 12305 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12310 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 12306 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12311} 12307}
12312 12308
12313/* Chips other than 5700/5701 use the NVRAM for fetching info. */ 12309/* Chips other than 5700/5701 use the NVRAM for fetching info. */
@@ -12327,7 +12323,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
12327 12323
12328 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && 12324 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12329 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 12325 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12330 tp->tg3_flags |= TG3_FLAG_NVRAM; 12326 tg3_flag_set(tp, NVRAM);
12331 12327
12332 if (tg3_nvram_lock(tp)) { 12328 if (tg3_nvram_lock(tp)) {
12333 netdev_warn(tp->dev, 12329 netdev_warn(tp->dev,
@@ -12369,7 +12365,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
12369 tg3_nvram_unlock(tp); 12365 tg3_nvram_unlock(tp);
12370 12366
12371 } else { 12367 } else {
12372 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 12368 tg3_flag_clear(tp, NVRAM);
12369 tg3_flag_clear(tp, NVRAM_BUFFERED);
12373 12370
12374 tg3_get_eeprom_size(tp); 12371 tg3_get_eeprom_size(tp);
12375 } 12372 }
@@ -12552,7 +12549,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12552 nvram_cmd |= NVRAM_CMD_LAST; 12549 nvram_cmd |= NVRAM_CMD_LAST;
12553 12550
12554 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && 12551 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12555 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && 12552 !tg3_flag(tp, 5755_PLUS) &&
12556 (tp->nvram_jedecnum == JEDEC_ST) && 12553 (tp->nvram_jedecnum == JEDEC_ST) &&
12557 (nvram_cmd & NVRAM_CMD_FIRST)) { 12554 (nvram_cmd & NVRAM_CMD_FIRST)) {
12558 12555
@@ -12562,7 +12559,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12562 12559
12563 break; 12560 break;
12564 } 12561 }
12565 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { 12562 if (!tg3_flag(tp, FLASH)) {
12566 /* We always do complete word writes to eeprom. */ 12563 /* We always do complete word writes to eeprom. */
12567 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); 12564 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12568 } 12565 }
@@ -12578,13 +12575,13 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12578{ 12575{
12579 int ret; 12576 int ret;
12580 12577
12581 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { 12578 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12582 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & 12579 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12583 ~GRC_LCLCTRL_GPIO_OUTPUT1); 12580 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12584 udelay(40); 12581 udelay(40);
12585 } 12582 }
12586 12583
12587 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { 12584 if (!tg3_flag(tp, NVRAM)) {
12588 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); 12585 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12589 } else { 12586 } else {
12590 u32 grc_mode; 12587 u32 grc_mode;
@@ -12594,16 +12591,13 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12594 return ret; 12591 return ret;
12595 12592
12596 tg3_enable_nvram_access(tp); 12593 tg3_enable_nvram_access(tp);
12597 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 12594 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12598 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12599 tw32(NVRAM_WRITE1, 0x406); 12595 tw32(NVRAM_WRITE1, 0x406);
12600 12596
12601 grc_mode = tr32(GRC_MODE); 12597 grc_mode = tr32(GRC_MODE);
12602 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); 12598 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12603 12599
12604 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || 12600 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12605 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12606
12607 ret = tg3_nvram_write_block_buffered(tp, offset, len, 12601 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12608 buf); 12602 buf);
12609 } else { 12603 } else {
@@ -12618,7 +12612,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12618 tg3_nvram_unlock(tp); 12612 tg3_nvram_unlock(tp);
12619 } 12613 }
12620 12614
12621 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { 12615 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12622 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 12616 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12623 udelay(40); 12617 udelay(40);
12624 } 12618 }
@@ -12740,19 +12734,20 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12740 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 12734 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12741 12735
12742 /* Assume an onboard device and WOL capable by default. */ 12736 /* Assume an onboard device and WOL capable by default. */
12743 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; 12737 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12738 tg3_flag_set(tp, WOL_CAP);
12744 12739
12745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 12740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12746 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { 12741 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12747 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; 12742 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12748 tp->tg3_flags2 |= TG3_FLG2_IS_NIC; 12743 tg3_flag_set(tp, IS_NIC);
12749 } 12744 }
12750 val = tr32(VCPU_CFGSHDW); 12745 val = tr32(VCPU_CFGSHDW);
12751 if (val & VCPU_CFGSHDW_ASPM_DBNC) 12746 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12752 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; 12747 tg3_flag_set(tp, ASPM_WORKAROUND);
12753 if ((val & VCPU_CFGSHDW_WOL_ENABLE) && 12748 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12754 (val & VCPU_CFGSHDW_WOL_MAGPKT)) 12749 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12755 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 12750 tg3_flag_set(tp, WOL_ENABLE);
12756 goto done; 12751 goto done;
12757 } 12752 }
12758 12753
@@ -12793,13 +12788,13 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12793 12788
12794 tp->phy_id = eeprom_phy_id; 12789 tp->phy_id = eeprom_phy_id;
12795 if (eeprom_phy_serdes) { 12790 if (eeprom_phy_serdes) {
12796 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 12791 if (!tg3_flag(tp, 5705_PLUS))
12797 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; 12792 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12798 else 12793 else
12799 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; 12794 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12800 } 12795 }
12801 12796
12802 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 12797 if (tg3_flag(tp, 5750_PLUS))
12803 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | 12798 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12804 SHASTA_EXT_LED_MODE_MASK); 12799 SHASTA_EXT_LED_MODE_MASK);
12805 else 12800 else
@@ -12859,34 +12854,34 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12859 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 12854 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12860 12855
12861 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { 12856 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12862 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 12857 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12863 if ((tp->pdev->subsystem_vendor == 12858 if ((tp->pdev->subsystem_vendor ==
12864 PCI_VENDOR_ID_ARIMA) && 12859 PCI_VENDOR_ID_ARIMA) &&
12865 (tp->pdev->subsystem_device == 0x205a || 12860 (tp->pdev->subsystem_device == 0x205a ||
12866 tp->pdev->subsystem_device == 0x2063)) 12861 tp->pdev->subsystem_device == 0x2063))
12867 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; 12862 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12868 } else { 12863 } else {
12869 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; 12864 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12870 tp->tg3_flags2 |= TG3_FLG2_IS_NIC; 12865 tg3_flag_set(tp, IS_NIC);
12871 } 12866 }
12872 12867
12873 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 12868 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12874 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 12869 tg3_flag_set(tp, ENABLE_ASF);
12875 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 12870 if (tg3_flag(tp, 5750_PLUS))
12876 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 12871 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
12877 } 12872 }
12878 12873
12879 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && 12874 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12880 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) 12875 tg3_flag(tp, 5750_PLUS))
12881 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; 12876 tg3_flag_set(tp, ENABLE_APE);
12882 12877
12883 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && 12878 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12884 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) 12879 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12885 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; 12880 tg3_flag_clear(tp, WOL_CAP);
12886 12881
12887 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && 12882 if (tg3_flag(tp, WOL_CAP) &&
12888 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) 12883 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12889 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 12884 tg3_flag_set(tp, WOL_ENABLE);
12890 12885
12891 if (cfg2 & (1 << 17)) 12886 if (cfg2 & (1 << 17))
12892 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; 12887 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
@@ -12896,33 +12891,33 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12896 if (cfg2 & (1 << 18)) 12891 if (cfg2 & (1 << 18))
12897 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; 12892 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12898 12893
12899 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) || 12894 if ((tg3_flag(tp, 57765_PLUS) ||
12900 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && 12895 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12901 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) && 12896 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12902 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) 12897 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12903 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; 12898 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12904 12899
12905 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 12900 if (tg3_flag(tp, PCI_EXPRESS) &&
12906 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && 12901 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12907 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { 12902 !tg3_flag(tp, 57765_PLUS)) {
12908 u32 cfg3; 12903 u32 cfg3;
12909 12904
12910 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); 12905 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12911 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) 12906 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12912 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; 12907 tg3_flag_set(tp, ASPM_WORKAROUND);
12913 } 12908 }
12914 12909
12915 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) 12910 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12916 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; 12911 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
12917 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) 12912 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12918 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; 12913 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
12919 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) 12914 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12920 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; 12915 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
12921 } 12916 }
12922done: 12917done:
12923 if (tp->tg3_flags & TG3_FLAG_WOL_CAP) 12918 if (tg3_flag(tp, WOL_CAP))
12924 device_set_wakeup_enable(&tp->pdev->dev, 12919 device_set_wakeup_enable(&tp->pdev->dev,
12925 tp->tg3_flags & TG3_FLAG_WOL_ENABLE); 12920 tg3_flag(tp, WOL_ENABLE));
12926 else 12921 else
12927 device_set_wakeup_capable(&tp->pdev->dev, false); 12922 device_set_wakeup_capable(&tp->pdev->dev, false);
12928} 12923}
@@ -13012,18 +13007,17 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
13012 int err; 13007 int err;
13013 13008
13014 /* flow control autonegotiation is default behavior */ 13009 /* flow control autonegotiation is default behavior */
13015 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 13010 tg3_flag_set(tp, PAUSE_AUTONEG);
13016 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 13011 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13017 13012
13018 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) 13013 if (tg3_flag(tp, USE_PHYLIB))
13019 return tg3_phy_init(tp); 13014 return tg3_phy_init(tp);
13020 13015
13021 /* Reading the PHY ID register can conflict with ASF 13016 /* Reading the PHY ID register can conflict with ASF
13022 * firmware access to the PHY hardware. 13017 * firmware access to the PHY hardware.
13023 */ 13018 */
13024 err = 0; 13019 err = 0;
13025 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 13020 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13026 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
13027 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; 13021 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13028 } else { 13022 } else {
13029 /* Now read the physical PHY_ID from the chip and verify 13023 /* Now read the physical PHY_ID from the chip and verify
@@ -13079,8 +13073,8 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
13079 tg3_phy_init_link_config(tp); 13073 tg3_phy_init_link_config(tp);
13080 13074
13081 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && 13075 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13082 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && 13076 !tg3_flag(tp, ENABLE_APE) &&
13083 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 13077 !tg3_flag(tp, ENABLE_ASF)) {
13084 u32 bmsr, adv_reg, tg3_ctrl, mask; 13078 u32 bmsr, adv_reg, tg3_ctrl, mask;
13085 13079
13086 tg3_readphy(tp, MII_BMSR, &bmsr); 13080 tg3_readphy(tp, MII_BMSR, &bmsr);
@@ -13399,7 +13393,7 @@ static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13399 if (offset == TG3_NVM_DIR_END) 13393 if (offset == TG3_NVM_DIR_END)
13400 return; 13394 return;
13401 13395
13402 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) 13396 if (!tg3_flag(tp, 5705_PLUS))
13403 start = 0x08000000; 13397 start = 0x08000000;
13404 else if (tg3_nvram_read(tp, offset - 4, &start)) 13398 else if (tg3_nvram_read(tp, offset - 4, &start))
13405 return; 13399 return;
@@ -13439,8 +13433,7 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13439 u32 apedata; 13433 u32 apedata;
13440 char *fwtype; 13434 char *fwtype;
13441 13435
13442 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || 13436 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13443 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13444 return; 13437 return;
13445 13438
13446 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); 13439 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
@@ -13454,7 +13447,7 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13454 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); 13447 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13455 13448
13456 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { 13449 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13457 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI; 13450 tg3_flag_set(tp, APE_HAS_NCSI);
13458 fwtype = "NCSI"; 13451 fwtype = "NCSI";
13459 } else { 13452 } else {
13460 fwtype = "DASH"; 13453 fwtype = "DASH";
@@ -13478,7 +13471,7 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13478 if (tp->fw_ver[0] != 0) 13471 if (tp->fw_ver[0] != 0)
13479 vpd_vers = true; 13472 vpd_vers = true;
13480 13473
13481 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { 13474 if (tg3_flag(tp, NO_NVRAM)) {
13482 strcat(tp->fw_ver, "sb"); 13475 strcat(tp->fw_ver, "sb");
13483 return; 13476 return;
13484 } 13477 }
@@ -13495,8 +13488,7 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13495 else 13488 else
13496 return; 13489 return;
13497 13490
13498 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 13491 if (!tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || vpd_vers)
13499 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13500 goto done; 13492 goto done;
13501 13493
13502 tg3_read_mgmtfw_ver(tp); 13494 tg3_read_mgmtfw_ver(tp);
@@ -13509,10 +13501,9 @@ static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13509 13501
13510static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) 13502static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13511{ 13503{
13512 if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) 13504 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13513 return TG3_RX_RET_MAX_SIZE_5717; 13505 return TG3_RX_RET_MAX_SIZE_5717;
13514 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && 13506 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13515 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13516 return TG3_RX_RET_MAX_SIZE_5700; 13507 return TG3_RX_RET_MAX_SIZE_5700;
13517 else 13508 else
13518 return TG3_RX_RET_MAX_SIZE_5705; 13509 return TG3_RX_RET_MAX_SIZE_5705;
@@ -13638,8 +13629,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13638 if (bridge->subordinate && 13629 if (bridge->subordinate &&
13639 (bridge->subordinate->number == 13630 (bridge->subordinate->number ==
13640 tp->pdev->bus->number)) { 13631 tp->pdev->bus->number)) {
13641 13632 tg3_flag_set(tp, ICH_WORKAROUND);
13642 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13643 pci_dev_put(bridge); 13633 pci_dev_put(bridge);
13644 break; 13634 break;
13645 } 13635 }
@@ -13671,7 +13661,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13671 tp->pdev->bus->number) && 13661 tp->pdev->bus->number) &&
13672 (bridge->subordinate->subordinate >= 13662 (bridge->subordinate->subordinate >=
13673 tp->pdev->bus->number)) { 13663 tp->pdev->bus->number)) {
13674 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; 13664 tg3_flag_set(tp, 5701_DMA_BUG);
13675 pci_dev_put(bridge); 13665 pci_dev_put(bridge);
13676 break; 13666 break;
13677 } 13667 }
@@ -13686,8 +13676,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13686 */ 13676 */
13687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || 13677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { 13678 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13689 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; 13679 tg3_flag_set(tp, 5780_CLASS);
13690 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; 13680 tg3_flag_set(tp, 40BIT_DMA_BUG);
13691 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); 13681 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13692 } else { 13682 } else {
13693 struct pci_dev *bridge = NULL; 13683 struct pci_dev *bridge = NULL;
@@ -13701,7 +13691,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13701 tp->pdev->bus->number) && 13691 tp->pdev->bus->number) &&
13702 (bridge->subordinate->subordinate >= 13692 (bridge->subordinate->subordinate >=
13703 tp->pdev->bus->number)) { 13693 tp->pdev->bus->number)) {
13704 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; 13694 tg3_flag_set(tp, 40BIT_DMA_BUG);
13705 pci_dev_put(bridge); 13695 pci_dev_put(bridge);
13706 break; 13696 break;
13707 } 13697 }
@@ -13723,11 +13713,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 13713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13724 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 13714 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13725 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) 13715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13726 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; 13716 tg3_flag_set(tp, 5717_PLUS);
13727 13717
13728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || 13718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13729 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) 13719 tg3_flag(tp, 5717_PLUS))
13730 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS; 13720 tg3_flag_set(tp, 57765_PLUS);
13731 13721
13732 /* Intentionally exclude ASIC_REV_5906 */ 13722 /* Intentionally exclude ASIC_REV_5906 */
13733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 13723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
@@ -13736,19 +13726,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 13726 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 13727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13738 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 13728 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13739 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) 13729 tg3_flag(tp, 57765_PLUS))
13740 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; 13730 tg3_flag_set(tp, 5755_PLUS);
13741 13731
13742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 13732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13743 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || 13733 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13744 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || 13734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13745 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || 13735 tg3_flag(tp, 5755_PLUS) ||
13746 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 13736 tg3_flag(tp, 5780_CLASS))
13747 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 13737 tg3_flag_set(tp, 5750_PLUS);
13748 13738
13749 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || 13739 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13750 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) 13740 tg3_flag(tp, 5750_PLUS))
13751 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; 13741 tg3_flag_set(tp, 5705_PLUS);
13752 13742
13753 /* 5700 B0 chips do not support checksumming correctly due 13743 /* 5700 B0 chips do not support checksumming correctly due
13754 * to hardware bugs. 13744 * to hardware bugs.
@@ -13756,7 +13746,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13756 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { 13746 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13757 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 13747 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13758 13748
13759 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 13749 if (tg3_flag(tp, 5755_PLUS))
13760 features |= NETIF_F_IPV6_CSUM; 13750 features |= NETIF_F_IPV6_CSUM;
13761 tp->dev->features |= features; 13751 tp->dev->features |= features;
13762 tp->dev->hw_features |= features; 13752 tp->dev->hw_features |= features;
@@ -13766,20 +13756,21 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13766 /* Determine TSO capabilities */ 13756 /* Determine TSO capabilities */
13767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) 13757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13768 ; /* Do nothing. HW bug. */ 13758 ; /* Do nothing. HW bug. */
13769 else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) 13759 else if (tg3_flag(tp, 57765_PLUS))
13770 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; 13760 tg3_flag_set(tp, HW_TSO_3);
13771 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || 13761 else if (tg3_flag(tp, 5755_PLUS) ||
13772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 13762 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13773 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; 13763 tg3_flag_set(tp, HW_TSO_2);
13774 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 13764 else if (tg3_flag(tp, 5750_PLUS)) {
13775 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; 13765 tg3_flag_set(tp, HW_TSO_1);
13766 tg3_flag_set(tp, TSO_BUG);
13776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && 13767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13777 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) 13768 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13778 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; 13769 tg3_flag_clear(tp, TSO_BUG);
13779 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && 13770 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13780 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && 13771 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13781 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { 13772 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13782 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; 13773 tg3_flag_set(tp, TSO_BUG);
13783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) 13774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13784 tp->fw_needed = FIRMWARE_TG3TSO5; 13775 tp->fw_needed = FIRMWARE_TG3TSO5;
13785 else 13776 else
@@ -13788,22 +13779,22 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13788 13779
13789 tp->irq_max = 1; 13780 tp->irq_max = 1;
13790 13781
13791 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 13782 if (tg3_flag(tp, 5750_PLUS)) {
13792 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; 13783 tg3_flag_set(tp, SUPPORT_MSI);
13793 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || 13784 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13794 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || 13785 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13795 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && 13786 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13796 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && 13787 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13797 tp->pdev_peer == tp->pdev)) 13788 tp->pdev_peer == tp->pdev))
13798 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; 13789 tg3_flag_clear(tp, SUPPORT_MSI);
13799 13790
13800 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || 13791 if (tg3_flag(tp, 5755_PLUS) ||
13801 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 13792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13802 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; 13793 tg3_flag_set(tp, 1SHOT_MSI);
13803 } 13794 }
13804 13795
13805 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { 13796 if (tg3_flag(tp, 57765_PLUS)) {
13806 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; 13797 tg3_flag_set(tp, SUPPORT_MSIX);
13807 tp->irq_max = TG3_IRQ_MAX_VECS; 13798 tp->irq_max = TG3_IRQ_MAX_VECS;
13808 } 13799 }
13809 } 13800 }
@@ -13811,23 +13802,23 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 13802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13812 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 13803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 13804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13814 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; 13805 tg3_flag_set(tp, SHORT_DMA_BUG);
13815 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { 13806 else if (!tg3_flag(tp, 5755_PLUS)) {
13816 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; 13807 tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
13817 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; 13808 tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
13818 } 13809 }
13819 13810
13820 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) 13811 if (tg3_flag(tp, 5717_PLUS))
13821 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP; 13812 tg3_flag_set(tp, LRG_PROD_RING_CAP);
13822 13813
13823 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) && 13814 if (tg3_flag(tp, 57765_PLUS) &&
13824 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719) 13815 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13825 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; 13816 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
13826 13817
13827 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 13818 if (!tg3_flag(tp, 5705_PLUS) ||
13828 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 13819 tg3_flag(tp, 5780_CLASS) ||
13829 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) 13820 tg3_flag(tp, USE_JUMBO_BDFLAG))
13830 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; 13821 tg3_flag_set(tp, JUMBO_CAPABLE);
13831 13822
13832 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 13823 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13833 &pci_state_reg); 13824 &pci_state_reg);
@@ -13836,7 +13827,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13836 if (tp->pcie_cap != 0) { 13827 if (tp->pcie_cap != 0) {
13837 u16 lnkctl; 13828 u16 lnkctl;
13838 13829
13839 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 13830 tg3_flag_set(tp, PCI_EXPRESS);
13840 13831
13841 tp->pcie_readrq = 4096; 13832 tp->pcie_readrq = 4096;
13842 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 13833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
@@ -13850,19 +13841,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13850 &lnkctl); 13841 &lnkctl);
13851 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { 13842 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 13843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13853 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; 13844 tg3_flag_clear(tp, HW_TSO_2);
13854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 13845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 13846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13856 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || 13847 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13857 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) 13848 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13858 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; 13849 tg3_flag_set(tp, CLKREQ_BUG);
13859 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { 13850 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13860 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; 13851 tg3_flag_set(tp, L1PLLPD_EN);
13861 } 13852 }
13862 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { 13853 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13863 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 13854 tg3_flag_set(tp, PCI_EXPRESS);
13864 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 13855 } else if (!tg3_flag(tp, 5705_PLUS) ||
13865 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 13856 tg3_flag(tp, 5780_CLASS)) {
13866 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); 13857 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13867 if (!tp->pcix_cap) { 13858 if (!tp->pcix_cap) {
13868 dev_err(&tp->pdev->dev, 13859 dev_err(&tp->pdev->dev,
@@ -13871,7 +13862,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13871 } 13862 }
13872 13863
13873 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) 13864 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13874 tp->tg3_flags |= TG3_FLAG_PCIX_MODE; 13865 tg3_flag_set(tp, PCIX_MODE);
13875 } 13866 }
13876 13867
13877 /* If we have an AMD 762 or VIA K8T800 chipset, write 13868 /* If we have an AMD 762 or VIA K8T800 chipset, write
@@ -13881,8 +13872,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13881 * posted to the chip in order. 13872 * posted to the chip in order.
13882 */ 13873 */
13883 if (pci_dev_present(tg3_write_reorder_chipsets) && 13874 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13884 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) 13875 !tg3_flag(tp, PCI_EXPRESS))
13885 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; 13876 tg3_flag_set(tp, MBOX_WRITE_REORDER);
13886 13877
13887 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, 13878 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13888 &tp->pci_cacheline_sz); 13879 &tp->pci_cacheline_sz);
@@ -13899,17 +13890,17 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13899 /* 5700 BX chips need to have their TX producer index 13890 /* 5700 BX chips need to have their TX producer index
13900 * mailboxes written twice to workaround a bug. 13891 * mailboxes written twice to workaround a bug.
13901 */ 13892 */
13902 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; 13893 tg3_flag_set(tp, TXD_MBOX_HWBUG);
13903 13894
13904 /* If we are in PCI-X mode, enable register write workaround. 13895 /* If we are in PCI-X mode, enable register write workaround.
13905 * 13896 *
13906 * The workaround is to use indirect register accesses 13897 * The workaround is to use indirect register accesses
13907 * for all chip writes not to mailbox registers. 13898 * for all chip writes not to mailbox registers.
13908 */ 13899 */
13909 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { 13900 if (tg3_flag(tp, PCIX_MODE)) {
13910 u32 pm_reg; 13901 u32 pm_reg;
13911 13902
13912 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; 13903 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
13913 13904
13914 /* The chip can have it's power management PCI config 13905 /* The chip can have it's power management PCI config
13915 * space registers clobbered due to this bug. 13906 * space registers clobbered due to this bug.
@@ -13932,9 +13923,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13932 } 13923 }
13933 13924
13934 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) 13925 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13935 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; 13926 tg3_flag_set(tp, PCI_HIGH_SPEED);
13936 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) 13927 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13937 tp->tg3_flags |= TG3_FLAG_PCI_32BIT; 13928 tg3_flag_set(tp, PCI_32BIT);
13938 13929
13939 /* Chip-specific fixup from Broadcom driver */ 13930 /* Chip-specific fixup from Broadcom driver */
13940 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && 13931 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
@@ -13952,10 +13943,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13952 tp->write32_rx_mbox = tg3_write32; 13943 tp->write32_rx_mbox = tg3_write32;
13953 13944
13954 /* Various workaround register access methods */ 13945 /* Various workaround register access methods */
13955 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) 13946 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
13956 tp->write32 = tg3_write_indirect_reg32; 13947 tp->write32 = tg3_write_indirect_reg32;
13957 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || 13948 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13958 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 13949 (tg3_flag(tp, PCI_EXPRESS) &&
13959 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { 13950 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13960 /* 13951 /*
13961 * Back to back register writes can cause problems on these 13952 * Back to back register writes can cause problems on these
@@ -13967,14 +13958,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13967 tp->write32 = tg3_write_flush_reg32; 13958 tp->write32 = tg3_write_flush_reg32;
13968 } 13959 }
13969 13960
13970 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || 13961 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
13971 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13972 tp->write32_tx_mbox = tg3_write32_tx_mbox; 13962 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13973 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) 13963 if (tg3_flag(tp, MBOX_WRITE_REORDER))
13974 tp->write32_rx_mbox = tg3_write_flush_reg32; 13964 tp->write32_rx_mbox = tg3_write_flush_reg32;
13975 } 13965 }
13976 13966
13977 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { 13967 if (tg3_flag(tp, ICH_WORKAROUND)) {
13978 tp->read32 = tg3_read_indirect_reg32; 13968 tp->read32 = tg3_read_indirect_reg32;
13979 tp->write32 = tg3_write_indirect_reg32; 13969 tp->write32 = tg3_write_indirect_reg32;
13980 tp->read32_mbox = tg3_read_indirect_mbox; 13970 tp->read32_mbox = tg3_read_indirect_mbox;
@@ -13997,13 +13987,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13997 } 13987 }
13998 13988
13999 if (tp->write32 == tg3_write_indirect_reg32 || 13989 if (tp->write32 == tg3_write_indirect_reg32 ||
14000 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && 13990 (tg3_flag(tp, PCIX_MODE) &&
14001 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 13991 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) 13992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14003 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; 13993 tg3_flag_set(tp, SRAM_USE_CONFIG);
14004 13994
14005 /* Get eeprom hw config before calling tg3_set_power_state(). 13995 /* Get eeprom hw config before calling tg3_set_power_state().
14006 * In particular, the TG3_FLG2_IS_NIC flag must be 13996 * In particular, the TG3_FLAG_IS_NIC flag must be
14007 * determined before calling tg3_set_power_state() so that 13997 * determined before calling tg3_set_power_state() so that
14008 * we know whether or not to switch out of Vaux power. 13998 * we know whether or not to switch out of Vaux power.
14009 * When the flag is set, it means that GPIO1 is used for eeprom 13999 * When the flag is set, it means that GPIO1 is used for eeprom
@@ -14012,7 +14002,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14012 */ 14002 */
14013 tg3_get_eeprom_hw_cfg(tp); 14003 tg3_get_eeprom_hw_cfg(tp);
14014 14004
14015 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 14005 if (tg3_flag(tp, ENABLE_APE)) {
14016 /* Allow reads and writes to the 14006 /* Allow reads and writes to the
14017 * APE register and memory space. 14007 * APE register and memory space.
14018 */ 14008 */
@@ -14027,8 +14017,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 14017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 14018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 14019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14030 (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) 14020 tg3_flag(tp, 57765_PLUS))
14031 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 14021 tg3_flag_set(tp, CPMU_PRESENT);
14032 14022
14033 /* Set up tp->grc_local_ctrl before calling tg3_power_up(). 14023 /* Set up tp->grc_local_ctrl before calling tg3_power_up().
14034 * GPIO1 driven high will bring 5700's external PHY out of reset. 14024 * GPIO1 driven high will bring 5700's external PHY out of reset.
@@ -14036,7 +14026,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14036 */ 14026 */
14037 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; 14027 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14038 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || 14028 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
14039 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) 14029 tg3_flag(tp, EEPROM_WRITE_PROT))
14040 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | 14030 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14041 GRC_LCLCTRL_GPIO_OUTPUT1); 14031 GRC_LCLCTRL_GPIO_OUTPUT1);
14042 /* Unused GPIO3 must be driven as output on 5752 because there 14032 /* Unused GPIO3 must be driven as output on 5752 because there
@@ -14054,7 +14044,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14054 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { 14044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14055 /* Turn off the debug UART. */ 14045 /* Turn off the debug UART. */
14056 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; 14046 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14057 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) 14047 if (tg3_flag(tp, IS_NIC))
14058 /* Keep VMain power. */ 14048 /* Keep VMain power. */
14059 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | 14049 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14060 GRC_LCLCTRL_GPIO_OUTPUT0; 14050 GRC_LCLCTRL_GPIO_OUTPUT0;
@@ -14070,18 +14060,17 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14070 /* Derive initial jumbo mode from MTU assigned in 14060 /* Derive initial jumbo mode from MTU assigned in
14071 * ether_setup() via the alloc_etherdev() call 14061 * ether_setup() via the alloc_etherdev() call
14072 */ 14062 */
14073 if (tp->dev->mtu > ETH_DATA_LEN && 14063 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14074 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) 14064 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14075 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
14076 14065
14077 /* Determine WakeOnLan speed to use. */ 14066 /* Determine WakeOnLan speed to use. */
14078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 14067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14079 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || 14068 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14080 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || 14069 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14081 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { 14070 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14082 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); 14071 tg3_flag_clear(tp, WOL_SPEED_100MB);
14083 } else { 14072 } else {
14084 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; 14073 tg3_flag_set(tp, WOL_SPEED_100MB);
14085 } 14074 }
14086 14075
14087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 14076 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
@@ -14102,11 +14091,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14102 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) 14091 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14103 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; 14092 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14104 14093
14105 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 14094 if (tg3_flag(tp, 5705_PLUS) &&
14106 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && 14095 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14107 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && 14096 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && 14097 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14109 !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) { 14098 !tg3_flag(tp, 57765_PLUS)) {
14110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 14099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || 14100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 14101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -14127,7 +14116,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14127 tp->phy_otp = TG3_OTP_DEFAULT; 14116 tp->phy_otp = TG3_OTP_DEFAULT;
14128 } 14117 }
14129 14118
14130 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) 14119 if (tg3_flag(tp, CPMU_PRESENT))
14131 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; 14120 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14132 else 14121 else
14133 tp->mi_mode = MAC_MI_MODE_BASE; 14122 tp->mi_mode = MAC_MI_MODE_BASE;
@@ -14147,7 +14136,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14147 14136
14148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 14137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) 14138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14150 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; 14139 tg3_flag_set(tp, USE_PHYLIB);
14151 14140
14152 err = tg3_mdio_init(tp); 14141 err = tg3_mdio_init(tp);
14153 if (err) 14142 if (err)
@@ -14174,7 +14163,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14174 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 14163 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14175 &pci_state_reg); 14164 &pci_state_reg);
14176 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && 14165 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14177 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { 14166 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14178 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); 14167 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14179 14168
14180 if (chiprevid == CHIPREV_ID_5701_A0 || 14169 if (chiprevid == CHIPREV_ID_5701_A0 ||
@@ -14193,7 +14182,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14193 writel(0x00000000, sram_base + 4); 14182 writel(0x00000000, sram_base + 4);
14194 writel(0xffffffff, sram_base + 4); 14183 writel(0xffffffff, sram_base + 4);
14195 if (readl(sram_base) != 0x00000000) 14184 if (readl(sram_base) != 0x00000000)
14196 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; 14185 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14197 } 14186 }
14198 } 14187 }
14199 14188
@@ -14206,12 +14195,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 14195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14207 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || 14196 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14208 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) 14197 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14209 tp->tg3_flags2 |= TG3_FLG2_IS_5788; 14198 tg3_flag_set(tp, IS_5788);
14210 14199
14211 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && 14200 if (!tg3_flag(tp, IS_5788) &&
14212 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) 14201 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
14213 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; 14202 tg3_flag_set(tp, TAGGED_STATUS);
14214 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { 14203 if (tg3_flag(tp, TAGGED_STATUS)) {
14215 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | 14204 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14216 HOSTCC_MODE_CLRTICK_TXBD); 14205 HOSTCC_MODE_CLRTICK_TXBD);
14217 14206
@@ -14221,7 +14210,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14221 } 14210 }
14222 14211
14223 /* Preserve the APE MAC_MODE bits */ 14212 /* Preserve the APE MAC_MODE bits */
14224 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) 14213 if (tg3_flag(tp, ENABLE_APE))
14225 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; 14214 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14226 else 14215 else
14227 tp->mac_mode = TG3_DEF_MAC_MODE; 14216 tp->mac_mode = TG3_DEF_MAC_MODE;
@@ -14268,9 +14257,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14268 * status register in those cases. 14257 * status register in those cases.
14269 */ 14258 */
14270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) 14259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14271 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; 14260 tg3_flag_set(tp, USE_LINKCHG_REG);
14272 else 14261 else
14273 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; 14262 tg3_flag_clear(tp, USE_LINKCHG_REG);
14274 14263
14275 /* The led_ctrl is set during tg3_phy_probe, here we might 14264 /* The led_ctrl is set during tg3_phy_probe, here we might
14276 * have to force the link status polling mechanism based 14265 * have to force the link status polling mechanism based
@@ -14280,19 +14269,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14280 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && 14269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14281 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { 14270 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14282 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; 14271 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14283 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; 14272 tg3_flag_set(tp, USE_LINKCHG_REG);
14284 } 14273 }
14285 14274
14286 /* For all SERDES we poll the MAC status register. */ 14275 /* For all SERDES we poll the MAC status register. */
14287 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) 14276 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14288 tp->tg3_flags |= TG3_FLAG_POLL_SERDES; 14277 tg3_flag_set(tp, POLL_SERDES);
14289 else 14278 else
14290 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; 14279 tg3_flag_clear(tp, POLL_SERDES);
14291 14280
14292 tp->rx_offset = NET_IP_ALIGN; 14281 tp->rx_offset = NET_IP_ALIGN;
14293 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; 14282 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && 14283 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14295 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { 14284 tg3_flag(tp, PCIX_MODE)) {
14296 tp->rx_offset = 0; 14285 tp->rx_offset = 0;
14297#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 14286#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14298 tp->rx_copy_thresh = ~(u16)0; 14287 tp->rx_copy_thresh = ~(u16)0;
@@ -14313,7 +14302,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) 14302 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14314 tp->rx_std_max_post = 8; 14303 tp->rx_std_max_post = 8;
14315 14304
14316 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) 14305 if (tg3_flag(tp, ASPM_WORKAROUND))
14317 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & 14306 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14318 PCIE_PWR_MGMT_L1_THRESH_MSK; 14307 PCIE_PWR_MGMT_L1_THRESH_MSK;
14319 14308
@@ -14361,14 +14350,14 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
14361 14350
14362 mac_offset = 0x7c; 14351 mac_offset = 0x7c;
14363 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || 14352 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14364 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 14353 tg3_flag(tp, 5780_CLASS)) {
14365 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) 14354 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14366 mac_offset = 0xcc; 14355 mac_offset = 0xcc;
14367 if (tg3_nvram_lock(tp)) 14356 if (tg3_nvram_lock(tp))
14368 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); 14357 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14369 else 14358 else
14370 tg3_nvram_unlock(tp); 14359 tg3_nvram_unlock(tp);
14371 } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { 14360 } else if (tg3_flag(tp, 5717_PLUS)) {
14372 if (PCI_FUNC(tp->pdev->devfn) & 1) 14361 if (PCI_FUNC(tp->pdev->devfn) & 1)
14373 mac_offset = 0xcc; 14362 mac_offset = 0xcc;
14374 if (PCI_FUNC(tp->pdev->devfn) > 1) 14363 if (PCI_FUNC(tp->pdev->devfn) > 1)
@@ -14393,7 +14382,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
14393 } 14382 }
14394 if (!addr_ok) { 14383 if (!addr_ok) {
14395 /* Next, try NVRAM. */ 14384 /* Next, try NVRAM. */
14396 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && 14385 if (!tg3_flag(tp, NO_NVRAM) &&
14397 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && 14386 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14398 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { 14387 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14399 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); 14388 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
@@ -14444,7 +14433,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14444 */ 14433 */
14445 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && 14434 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14446 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && 14435 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14447 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) 14436 !tg3_flag(tp, PCI_EXPRESS))
14448 goto out; 14437 goto out;
14449 14438
14450#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) 14439#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
@@ -14457,7 +14446,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14457#endif 14446#endif
14458#endif 14447#endif
14459 14448
14460 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { 14449 if (tg3_flag(tp, 57765_PLUS)) {
14461 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; 14450 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14462 goto out; 14451 goto out;
14463 } 14452 }
@@ -14476,8 +14465,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14476 * other than 5700 and 5701 which do not implement the 14465 * other than 5700 and 5701 which do not implement the
14477 * boundary bits. 14466 * boundary bits.
14478 */ 14467 */
14479 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && 14468 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14480 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14481 switch (cacheline_size) { 14469 switch (cacheline_size) {
14482 case 16: 14470 case 16:
14483 case 32: 14471 case 32:
@@ -14502,7 +14490,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14502 DMA_RWCTRL_WRITE_BNDRY_384_PCIX); 14490 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14503 break; 14491 break;
14504 } 14492 }
14505 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 14493 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14506 switch (cacheline_size) { 14494 switch (cacheline_size) {
14507 case 16: 14495 case 16:
14508 case 32: 14496 case 32:
@@ -14674,13 +14662,13 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14674 14662
14675 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); 14663 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14676 14664
14677 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) 14665 if (tg3_flag(tp, 57765_PLUS))
14678 goto out; 14666 goto out;
14679 14667
14680 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 14668 if (tg3_flag(tp, PCI_EXPRESS)) {
14681 /* DMA read watermark not used on PCIE */ 14669 /* DMA read watermark not used on PCIE */
14682 tp->dma_rwctrl |= 0x00180000; 14670 tp->dma_rwctrl |= 0x00180000;
14683 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { 14671 } else if (!tg3_flag(tp, PCIX_MODE)) {
14684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || 14672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14685 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 14673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14686 tp->dma_rwctrl |= 0x003f0000; 14674 tp->dma_rwctrl |= 0x003f0000;
@@ -14696,7 +14684,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14696 * do the less restrictive ONE_DMA workaround for 14684 * do the less restrictive ONE_DMA workaround for
14697 * better performance. 14685 * better performance.
14698 */ 14686 */
14699 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && 14687 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) 14688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14701 tp->dma_rwctrl |= 0x8000; 14689 tp->dma_rwctrl |= 0x8000;
14702 else if (ccval == 0x6 || ccval == 0x7) 14690 else if (ccval == 0x6 || ccval == 0x7)
@@ -14848,7 +14836,7 @@ out_nofree:
14848 14836
14849static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) 14837static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14850{ 14838{
14851 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) { 14839 if (tg3_flag(tp, 57765_PLUS)) {
14852 tp->bufmgr_config.mbuf_read_dma_low_water = 14840 tp->bufmgr_config.mbuf_read_dma_low_water =
14853 DEFAULT_MB_RDMA_LOW_WATER_5705; 14841 DEFAULT_MB_RDMA_LOW_WATER_5705;
14854 tp->bufmgr_config.mbuf_mac_rx_low_water = 14842 tp->bufmgr_config.mbuf_mac_rx_low_water =
@@ -14862,7 +14850,7 @@ static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14862 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; 14850 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14863 tp->bufmgr_config.mbuf_high_water_jumbo = 14851 tp->bufmgr_config.mbuf_high_water_jumbo =
14864 DEFAULT_MB_HIGH_WATER_JUMBO_57765; 14852 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14865 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 14853 } else if (tg3_flag(tp, 5705_PLUS)) {
14866 tp->bufmgr_config.mbuf_read_dma_low_water = 14854 tp->bufmgr_config.mbuf_read_dma_low_water =
14867 DEFAULT_MB_RDMA_LOW_WATER_5705; 14855 DEFAULT_MB_RDMA_LOW_WATER_5705;
14868 tp->bufmgr_config.mbuf_mac_rx_low_water = 14856 tp->bufmgr_config.mbuf_mac_rx_low_water =
@@ -14935,10 +14923,10 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
14935 14923
14936static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) 14924static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14937{ 14925{
14938 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 14926 if (tg3_flag(tp, PCI_EXPRESS)) {
14939 strcpy(str, "PCI Express"); 14927 strcpy(str, "PCI Express");
14940 return str; 14928 return str;
14941 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { 14929 } else if (tg3_flag(tp, PCIX_MODE)) {
14942 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; 14930 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14943 14931
14944 strcpy(str, "PCIX:"); 14932 strcpy(str, "PCIX:");
@@ -14957,12 +14945,12 @@ static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14957 strcat(str, "100MHz"); 14945 strcat(str, "100MHz");
14958 } else { 14946 } else {
14959 strcpy(str, "PCI:"); 14947 strcpy(str, "PCI:");
14960 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) 14948 if (tg3_flag(tp, PCI_HIGH_SPEED))
14961 strcat(str, "66MHz"); 14949 strcat(str, "66MHz");
14962 else 14950 else
14963 strcat(str, "33MHz"); 14951 strcat(str, "33MHz");
14964 } 14952 }
14965 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) 14953 if (tg3_flag(tp, PCI_32BIT))
14966 strcat(str, ":32-bit"); 14954 strcat(str, ":32-bit");
14967 else 14955 else
14968 strcat(str, ":64-bit"); 14956 strcat(str, ":64-bit");
@@ -15021,7 +15009,7 @@ static void __devinit tg3_init_coal(struct tg3 *tp)
15021 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; 15009 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15022 } 15010 }
15023 15011
15024 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 15012 if (tg3_flag(tp, 5705_PLUS)) {
15025 ec->rx_coalesce_usecs_irq = 0; 15013 ec->rx_coalesce_usecs_irq = 0;
15026 ec->tx_coalesce_usecs_irq = 0; 15014 ec->tx_coalesce_usecs_irq = 0;
15027 ec->stats_block_coalesce_usecs = 0; 15015 ec->stats_block_coalesce_usecs = 0;
@@ -15166,8 +15154,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15166 goto err_out_iounmap; 15154 goto err_out_iounmap;
15167 } 15155 }
15168 15156
15169 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && 15157 if (tg3_flag(tp, 5755_PLUS) && !tg3_flag(tp, 5717_PLUS))
15170 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
15171 dev->netdev_ops = &tg3_netdev_ops; 15158 dev->netdev_ops = &tg3_netdev_ops;
15172 else 15159 else
15173 dev->netdev_ops = &tg3_netdev_ops_dma_bug; 15160 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
@@ -15179,9 +15166,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15179 * On 64-bit systems without IOMMU, use 64-bit dma_mask and 15166 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15180 * do DMA address check in tg3_start_xmit(). 15167 * do DMA address check in tg3_start_xmit().
15181 */ 15168 */
15182 if (tp->tg3_flags2 & TG3_FLG2_IS_5788) 15169 if (tg3_flag(tp, IS_5788))
15183 persist_dma_mask = dma_mask = DMA_BIT_MASK(32); 15170 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15184 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { 15171 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15185 persist_dma_mask = dma_mask = DMA_BIT_MASK(40); 15172 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15186#ifdef CONFIG_HIGHMEM 15173#ifdef CONFIG_HIGHMEM
15187 dma_mask = DMA_BIT_MASK(64); 15174 dma_mask = DMA_BIT_MASK(64);
@@ -15215,11 +15202,14 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15215 tg3_init_bufmgr_config(tp); 15202 tg3_init_bufmgr_config(tp);
15216 15203
15217 /* Selectively allow TSO based on operating conditions */ 15204 /* Selectively allow TSO based on operating conditions */
15218 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || 15205 if ((tg3_flag(tp, HW_TSO_1) ||
15219 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) 15206 tg3_flag(tp, HW_TSO_2) ||
15220 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 15207 tg3_flag(tp, HW_TSO_3)) ||
15208 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
15209 tg3_flag_set(tp, TSO_CAPABLE);
15221 else { 15210 else {
15222 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); 15211 tg3_flag_clear(tp, TSO_CAPABLE);
15212 tg3_flag_clear(tp, TSO_BUG);
15223 tp->fw_needed = NULL; 15213 tp->fw_needed = NULL;
15224 } 15214 }
15225 15215
@@ -15230,18 +15220,19 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15230 * Firmware TSO on older chips gives lower performance, so it 15220 * Firmware TSO on older chips gives lower performance, so it
15231 * is off by default, but can be enabled using ethtool. 15221 * is off by default, but can be enabled using ethtool.
15232 */ 15222 */
15233 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && 15223 if ((tg3_flag(tp, HW_TSO_1) ||
15224 tg3_flag(tp, HW_TSO_2) ||
15225 tg3_flag(tp, HW_TSO_3)) &&
15234 (dev->features & NETIF_F_IP_CSUM)) 15226 (dev->features & NETIF_F_IP_CSUM))
15235 hw_features |= NETIF_F_TSO; 15227 hw_features |= NETIF_F_TSO;
15236 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || 15228 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15237 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
15238 if (dev->features & NETIF_F_IPV6_CSUM) 15229 if (dev->features & NETIF_F_IPV6_CSUM)
15239 hw_features |= NETIF_F_TSO6; 15230 hw_features |= NETIF_F_TSO6;
15240 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || 15231 if (tg3_flag(tp, HW_TSO_3) ||
15241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 15232 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15242 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && 15233 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15243 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || 15234 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || 15235 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) 15236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15246 hw_features |= NETIF_F_TSO_ECN; 15237 hw_features |= NETIF_F_TSO_ECN;
15247 } 15238 }
@@ -15251,9 +15242,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15251 dev->vlan_features |= hw_features; 15242 dev->vlan_features |= hw_features;
15252 15243
15253 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && 15244 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15254 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && 15245 !tg3_flag(tp, TSO_CAPABLE) &&
15255 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { 15246 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15256 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; 15247 tg3_flag_set(tp, MAX_RXPEND_64);
15257 tp->rx_pending = 63; 15248 tp->rx_pending = 63;
15258 } 15249 }
15259 15250
@@ -15264,7 +15255,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15264 goto err_out_iounmap; 15255 goto err_out_iounmap;
15265 } 15256 }
15266 15257
15267 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 15258 if (tg3_flag(tp, ENABLE_APE)) {
15268 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); 15259 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15269 if (!tp->aperegs) { 15260 if (!tp->aperegs) {
15270 dev_err(&pdev->dev, 15261 dev_err(&pdev->dev,
@@ -15275,7 +15266,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15275 15266
15276 tg3_ape_lock_init(tp); 15267 tg3_ape_lock_init(tp);
15277 15268
15278 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) 15269 if (tg3_flag(tp, ENABLE_ASF))
15279 tg3_read_dash_ver(tp); 15270 tg3_read_dash_ver(tp);
15280 } 15271 }
15281 15272
@@ -15319,7 +15310,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15319 else 15310 else
15320 tnapi->coal_now = HOSTCC_MODE_NOW; 15311 tnapi->coal_now = HOSTCC_MODE_NOW;
15321 15312
15322 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) 15313 if (!tg3_flag(tp, SUPPORT_MSIX))
15323 break; 15314 break;
15324 15315
15325 /* 15316 /*
@@ -15381,10 +15372,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
15381 15372
15382 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", 15373 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15383 (dev->features & NETIF_F_RXCSUM) != 0, 15374 (dev->features & NETIF_F_RXCSUM) != 0,
15384 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, 15375 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15385 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, 15376 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15386 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, 15377 tg3_flag(tp, ENABLE_ASF) != 0,
15387 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); 15378 tg3_flag(tp, TSO_CAPABLE) != 0);
15388 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", 15379 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15389 tp->dma_rwctrl, 15380 tp->dma_rwctrl,
15390 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : 15381 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
@@ -15430,7 +15421,7 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
15430 15421
15431 cancel_work_sync(&tp->reset_task); 15422 cancel_work_sync(&tp->reset_task);
15432 15423
15433 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 15424 if (!tg3_flag(tp, USE_PHYLIB)) {
15434 tg3_phy_fini(tp); 15425 tg3_phy_fini(tp);
15435 tg3_mdio_fini(tp); 15426 tg3_mdio_fini(tp);
15436 } 15427 }
@@ -15476,7 +15467,7 @@ static int tg3_suspend(struct device *device)
15476 15467
15477 tg3_full_lock(tp, 0); 15468 tg3_full_lock(tp, 0);
15478 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 15469 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15479 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 15470 tg3_flag_clear(tp, INIT_COMPLETE);
15480 tg3_full_unlock(tp); 15471 tg3_full_unlock(tp);
15481 15472
15482 err = tg3_power_down_prepare(tp); 15473 err = tg3_power_down_prepare(tp);
@@ -15485,7 +15476,7 @@ static int tg3_suspend(struct device *device)
15485 15476
15486 tg3_full_lock(tp, 0); 15477 tg3_full_lock(tp, 0);
15487 15478
15488 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 15479 tg3_flag_set(tp, INIT_COMPLETE);
15489 err2 = tg3_restart_hw(tp, 1); 15480 err2 = tg3_restart_hw(tp, 1);
15490 if (err2) 15481 if (err2)
15491 goto out; 15482 goto out;
@@ -15520,7 +15511,7 @@ static int tg3_resume(struct device *device)
15520 15511
15521 tg3_full_lock(tp, 0); 15512 tg3_full_lock(tp, 0);
15522 15513
15523 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 15514 tg3_flag_set(tp, INIT_COMPLETE);
15524 err = tg3_restart_hw(tp, 1); 15515 err = tg3_restart_hw(tp, 1);
15525 if (err) 15516 if (err)
15526 goto out; 15517 goto out;
@@ -15575,12 +15566,12 @@ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15575 tg3_netif_stop(tp); 15566 tg3_netif_stop(tp);
15576 15567
15577 del_timer_sync(&tp->timer); 15568 del_timer_sync(&tp->timer);
15578 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 15569 tg3_flag_clear(tp, RESTART_TIMER);
15579 15570
15580 /* Want to make sure that the reset task doesn't run */ 15571 /* Want to make sure that the reset task doesn't run */
15581 cancel_work_sync(&tp->reset_task); 15572 cancel_work_sync(&tp->reset_task);
15582 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; 15573 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15583 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 15574 tg3_flag_clear(tp, RESTART_TIMER);
15584 15575
15585 netif_device_detach(netdev); 15576 netif_device_detach(netdev);
15586 15577
@@ -15665,7 +15656,7 @@ static void tg3_io_resume(struct pci_dev *pdev)
15665 goto done; 15656 goto done;
15666 15657
15667 tg3_full_lock(tp, 0); 15658 tg3_full_lock(tp, 0);
15668 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 15659 tg3_flag_set(tp, INIT_COMPLETE);
15669 err = tg3_restart_hw(tp, 1); 15660 err = tg3_restart_hw(tp, 1);
15670 tg3_full_unlock(tp); 15661 tg3_full_unlock(tp);
15671 if (err) { 15662 if (err) {
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 6f37d2a23544..ce010cd33895 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2816,6 +2816,86 @@ struct tg3_napi {
2816 unsigned int irq_vec; 2816 unsigned int irq_vec;
2817}; 2817};
2818 2818
2819enum TG3_FLAGS {
2820 TG3_FLAG_TAGGED_STATUS = 0,
2821 TG3_FLAG_TXD_MBOX_HWBUG,
2822 TG3_FLAG_USE_LINKCHG_REG,
2823 TG3_FLAG_ERROR_PROCESSED,
2824 TG3_FLAG_ENABLE_ASF,
2825 TG3_FLAG_ASPM_WORKAROUND,
2826 TG3_FLAG_POLL_SERDES,
2827 TG3_FLAG_MBOX_WRITE_REORDER,
2828 TG3_FLAG_PCIX_TARGET_HWBUG,
2829 TG3_FLAG_WOL_SPEED_100MB,
2830 TG3_FLAG_WOL_ENABLE,
2831 TG3_FLAG_EEPROM_WRITE_PROT,
2832 TG3_FLAG_NVRAM,
2833 TG3_FLAG_NVRAM_BUFFERED,
2834 TG3_FLAG_SUPPORT_MSI,
2835 TG3_FLAG_SUPPORT_MSIX,
2836 TG3_FLAG_PCIX_MODE,
2837 TG3_FLAG_PCI_HIGH_SPEED,
2838 TG3_FLAG_PCI_32BIT,
2839 TG3_FLAG_SRAM_USE_CONFIG,
2840 TG3_FLAG_TX_RECOVERY_PENDING,
2841 TG3_FLAG_WOL_CAP,
2842 TG3_FLAG_JUMBO_RING_ENABLE,
2843 TG3_FLAG_PAUSE_AUTONEG,
2844 TG3_FLAG_CPMU_PRESENT,
2845 TG3_FLAG_40BIT_DMA_BUG,
2846 TG3_FLAG_BROKEN_CHECKSUMS,
2847 TG3_FLAG_JUMBO_CAPABLE,
2848 TG3_FLAG_CHIP_RESETTING,
2849 TG3_FLAG_INIT_COMPLETE,
2850 TG3_FLAG_RESTART_TIMER,
2851 TG3_FLAG_TSO_BUG,
2852 TG3_FLAG_IS_5788,
2853 TG3_FLAG_MAX_RXPEND_64,
2854 TG3_FLAG_TSO_CAPABLE,
2855 TG3_FLAG_PCI_EXPRESS,
2856 TG3_FLAG_ASF_NEW_HANDSHAKE,
2857 TG3_FLAG_HW_AUTONEG,
2858 TG3_FLAG_IS_NIC,
2859 TG3_FLAG_FLASH,
2860 TG3_FLAG_HW_TSO_1,
2861 TG3_FLAG_5705_PLUS,
2862 TG3_FLAG_5750_PLUS,
2863 TG3_FLAG_HW_TSO_3,
2864 TG3_FLAG_USING_MSI,
2865 TG3_FLAG_USING_MSIX,
2866 TG3_FLAG_ICH_WORKAROUND,
2867 TG3_FLAG_5780_CLASS,
2868 TG3_FLAG_HW_TSO_2,
2869 TG3_FLAG_1SHOT_MSI,
2870 TG3_FLAG_NO_FWARE_REPORTED,
2871 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
2872 TG3_FLAG_ENABLE_APE,
2873 TG3_FLAG_PROTECTED_NVRAM,
2874 TG3_FLAG_5701_DMA_BUG,
2875 TG3_FLAG_USE_PHYLIB,
2876 TG3_FLAG_MDIOBUS_INITED,
2877 TG3_FLAG_LRG_PROD_RING_CAP,
2878 TG3_FLAG_RGMII_INBAND_DISABLE,
2879 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
2880 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
2881 TG3_FLAG_CLKREQ_BUG,
2882 TG3_FLAG_5755_PLUS,
2883 TG3_FLAG_NO_NVRAM,
2884 TG3_FLAG_ENABLE_RSS,
2885 TG3_FLAG_ENABLE_TSS,
2886 TG3_FLAG_4G_DMA_BNDRY_BUG,
2887 TG3_FLAG_40BIT_DMA_LIMIT_BUG,
2888 TG3_FLAG_SHORT_DMA_BUG,
2889 TG3_FLAG_USE_JUMBO_BDFLAG,
2890 TG3_FLAG_L1PLLPD_EN,
2891 TG3_FLAG_57765_PLUS,
2892 TG3_FLAG_APE_HAS_NCSI,
2893 TG3_FLAG_5717_PLUS,
2894
2895 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
2896 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
2897};
2898
2819struct tg3 { 2899struct tg3 {
2820 /* begin "general, frequently-used members" cacheline section */ 2900 /* begin "general, frequently-used members" cacheline section */
2821 2901
@@ -2839,7 +2919,7 @@ struct tg3 {
2839 /* SMP locking strategy: 2919 /* SMP locking strategy:
2840 * 2920 *
2841 * lock: Held during reset, PHY access, timer, and when 2921 * lock: Held during reset, PHY access, timer, and when
2842 * updating tg3_flags and tg3_flags2. 2922 * updating tg3_flags.
2843 * 2923 *
2844 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 2924 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2845 * netif_tx_lock when it needs to call 2925 * netif_tx_lock when it needs to call
@@ -2896,95 +2976,13 @@ struct tg3 {
2896 struct tg3_ethtool_stats estats; 2976 struct tg3_ethtool_stats estats;
2897 struct tg3_ethtool_stats estats_prev; 2977 struct tg3_ethtool_stats estats_prev;
2898 2978
2979 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
2980
2899 union { 2981 union {
2900 unsigned long phy_crc_errors; 2982 unsigned long phy_crc_errors;
2901 unsigned long last_event_jiffies; 2983 unsigned long last_event_jiffies;
2902 }; 2984 };
2903 2985
2904 u32 tg3_flags;
2905#define TG3_FLAG_TAGGED_STATUS 0x00000001
2906#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2907#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2908#define TG3_FLAG_ERROR_PROCESSED 0x00000010
2909#define TG3_FLAG_ENABLE_ASF 0x00000020
2910#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
2911#define TG3_FLAG_POLL_SERDES 0x00000080
2912#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2913#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2914#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2915#define TG3_FLAG_WOL_ENABLE 0x00000800
2916#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2917#define TG3_FLAG_NVRAM 0x00002000
2918#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2919#define TG3_FLAG_SUPPORT_MSI 0x00008000
2920#define TG3_FLAG_SUPPORT_MSIX 0x00010000
2921#define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
2922 TG3_FLAG_SUPPORT_MSIX)
2923#define TG3_FLAG_PCIX_MODE 0x00020000
2924#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2925#define TG3_FLAG_PCI_32BIT 0x00080000
2926#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2927#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2928#define TG3_FLAG_WOL_CAP 0x00400000
2929#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2930#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2931#define TG3_FLAG_CPMU_PRESENT 0x04000000
2932#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
2933#define TG3_FLAG_JUMBO_CAPABLE 0x20000000
2934#define TG3_FLAG_CHIP_RESETTING 0x40000000
2935#define TG3_FLAG_INIT_COMPLETE 0x80000000
2936 u32 tg3_flags2;
2937#define TG3_FLG2_RESTART_TIMER 0x00000001
2938#define TG3_FLG2_TSO_BUG 0x00000002
2939#define TG3_FLG2_IS_5788 0x00000008
2940#define TG3_FLG2_MAX_RXPEND_64 0x00000010
2941#define TG3_FLG2_TSO_CAPABLE 0x00000020
2942#define TG3_FLG2_PCI_EXPRESS 0x00000200
2943#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2944#define TG3_FLG2_HW_AUTONEG 0x00000800
2945#define TG3_FLG2_IS_NIC 0x00001000
2946#define TG3_FLG2_FLASH 0x00008000
2947#define TG3_FLG2_HW_TSO_1 0x00010000
2948#define TG3_FLG2_5705_PLUS 0x00040000
2949#define TG3_FLG2_5750_PLUS 0x00080000
2950#define TG3_FLG2_HW_TSO_3 0x00100000
2951#define TG3_FLG2_USING_MSI 0x00200000
2952#define TG3_FLG2_USING_MSIX 0x00400000
2953#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
2954 TG3_FLG2_USING_MSIX)
2955#define TG3_FLG2_ICH_WORKAROUND 0x02000000
2956#define TG3_FLG2_5780_CLASS 0x04000000
2957#define TG3_FLG2_HW_TSO_2 0x08000000
2958#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
2959 TG3_FLG2_HW_TSO_2 | \
2960 TG3_FLG2_HW_TSO_3)
2961#define TG3_FLG2_1SHOT_MSI 0x10000000
2962#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2963 u32 tg3_flags3;
2964#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
2965#define TG3_FLG3_ENABLE_APE 0x00000002
2966#define TG3_FLG3_PROTECTED_NVRAM 0x00000004
2967#define TG3_FLG3_5701_DMA_BUG 0x00000008
2968#define TG3_FLG3_USE_PHYLIB 0x00000010
2969#define TG3_FLG3_MDIOBUS_INITED 0x00000020
2970#define TG3_FLG3_LRG_PROD_RING_CAP 0x00000080
2971#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
2972#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2973#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
2974#define TG3_FLG3_CLKREQ_BUG 0x00000800
2975#define TG3_FLG3_5755_PLUS 0x00002000
2976#define TG3_FLG3_NO_NVRAM 0x00004000
2977#define TG3_FLG3_ENABLE_RSS 0x00020000
2978#define TG3_FLG3_ENABLE_TSS 0x00040000
2979#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
2980#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
2981#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
2982#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
2983#define TG3_FLG3_L1PLLPD_EN 0x00800000
2984#define TG3_FLG3_57765_PLUS 0x01000000
2985#define TG3_FLG3_APE_HAS_NCSI 0x02000000
2986#define TG3_FLG3_5717_PLUS 0x04000000
2987
2988 struct timer_list timer; 2986 struct timer_list timer;
2989 u16 timer_counter; 2987 u16 timer_counter;
2990 u16 timer_multiplier; 2988 u16 timer_multiplier;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 20:26:34 -0500