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-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c2
-rw-r--r--arch/blackfin/lib/ins.S21
-rw-r--r--arch/blackfin/lib/outs.S16
-rw-r--r--include/asm-blackfin/io.h2
4 files changed, 37 insertions, 4 deletions
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 053edff6c0d8..4367330909b2 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -90,7 +90,9 @@ EXPORT_SYMBOL(__umodsi3);
90EXPORT_SYMBOL(outsb); 90EXPORT_SYMBOL(outsb);
91EXPORT_SYMBOL(insb); 91EXPORT_SYMBOL(insb);
92EXPORT_SYMBOL(outsw); 92EXPORT_SYMBOL(outsw);
93EXPORT_SYMBOL(outsw_8);
93EXPORT_SYMBOL(insw); 94EXPORT_SYMBOL(insw);
95EXPORT_SYMBOL(insw_8);
94EXPORT_SYMBOL(outsl); 96EXPORT_SYMBOL(outsl);
95EXPORT_SYMBOL(insl); 97EXPORT_SYMBOL(insl);
96EXPORT_SYMBOL(insl_16); 98EXPORT_SYMBOL(insl_16);
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index df7b8833a0c5..eba2343b1b59 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -7,7 +7,7 @@
7 * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops. 7 * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc. 10 * Copyright 2004-2008 Analog Devices Inc.
11 * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> 11 * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
12 * 12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
@@ -63,6 +63,23 @@ ENTRY(_insw)
63 RTS; 63 RTS;
64ENDPROC(_insw) 64ENDPROC(_insw)
65 65
66ENTRY(_insw_8)
67 P0 = R0; /* P0 = port */
68 cli R3;
69 P1 = R1; /* P1 = address */
70 P2 = R2; /* P2 = count */
71 SSYNC;
72 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
73.Lword8_loop_s: R0 = W[P0];
74 B[P1++] = R0;
75 R0 = R0 >> 8;
76 B[P1++] = R0;
77 NOP;
78.Lword8_loop_e: NOP;
79 sti R3;
80 RTS;
81ENDPROC(_insw_8)
82
66ENTRY(_insb) 83ENTRY(_insb)
67 P0 = R0; /* P0 = port */ 84 P0 = R0; /* P0 = port */
68 cli R3; 85 cli R3;
@@ -78,8 +95,6 @@ ENTRY(_insb)
78 RTS; 95 RTS;
79ENDPROC(_insb) 96ENDPROC(_insb)
80 97
81
82
83ENTRY(_insl_16) 98ENTRY(_insl_16)
84 P0 = R0; /* P0 = port */ 99 P0 = R0; /* P0 = port */
85 cli R3; 100 cli R3;
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
index 4c3da8ae094e..3daf96035bf6 100644
--- a/arch/blackfin/lib/outs.S
+++ b/arch/blackfin/lib/outs.S
@@ -7,7 +7,7 @@
7 * Description: Implementation of outs{bwl} for BlackFin processors using zero overhead loops. 7 * Description: Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
8 * 8 *
9 * Modified: Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> 9 * Modified: Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
10 * Copyright 2004-2006 Analog Devices Inc. 10 * Copyright 2004-2008 Analog Devices Inc.
11 * 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * 13 *
@@ -63,3 +63,17 @@ ENTRY(_outsb)
63.Lbyte_loop_e: B[P0] = R0; 63.Lbyte_loop_e: B[P0] = R0;
64 RTS; 64 RTS;
65ENDPROC(_outsb) 65ENDPROC(_outsb)
66
67ENTRY(_outsw_8)
68 P0 = R0; /* P0 = port */
69 P1 = R1; /* P1 = address */
70 P2 = R2; /* P2 = count */
71
72 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
73.Lword8_loop_s: R1 = B[P1++];
74 R0 = B[P1++];
75 R0 = R0 << 8;
76 R0 = R0 + R1;
77.Lword8_loop_e: W[P0] = R0;
78 RTS;
79ENDPROC(_outsw)
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index 574fe56989d1..cbbf7ffdbbff 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -117,10 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr)
117 117
118extern void outsb(unsigned long port, const void *addr, unsigned long count); 118extern void outsb(unsigned long port, const void *addr, unsigned long count);
119extern void outsw(unsigned long port, const void *addr, unsigned long count); 119extern void outsw(unsigned long port, const void *addr, unsigned long count);
120extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
120extern void outsl(unsigned long port, const void *addr, unsigned long count); 121extern void outsl(unsigned long port, const void *addr, unsigned long count);
121 122
122extern void insb(unsigned long port, void *addr, unsigned long count); 123extern void insb(unsigned long port, void *addr, unsigned long count);
123extern void insw(unsigned long port, void *addr, unsigned long count); 124extern void insw(unsigned long port, void *addr, unsigned long count);
125extern void insw_8(unsigned long port, void *addr, unsigned long count);
124extern void insl(unsigned long port, void *addr, unsigned long count); 126extern void insl(unsigned long port, void *addr, unsigned long count);
125extern void insl_16(unsigned long port, void *addr, unsigned long count); 127extern void insl_16(unsigned long port, void *addr, unsigned long count);
126 128