diff options
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 72 |
1 files changed, 70 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 9f7499b6d435..4619d5fe606c 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -38,11 +38,33 @@ static void pxa_unmask_low_irq(unsigned int irq) | |||
38 | ICMR |= (1 << (irq + PXA_IRQ_SKIP)); | 38 | ICMR |= (1 << (irq + PXA_IRQ_SKIP)); |
39 | } | 39 | } |
40 | 40 | ||
41 | static int pxa_set_wake(unsigned int irq, unsigned int on) | ||
42 | { | ||
43 | u32 mask; | ||
44 | |||
45 | switch (irq) { | ||
46 | case IRQ_RTCAlrm: | ||
47 | mask = PWER_RTC; | ||
48 | break; | ||
49 | #ifdef CONFIG_PXA27x | ||
50 | /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ | ||
51 | #endif | ||
52 | default: | ||
53 | return -EINVAL; | ||
54 | } | ||
55 | if (on) | ||
56 | PWER |= mask; | ||
57 | else | ||
58 | PWER &= ~mask; | ||
59 | return 0; | ||
60 | } | ||
61 | |||
41 | static struct irq_chip pxa_internal_chip_low = { | 62 | static struct irq_chip pxa_internal_chip_low = { |
42 | .name = "SC", | 63 | .name = "SC", |
43 | .ack = pxa_mask_low_irq, | 64 | .ack = pxa_mask_low_irq, |
44 | .mask = pxa_mask_low_irq, | 65 | .mask = pxa_mask_low_irq, |
45 | .unmask = pxa_unmask_low_irq, | 66 | .unmask = pxa_unmask_low_irq, |
67 | .set_wake = pxa_set_wake, | ||
46 | }; | 68 | }; |
47 | 69 | ||
48 | #if PXA_INTERNAL_IRQS > 32 | 70 | #if PXA_INTERNAL_IRQS > 32 |
@@ -70,6 +92,26 @@ static struct irq_chip pxa_internal_chip_high = { | |||
70 | 92 | ||
71 | #endif | 93 | #endif |
72 | 94 | ||
95 | /* Note that if an input/irq line ever gets changed to an output during | ||
96 | * suspend, the relevant PWER, PRER, and PFER bits should be cleared. | ||
97 | */ | ||
98 | #ifdef CONFIG_PXA27x | ||
99 | |||
100 | /* PXA27x: Various gpios can issue wakeup events. This logic only | ||
101 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | ||
102 | */ | ||
103 | #define PXA27x_GPIO_NOWAKE_MASK \ | ||
104 | ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) | ||
105 | #define WAKEMASK(gpio) \ | ||
106 | (((gpio) <= 15) \ | ||
107 | ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ | ||
108 | : ((gpio == 35) ? (1 << 24) : 0)) | ||
109 | #else | ||
110 | |||
111 | /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ | ||
112 | #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) | ||
113 | #endif | ||
114 | |||
73 | /* | 115 | /* |
74 | * PXA GPIO edge detection for IRQs: | 116 | * PXA GPIO edge detection for IRQs: |
75 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | 117 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. |
@@ -83,9 +125,11 @@ static long GPIO_IRQ_mask[4]; | |||
83 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | 125 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) |
84 | { | 126 | { |
85 | int gpio, idx; | 127 | int gpio, idx; |
128 | u32 mask; | ||
86 | 129 | ||
87 | gpio = IRQ_TO_GPIO(irq); | 130 | gpio = IRQ_TO_GPIO(irq); |
88 | idx = gpio >> 5; | 131 | idx = gpio >> 5; |
132 | mask = WAKEMASK(gpio); | ||
89 | 133 | ||
90 | if (type == IRQT_PROBE) { | 134 | if (type == IRQT_PROBE) { |
91 | /* Don't mess with enabled GPIOs using preconfigured edges or | 135 | /* Don't mess with enabled GPIOs using preconfigured edges or |
@@ -105,14 +149,20 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |||
105 | if (type & __IRQT_RISEDGE) { | 149 | if (type & __IRQT_RISEDGE) { |
106 | /* printk("rising "); */ | 150 | /* printk("rising "); */ |
107 | __set_bit (gpio, GPIO_IRQ_rising_edge); | 151 | __set_bit (gpio, GPIO_IRQ_rising_edge); |
108 | } else | 152 | PRER |= mask; |
153 | } else { | ||
109 | __clear_bit (gpio, GPIO_IRQ_rising_edge); | 154 | __clear_bit (gpio, GPIO_IRQ_rising_edge); |
155 | PRER &= ~mask; | ||
156 | } | ||
110 | 157 | ||
111 | if (type & __IRQT_FALEDGE) { | 158 | if (type & __IRQT_FALEDGE) { |
112 | /* printk("falling "); */ | 159 | /* printk("falling "); */ |
113 | __set_bit (gpio, GPIO_IRQ_falling_edge); | 160 | __set_bit (gpio, GPIO_IRQ_falling_edge); |
114 | } else | 161 | PFER |= mask; |
162 | } else { | ||
115 | __clear_bit (gpio, GPIO_IRQ_falling_edge); | 163 | __clear_bit (gpio, GPIO_IRQ_falling_edge); |
164 | PFER &= ~mask; | ||
165 | } | ||
116 | 166 | ||
117 | /* printk("edges\n"); */ | 167 | /* printk("edges\n"); */ |
118 | 168 | ||
@@ -130,12 +180,29 @@ static void pxa_ack_low_gpio(unsigned int irq) | |||
130 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | 180 | GEDR0 = (1 << (irq - IRQ_GPIO0)); |
131 | } | 181 | } |
132 | 182 | ||
183 | static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) | ||
184 | { | ||
185 | int gpio = IRQ_TO_GPIO(irq); | ||
186 | u32 mask = WAKEMASK(gpio); | ||
187 | |||
188 | if (!mask) | ||
189 | return -EINVAL; | ||
190 | |||
191 | if (on) | ||
192 | PWER |= mask; | ||
193 | else | ||
194 | PWER &= ~mask; | ||
195 | return 0; | ||
196 | } | ||
197 | |||
198 | |||
133 | static struct irq_chip pxa_low_gpio_chip = { | 199 | static struct irq_chip pxa_low_gpio_chip = { |
134 | .name = "GPIO-l", | 200 | .name = "GPIO-l", |
135 | .ack = pxa_ack_low_gpio, | 201 | .ack = pxa_ack_low_gpio, |
136 | .mask = pxa_mask_low_irq, | 202 | .mask = pxa_mask_low_irq, |
137 | .unmask = pxa_unmask_low_irq, | 203 | .unmask = pxa_unmask_low_irq, |
138 | .set_type = pxa_gpio_irq_type, | 204 | .set_type = pxa_gpio_irq_type, |
205 | .set_wake = pxa_set_gpio_wake, | ||
139 | }; | 206 | }; |
140 | 207 | ||
141 | /* | 208 | /* |
@@ -244,6 +311,7 @@ static struct irq_chip pxa_muxed_gpio_chip = { | |||
244 | .mask = pxa_mask_muxed_gpio, | 311 | .mask = pxa_mask_muxed_gpio, |
245 | .unmask = pxa_unmask_muxed_gpio, | 312 | .unmask = pxa_unmask_muxed_gpio, |
246 | .set_type = pxa_gpio_irq_type, | 313 | .set_type = pxa_gpio_irq_type, |
314 | .set_wake = pxa_set_gpio_wake, | ||
247 | }; | 315 | }; |
248 | 316 | ||
249 | 317 | ||