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-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c9
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h2
2 files changed, 9 insertions, 2 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 865ddd82b268..d50cf78c234d 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -301,12 +301,17 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
301 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg); 301 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
302 /* 302 /*
303 * Enable Receive PFC 303 * Enable Receive PFC
304 * We will always honor XOFF frames we receive when 304 * 82599 will always honor XOFF frames we receive when
305 * we are in PFC mode. 305 * we are in PFC mode however X540 only honors enabled
306 * traffic classes.
306 */ 307 */
307 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 308 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
308 reg &= ~IXGBE_MFLCN_RFCE; 309 reg &= ~IXGBE_MFLCN_RFCE;
309 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF; 310 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
311
312 if (hw->mac.type == ixgbe_mac_X540)
313 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
314
310 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); 315 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
311 316
312 } else { 317 } else {
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 7d0b37d2ab7b..f5bec9754c00 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1728,6 +1728,8 @@
1728#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 1728#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1729#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 1729#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1730 1730
1731#define IXGBE_MFLCN_RPFCE_SHIFT 4
1732
1731/* Multiple Receive Queue Control */ 1733/* Multiple Receive Queue Control */
1732#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 1734#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1733#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 1735#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */