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-rw-r--r--drivers/net/pcnet32.c98
1 files changed, 48 insertions, 50 deletions
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 36f92dd55508..5f994b5beda1 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -210,31 +210,31 @@ static int homepna[MAX_UNITS];
210 210
211/* The PCNET32 Rx and Tx ring descriptors. */ 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head { 212struct pcnet32_rx_head {
213 u32 base; 213 __le32 base;
214 s16 buf_length; /* two`s complement of length */ 214 __le16 buf_length; /* two`s complement of length */
215 s16 status; 215 __le16 status;
216 u32 msg_length; 216 __le32 msg_length;
217 u32 reserved; 217 __le32 reserved;
218}; 218};
219 219
220struct pcnet32_tx_head { 220struct pcnet32_tx_head {
221 u32 base; 221 __le32 base;
222 s16 length; /* two`s complement of length */ 222 __le16 length; /* two`s complement of length */
223 s16 status; 223 __le16 status;
224 u32 misc; 224 __le32 misc;
225 u32 reserved; 225 __le32 reserved;
226}; 226};
227 227
228/* The PCNET32 32-Bit initialization block, described in databook. */ 228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block { 229struct pcnet32_init_block {
230 u16 mode; 230 __le16 mode;
231 u16 tlen_rlen; 231 __le16 tlen_rlen;
232 u8 phys_addr[6]; 232 u8 phys_addr[6];
233 u16 reserved; 233 __le16 reserved;
234 u32 filter[2]; 234 __le32 filter[2];
235 /* Receive and transmit ring base, along with extra bits. */ 235 /* Receive and transmit ring base, along with extra bits. */
236 u32 rx_ring; 236 __le32 rx_ring;
237 u32 tx_ring; 237 __le32 tx_ring;
238}; 238};
239 239
240/* PCnet32 access functions */ 240/* PCnet32 access functions */
@@ -610,9 +610,9 @@ static void pcnet32_realloc_rx_ring(struct net_device *dev,
610 new_dma_addr_list[new] = 610 new_dma_addr_list[new] =
611 pci_map_single(lp->pci_dev, rx_skbuff->data, 611 pci_map_single(lp->pci_dev, rx_skbuff->data,
612 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); 612 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
613 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]); 613 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
614 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); 614 new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
615 new_rx_ring[new].status = le16_to_cpu(0x8000); 615 new_rx_ring[new].status = cpu_to_le16(0x8000);
616 } 616 }
617 /* and free any unneeded buffers */ 617 /* and free any unneeded buffers */
618 for (; new < lp->rx_ring_size; new++) { 618 for (; new < lp->rx_ring_size; new++) {
@@ -888,7 +888,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
888 int x, i; /* counters */ 888 int x, i; /* counters */
889 int numbuffs = 4; /* number of TX/RX buffers and descs */ 889 int numbuffs = 4; /* number of TX/RX buffers and descs */
890 u16 status = 0x8300; /* TX ring status */ 890 u16 status = 0x8300; /* TX ring status */
891 u16 teststatus; /* test of ring status */ 891 __le16 teststatus; /* test of ring status */
892 int rc; /* return code */ 892 int rc; /* return code */
893 int size; /* size of packets */ 893 int size; /* size of packets */
894 unsigned char *packet; /* source packet data */ 894 unsigned char *packet; /* source packet data */
@@ -935,7 +935,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
935 packet = skb->data; 935 packet = skb->data;
936 skb_put(skb, size); /* create space for data */ 936 skb_put(skb, size); /* create space for data */
937 lp->tx_skbuff[x] = skb; 937 lp->tx_skbuff[x] = skb;
938 lp->tx_ring[x].length = le16_to_cpu(-skb->len); 938 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
939 lp->tx_ring[x].misc = 0; 939 lp->tx_ring[x].misc = 0;
940 940
941 /* put DA and SA into the skb */ 941 /* put DA and SA into the skb */
@@ -955,10 +955,9 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
955 lp->tx_dma_addr[x] = 955 lp->tx_dma_addr[x] =
956 pci_map_single(lp->pci_dev, skb->data, skb->len, 956 pci_map_single(lp->pci_dev, skb->data, skb->len,
957 PCI_DMA_TODEVICE); 957 PCI_DMA_TODEVICE);
958 lp->tx_ring[x].base = 958 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
959 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
960 wmb(); /* Make sure owner changes after all others are visible */ 959 wmb(); /* Make sure owner changes after all others are visible */
961 lp->tx_ring[x].status = le16_to_cpu(status); 960 lp->tx_ring[x].status = cpu_to_le16(status);
962 } 961 }
963 } 962 }
964 963
@@ -969,7 +968,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
969 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 968 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
970 lp->a.write_csr(ioaddr, CSR15, x | 0x0044); 969 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
971 970
972 teststatus = le16_to_cpu(0x8000); 971 teststatus = cpu_to_le16(0x8000);
973 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 972 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
974 973
975 /* Check status of descriptors */ 974 /* Check status of descriptors */
@@ -1099,6 +1098,7 @@ static int pcnet32_phys_id(struct net_device *dev, u32 data)
1099 mod_timer(&lp->blink_timer, jiffies); 1098 mod_timer(&lp->blink_timer, jiffies);
1100 set_current_state(TASK_INTERRUPTIBLE); 1099 set_current_state(TASK_INTERRUPTIBLE);
1101 1100
1101 /* AV: the limit here makes no sense whatsoever */
1102 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))) 1102 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1103 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ); 1103 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1104 1104
@@ -1224,7 +1224,7 @@ static void pcnet32_rx_entry(struct net_device *dev,
1224 newskb->data, 1224 newskb->data,
1225 PKT_BUF_SZ - 2, 1225 PKT_BUF_SZ - 2,
1226 PCI_DMA_FROMDEVICE); 1226 PCI_DMA_FROMDEVICE);
1227 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]); 1227 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1228 rx_in_place = 1; 1228 rx_in_place = 1;
1229 } else 1229 } else
1230 skb = NULL; 1230 skb = NULL;
@@ -1283,9 +1283,9 @@ static int pcnet32_rx(struct net_device *dev, int budget)
1283 * The docs say that the buffer length isn't touched, but Andrew 1283 * The docs say that the buffer length isn't touched, but Andrew
1284 * Boyd of QNX reports that some revs of the 79C965 clear it. 1284 * Boyd of QNX reports that some revs of the 79C965 clear it.
1285 */ 1285 */
1286 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ); 1286 rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
1287 wmb(); /* Make sure owner changes after others are visible */ 1287 wmb(); /* Make sure owner changes after others are visible */
1288 rxp->status = le16_to_cpu(0x8000); 1288 rxp->status = cpu_to_le16(0x8000);
1289 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1289 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1290 rxp = &lp->rx_ring[entry]; 1290 rxp = &lp->rx_ring[entry];
1291 } 1291 }
@@ -1875,15 +1875,15 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1875 && dev->dev_addr[2] == 0x75) 1875 && dev->dev_addr[2] == 0x75)
1876 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1876 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1877 1877
1878 lp->init_block->mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */ 1878 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1879 lp->init_block->tlen_rlen = 1879 lp->init_block->tlen_rlen =
1880 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); 1880 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1881 for (i = 0; i < 6; i++) 1881 for (i = 0; i < 6; i++)
1882 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1882 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1883 lp->init_block->filter[0] = 0x00000000; 1883 lp->init_block->filter[0] = 0x00000000;
1884 lp->init_block->filter[1] = 0x00000000; 1884 lp->init_block->filter[1] = 0x00000000;
1885 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); 1885 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1886 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); 1886 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1887 1887
1888 /* switch pcnet32 to 32bit mode */ 1888 /* switch pcnet32 to 32bit mode */
1889 a->write_bcr(ioaddr, 20, 2); 1889 a->write_bcr(ioaddr, 20, 2);
@@ -2274,7 +2274,7 @@ static int pcnet32_open(struct net_device *dev)
2274#endif 2274#endif
2275 2275
2276 lp->init_block->mode = 2276 lp->init_block->mode =
2277 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); 2277 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2278 pcnet32_load_multicast(dev); 2278 pcnet32_load_multicast(dev);
2279 2279
2280 if (pcnet32_init_ring(dev)) { 2280 if (pcnet32_init_ring(dev)) {
@@ -2401,10 +2401,10 @@ static int pcnet32_init_ring(struct net_device *dev)
2401 lp->rx_dma_addr[i] = 2401 lp->rx_dma_addr[i] =
2402 pci_map_single(lp->pci_dev, rx_skbuff->data, 2402 pci_map_single(lp->pci_dev, rx_skbuff->data,
2403 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); 2403 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2404 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]); 2404 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2405 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); 2405 lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
2406 wmb(); /* Make sure owner changes after all others are visible */ 2406 wmb(); /* Make sure owner changes after all others are visible */
2407 lp->rx_ring[i].status = le16_to_cpu(0x8000); 2407 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2408 } 2408 }
2409 /* The Tx buffer address is filled in as needed, but we do need to clear 2409 /* The Tx buffer address is filled in as needed, but we do need to clear
2410 * the upper ownership bit. */ 2410 * the upper ownership bit. */
@@ -2416,11 +2416,11 @@ static int pcnet32_init_ring(struct net_device *dev)
2416 } 2416 }
2417 2417
2418 lp->init_block->tlen_rlen = 2418 lp->init_block->tlen_rlen =
2419 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); 2419 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2420 for (i = 0; i < 6; i++) 2420 for (i = 0; i < 6; i++)
2421 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2421 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2422 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); 2422 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2423 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); 2423 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2424 wmb(); /* Make sure all changes are visible */ 2424 wmb(); /* Make sure all changes are visible */
2425 return 0; 2425 return 0;
2426} 2426}
@@ -2529,16 +2529,16 @@ static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2529 /* Caution: the write order is important here, set the status 2529 /* Caution: the write order is important here, set the status
2530 * with the "ownership" bits last. */ 2530 * with the "ownership" bits last. */
2531 2531
2532 lp->tx_ring[entry].length = le16_to_cpu(-skb->len); 2532 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2533 2533
2534 lp->tx_ring[entry].misc = 0x00000000; 2534 lp->tx_ring[entry].misc = 0x00000000;
2535 2535
2536 lp->tx_skbuff[entry] = skb; 2536 lp->tx_skbuff[entry] = skb;
2537 lp->tx_dma_addr[entry] = 2537 lp->tx_dma_addr[entry] =
2538 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2538 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2539 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]); 2539 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2540 wmb(); /* Make sure owner changes after all others are visible */ 2540 wmb(); /* Make sure owner changes after all others are visible */
2541 lp->tx_ring[entry].status = le16_to_cpu(status); 2541 lp->tx_ring[entry].status = cpu_to_le16(status);
2542 2542
2543 lp->cur_tx++; 2543 lp->cur_tx++;
2544 lp->stats.tx_bytes += skb->len; 2544 lp->stats.tx_bytes += skb->len;
@@ -2709,7 +2709,7 @@ static void pcnet32_load_multicast(struct net_device *dev)
2709{ 2709{
2710 struct pcnet32_private *lp = netdev_priv(dev); 2710 struct pcnet32_private *lp = netdev_priv(dev);
2711 volatile struct pcnet32_init_block *ib = lp->init_block; 2711 volatile struct pcnet32_init_block *ib = lp->init_block;
2712 volatile u16 *mcast_table = (u16 *) & ib->filter; 2712 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2713 struct dev_mc_list *dmi = dev->mc_list; 2713 struct dev_mc_list *dmi = dev->mc_list;
2714 unsigned long ioaddr = dev->base_addr; 2714 unsigned long ioaddr = dev->base_addr;
2715 char *addrs; 2715 char *addrs;
@@ -2718,8 +2718,8 @@ static void pcnet32_load_multicast(struct net_device *dev)
2718 2718
2719 /* set all multicast bits */ 2719 /* set all multicast bits */
2720 if (dev->flags & IFF_ALLMULTI) { 2720 if (dev->flags & IFF_ALLMULTI) {
2721 ib->filter[0] = 0xffffffff; 2721 ib->filter[0] = cpu_to_le32(~0U);
2722 ib->filter[1] = 0xffffffff; 2722 ib->filter[1] = cpu_to_le32(~0U);
2723 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2723 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2724 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2724 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2725 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2725 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
@@ -2741,9 +2741,7 @@ static void pcnet32_load_multicast(struct net_device *dev)
2741 2741
2742 crc = ether_crc_le(6, addrs); 2742 crc = ether_crc_le(6, addrs);
2743 crc = crc >> 26; 2743 crc = crc >> 26;
2744 mcast_table[crc >> 4] = 2744 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2745 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2746 (1 << (crc & 0xf)));
2747 } 2745 }
2748 for (i = 0; i < 4; i++) 2746 for (i = 0; i < 4; i++)
2749 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i, 2747 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
@@ -2769,12 +2767,12 @@ static void pcnet32_set_multicast_list(struct net_device *dev)
2769 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", 2767 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2770 dev->name); 2768 dev->name);
2771 lp->init_block->mode = 2769 lp->init_block->mode =
2772 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2770 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2773 7); 2771 7);
2774 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000); 2772 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2775 } else { 2773 } else {
2776 lp->init_block->mode = 2774 lp->init_block->mode =
2777 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); 2775 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2778 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2776 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2779 pcnet32_load_multicast(dev); 2777 pcnet32_load_multicast(dev);
2780 } 2778 }