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-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c453
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c779
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h19
3 files changed, 637 insertions, 614 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index f2b2f45d3a78..626667c3101c 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -30,8 +30,6 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData, 31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value); 32 u32 reg, u32 value);
33static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 33
36MODULE_AUTHOR("Atheros Communications"); 34MODULE_AUTHOR("Atheros Communications");
37MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -1930,457 +1928,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1930 return true; 1928 return true;
1931} 1929}
1932 1930
1933static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1934{
1935 int bb_spur = AR_NO_SPUR;
1936 int freq;
1937 int bin, cur_bin;
1938 int bb_spur_off, spur_subchannel_sd;
1939 int spur_freq_sd;
1940 int spur_delta_phase;
1941 int denominator;
1942 int upper, lower, cur_vit_mask;
1943 int tmp, newVal;
1944 int i;
1945 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1946 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1947 };
1948 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1949 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1950 };
1951 int inc[4] = { 0, 100, 0, 0 };
1952 struct chan_centers centers;
1953
1954 int8_t mask_m[123];
1955 int8_t mask_p[123];
1956 int8_t mask_amt;
1957 int tmp_mask;
1958 int cur_bb_spur;
1959 bool is2GHz = IS_CHAN_2GHZ(chan);
1960
1961 memset(&mask_m, 0, sizeof(int8_t) * 123);
1962 memset(&mask_p, 0, sizeof(int8_t) * 123);
1963
1964 ath9k_hw_get_channel_centers(ah, chan, &centers);
1965 freq = centers.synth_center;
1966
1967 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1968 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1969 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1970
1971 if (is2GHz)
1972 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1973 else
1974 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1975
1976 if (AR_NO_SPUR == cur_bb_spur)
1977 break;
1978 cur_bb_spur = cur_bb_spur - freq;
1979
1980 if (IS_CHAN_HT40(chan)) {
1981 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1982 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1983 bb_spur = cur_bb_spur;
1984 break;
1985 }
1986 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1987 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1988 bb_spur = cur_bb_spur;
1989 break;
1990 }
1991 }
1992
1993 if (AR_NO_SPUR == bb_spur) {
1994 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1995 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1996 return;
1997 } else {
1998 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1999 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
2000 }
2001
2002 bin = bb_spur * 320;
2003
2004 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2005
2006 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2007 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2008 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2009 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2010 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
2011
2012 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2013 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2014 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2015 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2016 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2017 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
2018
2019 if (IS_CHAN_HT40(chan)) {
2020 if (bb_spur < 0) {
2021 spur_subchannel_sd = 1;
2022 bb_spur_off = bb_spur + 10;
2023 } else {
2024 spur_subchannel_sd = 0;
2025 bb_spur_off = bb_spur - 10;
2026 }
2027 } else {
2028 spur_subchannel_sd = 0;
2029 bb_spur_off = bb_spur;
2030 }
2031
2032 if (IS_CHAN_HT40(chan))
2033 spur_delta_phase =
2034 ((bb_spur * 262144) /
2035 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2036 else
2037 spur_delta_phase =
2038 ((bb_spur * 524288) /
2039 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2040
2041 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2042 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2043
2044 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2045 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2046 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2047 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2048
2049 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2050 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2051
2052 cur_bin = -6000;
2053 upper = bin + 100;
2054 lower = bin - 100;
2055
2056 for (i = 0; i < 4; i++) {
2057 int pilot_mask = 0;
2058 int chan_mask = 0;
2059 int bp = 0;
2060 for (bp = 0; bp < 30; bp++) {
2061 if ((cur_bin > lower) && (cur_bin < upper)) {
2062 pilot_mask = pilot_mask | 0x1 << bp;
2063 chan_mask = chan_mask | 0x1 << bp;
2064 }
2065 cur_bin += 100;
2066 }
2067 cur_bin += inc[i];
2068 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2069 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2070 }
2071
2072 cur_vit_mask = 6100;
2073 upper = bin + 120;
2074 lower = bin - 120;
2075
2076 for (i = 0; i < 123; i++) {
2077 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2078
2079 /* workaround for gcc bug #37014 */
2080 volatile int tmp_v = abs(cur_vit_mask - bin);
2081
2082 if (tmp_v < 75)
2083 mask_amt = 1;
2084 else
2085 mask_amt = 0;
2086 if (cur_vit_mask < 0)
2087 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2088 else
2089 mask_p[cur_vit_mask / 100] = mask_amt;
2090 }
2091 cur_vit_mask -= 100;
2092 }
2093
2094 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2095 | (mask_m[48] << 26) | (mask_m[49] << 24)
2096 | (mask_m[50] << 22) | (mask_m[51] << 20)
2097 | (mask_m[52] << 18) | (mask_m[53] << 16)
2098 | (mask_m[54] << 14) | (mask_m[55] << 12)
2099 | (mask_m[56] << 10) | (mask_m[57] << 8)
2100 | (mask_m[58] << 6) | (mask_m[59] << 4)
2101 | (mask_m[60] << 2) | (mask_m[61] << 0);
2102 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2103 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2104
2105 tmp_mask = (mask_m[31] << 28)
2106 | (mask_m[32] << 26) | (mask_m[33] << 24)
2107 | (mask_m[34] << 22) | (mask_m[35] << 20)
2108 | (mask_m[36] << 18) | (mask_m[37] << 16)
2109 | (mask_m[48] << 14) | (mask_m[39] << 12)
2110 | (mask_m[40] << 10) | (mask_m[41] << 8)
2111 | (mask_m[42] << 6) | (mask_m[43] << 4)
2112 | (mask_m[44] << 2) | (mask_m[45] << 0);
2113 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2114 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2115
2116 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2117 | (mask_m[18] << 26) | (mask_m[18] << 24)
2118 | (mask_m[20] << 22) | (mask_m[20] << 20)
2119 | (mask_m[22] << 18) | (mask_m[22] << 16)
2120 | (mask_m[24] << 14) | (mask_m[24] << 12)
2121 | (mask_m[25] << 10) | (mask_m[26] << 8)
2122 | (mask_m[27] << 6) | (mask_m[28] << 4)
2123 | (mask_m[29] << 2) | (mask_m[30] << 0);
2124 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2125 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2126
2127 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2128 | (mask_m[2] << 26) | (mask_m[3] << 24)
2129 | (mask_m[4] << 22) | (mask_m[5] << 20)
2130 | (mask_m[6] << 18) | (mask_m[7] << 16)
2131 | (mask_m[8] << 14) | (mask_m[9] << 12)
2132 | (mask_m[10] << 10) | (mask_m[11] << 8)
2133 | (mask_m[12] << 6) | (mask_m[13] << 4)
2134 | (mask_m[14] << 2) | (mask_m[15] << 0);
2135 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2136 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2137
2138 tmp_mask = (mask_p[15] << 28)
2139 | (mask_p[14] << 26) | (mask_p[13] << 24)
2140 | (mask_p[12] << 22) | (mask_p[11] << 20)
2141 | (mask_p[10] << 18) | (mask_p[9] << 16)
2142 | (mask_p[8] << 14) | (mask_p[7] << 12)
2143 | (mask_p[6] << 10) | (mask_p[5] << 8)
2144 | (mask_p[4] << 6) | (mask_p[3] << 4)
2145 | (mask_p[2] << 2) | (mask_p[1] << 0);
2146 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2147 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2148
2149 tmp_mask = (mask_p[30] << 28)
2150 | (mask_p[29] << 26) | (mask_p[28] << 24)
2151 | (mask_p[27] << 22) | (mask_p[26] << 20)
2152 | (mask_p[25] << 18) | (mask_p[24] << 16)
2153 | (mask_p[23] << 14) | (mask_p[22] << 12)
2154 | (mask_p[21] << 10) | (mask_p[20] << 8)
2155 | (mask_p[19] << 6) | (mask_p[18] << 4)
2156 | (mask_p[17] << 2) | (mask_p[16] << 0);
2157 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2158 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2159
2160 tmp_mask = (mask_p[45] << 28)
2161 | (mask_p[44] << 26) | (mask_p[43] << 24)
2162 | (mask_p[42] << 22) | (mask_p[41] << 20)
2163 | (mask_p[40] << 18) | (mask_p[39] << 16)
2164 | (mask_p[38] << 14) | (mask_p[37] << 12)
2165 | (mask_p[36] << 10) | (mask_p[35] << 8)
2166 | (mask_p[34] << 6) | (mask_p[33] << 4)
2167 | (mask_p[32] << 2) | (mask_p[31] << 0);
2168 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2169 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2170
2171 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2172 | (mask_p[59] << 26) | (mask_p[58] << 24)
2173 | (mask_p[57] << 22) | (mask_p[56] << 20)
2174 | (mask_p[55] << 18) | (mask_p[54] << 16)
2175 | (mask_p[53] << 14) | (mask_p[52] << 12)
2176 | (mask_p[51] << 10) | (mask_p[50] << 8)
2177 | (mask_p[49] << 6) | (mask_p[48] << 4)
2178 | (mask_p[47] << 2) | (mask_p[46] << 0);
2179 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2180 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2181}
2182
2183static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2184{
2185 int bb_spur = AR_NO_SPUR;
2186 int bin, cur_bin;
2187 int spur_freq_sd;
2188 int spur_delta_phase;
2189 int denominator;
2190 int upper, lower, cur_vit_mask;
2191 int tmp, new;
2192 int i;
2193 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2194 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2195 };
2196 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2197 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2198 };
2199 int inc[4] = { 0, 100, 0, 0 };
2200
2201 int8_t mask_m[123];
2202 int8_t mask_p[123];
2203 int8_t mask_amt;
2204 int tmp_mask;
2205 int cur_bb_spur;
2206 bool is2GHz = IS_CHAN_2GHZ(chan);
2207
2208 memset(&mask_m, 0, sizeof(int8_t) * 123);
2209 memset(&mask_p, 0, sizeof(int8_t) * 123);
2210
2211 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2212 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2213 if (AR_NO_SPUR == cur_bb_spur)
2214 break;
2215 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2216 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2217 bb_spur = cur_bb_spur;
2218 break;
2219 }
2220 }
2221
2222 if (AR_NO_SPUR == bb_spur)
2223 return;
2224
2225 bin = bb_spur * 32;
2226
2227 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2228 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2229 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2230 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2231 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2232
2233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2234
2235 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2236 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2237 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2238 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2239 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2240 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2241
2242 spur_delta_phase = ((bb_spur * 524288) / 100) &
2243 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2244
2245 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2246 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2247
2248 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2249 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2250 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2251 REG_WRITE(ah, AR_PHY_TIMING11, new);
2252
2253 cur_bin = -6000;
2254 upper = bin + 100;
2255 lower = bin - 100;
2256
2257 for (i = 0; i < 4; i++) {
2258 int pilot_mask = 0;
2259 int chan_mask = 0;
2260 int bp = 0;
2261 for (bp = 0; bp < 30; bp++) {
2262 if ((cur_bin > lower) && (cur_bin < upper)) {
2263 pilot_mask = pilot_mask | 0x1 << bp;
2264 chan_mask = chan_mask | 0x1 << bp;
2265 }
2266 cur_bin += 100;
2267 }
2268 cur_bin += inc[i];
2269 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2270 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2271 }
2272
2273 cur_vit_mask = 6100;
2274 upper = bin + 120;
2275 lower = bin - 120;
2276
2277 for (i = 0; i < 123; i++) {
2278 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2279
2280 /* workaround for gcc bug #37014 */
2281 volatile int tmp_v = abs(cur_vit_mask - bin);
2282
2283 if (tmp_v < 75)
2284 mask_amt = 1;
2285 else
2286 mask_amt = 0;
2287 if (cur_vit_mask < 0)
2288 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2289 else
2290 mask_p[cur_vit_mask / 100] = mask_amt;
2291 }
2292 cur_vit_mask -= 100;
2293 }
2294
2295 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2296 | (mask_m[48] << 26) | (mask_m[49] << 24)
2297 | (mask_m[50] << 22) | (mask_m[51] << 20)
2298 | (mask_m[52] << 18) | (mask_m[53] << 16)
2299 | (mask_m[54] << 14) | (mask_m[55] << 12)
2300 | (mask_m[56] << 10) | (mask_m[57] << 8)
2301 | (mask_m[58] << 6) | (mask_m[59] << 4)
2302 | (mask_m[60] << 2) | (mask_m[61] << 0);
2303 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2304 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2305
2306 tmp_mask = (mask_m[31] << 28)
2307 | (mask_m[32] << 26) | (mask_m[33] << 24)
2308 | (mask_m[34] << 22) | (mask_m[35] << 20)
2309 | (mask_m[36] << 18) | (mask_m[37] << 16)
2310 | (mask_m[48] << 14) | (mask_m[39] << 12)
2311 | (mask_m[40] << 10) | (mask_m[41] << 8)
2312 | (mask_m[42] << 6) | (mask_m[43] << 4)
2313 | (mask_m[44] << 2) | (mask_m[45] << 0);
2314 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2315 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2316
2317 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2318 | (mask_m[18] << 26) | (mask_m[18] << 24)
2319 | (mask_m[20] << 22) | (mask_m[20] << 20)
2320 | (mask_m[22] << 18) | (mask_m[22] << 16)
2321 | (mask_m[24] << 14) | (mask_m[24] << 12)
2322 | (mask_m[25] << 10) | (mask_m[26] << 8)
2323 | (mask_m[27] << 6) | (mask_m[28] << 4)
2324 | (mask_m[29] << 2) | (mask_m[30] << 0);
2325 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2326 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2327
2328 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2329 | (mask_m[2] << 26) | (mask_m[3] << 24)
2330 | (mask_m[4] << 22) | (mask_m[5] << 20)
2331 | (mask_m[6] << 18) | (mask_m[7] << 16)
2332 | (mask_m[8] << 14) | (mask_m[9] << 12)
2333 | (mask_m[10] << 10) | (mask_m[11] << 8)
2334 | (mask_m[12] << 6) | (mask_m[13] << 4)
2335 | (mask_m[14] << 2) | (mask_m[15] << 0);
2336 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2337 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2338
2339 tmp_mask = (mask_p[15] << 28)
2340 | (mask_p[14] << 26) | (mask_p[13] << 24)
2341 | (mask_p[12] << 22) | (mask_p[11] << 20)
2342 | (mask_p[10] << 18) | (mask_p[9] << 16)
2343 | (mask_p[8] << 14) | (mask_p[7] << 12)
2344 | (mask_p[6] << 10) | (mask_p[5] << 8)
2345 | (mask_p[4] << 6) | (mask_p[3] << 4)
2346 | (mask_p[2] << 2) | (mask_p[1] << 0);
2347 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2348 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2349
2350 tmp_mask = (mask_p[30] << 28)
2351 | (mask_p[29] << 26) | (mask_p[28] << 24)
2352 | (mask_p[27] << 22) | (mask_p[26] << 20)
2353 | (mask_p[25] << 18) | (mask_p[24] << 16)
2354 | (mask_p[23] << 14) | (mask_p[22] << 12)
2355 | (mask_p[21] << 10) | (mask_p[20] << 8)
2356 | (mask_p[19] << 6) | (mask_p[18] << 4)
2357 | (mask_p[17] << 2) | (mask_p[16] << 0);
2358 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2359 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2360
2361 tmp_mask = (mask_p[45] << 28)
2362 | (mask_p[44] << 26) | (mask_p[43] << 24)
2363 | (mask_p[42] << 22) | (mask_p[41] << 20)
2364 | (mask_p[40] << 18) | (mask_p[39] << 16)
2365 | (mask_p[38] << 14) | (mask_p[37] << 12)
2366 | (mask_p[36] << 10) | (mask_p[35] << 8)
2367 | (mask_p[34] << 6) | (mask_p[33] << 4)
2368 | (mask_p[32] << 2) | (mask_p[31] << 0);
2369 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2370 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2371
2372 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2373 | (mask_p[59] << 26) | (mask_p[58] << 24)
2374 | (mask_p[57] << 22) | (mask_p[56] << 20)
2375 | (mask_p[55] << 18) | (mask_p[54] << 16)
2376 | (mask_p[53] << 14) | (mask_p[52] << 12)
2377 | (mask_p[51] << 10) | (mask_p[50] << 8)
2378 | (mask_p[49] << 6) | (mask_p[48] << 4)
2379 | (mask_p[47] << 2) | (mask_p[46] << 0);
2380 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2381 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2382}
2383
2384static void ath9k_enable_rfkill(struct ath_hw *ah) 1931static void ath9k_enable_rfkill(struct ath_hw *ah)
2385{ 1932{
2386 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1933 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index bfcb9af4ae3c..8e4c3bd84bc0 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -52,96 +52,13 @@
52 * Used for both the chipsets with an external AR2133/AR5133 radios and 52 * Used for both the chipsets with an external AR2133/AR5133 radios and
53 * single-chip devices. 53 * single-chip devices.
54 */ 54 */
55void 55void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,
56ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, 56 u32 freqIndex, int regWrites)
57 int regWrites)
58{ 57{
59 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 58 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
60} 59}
61 60
62/** 61/**
63 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
64 * @ah: atheros hardware stucture
65 * @chan:
66 *
67 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
68 * the channel value. Assumes writes enabled to analog bus and bank6 register
69 * cache in ah->analogBank6Data.
70 */
71int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
72{
73 struct ath_common *common = ath9k_hw_common(ah);
74 u32 channelSel = 0;
75 u32 bModeSynth = 0;
76 u32 aModeRefSel = 0;
77 u32 reg32 = 0;
78 u16 freq;
79 struct chan_centers centers;
80
81 ath9k_hw_get_channel_centers(ah, chan, &centers);
82 freq = centers.synth_center;
83
84 if (freq < 4800) {
85 u32 txctl;
86
87 if (((freq - 2192) % 5) == 0) {
88 channelSel = ((freq - 672) * 2 - 3040) / 10;
89 bModeSynth = 0;
90 } else if (((freq - 2224) % 5) == 0) {
91 channelSel = ((freq - 704) * 2 - 3040) / 10;
92 bModeSynth = 1;
93 } else {
94 ath_print(common, ATH_DBG_FATAL,
95 "Invalid channel %u MHz\n", freq);
96 return -EINVAL;
97 }
98
99 channelSel = (channelSel << 2) & 0xff;
100 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
101
102 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
103 if (freq == 2484) {
104
105 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
106 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
107 } else {
108 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
109 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
110 }
111
112 } else if ((freq % 20) == 0 && freq >= 5120) {
113 channelSel =
114 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
115 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
116 } else if ((freq % 10) == 0) {
117 channelSel =
118 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
119 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
120 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
121 else
122 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
123 } else if ((freq % 5) == 0) {
124 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
125 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
126 } else {
127 ath_print(common, ATH_DBG_FATAL,
128 "Invalid channel %u MHz\n", freq);
129 return -EINVAL;
130 }
131
132 reg32 =
133 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
134 (1 << 5) | 0x1;
135
136 REG_WRITE(ah, AR_PHY(0x37), reg32);
137
138 ah->curchan = chan;
139 ah->curchan_rad_index = -1;
140
141 return 0;
142}
143
144/**
145 * ath9k_hw_ar9280_set_channel - set channel on single-chip device 62 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
146 * @ah: atheros hardware structure 63 * @ah: atheros hardware structure
147 * @chan: 64 * @chan:
@@ -255,6 +172,622 @@ int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
255} 172}
256 173
257/** 174/**
175 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
176 * @ah: atheros hardware structure
177 * @chan:
178 *
179 * For single-chip solutions. Converts to baseband spur frequency given the
180 * input channel frequency and compute register settings below.
181 */
182void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
183{
184 int bb_spur = AR_NO_SPUR;
185 int freq;
186 int bin, cur_bin;
187 int bb_spur_off, spur_subchannel_sd;
188 int spur_freq_sd;
189 int spur_delta_phase;
190 int denominator;
191 int upper, lower, cur_vit_mask;
192 int tmp, newVal;
193 int i;
194 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
195 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
196 };
197 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
198 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
199 };
200 int inc[4] = { 0, 100, 0, 0 };
201 struct chan_centers centers;
202
203 int8_t mask_m[123];
204 int8_t mask_p[123];
205 int8_t mask_amt;
206 int tmp_mask;
207 int cur_bb_spur;
208 bool is2GHz = IS_CHAN_2GHZ(chan);
209
210 memset(&mask_m, 0, sizeof(int8_t) * 123);
211 memset(&mask_p, 0, sizeof(int8_t) * 123);
212
213 ath9k_hw_get_channel_centers(ah, chan, &centers);
214 freq = centers.synth_center;
215
216 ah->config.spurmode = SPUR_ENABLE_EEPROM;
217 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
218 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
219
220 if (is2GHz)
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
222 else
223 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
224
225 if (AR_NO_SPUR == cur_bb_spur)
226 break;
227 cur_bb_spur = cur_bb_spur - freq;
228
229 if (IS_CHAN_HT40(chan)) {
230 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
231 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
232 bb_spur = cur_bb_spur;
233 break;
234 }
235 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
236 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
237 bb_spur = cur_bb_spur;
238 break;
239 }
240 }
241
242 if (AR_NO_SPUR == bb_spur) {
243 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
244 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
245 return;
246 } else {
247 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
248 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
249 }
250
251 bin = bb_spur * 320;
252
253 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
254
255 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
256 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
257 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
258 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
259 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
260
261 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
262 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
263 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
264 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
265 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
266 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
267
268 if (IS_CHAN_HT40(chan)) {
269 if (bb_spur < 0) {
270 spur_subchannel_sd = 1;
271 bb_spur_off = bb_spur + 10;
272 } else {
273 spur_subchannel_sd = 0;
274 bb_spur_off = bb_spur - 10;
275 }
276 } else {
277 spur_subchannel_sd = 0;
278 bb_spur_off = bb_spur;
279 }
280
281 if (IS_CHAN_HT40(chan))
282 spur_delta_phase =
283 ((bb_spur * 262144) /
284 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
285 else
286 spur_delta_phase =
287 ((bb_spur * 524288) /
288 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
289
290 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
291 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
292
293 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
294 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
295 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
296 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
297
298 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
299 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
300
301 cur_bin = -6000;
302 upper = bin + 100;
303 lower = bin - 100;
304
305 for (i = 0; i < 4; i++) {
306 int pilot_mask = 0;
307 int chan_mask = 0;
308 int bp = 0;
309 for (bp = 0; bp < 30; bp++) {
310 if ((cur_bin > lower) && (cur_bin < upper)) {
311 pilot_mask = pilot_mask | 0x1 << bp;
312 chan_mask = chan_mask | 0x1 << bp;
313 }
314 cur_bin += 100;
315 }
316 cur_bin += inc[i];
317 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
318 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
319 }
320
321 cur_vit_mask = 6100;
322 upper = bin + 120;
323 lower = bin - 120;
324
325 for (i = 0; i < 123; i++) {
326 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
327
328 /* workaround for gcc bug #37014 */
329 volatile int tmp_v = abs(cur_vit_mask - bin);
330
331 if (tmp_v < 75)
332 mask_amt = 1;
333 else
334 mask_amt = 0;
335 if (cur_vit_mask < 0)
336 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
337 else
338 mask_p[cur_vit_mask / 100] = mask_amt;
339 }
340 cur_vit_mask -= 100;
341 }
342
343 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
344 | (mask_m[48] << 26) | (mask_m[49] << 24)
345 | (mask_m[50] << 22) | (mask_m[51] << 20)
346 | (mask_m[52] << 18) | (mask_m[53] << 16)
347 | (mask_m[54] << 14) | (mask_m[55] << 12)
348 | (mask_m[56] << 10) | (mask_m[57] << 8)
349 | (mask_m[58] << 6) | (mask_m[59] << 4)
350 | (mask_m[60] << 2) | (mask_m[61] << 0);
351 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
352 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
353
354 tmp_mask = (mask_m[31] << 28)
355 | (mask_m[32] << 26) | (mask_m[33] << 24)
356 | (mask_m[34] << 22) | (mask_m[35] << 20)
357 | (mask_m[36] << 18) | (mask_m[37] << 16)
358 | (mask_m[48] << 14) | (mask_m[39] << 12)
359 | (mask_m[40] << 10) | (mask_m[41] << 8)
360 | (mask_m[42] << 6) | (mask_m[43] << 4)
361 | (mask_m[44] << 2) | (mask_m[45] << 0);
362 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
363 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
364
365 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
366 | (mask_m[18] << 26) | (mask_m[18] << 24)
367 | (mask_m[20] << 22) | (mask_m[20] << 20)
368 | (mask_m[22] << 18) | (mask_m[22] << 16)
369 | (mask_m[24] << 14) | (mask_m[24] << 12)
370 | (mask_m[25] << 10) | (mask_m[26] << 8)
371 | (mask_m[27] << 6) | (mask_m[28] << 4)
372 | (mask_m[29] << 2) | (mask_m[30] << 0);
373 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
374 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
375
376 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
377 | (mask_m[2] << 26) | (mask_m[3] << 24)
378 | (mask_m[4] << 22) | (mask_m[5] << 20)
379 | (mask_m[6] << 18) | (mask_m[7] << 16)
380 | (mask_m[8] << 14) | (mask_m[9] << 12)
381 | (mask_m[10] << 10) | (mask_m[11] << 8)
382 | (mask_m[12] << 6) | (mask_m[13] << 4)
383 | (mask_m[14] << 2) | (mask_m[15] << 0);
384 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
385 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
386
387 tmp_mask = (mask_p[15] << 28)
388 | (mask_p[14] << 26) | (mask_p[13] << 24)
389 | (mask_p[12] << 22) | (mask_p[11] << 20)
390 | (mask_p[10] << 18) | (mask_p[9] << 16)
391 | (mask_p[8] << 14) | (mask_p[7] << 12)
392 | (mask_p[6] << 10) | (mask_p[5] << 8)
393 | (mask_p[4] << 6) | (mask_p[3] << 4)
394 | (mask_p[2] << 2) | (mask_p[1] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
397
398 tmp_mask = (mask_p[30] << 28)
399 | (mask_p[29] << 26) | (mask_p[28] << 24)
400 | (mask_p[27] << 22) | (mask_p[26] << 20)
401 | (mask_p[25] << 18) | (mask_p[24] << 16)
402 | (mask_p[23] << 14) | (mask_p[22] << 12)
403 | (mask_p[21] << 10) | (mask_p[20] << 8)
404 | (mask_p[19] << 6) | (mask_p[18] << 4)
405 | (mask_p[17] << 2) | (mask_p[16] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
408
409 tmp_mask = (mask_p[45] << 28)
410 | (mask_p[44] << 26) | (mask_p[43] << 24)
411 | (mask_p[42] << 22) | (mask_p[41] << 20)
412 | (mask_p[40] << 18) | (mask_p[39] << 16)
413 | (mask_p[38] << 14) | (mask_p[37] << 12)
414 | (mask_p[36] << 10) | (mask_p[35] << 8)
415 | (mask_p[34] << 6) | (mask_p[33] << 4)
416 | (mask_p[32] << 2) | (mask_p[31] << 0);
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
419
420 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
421 | (mask_p[59] << 26) | (mask_p[58] << 24)
422 | (mask_p[57] << 22) | (mask_p[56] << 20)
423 | (mask_p[55] << 18) | (mask_p[54] << 16)
424 | (mask_p[53] << 14) | (mask_p[52] << 12)
425 | (mask_p[51] << 10) | (mask_p[50] << 8)
426 | (mask_p[49] << 6) | (mask_p[48] << 4)
427 | (mask_p[47] << 2) | (mask_p[46] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
430}
431
432/* All code below is for non single-chip solutions */
433
434/**
435 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
436 * @ah: atheros hardware stucture
437 * @chan:
438 *
439 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
440 * the channel value. Assumes writes enabled to analog bus and bank6 register
441 * cache in ah->analogBank6Data.
442 */
443int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
444{
445 struct ath_common *common = ath9k_hw_common(ah);
446 u32 channelSel = 0;
447 u32 bModeSynth = 0;
448 u32 aModeRefSel = 0;
449 u32 reg32 = 0;
450 u16 freq;
451 struct chan_centers centers;
452
453 ath9k_hw_get_channel_centers(ah, chan, &centers);
454 freq = centers.synth_center;
455
456 if (freq < 4800) {
457 u32 txctl;
458
459 if (((freq - 2192) % 5) == 0) {
460 channelSel = ((freq - 672) * 2 - 3040) / 10;
461 bModeSynth = 0;
462 } else if (((freq - 2224) % 5) == 0) {
463 channelSel = ((freq - 704) * 2 - 3040) / 10;
464 bModeSynth = 1;
465 } else {
466 ath_print(common, ATH_DBG_FATAL,
467 "Invalid channel %u MHz\n", freq);
468 return -EINVAL;
469 }
470
471 channelSel = (channelSel << 2) & 0xff;
472 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
473
474 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
475 if (freq == 2484) {
476
477 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
478 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
479 } else {
480 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
481 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
482 }
483
484 } else if ((freq % 20) == 0 && freq >= 5120) {
485 channelSel =
486 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
487 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
488 } else if ((freq % 10) == 0) {
489 channelSel =
490 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
491 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
492 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
493 else
494 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
495 } else if ((freq % 5) == 0) {
496 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
497 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
498 } else {
499 ath_print(common, ATH_DBG_FATAL,
500 "Invalid channel %u MHz\n", freq);
501 return -EINVAL;
502 }
503
504 reg32 =
505 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
506 (1 << 5) | 0x1;
507
508 REG_WRITE(ah, AR_PHY(0x37), reg32);
509
510 ah->curchan = chan;
511 ah->curchan_rad_index = -1;
512
513 return 0;
514}
515
516/**
517 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
518 * @ah: atheros hardware structure
519 * @chan:
520 *
521 * For non single-chip solutions. Converts to baseband spur frequency given the
522 * input channel frequency and compute register settings below.
523 */
524void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
525{
526 int bb_spur = AR_NO_SPUR;
527 int bin, cur_bin;
528 int spur_freq_sd;
529 int spur_delta_phase;
530 int denominator;
531 int upper, lower, cur_vit_mask;
532 int tmp, new;
533 int i;
534 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
535 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
536 };
537 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
538 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
539 };
540 int inc[4] = { 0, 100, 0, 0 };
541
542 int8_t mask_m[123];
543 int8_t mask_p[123];
544 int8_t mask_amt;
545 int tmp_mask;
546 int cur_bb_spur;
547 bool is2GHz = IS_CHAN_2GHZ(chan);
548
549 memset(&mask_m, 0, sizeof(int8_t) * 123);
550 memset(&mask_p, 0, sizeof(int8_t) * 123);
551
552 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
553 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
554 if (AR_NO_SPUR == cur_bb_spur)
555 break;
556 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
557 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
558 bb_spur = cur_bb_spur;
559 break;
560 }
561 }
562
563 if (AR_NO_SPUR == bb_spur)
564 return;
565
566 bin = bb_spur * 32;
567
568 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
569 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
570 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
571 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
572 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
573
574 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
575
576 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
577 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
578 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
579 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
580 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
581 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
582
583 spur_delta_phase = ((bb_spur * 524288) / 100) &
584 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
585
586 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
587 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
588
589 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
590 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
591 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
592 REG_WRITE(ah, AR_PHY_TIMING11, new);
593
594 cur_bin = -6000;
595 upper = bin + 100;
596 lower = bin - 100;
597
598 for (i = 0; i < 4; i++) {
599 int pilot_mask = 0;
600 int chan_mask = 0;
601 int bp = 0;
602 for (bp = 0; bp < 30; bp++) {
603 if ((cur_bin > lower) && (cur_bin < upper)) {
604 pilot_mask = pilot_mask | 0x1 << bp;
605 chan_mask = chan_mask | 0x1 << bp;
606 }
607 cur_bin += 100;
608 }
609 cur_bin += inc[i];
610 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
611 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
612 }
613
614 cur_vit_mask = 6100;
615 upper = bin + 120;
616 lower = bin - 120;
617
618 for (i = 0; i < 123; i++) {
619 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
620
621 /* workaround for gcc bug #37014 */
622 volatile int tmp_v = abs(cur_vit_mask - bin);
623
624 if (tmp_v < 75)
625 mask_amt = 1;
626 else
627 mask_amt = 0;
628 if (cur_vit_mask < 0)
629 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
630 else
631 mask_p[cur_vit_mask / 100] = mask_amt;
632 }
633 cur_vit_mask -= 100;
634 }
635
636 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
637 | (mask_m[48] << 26) | (mask_m[49] << 24)
638 | (mask_m[50] << 22) | (mask_m[51] << 20)
639 | (mask_m[52] << 18) | (mask_m[53] << 16)
640 | (mask_m[54] << 14) | (mask_m[55] << 12)
641 | (mask_m[56] << 10) | (mask_m[57] << 8)
642 | (mask_m[58] << 6) | (mask_m[59] << 4)
643 | (mask_m[60] << 2) | (mask_m[61] << 0);
644 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
645 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
646
647 tmp_mask = (mask_m[31] << 28)
648 | (mask_m[32] << 26) | (mask_m[33] << 24)
649 | (mask_m[34] << 22) | (mask_m[35] << 20)
650 | (mask_m[36] << 18) | (mask_m[37] << 16)
651 | (mask_m[48] << 14) | (mask_m[39] << 12)
652 | (mask_m[40] << 10) | (mask_m[41] << 8)
653 | (mask_m[42] << 6) | (mask_m[43] << 4)
654 | (mask_m[44] << 2) | (mask_m[45] << 0);
655 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
656 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
657
658 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
659 | (mask_m[18] << 26) | (mask_m[18] << 24)
660 | (mask_m[20] << 22) | (mask_m[20] << 20)
661 | (mask_m[22] << 18) | (mask_m[22] << 16)
662 | (mask_m[24] << 14) | (mask_m[24] << 12)
663 | (mask_m[25] << 10) | (mask_m[26] << 8)
664 | (mask_m[27] << 6) | (mask_m[28] << 4)
665 | (mask_m[29] << 2) | (mask_m[30] << 0);
666 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
667 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
668
669 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
670 | (mask_m[2] << 26) | (mask_m[3] << 24)
671 | (mask_m[4] << 22) | (mask_m[5] << 20)
672 | (mask_m[6] << 18) | (mask_m[7] << 16)
673 | (mask_m[8] << 14) | (mask_m[9] << 12)
674 | (mask_m[10] << 10) | (mask_m[11] << 8)
675 | (mask_m[12] << 6) | (mask_m[13] << 4)
676 | (mask_m[14] << 2) | (mask_m[15] << 0);
677 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
678 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
679
680 tmp_mask = (mask_p[15] << 28)
681 | (mask_p[14] << 26) | (mask_p[13] << 24)
682 | (mask_p[12] << 22) | (mask_p[11] << 20)
683 | (mask_p[10] << 18) | (mask_p[9] << 16)
684 | (mask_p[8] << 14) | (mask_p[7] << 12)
685 | (mask_p[6] << 10) | (mask_p[5] << 8)
686 | (mask_p[4] << 6) | (mask_p[3] << 4)
687 | (mask_p[2] << 2) | (mask_p[1] << 0);
688 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
689 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
690
691 tmp_mask = (mask_p[30] << 28)
692 | (mask_p[29] << 26) | (mask_p[28] << 24)
693 | (mask_p[27] << 22) | (mask_p[26] << 20)
694 | (mask_p[25] << 18) | (mask_p[24] << 16)
695 | (mask_p[23] << 14) | (mask_p[22] << 12)
696 | (mask_p[21] << 10) | (mask_p[20] << 8)
697 | (mask_p[19] << 6) | (mask_p[18] << 4)
698 | (mask_p[17] << 2) | (mask_p[16] << 0);
699 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
700 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
701
702 tmp_mask = (mask_p[45] << 28)
703 | (mask_p[44] << 26) | (mask_p[43] << 24)
704 | (mask_p[42] << 22) | (mask_p[41] << 20)
705 | (mask_p[40] << 18) | (mask_p[39] << 16)
706 | (mask_p[38] << 14) | (mask_p[37] << 12)
707 | (mask_p[36] << 10) | (mask_p[35] << 8)
708 | (mask_p[34] << 6) | (mask_p[33] << 4)
709 | (mask_p[32] << 2) | (mask_p[31] << 0);
710 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
711 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
712
713 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
714 | (mask_p[59] << 26) | (mask_p[58] << 24)
715 | (mask_p[57] << 22) | (mask_p[56] << 20)
716 | (mask_p[55] << 18) | (mask_p[54] << 16)
717 | (mask_p[53] << 14) | (mask_p[52] << 12)
718 | (mask_p[51] << 10) | (mask_p[50] << 8)
719 | (mask_p[49] << 6) | (mask_p[48] << 4)
720 | (mask_p[47] << 2) | (mask_p[46] << 0);
721 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
722 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
723}
724
725/**
726 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
727 * @ah: atheros hardware structure
728 *
729 * Only required for older devices with external AR2133/AR5133 radios.
730 */
731int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
732{
733#define ATH_ALLOC_BANK(bank, size) do { \
734 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
735 if (!bank) { \
736 ath_print(common, ATH_DBG_FATAL, \
737 "Cannot allocate RF banks\n"); \
738 return -ENOMEM; \
739 } \
740 } while (0);
741
742 struct ath_common *common = ath9k_hw_common(ah);
743
744 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
745
746 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
747 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
748 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
749 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
750 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
751 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
752 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
753 ATH_ALLOC_BANK(ah->addac5416_21,
754 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
755 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
756
757 return 0;
758#undef ATH_ALLOC_BANK
759}
760
761
762/**
763 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
764 * @ah: atheros hardware struture
765 * For the external AR2133/AR5133 radios banks.
766 */
767void
768ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
769{
770#define ATH_FREE_BANK(bank) do { \
771 kfree(bank); \
772 bank = NULL; \
773 } while (0);
774
775 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
776
777 ATH_FREE_BANK(ah->analogBank0Data);
778 ATH_FREE_BANK(ah->analogBank1Data);
779 ATH_FREE_BANK(ah->analogBank2Data);
780 ATH_FREE_BANK(ah->analogBank3Data);
781 ATH_FREE_BANK(ah->analogBank6Data);
782 ATH_FREE_BANK(ah->analogBank6TPCData);
783 ATH_FREE_BANK(ah->analogBank7Data);
784 ATH_FREE_BANK(ah->addac5416_21);
785 ATH_FREE_BANK(ah->bank6Temp);
786
787#undef ATH_FREE_BANK
788}
789
790/**
258 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters 791 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
259 * @rfbuf: 792 * @rfbuf:
260 * @reg32: 793 * @reg32:
@@ -265,10 +798,9 @@ int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
265 * Performs analog "swizzling" of parameters into their location. 798 * Performs analog "swizzling" of parameters into their location.
266 * Used on external AR2133/AR5133 radios. 799 * Used on external AR2133/AR5133 radios.
267 */ 800 */
268static void 801static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
269ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 802 u32 numBits, u32 firstBit,
270 u32 numBits, u32 firstBit, 803 u32 column)
271 u32 column)
272{ 804{
273 u32 tmp32, mask, arrayEntry, lastBit; 805 u32 tmp32, mask, arrayEntry, lastBit;
274 int32_t bitPosition, bitsLeft; 806 int32_t bitPosition, bitsLeft;
@@ -304,9 +836,8 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
304 * all rf registers. This routine requires access to the analog 836 * all rf registers. This routine requires access to the analog
305 * rf device. This is not required for single-chip devices. 837 * rf device. This is not required for single-chip devices.
306 */ 838 */
307bool 839bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
308ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 840 u16 modesIndex)
309 u16 modesIndex)
310{ 841{
311 u32 eepMinorRev; 842 u32 eepMinorRev;
312 u32 ob5GHz = 0, db5GHz = 0; 843 u32 ob5GHz = 0, db5GHz = 0;
@@ -384,70 +915,6 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
384} 915}
385 916
386/** 917/**
387 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
388 * @ah: atheros hardware struture
389 * For the external AR2133/AR5133 radios banks.
390 */
391void
392ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
393{
394#define ATH_FREE_BANK(bank) do { \
395 kfree(bank); \
396 bank = NULL; \
397 } while (0);
398
399 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
400
401 ATH_FREE_BANK(ah->analogBank0Data);
402 ATH_FREE_BANK(ah->analogBank1Data);
403 ATH_FREE_BANK(ah->analogBank2Data);
404 ATH_FREE_BANK(ah->analogBank3Data);
405 ATH_FREE_BANK(ah->analogBank6Data);
406 ATH_FREE_BANK(ah->analogBank6TPCData);
407 ATH_FREE_BANK(ah->analogBank7Data);
408 ATH_FREE_BANK(ah->addac5416_21);
409 ATH_FREE_BANK(ah->bank6Temp);
410
411#undef ATH_FREE_BANK
412}
413
414/**
415 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
416 * @ah: atheros hardware structure
417 *
418 * Only required for older devices with external AR2133/AR5133 radios.
419 */
420int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
421{
422#define ATH_ALLOC_BANK(bank, size) do { \
423 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
424 if (!bank) { \
425 ath_print(common, ATH_DBG_FATAL, \
426 "Cannot allocate RF banks\n"); \
427 return -ENOMEM; \
428 } \
429 } while (0);
430
431 struct ath_common *common = ath9k_hw_common(ah);
432
433 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
434
435 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
436 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
437 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
438 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
439 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
440 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
441 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
442 ATH_ALLOC_BANK(ah->addac5416_21,
443 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
444 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
445
446 return 0;
447#undef ATH_ALLOC_BANK
448}
449
450/**
451 * ath9k_hw_decrease_chain_power() 918 * ath9k_hw_decrease_chain_power()
452 * 919 *
453 * @ah: atheros hardware structure 920 * @ah: atheros hardware structure
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index bef9b41d250f..ba297bef7dc5 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,19 +17,28 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); 20/* Common between single chip and non single-chip solutions */
21int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
22void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 21void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,
23 u32 freqIndex, int regWrites); 22 u32 freqIndex, int regWrites);
23
24/* Single chip radio settings */
25int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
26void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
27
28/* Routines below are for non single-chip solutions */
29int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
30void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
31
32int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
33void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
34
24bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 35bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
25 struct ath9k_channel *chan, 36 struct ath9k_channel *chan,
26 u16 modesIndex); 37 u16 modesIndex);
38
27void ath9k_hw_decrease_chain_power(struct ath_hw *ah, 39void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
28 struct ath9k_channel *chan); 40 struct ath9k_channel *chan);
29 41
30void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32
33#define AR_PHY_BASE 0x9800 42#define AR_PHY_BASE 0x9800
34#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 43#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
35 44
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 00:29:31 -0400