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-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h33
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h34
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF544.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF547.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF548.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF549.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h33
7 files changed, 1 insertions, 231 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 3f4de5d9d4cb..50e14e7da3ee 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -873,39 +873,6 @@
873 873
874 874
875/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 875/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
876#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
877#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
878#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
879#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
880#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
881#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
882#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
883#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
884#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
885#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
886#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
887#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
888#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
889#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
890#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
891#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
892#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
893#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
894#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
895#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
896#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
897#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
898#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
899#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
900#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
901#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
902#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
903#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
904#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
905#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
906#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
907#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
908
909 876
910/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 877/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
911#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 878#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 78227bc855df..048d26a61fd1 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -858,39 +858,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
858#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 858#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
859#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 859#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
860 860
861/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 861/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
862#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
863#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
864#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
865#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
866#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
867#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
868#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
869#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
870#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
871#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
872#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
873#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
874#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
875#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
876#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
877#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
878#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
879#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
880#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
881#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
882#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
883#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
884#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
885#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
886#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
887#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
888#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
889#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
890#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
891#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
892#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
893#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
894 862
895/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 863/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
896#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 864#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
index 7a2d177c8dc2..ea9b4ab496f3 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF544.h
@@ -113,39 +113,6 @@
113 113
114/* Two Wire Interface Registers (TWI1) */ 114/* Two Wire Interface Registers (TWI1) */
115 115
116#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
117#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
118#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
119#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
120#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
121#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
122#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
123#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
124#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
125#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
126#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
127#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
128#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
129#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
130#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
131#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
132#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
133#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
134#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
135#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
136#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
137#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
138#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
139#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
140#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
141#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
142#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
143#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
144#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
145#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
146#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
147#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
148
149/* CAN Controller 1 Config 1 Registers */ 116/* CAN Controller 1 Config 1 Registers */
150 117
151#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) 118#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
index d0a200b08abd..ba716277c00d 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF547.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
index 674be0216bff..ae971ebff6a0 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF548.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
index 2ab5b7c00820..38eafe71913d 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF549.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 19ddcd83c71f..d8d2f1f127db 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -211,39 +211,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
211 211
212/* Two Wire Interface Registers (TWI0) */ 212/* Two Wire Interface Registers (TWI0) */
213 213
214#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
215#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
216#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
217#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
218#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
219#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
220#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
221#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
222#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
223#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
224#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
225#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
226#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
227#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
228#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
229#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
230#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
231#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
232#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
233#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
234#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
235#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
236#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
237#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
238#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
239#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
240#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
241#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
242#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
243#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246
247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 214/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
248 215
249/* SPORT1 Registers */ 216/* SPORT1 Registers */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 18:24:38 -0500