2 files changed, 33 insertions, 12 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 81dafc26cdff..bb95c6ecda49 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7819,11 +7819,26 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tw32_f(TG3_CPMU_EEE_CTRL,
                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
 
-                tw32_f(TG3_CPMU_EEE_MODE,
-                       TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
-                       TG3_CPMU_EEEMD_LPI_IN_TX |
-                       TG3_CPMU_EEEMD_LPI_IN_RX |
-                       TG3_CPMU_EEEMD_EEE_ENABLE);
+                val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+                      TG3_CPMU_EEEMD_LPI_IN_TX |
+                      TG3_CPMU_EEEMD_LPI_IN_RX |
+                      TG3_CPMU_EEEMD_EEE_ENABLE;
+
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                        val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
+
+                if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                        val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
+
+                tw32_f(TG3_CPMU_EEE_MODE, val);
+
+                tw32_f(TG3_CPMU_EEE_DBTMR1,
+                       TG3_CPMU_DBTMR1_PCIEXIT_2047US |
+                       TG3_CPMU_DBTMR1_LNKIDLE_2047US);
+
+                tw32_f(TG3_CPMU_EEE_DBTMR2,
+                       TG3_CPMU_DBTMR1_APE_TX_2047US |
+                       TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
         }
 
         if (reset_phy)
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 6e72c6bd2675..d62c8d937c82 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1094,13 +1094,19 @@
 /* 0x3664 --> 0x36b0 unused */
 
 #define TG3_CPMU_EEE_MODE               0x000036b0
-#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008
-#define TG3_CPMU_EEEMD_LPI_ENABLE        0x00000080
-#define TG3_CPMU_EEEMD_LPI_IN_TX         0x00000100
-#define TG3_CPMU_EEEMD_LPI_IN_RX         0x00000200
-#define TG3_CPMU_EEEMD_EEE_ENABLE        0x00100000
-/* 0x36b4 --> 0x36b8 unused */
-
+#define  TG3_CPMU_EEEMD_APE_TX_DET_EN    0x00000004
+#define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET  0x00000008
+#define  TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
+#define  TG3_CPMU_EEEMD_LPI_ENABLE       0x00000080
+#define  TG3_CPMU_EEEMD_LPI_IN_TX        0x00000100
+#define  TG3_CPMU_EEEMD_LPI_IN_RX        0x00000200
+#define  TG3_CPMU_EEEMD_EEE_ENABLE       0x00100000
+#define TG3_CPMU_EEE_DBTMR1             0x000036b4
+#define  TG3_CPMU_DBTMR1_PCIEXIT_2047US  0x07ff0000
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US  0x000070ff
+#define TG3_CPMU_EEE_DBTMR2             0x000036b8
+#define  TG3_CPMU_DBTMR1_APE_TX_2047US   0x07ff0000
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US  0x000070ff
 #define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004