aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/hwmon/wm831x37
-rw-r--r--Documentation/hwmon/wm835026
-rw-r--r--MAINTAINERS20
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c122
-rw-r--r--drivers/gpio/Kconfig7
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/wm831x-gpio.c252
-rw-r--r--drivers/hwmon/Kconfig21
-rw-r--r--drivers/hwmon/Makefile2
-rw-r--r--drivers/hwmon/wm831x-hwmon.c226
-rw-r--r--drivers/hwmon/wm8350-hwmon.c151
-rw-r--r--drivers/input/misc/Kconfig20
-rw-r--r--drivers/input/misc/Makefile3
-rw-r--r--drivers/input/misc/pcap_keys.c144
-rw-r--r--drivers/input/misc/wm831x-on.c163
-rw-r--r--drivers/input/touchscreen/Kconfig9
-rw-r--r--drivers/input/touchscreen/Makefile1
-rw-r--r--drivers/input/touchscreen/pcap_ts.c271
-rw-r--r--drivers/mfd/Kconfig42
-rw-r--r--drivers/mfd/Makefile6
-rw-r--r--drivers/mfd/ab3100-core.c62
-rw-r--r--drivers/mfd/ab3100-otp.c268
-rw-r--r--drivers/mfd/dm355evm_msp.c12
-rw-r--r--drivers/mfd/ezx-pcap.c105
-rw-r--r--drivers/mfd/mc13783-core.c427
-rw-r--r--drivers/mfd/mfd-core.c2
-rw-r--r--drivers/mfd/pcf50633-adc.c32
-rw-r--r--drivers/mfd/pcf50633-core.c5
-rw-r--r--drivers/mfd/twl4030-core.c23
-rw-r--r--drivers/mfd/twl4030-irq.c2
-rw-r--r--drivers/mfd/twl4030-power.c472
-rw-r--r--drivers/mfd/wm831x-core.c1549
-rw-r--r--drivers/mfd/wm831x-irq.c559
-rw-r--r--drivers/mfd/wm831x-otp.c83
-rw-r--r--drivers/mfd/wm8350-core.c27
-rw-r--r--drivers/regulator/Kconfig31
-rw-r--r--drivers/regulator/Makefile6
-rw-r--r--drivers/regulator/ab3100.c700
-rw-r--r--drivers/regulator/core.c24
-rw-r--r--drivers/regulator/mc13783.c410
-rw-r--r--drivers/regulator/pcap-regulator.c318
-rw-r--r--drivers/regulator/wm831x-dcdc.c862
-rw-r--r--drivers/regulator/wm831x-isink.c260
-rw-r--r--drivers/regulator/wm831x-ldo.c852
-rw-r--r--drivers/rtc/Kconfig19
-rw-r--r--drivers/rtc/Makefile2
-rw-r--r--drivers/rtc/rtc-ab3100.c281
-rw-r--r--drivers/rtc/rtc-wm831x.c523
-rw-r--r--include/linux/i2c/twl4030.h94
-rw-r--r--include/linux/mfd/ab3100.h37
-rw-r--r--include/linux/mfd/core.h1
-rw-r--r--include/linux/mfd/ezx-pcap.h7
-rw-r--r--include/linux/mfd/mc13783-private.h396
-rw-r--r--include/linux/mfd/mc13783.h84
-rw-r--r--include/linux/mfd/pcf50633/adc.h3
-rw-r--r--include/linux/mfd/pcf50633/core.h1
-rw-r--r--include/linux/mfd/wm831x/auxadc.h216
-rw-r--r--include/linux/mfd/wm831x/core.h289
-rw-r--r--include/linux/mfd/wm831x/gpio.h55
-rw-r--r--include/linux/mfd/wm831x/irq.h764
-rw-r--r--include/linux/mfd/wm831x/otp.h162
-rw-r--r--include/linux/mfd/wm831x/pdata.h113
-rw-r--r--include/linux/mfd/wm831x/regulator.h1218
-rw-r--r--include/linux/mfd/wm8350/core.h7
-rw-r--r--include/linux/regulator/driver.h2
65 files changed, 12770 insertions, 119 deletions
diff --git a/Documentation/hwmon/wm831x b/Documentation/hwmon/wm831x
new file mode 100644
index 000000000000..24f47d8f6a42
--- /dev/null
+++ b/Documentation/hwmon/wm831x
@@ -0,0 +1,37 @@
1Kernel driver wm831x-hwmon
2==========================
3
4Supported chips:
5 * Wolfson Microelectronics WM831x PMICs
6 Prefix: 'wm831x'
7 Datasheet:
8 http://www.wolfsonmicro.com/products/WM8310
9 http://www.wolfsonmicro.com/products/WM8311
10 http://www.wolfsonmicro.com/products/WM8312
11
12Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
13
14Description
15-----------
16
17The WM831x series of PMICs include an AUXADC which can be used to
18monitor a range of system operating parameters, including the voltages
19of the major supplies within the system. Currently the driver provides
20reporting of all the input values but does not provide any alarms.
21
22Voltage Monitoring
23------------------
24
25Voltages are sampled by a 12 bit ADC. Voltages in milivolts are 1.465
26times the ADC value.
27
28Temperature Monitoring
29----------------------
30
31Temperatures are sampled by a 12 bit ADC. Chip and battery temperatures
32are available. The chip temperature is calculated as:
33
34 Degrees celsius = (512.18 - data) / 1.0983
35
36while the battery temperature calculation will depend on the NTC
37thermistor component.
diff --git a/Documentation/hwmon/wm8350 b/Documentation/hwmon/wm8350
new file mode 100644
index 000000000000..98f923bd2e92
--- /dev/null
+++ b/Documentation/hwmon/wm8350
@@ -0,0 +1,26 @@
1Kernel driver wm8350-hwmon
2==========================
3
4Supported chips:
5 * Wolfson Microelectronics WM835x PMICs
6 Prefix: 'wm8350'
7 Datasheet:
8 http://www.wolfsonmicro.com/products/WM8350
9 http://www.wolfsonmicro.com/products/WM8351
10 http://www.wolfsonmicro.com/products/WM8352
11
12Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
13
14Description
15-----------
16
17The WM835x series of PMICs include an AUXADC which can be used to
18monitor a range of system operating parameters, including the voltages
19of the major supplies within the system. Currently the driver provides
20simple access to these major supplies.
21
22Voltage Monitoring
23------------------
24
25Voltages are sampled by a 12 bit ADC. For the internal supplies the ADC
26is referenced to the system VRTC.
diff --git a/MAINTAINERS b/MAINTAINERS
index e2b9486fd1a9..bd3f026dbe61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5683,6 +5683,26 @@ S: Supported
5683F: drivers/input/touchscreen/*wm97* 5683F: drivers/input/touchscreen/*wm97*
5684F: include/linux/wm97xx.h 5684F: include/linux/wm97xx.h
5685 5685
5686WOLFSON MICROELECTRONICS PMIC DRIVERS
5687P: Mark Brown
5688M: broonie@opensource.wolfsonmicro.com
5689L: linux-kernel@vger.kernel.org
5690T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
5691W: http://opensource.wolfsonmicro.com/node/8
5692S: Supported
5693F: drivers/leds/leds-wm83*.c
5694F: drivers/mfd/wm8*.c
5695F: drivers/power/wm83*.c
5696F: drivers/rtc/rtc-wm83*.c
5697F: drivers/regulator/wm8*.c
5698F: drivers/video/backlight/wm83*_bl.c
5699F: drivers/watchdog/wm83*_wdt.c
5700F: include/linux/mfd/wm831x/
5701F: include/linux/mfd/wm8350/
5702F: include/linux/mfd/wm8400/
5703F: sound/soc/codecs/wm8350.c
5704F: sound/soc/codecs/wm8400.c
5705
5686X.25 NETWORK LAYER 5706X.25 NETWORK LAYER
5687M: Henner Eisen <eis@baty.hanse.de> 5707M: Henner Eisen <eis@baty.hanse.de>
5688L: linux-x25@vger.kernel.org 5708L: linux-x25@vger.kernel.org
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 56d931a425f7..e70baa799018 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/board-rx51-flash.c 2 * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
3 * 3 *
4 * Copyright (C) 2008-2009 Nokia 4 * Copyright (C) 2008-2009 Nokia
5 * 5 *
@@ -282,7 +282,124 @@ static struct twl4030_usb_data rx51_usb_data = {
282 .usb_mode = T2_USB_MODE_ULPI, 282 .usb_mode = T2_USB_MODE_ULPI,
283}; 283};
284 284
285static struct twl4030_platform_data rx51_twldata = { 285static struct twl4030_ins sleep_on_seq[] __initdata = {
286/*
287 * Turn off VDD1 and VDD2.
288 */
289 {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
290 {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
291/*
292 * And also turn off the OMAP3 PLLs and the sysclk output.
293 */
294 {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
295 {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3},
296};
297
298static struct twl4030_script sleep_on_script __initdata = {
299 .script = sleep_on_seq,
300 .size = ARRAY_SIZE(sleep_on_seq),
301 .flags = TWL4030_SLEEP_SCRIPT,
302};
303
304static struct twl4030_ins wakeup_seq[] __initdata = {
305/*
306 * Reenable the OMAP3 PLLs.
307 * Wakeup VDD1 and VDD2.
308 * Reenable sysclk output.
309 */
310 {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
311 {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
312 {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
313 {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
314};
315
316static struct twl4030_script wakeup_script __initdata = {
317 .script = wakeup_seq,
318 .size = ARRAY_SIZE(wakeup_seq),
319 .flags = TWL4030_WAKEUP12_SCRIPT,
320};
321
322static struct twl4030_ins wakeup_p3_seq[] __initdata = {
323/*
324 * Wakeup VDD1 (dummy to be able to insert a delay)
325 * Enable CLKEN
326 */
327 {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3},
328};
329
330static struct twl4030_script wakeup_p3_script __initdata = {
331 .script = wakeup_p3_seq,
332 .size = ARRAY_SIZE(wakeup_p3_seq),
333 .flags = TWL4030_WAKEUP3_SCRIPT,
334};
335
336static struct twl4030_ins wrst_seq[] __initdata = {
337/*
338 * Reset twl4030.
339 * Reset VDD1 regulator.
340 * Reset VDD2 regulator.
341 * Reset VPLL1 regulator.
342 * Enable sysclk output.
343 * Reenable twl4030.
344 */
345 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
346 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
347 0x13},
348 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13},
349 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
350 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
351 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
352 {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
353 {MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
354 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
355};
356
357static struct twl4030_script wrst_script __initdata = {
358 .script = wrst_seq,
359 .size = ARRAY_SIZE(wrst_seq),
360 .flags = TWL4030_WRST_SCRIPT,
361};
362
363static struct twl4030_script *twl4030_scripts[] __initdata = {
364 /* wakeup12 script should be loaded before sleep script, otherwise a
365 board might hit retention before loading of wakeup script is
366 completed. This can cause boot failures depending on timing issues.
367 */
368 &wakeup_script,
369 &sleep_on_script,
370 &wakeup_p3_script,
371 &wrst_script,
372};
373
374static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
375 { .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 },
376 { .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 },
377 { .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 },
378 { .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3},
379 { .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1,
380 .type2 = 3},
381 { .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3},
382 { .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3},
383 { .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3},
384 { .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3},
385 { .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3},
386 { .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3},
387 { .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1,
388 .type2 = 3},
389 { .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1,
390 .type2 = 1 },
391 { 0, 0},
392};
393
394static struct twl4030_power_data rx51_t2scripts_data __initdata = {
395 .scripts = twl4030_scripts,
396 .num = ARRAY_SIZE(twl4030_scripts),
397 .resource_config = twl4030_rconfig,
398};
399
400
401
402static struct twl4030_platform_data rx51_twldata __initdata = {
286 .irq_base = TWL4030_IRQ_BASE, 403 .irq_base = TWL4030_IRQ_BASE,
287 .irq_end = TWL4030_IRQ_END, 404 .irq_end = TWL4030_IRQ_END,
288 405
@@ -291,6 +408,7 @@ static struct twl4030_platform_data rx51_twldata = {
291 .keypad = &rx51_kp_data, 408 .keypad = &rx51_kp_data,
292 .madc = &rx51_madc_data, 409 .madc = &rx51_madc_data,
293 .usb = &rx51_usb_data, 410 .usb = &rx51_usb_data,
411 .power = &rx51_t2scripts_data,
294 412
295 .vaux1 = &rx51_vaux1, 413 .vaux1 = &rx51_vaux1,
296 .vaux2 = &rx51_vaux2, 414 .vaux2 = &rx51_vaux2,
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 96dda81c9228..6b4c484a699a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -155,6 +155,13 @@ config GPIO_TWL4030
155 Say yes here to access the GPIO signals of various multi-function 155 Say yes here to access the GPIO signals of various multi-function
156 power management chips from Texas Instruments. 156 power management chips from Texas Instruments.
157 157
158config GPIO_WM831X
159 tristate "WM831x GPIOs"
160 depends on MFD_WM831X
161 help
162 Say yes here to access the GPIO signals of WM831x power management
163 chips from Wolfson Microelectronics.
164
158comment "PCI GPIO expanders:" 165comment "PCI GPIO expanders:"
159 166
160config GPIO_BT8XX 167config GPIO_BT8XX
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9244c6fcd8be..ea7c745f26a8 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
14obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o 14obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o
15obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o 15obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o
16obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o 16obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
17obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c
new file mode 100644
index 000000000000..f9c09a54ec7f
--- /dev/null
+++ b/drivers/gpio/wm831x-gpio.c
@@ -0,0 +1,252 @@
1/*
2 * wm831x-gpio.c -- gpiolib support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/gpio.h>
18#include <linux/mfd/core.h>
19#include <linux/platform_device.h>
20#include <linux/seq_file.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/pdata.h>
24#include <linux/mfd/wm831x/gpio.h>
25
26#define WM831X_GPIO_MAX 16
27
28struct wm831x_gpio {
29 struct wm831x *wm831x;
30 struct gpio_chip gpio_chip;
31};
32
33static inline struct wm831x_gpio *to_wm831x_gpio(struct gpio_chip *chip)
34{
35 return container_of(chip, struct wm831x_gpio, gpio_chip);
36}
37
38static int wm831x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
39{
40 struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
41 struct wm831x *wm831x = wm831x_gpio->wm831x;
42
43 return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset,
44 WM831X_GPN_DIR | WM831X_GPN_TRI,
45 WM831X_GPN_DIR);
46}
47
48static int wm831x_gpio_get(struct gpio_chip *chip, unsigned offset)
49{
50 struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
51 struct wm831x *wm831x = wm831x_gpio->wm831x;
52 int ret;
53
54 ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
55 if (ret < 0)
56 return ret;
57
58 if (ret & 1 << offset)
59 return 1;
60 else
61 return 0;
62}
63
64static int wm831x_gpio_direction_out(struct gpio_chip *chip,
65 unsigned offset, int value)
66{
67 struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
68 struct wm831x *wm831x = wm831x_gpio->wm831x;
69
70 return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset,
71 WM831X_GPN_DIR | WM831X_GPN_TRI, 0);
72}
73
74static void wm831x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
75{
76 struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
77 struct wm831x *wm831x = wm831x_gpio->wm831x;
78
79 wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << offset,
80 value << offset);
81}
82
83#ifdef CONFIG_DEBUG_FS
84static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
85{
86 struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
87 struct wm831x *wm831x = wm831x_gpio->wm831x;
88 int i;
89
90 for (i = 0; i < chip->ngpio; i++) {
91 int gpio = i + chip->base;
92 int reg;
93 const char *label, *pull, *powerdomain;
94
95 /* We report the GPIO even if it's not requested since
96 * we're also reporting things like alternate
97 * functions which apply even when the GPIO is not in
98 * use as a GPIO.
99 */
100 label = gpiochip_is_requested(chip, i);
101 if (!label)
102 label = "Unrequested";
103
104 seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label);
105
106 reg = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);
107 if (reg < 0) {
108 dev_err(wm831x->dev,
109 "GPIO control %d read failed: %d\n",
110 gpio, reg);
111 seq_printf(s, "\n");
112 continue;
113 }
114
115 switch (reg & WM831X_GPN_PULL_MASK) {
116 case WM831X_GPIO_PULL_NONE:
117 pull = "nopull";
118 break;
119 case WM831X_GPIO_PULL_DOWN:
120 pull = "pulldown";
121 break;
122 case WM831X_GPIO_PULL_UP:
123 pull = "pullup";
124 default:
125 pull = "INVALID PULL";
126 break;
127 }
128
129 switch (i + 1) {
130 case 1 ... 3:
131 case 7 ... 9:
132 if (reg & WM831X_GPN_PWR_DOM)
133 powerdomain = "VPMIC";
134 else
135 powerdomain = "DBVDD";
136 break;
137
138 case 4 ... 6:
139 case 10 ... 12:
140 if (reg & WM831X_GPN_PWR_DOM)
141 powerdomain = "SYSVDD";
142 else
143 powerdomain = "DBVDD";
144 break;
145
146 case 13 ... 16:
147 powerdomain = "TPVDD";
148 break;
149
150 default:
151 BUG();
152 break;
153 }
154
155 seq_printf(s, " %s %s %s %s%s\n"
156 " %s%s (0x%4x)\n",
157 reg & WM831X_GPN_DIR ? "in" : "out",
158 wm831x_gpio_get(chip, i) ? "high" : "low",
159 pull,
160 powerdomain,
161 reg & WM831X_GPN_POL ? " inverted" : "",
162 reg & WM831X_GPN_OD ? "open-drain" : "CMOS",
163 reg & WM831X_GPN_TRI ? " tristated" : "",
164 reg);
165 }
166}
167#else
168#define wm831x_gpio_dbg_show NULL
169#endif
170
171static struct gpio_chip template_chip = {
172 .label = "wm831x",
173 .owner = THIS_MODULE,
174 .direction_input = wm831x_gpio_direction_in,
175 .get = wm831x_gpio_get,
176 .direction_output = wm831x_gpio_direction_out,
177 .set = wm831x_gpio_set,
178 .dbg_show = wm831x_gpio_dbg_show,
179 .can_sleep = 1,
180};
181
182static int __devinit wm831x_gpio_probe(struct platform_device *pdev)
183{
184 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
185 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
186 struct wm831x_gpio *wm831x_gpio;
187 int ret;
188
189 wm831x_gpio = kzalloc(sizeof(*wm831x_gpio), GFP_KERNEL);
190 if (wm831x_gpio == NULL)
191 return -ENOMEM;
192
193 wm831x_gpio->wm831x = wm831x;
194 wm831x_gpio->gpio_chip = template_chip;
195 wm831x_gpio->gpio_chip.ngpio = WM831X_GPIO_MAX;
196 wm831x_gpio->gpio_chip.dev = &pdev->dev;
197 if (pdata && pdata->gpio_base)
198 wm831x_gpio->gpio_chip.base = pdata->gpio_base;
199 else
200 wm831x_gpio->gpio_chip.base = -1;
201
202 ret = gpiochip_add(&wm831x_gpio->gpio_chip);
203 if (ret < 0) {
204 dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
205 ret);
206 goto err;
207 }
208
209 platform_set_drvdata(pdev, wm831x_gpio);
210
211 return ret;
212
213err:
214 kfree(wm831x_gpio);
215 return ret;
216}
217
218static int __devexit wm831x_gpio_remove(struct platform_device *pdev)
219{
220 struct wm831x_gpio *wm831x_gpio = platform_get_drvdata(pdev);
221 int ret;
222
223 ret = gpiochip_remove(&wm831x_gpio->gpio_chip);
224 if (ret == 0)
225 kfree(wm831x_gpio);
226
227 return ret;
228}
229
230static struct platform_driver wm831x_gpio_driver = {
231 .driver.name = "wm831x-gpio",
232 .driver.owner = THIS_MODULE,
233 .probe = wm831x_gpio_probe,
234 .remove = __devexit_p(wm831x_gpio_remove),
235};
236
237static int __init wm831x_gpio_init(void)
238{
239 return platform_driver_register(&wm831x_gpio_driver);
240}
241subsys_initcall(wm831x_gpio_init);
242
243static void __exit wm831x_gpio_exit(void)
244{
245 platform_driver_unregister(&wm831x_gpio_driver);
246}
247module_exit(wm831x_gpio_exit);
248
249MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
250MODULE_DESCRIPTION("GPIO interface for WM831x PMICs");
251MODULE_LICENSE("GPL");
252MODULE_ALIAS("platform:wm831x-gpio");
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 461abb1e273a..ed7711d11ae8 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -946,6 +946,27 @@ config SENSORS_W83627EHF
946 This driver can also be built as a module. If so, the module 946 This driver can also be built as a module. If so, the module
947 will be called w83627ehf. 947 will be called w83627ehf.
948 948
949config SENSORS_WM831X
950 tristate "WM831x PMICs"
951 depends on MFD_WM831X
952 help
953 If you say yes here you get support for the hardware
954 monitoring functionality of the Wolfson Microelectronics
955 WM831x series of PMICs.
956
957 This driver can also be built as a module. If so, the module
958 will be called wm831x-hwmon.
959
960config SENSORS_WM8350
961 tristate "Wolfson Microelectronics WM835x"
962 depends on MFD_WM8350
963 help
964 If you say yes here you get support for the hardware
965 monitoring features of the WM835x series of PMICs.
966
967 This driver can also be built as a module. If so, the module
968 will be called wm8350-hwmon.
969
949config SENSORS_ULTRA45 970config SENSORS_ULTRA45
950 tristate "Sun Ultra45 PIC16F747" 971 tristate "Sun Ultra45 PIC16F747"
951 depends on SPARC64 972 depends on SPARC64
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 2e547881bc0a..bcf73a9bb619 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -93,6 +93,8 @@ obj-$(CONFIG_SENSORS_VT8231) += vt8231.o
93obj-$(CONFIG_SENSORS_W83627EHF) += w83627ehf.o 93obj-$(CONFIG_SENSORS_W83627EHF) += w83627ehf.o
94obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o 94obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o
95obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o 95obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
96obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
97obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
96 98
97ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y) 99ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y)
98EXTRA_CFLAGS += -DDEBUG 100EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/hwmon/wm831x-hwmon.c b/drivers/hwmon/wm831x-hwmon.c
new file mode 100644
index 000000000000..c16e9e74c356
--- /dev/null
+++ b/drivers/hwmon/wm831x-hwmon.c
@@ -0,0 +1,226 @@
1/*
2 * drivers/hwmon/wm831x-hwmon.c - Wolfson Microelectronics WM831x PMIC
3 * hardware monitoring features.
4 *
5 * Copyright (C) 2009 Wolfson Microelectronics plc
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License v2 as published by the
9 * Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/err.h>
25#include <linux/hwmon.h>
26#include <linux/hwmon-sysfs.h>
27
28#include <linux/mfd/wm831x/core.h>
29#include <linux/mfd/wm831x/auxadc.h>
30
31struct wm831x_hwmon {
32 struct wm831x *wm831x;
33 struct device *classdev;
34};
35
36static ssize_t show_name(struct device *dev,
37 struct device_attribute *attr, char *buf)
38{
39 return sprintf(buf, "wm831x\n");
40}
41
42static const char *input_names[] = {
43 [WM831X_AUX_SYSVDD] = "SYSVDD",
44 [WM831X_AUX_USB] = "USB",
45 [WM831X_AUX_BKUP_BATT] = "Backup battery",
46 [WM831X_AUX_BATT] = "Battery",
47 [WM831X_AUX_WALL] = "WALL",
48 [WM831X_AUX_CHIP_TEMP] = "PMIC",
49 [WM831X_AUX_BATT_TEMP] = "Battery",
50};
51
52
53static ssize_t show_voltage(struct device *dev,
54 struct device_attribute *attr, char *buf)
55{
56 struct wm831x_hwmon *hwmon = dev_get_drvdata(dev);
57 int channel = to_sensor_dev_attr(attr)->index;
58 int ret;
59
60 ret = wm831x_auxadc_read_uv(hwmon->wm831x, channel);
61 if (ret < 0)
62 return ret;
63
64 return sprintf(buf, "%d\n", DIV_ROUND_CLOSEST(ret, 1000));
65}
66
67static ssize_t show_chip_temp(struct device *dev,
68 struct device_attribute *attr, char *buf)
69{
70 struct wm831x_hwmon *hwmon = dev_get_drvdata(dev);
71 int channel = to_sensor_dev_attr(attr)->index;
72 int ret;
73
74 ret = wm831x_auxadc_read(hwmon->wm831x, channel);
75 if (ret < 0)
76 return ret;
77
78 /* Degrees celsius = (512.18-ret) / 1.0983 */
79 ret = 512180 - (ret * 1000);
80 ret = DIV_ROUND_CLOSEST(ret * 10000, 10983);
81
82 return sprintf(buf, "%d\n", ret);
83}
84
85static ssize_t show_label(struct device *dev,
86 struct device_attribute *attr, char *buf)
87{
88 int channel = to_sensor_dev_attr(attr)->index;
89
90 return sprintf(buf, "%s\n", input_names[channel]);
91}
92
93#define WM831X_VOLTAGE(id, name) \
94 static SENSOR_DEVICE_ATTR(in##id##_input, S_IRUGO, show_voltage, \
95 NULL, name)
96
97#define WM831X_NAMED_VOLTAGE(id, name) \
98 WM831X_VOLTAGE(id, name); \
99 static SENSOR_DEVICE_ATTR(in##id##_label, S_IRUGO, show_label, \
100 NULL, name)
101
102static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
103
104WM831X_VOLTAGE(0, WM831X_AUX_AUX1);
105WM831X_VOLTAGE(1, WM831X_AUX_AUX2);
106WM831X_VOLTAGE(2, WM831X_AUX_AUX3);
107WM831X_VOLTAGE(3, WM831X_AUX_AUX4);
108
109WM831X_NAMED_VOLTAGE(4, WM831X_AUX_SYSVDD);
110WM831X_NAMED_VOLTAGE(5, WM831X_AUX_USB);
111WM831X_NAMED_VOLTAGE(6, WM831X_AUX_BATT);
112WM831X_NAMED_VOLTAGE(7, WM831X_AUX_WALL);
113WM831X_NAMED_VOLTAGE(8, WM831X_AUX_BKUP_BATT);
114
115static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_chip_temp, NULL,
116 WM831X_AUX_CHIP_TEMP);
117static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_label, NULL,
118 WM831X_AUX_CHIP_TEMP);
119/* Report as a voltage since conversion depends on external components
120 * and that's what the ABI wants. */
121static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_voltage, NULL,
122 WM831X_AUX_BATT_TEMP);
123static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, show_label, NULL,
124 WM831X_AUX_BATT_TEMP);
125
126static struct attribute *wm831x_attributes[] = {
127 &dev_attr_name.attr,
128
129 &sensor_dev_attr_in0_input.dev_attr.attr,
130 &sensor_dev_attr_in1_input.dev_attr.attr,
131 &sensor_dev_attr_in2_input.dev_attr.attr,
132 &sensor_dev_attr_in3_input.dev_attr.attr,
133
134 &sensor_dev_attr_in4_input.dev_attr.attr,
135 &sensor_dev_attr_in4_label.dev_attr.attr,
136 &sensor_dev_attr_in5_input.dev_attr.attr,
137 &sensor_dev_attr_in5_label.dev_attr.attr,
138 &sensor_dev_attr_in6_input.dev_attr.attr,
139 &sensor_dev_attr_in6_label.dev_attr.attr,
140 &sensor_dev_attr_in7_input.dev_attr.attr,
141 &sensor_dev_attr_in7_label.dev_attr.attr,
142 &sensor_dev_attr_in8_input.dev_attr.attr,
143 &sensor_dev_attr_in8_label.dev_attr.attr,
144
145 &sensor_dev_attr_temp1_input.dev_attr.attr,
146 &sensor_dev_attr_temp1_label.dev_attr.attr,
147 &sensor_dev_attr_temp2_input.dev_attr.attr,
148 &sensor_dev_attr_temp2_label.dev_attr.attr,
149
150 NULL
151};
152
153static const struct attribute_group wm831x_attr_group = {
154 .attrs = wm831x_attributes,
155};
156
157static int __devinit wm831x_hwmon_probe(struct platform_device *pdev)
158{
159 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
160 struct wm831x_hwmon *hwmon;
161 int ret;
162
163 hwmon = kzalloc(sizeof(struct wm831x_hwmon), GFP_KERNEL);
164 if (!hwmon)
165 return -ENOMEM;
166
167 hwmon->wm831x = wm831x;
168
169 ret = sysfs_create_group(&pdev->dev.kobj, &wm831x_attr_group);
170 if (ret)
171 goto err;
172
173 hwmon->classdev = hwmon_device_register(&pdev->dev);
174 if (IS_ERR(hwmon->classdev)) {
175 ret = PTR_ERR(hwmon->classdev);
176 goto err_sysfs;
177 }
178
179 platform_set_drvdata(pdev, hwmon);
180
181 return 0;
182
183err_sysfs:
184 sysfs_remove_group(&pdev->dev.kobj, &wm831x_attr_group);
185err:
186 kfree(hwmon);
187 return ret;
188}
189
190static int __devexit wm831x_hwmon_remove(struct platform_device *pdev)
191{
192 struct wm831x_hwmon *hwmon = platform_get_drvdata(pdev);
193
194 hwmon_device_unregister(hwmon->classdev);
195 sysfs_remove_group(&pdev->dev.kobj, &wm831x_attr_group);
196 platform_set_drvdata(pdev, NULL);
197 kfree(hwmon);
198
199 return 0;
200}
201
202static struct platform_driver wm831x_hwmon_driver = {
203 .probe = wm831x_hwmon_probe,
204 .remove = __devexit_p(wm831x_hwmon_remove),
205 .driver = {
206 .name = "wm831x-hwmon",
207 .owner = THIS_MODULE,
208 },
209};
210
211static int __init wm831x_hwmon_init(void)
212{
213 return platform_driver_register(&wm831x_hwmon_driver);
214}
215module_init(wm831x_hwmon_init);
216
217static void __exit wm831x_hwmon_exit(void)
218{
219 platform_driver_unregister(&wm831x_hwmon_driver);
220}
221module_exit(wm831x_hwmon_exit);
222
223MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
224MODULE_DESCRIPTION("WM831x Hardware Monitoring");
225MODULE_LICENSE("GPL");
226MODULE_ALIAS("platform:wm831x-hwmon");
diff --git a/drivers/hwmon/wm8350-hwmon.c b/drivers/hwmon/wm8350-hwmon.c
new file mode 100644
index 000000000000..13290595ca86
--- /dev/null
+++ b/drivers/hwmon/wm8350-hwmon.c
@@ -0,0 +1,151 @@
1/*
2 * drivers/hwmon/wm8350-hwmon.c - Wolfson Microelectronics WM8350 PMIC
3 * hardware monitoring features.
4 *
5 * Copyright (C) 2009 Wolfson Microelectronics plc
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License v2 as published by the
9 * Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/err.h>
24#include <linux/platform_device.h>
25#include <linux/hwmon.h>
26#include <linux/hwmon-sysfs.h>
27
28#include <linux/mfd/wm8350/core.h>
29#include <linux/mfd/wm8350/comparator.h>
30
31static ssize_t show_name(struct device *dev,
32 struct device_attribute *attr, char *buf)
33{
34 return sprintf(buf, "wm8350\n");
35}
36
37static const char *input_names[] = {
38 [WM8350_AUXADC_USB] = "USB",
39 [WM8350_AUXADC_LINE] = "Line",
40 [WM8350_AUXADC_BATT] = "Battery",
41};
42
43
44static ssize_t show_voltage(struct device *dev,
45 struct device_attribute *attr, char *buf)
46{
47 struct wm8350 *wm8350 = dev_get_drvdata(dev);
48 int channel = to_sensor_dev_attr(attr)->index;
49 int val;
50
51 val = wm8350_read_auxadc(wm8350, channel, 0, 0) * WM8350_AUX_COEFF;
52 val = DIV_ROUND_CLOSEST(val, 1000);
53
54 return sprintf(buf, "%d\n", val);
55}
56
57static ssize_t show_label(struct device *dev,
58 struct device_attribute *attr, char *buf)
59{
60 int channel = to_sensor_dev_attr(attr)->index;
61
62 return sprintf(buf, "%s\n", input_names[channel]);
63}
64
65#define WM8350_NAMED_VOLTAGE(id, name) \
66 static SENSOR_DEVICE_ATTR(in##id##_input, S_IRUGO, show_voltage,\
67 NULL, name); \
68 static SENSOR_DEVICE_ATTR(in##id##_label, S_IRUGO, show_label, \
69 NULL, name)
70
71static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
72
73WM8350_NAMED_VOLTAGE(0, WM8350_AUXADC_USB);
74WM8350_NAMED_VOLTAGE(1, WM8350_AUXADC_BATT);
75WM8350_NAMED_VOLTAGE(2, WM8350_AUXADC_LINE);
76
77static struct attribute *wm8350_attributes[] = {
78 &dev_attr_name.attr,
79
80 &sensor_dev_attr_in0_input.dev_attr.attr,
81 &sensor_dev_attr_in0_label.dev_attr.attr,
82 &sensor_dev_attr_in1_input.dev_attr.attr,
83 &sensor_dev_attr_in1_label.dev_attr.attr,
84 &sensor_dev_attr_in2_input.dev_attr.attr,
85 &sensor_dev_attr_in2_label.dev_attr.attr,
86
87 NULL,
88};
89
90static const struct attribute_group wm8350_attr_group = {
91 .attrs = wm8350_attributes,
92};
93
94static int __devinit wm8350_hwmon_probe(struct platform_device *pdev)
95{
96 struct wm8350 *wm8350 = platform_get_drvdata(pdev);
97 int ret;
98
99 ret = sysfs_create_group(&pdev->dev.kobj, &wm8350_attr_group);
100 if (ret)
101 goto err;
102
103 wm8350->hwmon.classdev = hwmon_device_register(&pdev->dev);
104 if (IS_ERR(wm8350->hwmon.classdev)) {
105 ret = PTR_ERR(wm8350->hwmon.classdev);
106 goto err_group;
107 }
108
109 return 0;
110
111err_group:
112 sysfs_remove_group(&pdev->dev.kobj, &wm8350_attr_group);
113err:
114 return ret;
115}
116
117static int __devexit wm8350_hwmon_remove(struct platform_device *pdev)
118{
119 struct wm8350 *wm8350 = platform_get_drvdata(pdev);
120
121 hwmon_device_unregister(wm8350->hwmon.classdev);
122 sysfs_remove_group(&pdev->dev.kobj, &wm8350_attr_group);
123
124 return 0;
125}
126
127static struct platform_driver wm8350_hwmon_driver = {
128 .probe = wm8350_hwmon_probe,
129 .remove = __devexit_p(wm8350_hwmon_remove),
130 .driver = {
131 .name = "wm8350-hwmon",
132 .owner = THIS_MODULE,
133 },
134};
135
136static int __init wm8350_hwmon_init(void)
137{
138 return platform_driver_register(&wm8350_hwmon_driver);
139}
140module_init(wm8350_hwmon_init);
141
142static void __exit wm8350_hwmon_exit(void)
143{
144 platform_driver_unregister(&wm8350_hwmon_driver);
145}
146module_exit(wm8350_hwmon_exit);
147
148MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
149MODULE_DESCRIPTION("WM8350 Hardware Monitoring");
150MODULE_LICENSE("GPL");
151MODULE_ALIAS("platform:wm8350-hwmon");
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index cbe21bc96b52..1a50be379cbc 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -279,4 +279,24 @@ config INPUT_BFIN_ROTARY
279 To compile this driver as a module, choose M here: the 279 To compile this driver as a module, choose M here: the
280 module will be called bfin-rotary. 280 module will be called bfin-rotary.
281 281
282config INPUT_WM831X_ON
283 tristate "WM831X ON pin"
284 depends on MFD_WM831X
285 help
286 Support the ON pin of WM831X PMICs as an input device
287 reporting power button status.
288
289 To compile this driver as a module, choose M here: the module
290 will be called wm831x_on.
291
292config INPUT_PCAP
293 tristate "Motorola EZX PCAP misc input events"
294 depends on EZX_PCAP
295 help
296 Say Y here if you want to use Power key and Headphone button
297 on Motorola EZX phones.
298
299 To compile this driver as a module, choose M here: the
300 module will be called pcap_keys.
301
282endif 302endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 79c1e9a5ea31..bf4db626c313 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o
16obj-$(CONFIG_INPUT_IXP4XX_BEEPER) += ixp4xx-beeper.o 16obj-$(CONFIG_INPUT_IXP4XX_BEEPER) += ixp4xx-beeper.o
17obj-$(CONFIG_INPUT_KEYSPAN_REMOTE) += keyspan_remote.o 17obj-$(CONFIG_INPUT_KEYSPAN_REMOTE) += keyspan_remote.o
18obj-$(CONFIG_INPUT_M68K_BEEP) += m68kspkr.o 18obj-$(CONFIG_INPUT_M68K_BEEP) += m68kspkr.o
19obj-$(CONFIG_INPUT_PCAP) += pcap_keys.o
19obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o 20obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o
20obj-$(CONFIG_INPUT_PCSPKR) += pcspkr.o 21obj-$(CONFIG_INPUT_PCSPKR) += pcspkr.o
21obj-$(CONFIG_INPUT_POWERMATE) += powermate.o 22obj-$(CONFIG_INPUT_POWERMATE) += powermate.o
@@ -26,4 +27,6 @@ obj-$(CONFIG_INPUT_SPARCSPKR) += sparcspkr.o
26obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON) += twl4030-pwrbutton.o 27obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON) += twl4030-pwrbutton.o
27obj-$(CONFIG_INPUT_UINPUT) += uinput.o 28obj-$(CONFIG_INPUT_UINPUT) += uinput.o
28obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o 29obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o
30obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o
29obj-$(CONFIG_INPUT_YEALINK) += yealink.o 31obj-$(CONFIG_INPUT_YEALINK) += yealink.o
32
diff --git a/drivers/input/misc/pcap_keys.c b/drivers/input/misc/pcap_keys.c
new file mode 100644
index 000000000000..7ea969347ca9
--- /dev/null
+++ b/drivers/input/misc/pcap_keys.c
@@ -0,0 +1,144 @@
1/*
2 * Input driver for PCAP events:
3 * * Power key
4 * * Headphone button
5 *
6 * Copyright (c) 2008,2009 Ilya Petrov <ilya.muromec@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/input.h>
19#include <linux/mfd/ezx-pcap.h>
20
21struct pcap_keys {
22 struct pcap_chip *pcap;
23 struct input_dev *input;
24};
25
26/* PCAP2 interrupts us on keypress */
27static irqreturn_t pcap_keys_handler(int irq, void *_pcap_keys)
28{
29 struct pcap_keys *pcap_keys = _pcap_keys;
30 int pirq = irq_to_pcap(pcap_keys->pcap, irq);
31 u32 pstat;
32
33 ezx_pcap_read(pcap_keys->pcap, PCAP_REG_PSTAT, &pstat);
34 pstat &= 1 << pirq;
35
36 switch (pirq) {
37 case PCAP_IRQ_ONOFF:
38 input_report_key(pcap_keys->input, KEY_POWER, !pstat);
39 break;
40 case PCAP_IRQ_MIC:
41 input_report_key(pcap_keys->input, KEY_HP, !pstat);
42 break;
43 }
44
45 input_sync(pcap_keys->input);
46
47 return IRQ_HANDLED;
48}
49
50static int __devinit pcap_keys_probe(struct platform_device *pdev)
51{
52 int err = -ENOMEM;
53 struct pcap_keys *pcap_keys;
54 struct input_dev *input_dev;
55
56 pcap_keys = kmalloc(sizeof(struct pcap_keys), GFP_KERNEL);
57 if (!pcap_keys)
58 return err;
59
60 pcap_keys->pcap = dev_get_drvdata(pdev->dev.parent);
61
62 input_dev = input_allocate_device();
63 if (!input_dev)
64 goto fail;
65
66 pcap_keys->input = input_dev;
67
68 platform_set_drvdata(pdev, pcap_keys);
69 input_dev->name = pdev->name;
70 input_dev->phys = "pcap-keys/input0";
71 input_dev->id.bustype = BUS_HOST;
72 input_dev->dev.parent = &pdev->dev;
73
74 __set_bit(EV_KEY, input_dev->evbit);
75 __set_bit(KEY_POWER, input_dev->keybit);
76 __set_bit(KEY_HP, input_dev->keybit);
77
78 err = input_register_device(input_dev);
79 if (err)
80 goto fail_allocate;
81
82 err = request_irq(pcap_to_irq(pcap_keys->pcap, PCAP_IRQ_ONOFF),
83 pcap_keys_handler, 0, "Power key", pcap_keys);
84 if (err)
85 goto fail_register;
86
87 err = request_irq(pcap_to_irq(pcap_keys->pcap, PCAP_IRQ_MIC),
88 pcap_keys_handler, 0, "Headphone button", pcap_keys);
89 if (err)
90 goto fail_pwrkey;
91
92 return 0;
93
94fail_pwrkey:
95 free_irq(pcap_to_irq(pcap_keys->pcap, PCAP_IRQ_ONOFF), pcap_keys);
96fail_register:
97 input_unregister_device(input_dev);
98 goto fail;
99fail_allocate:
100 input_free_device(input_dev);
101fail:
102 kfree(pcap_keys);
103 return err;
104}
105
106static int __devexit pcap_keys_remove(struct platform_device *pdev)
107{
108 struct pcap_keys *pcap_keys = platform_get_drvdata(pdev);
109
110 free_irq(pcap_to_irq(pcap_keys->pcap, PCAP_IRQ_ONOFF), pcap_keys);
111 free_irq(pcap_to_irq(pcap_keys->pcap, PCAP_IRQ_MIC), pcap_keys);
112
113 input_unregister_device(pcap_keys->input);
114 kfree(pcap_keys);
115
116 return 0;
117}
118
119static struct platform_driver pcap_keys_device_driver = {
120 .probe = pcap_keys_probe,
121 .remove = __devexit_p(pcap_keys_remove),
122 .driver = {
123 .name = "pcap-keys",
124 .owner = THIS_MODULE,
125 }
126};
127
128static int __init pcap_keys_init(void)
129{
130 return platform_driver_register(&pcap_keys_device_driver);
131};
132
133static void __exit pcap_keys_exit(void)
134{
135 platform_driver_unregister(&pcap_keys_device_driver);
136};
137
138module_init(pcap_keys_init);
139module_exit(pcap_keys_exit);
140
141MODULE_DESCRIPTION("Motorola PCAP2 input events driver");
142MODULE_AUTHOR("Ilya Petrov <ilya.muromec@gmail.com>");
143MODULE_LICENSE("GPL");
144MODULE_ALIAS("platform:pcap_keys");
diff --git a/drivers/input/misc/wm831x-on.c b/drivers/input/misc/wm831x-on.c
new file mode 100644
index 000000000000..ba4f5dd7c60e
--- /dev/null
+++ b/drivers/input/misc/wm831x-on.c
@@ -0,0 +1,163 @@
1/**
2 * wm831x-on.c - WM831X ON pin driver
3 *
4 * Copyright (C) 2009 Wolfson Microelectronics plc
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/input.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/mfd/wm831x/core.h>
29
30struct wm831x_on {
31 struct input_dev *dev;
32 struct delayed_work work;
33 struct wm831x *wm831x;
34};
35
36/*
37 * The chip gives us an interrupt when the ON pin is asserted but we
38 * then need to poll to see when the pin is deasserted.
39 */
40static void wm831x_poll_on(struct work_struct *work)
41{
42 struct wm831x_on *wm831x_on = container_of(work, struct wm831x_on,
43 work.work);
44 struct wm831x *wm831x = wm831x_on->wm831x;
45 int poll, ret;
46
47 ret = wm831x_reg_read(wm831x, WM831X_ON_PIN_CONTROL);
48 if (ret >= 0) {
49 poll = !(ret & WM831X_ON_PIN_STS);
50
51 input_report_key(wm831x_on->dev, KEY_POWER, poll);
52 input_sync(wm831x_on->dev);
53 } else {
54 dev_err(wm831x->dev, "Failed to read ON status: %d\n", ret);
55 poll = 1;
56 }
57
58 if (poll)
59 schedule_delayed_work(&wm831x_on->work, 100);
60}
61
62static irqreturn_t wm831x_on_irq(int irq, void *data)
63{
64 struct wm831x_on *wm831x_on = data;
65
66 schedule_delayed_work(&wm831x_on->work, 0);
67
68 return IRQ_HANDLED;
69}
70
71static int __devinit wm831x_on_probe(struct platform_device *pdev)
72{
73 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
74 struct wm831x_on *wm831x_on;
75 int irq = platform_get_irq(pdev, 0);
76 int ret;
77
78 wm831x_on = kzalloc(sizeof(struct wm831x_on), GFP_KERNEL);
79 if (!wm831x_on) {
80 dev_err(&pdev->dev, "Can't allocate data\n");
81 return -ENOMEM;
82 }
83
84 wm831x_on->wm831x = wm831x;
85 INIT_DELAYED_WORK(&wm831x_on->work, wm831x_poll_on);
86
87 wm831x_on->dev = input_allocate_device();
88 if (!wm831x_on->dev) {
89 dev_err(&pdev->dev, "Can't allocate input dev\n");
90 ret = -ENOMEM;
91 goto err;
92 }
93
94 wm831x_on->dev->evbit[0] = BIT_MASK(EV_KEY);
95 wm831x_on->dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
96 wm831x_on->dev->name = "wm831x_on";
97 wm831x_on->dev->phys = "wm831x_on/input0";
98 wm831x_on->dev->dev.parent = &pdev->dev;
99
100 ret = wm831x_request_irq(wm831x, irq, wm831x_on_irq,
101 IRQF_TRIGGER_RISING, "wm831x_on", wm831x_on);
102 if (ret < 0) {
103 dev_err(&pdev->dev, "Unable to request IRQ: %d\n", ret);
104 goto err_input_dev;
105 }
106 ret = input_register_device(wm831x_on->dev);
107 if (ret) {
108 dev_dbg(&pdev->dev, "Can't register input device: %d\n", ret);
109 goto err_irq;
110 }
111
112 platform_set_drvdata(pdev, wm831x_on);
113
114 return 0;
115
116err_irq:
117 wm831x_free_irq(wm831x, irq, NULL);
118err_input_dev:
119 input_free_device(wm831x_on->dev);
120err:
121 kfree(wm831x_on);
122 return ret;
123}
124
125static int __devexit wm831x_on_remove(struct platform_device *pdev)
126{
127 struct wm831x_on *wm831x_on = platform_get_drvdata(pdev);
128 int irq = platform_get_irq(pdev, 0);
129
130 wm831x_free_irq(wm831x_on->wm831x, irq, wm831x_on);
131 cancel_delayed_work_sync(&wm831x_on->work);
132 input_unregister_device(wm831x_on->dev);
133 kfree(wm831x_on);
134
135 return 0;
136}
137
138static struct platform_driver wm831x_on_driver = {
139 .probe = wm831x_on_probe,
140 .remove = __devexit_p(wm831x_on_remove),
141 .driver = {
142 .name = "wm831x-on",
143 .owner = THIS_MODULE,
144 },
145};
146
147static int __init wm831x_on_init(void)
148{
149 return platform_driver_register(&wm831x_on_driver);
150}
151module_init(wm831x_on_init);
152
153static void __exit wm831x_on_exit(void)
154{
155 platform_driver_unregister(&wm831x_on_driver);
156}
157module_exit(wm831x_on_exit);
158
159MODULE_ALIAS("platform:wm831x-on");
160MODULE_DESCRIPTION("WM831x ON pin");
161MODULE_LICENSE("GPL");
162MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
163
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 87a1ae63bcc4..ab02d72afbf3 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -510,4 +510,13 @@ config TOUCHSCREEN_W90X900
510 To compile this driver as a module, choose M here: the 510 To compile this driver as a module, choose M here: the
511 module will be called w90p910_ts. 511 module will be called w90p910_ts.
512 512
513config TOUCHSCREEN_PCAP
514 tristate "Motorola PCAP touchscreen"
515 depends on EZX_PCAP
516 help
517 Say Y here if you have a Motorola EZX telephone and
518 want to enable support for the built-in touchscreen.
519
520 To compile this driver as a module, choose M here: the
521 module will be called pcap_ts.
513endif 522endif
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 3e1c5e0b952f..4599bf7ad819 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -40,3 +40,4 @@ obj-$(CONFIG_TOUCHSCREEN_WM97XX_ATMEL) += atmel-wm97xx.o
40obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o 40obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o
41obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE) += zylonite-wm97xx.o 41obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE) += zylonite-wm97xx.o
42obj-$(CONFIG_TOUCHSCREEN_W90X900) += w90p910_ts.o 42obj-$(CONFIG_TOUCHSCREEN_W90X900) += w90p910_ts.o
43obj-$(CONFIG_TOUCHSCREEN_PCAP) += pcap_ts.o
diff --git a/drivers/input/touchscreen/pcap_ts.c b/drivers/input/touchscreen/pcap_ts.c
new file mode 100644
index 000000000000..67fcd33595de
--- /dev/null
+++ b/drivers/input/touchscreen/pcap_ts.c
@@ -0,0 +1,271 @@
1/*
2 * Driver for Motorola PCAP2 touchscreen as found in the EZX phone platform.
3 *
4 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
5 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/fs.h>
16#include <linux/string.h>
17#include <linux/pm.h>
18#include <linux/timer.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/input.h>
22#include <linux/mfd/ezx-pcap.h>
23
24struct pcap_ts {
25 struct pcap_chip *pcap;
26 struct input_dev *input;
27 struct delayed_work work;
28 u16 x, y;
29 u16 pressure;
30 u8 read_state;
31};
32
33#define SAMPLE_DELAY 20 /* msecs */
34
35#define X_AXIS_MIN 0
36#define X_AXIS_MAX 1023
37#define Y_AXIS_MAX X_AXIS_MAX
38#define Y_AXIS_MIN X_AXIS_MIN
39#define PRESSURE_MAX X_AXIS_MAX
40#define PRESSURE_MIN X_AXIS_MIN
41
42static void pcap_ts_read_xy(void *data, u16 res[2])
43{
44 struct pcap_ts *pcap_ts = data;
45
46 switch (pcap_ts->read_state) {
47 case PCAP_ADC_TS_M_PRESSURE:
48 /* pressure reading is unreliable */
49 if (res[0] > PRESSURE_MIN && res[0] < PRESSURE_MAX)
50 pcap_ts->pressure = res[0];
51 pcap_ts->read_state = PCAP_ADC_TS_M_XY;
52 schedule_delayed_work(&pcap_ts->work, 0);
53 break;
54 case PCAP_ADC_TS_M_XY:
55 pcap_ts->y = res[0];
56 pcap_ts->x = res[1];
57 if (pcap_ts->x <= X_AXIS_MIN || pcap_ts->x >= X_AXIS_MAX ||
58 pcap_ts->y <= Y_AXIS_MIN || pcap_ts->y >= Y_AXIS_MAX) {
59 /* pen has been released */
60 input_report_abs(pcap_ts->input, ABS_PRESSURE, 0);
61 input_report_key(pcap_ts->input, BTN_TOUCH, 0);
62
63 pcap_ts->read_state = PCAP_ADC_TS_M_STANDBY;
64 schedule_delayed_work(&pcap_ts->work, 0);
65 } else {
66 /* pen is touching the screen */
67 input_report_abs(pcap_ts->input, ABS_X, pcap_ts->x);
68 input_report_abs(pcap_ts->input, ABS_Y, pcap_ts->y);
69 input_report_key(pcap_ts->input, BTN_TOUCH, 1);
70 input_report_abs(pcap_ts->input, ABS_PRESSURE,
71 pcap_ts->pressure);
72
73 /* switch back to pressure read mode */
74 pcap_ts->read_state = PCAP_ADC_TS_M_PRESSURE;
75 schedule_delayed_work(&pcap_ts->work,
76 msecs_to_jiffies(SAMPLE_DELAY));
77 }
78 input_sync(pcap_ts->input);
79 break;
80 default:
81 dev_warn(&pcap_ts->input->dev,
82 "pcap_ts: Warning, unhandled read_state %d\n",
83 pcap_ts->read_state);
84 break;
85 }
86}
87
88static void pcap_ts_work(struct work_struct *work)
89{
90 struct delayed_work *dw = container_of(work, struct delayed_work, work);
91 struct pcap_ts *pcap_ts = container_of(dw, struct pcap_ts, work);
92 u8 ch[2];
93
94 pcap_set_ts_bits(pcap_ts->pcap,
95 pcap_ts->read_state << PCAP_ADC_TS_M_SHIFT);
96
97 if (pcap_ts->read_state == PCAP_ADC_TS_M_STANDBY)
98 return;
99
100 /* start adc conversion */
101 ch[0] = PCAP_ADC_CH_TS_X1;
102 ch[1] = PCAP_ADC_CH_TS_Y1;
103 pcap_adc_async(pcap_ts->pcap, PCAP_ADC_BANK_1, 0, ch,
104 pcap_ts_read_xy, pcap_ts);
105}
106
107static irqreturn_t pcap_ts_event_touch(int pirq, void *data)
108{
109 struct pcap_ts *pcap_ts = data;
110
111 if (pcap_ts->read_state == PCAP_ADC_TS_M_STANDBY) {
112 pcap_ts->read_state = PCAP_ADC_TS_M_PRESSURE;
113 schedule_delayed_work(&pcap_ts->work, 0);
114 }
115 return IRQ_HANDLED;
116}
117
118static int pcap_ts_open(struct input_dev *dev)
119{
120 struct pcap_ts *pcap_ts = input_get_drvdata(dev);
121
122 pcap_ts->read_state = PCAP_ADC_TS_M_STANDBY;
123 schedule_delayed_work(&pcap_ts->work, 0);
124
125 return 0;
126}
127
128static void pcap_ts_close(struct input_dev *dev)
129{
130 struct pcap_ts *pcap_ts = input_get_drvdata(dev);
131
132 cancel_delayed_work_sync(&pcap_ts->work);
133
134 pcap_ts->read_state = PCAP_ADC_TS_M_NONTS;
135 pcap_set_ts_bits(pcap_ts->pcap,
136 pcap_ts->read_state << PCAP_ADC_TS_M_SHIFT);
137}
138
139static int __devinit pcap_ts_probe(struct platform_device *pdev)
140{
141 struct input_dev *input_dev;
142 struct pcap_ts *pcap_ts;
143 int err = -ENOMEM;
144
145 pcap_ts = kzalloc(sizeof(*pcap_ts), GFP_KERNEL);
146 if (!pcap_ts)
147 return err;
148
149 pcap_ts->pcap = dev_get_drvdata(pdev->dev.parent);
150 platform_set_drvdata(pdev, pcap_ts);
151
152 input_dev = input_allocate_device();
153 if (!input_dev)
154 goto fail;
155
156 INIT_DELAYED_WORK(&pcap_ts->work, pcap_ts_work);
157
158 pcap_ts->read_state = PCAP_ADC_TS_M_NONTS;
159 pcap_set_ts_bits(pcap_ts->pcap,
160 pcap_ts->read_state << PCAP_ADC_TS_M_SHIFT);
161
162 pcap_ts->input = input_dev;
163 input_set_drvdata(input_dev, pcap_ts);
164
165 input_dev->name = "pcap-touchscreen";
166 input_dev->phys = "pcap_ts/input0";
167 input_dev->id.bustype = BUS_HOST;
168 input_dev->id.vendor = 0x0001;
169 input_dev->id.product = 0x0002;
170 input_dev->id.version = 0x0100;
171 input_dev->dev.parent = &pdev->dev;
172 input_dev->open = pcap_ts_open;
173 input_dev->close = pcap_ts_close;
174
175 input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
176 input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
177 input_set_abs_params(input_dev, ABS_X, X_AXIS_MIN, X_AXIS_MAX, 0, 0);
178 input_set_abs_params(input_dev, ABS_Y, Y_AXIS_MIN, Y_AXIS_MAX, 0, 0);
179 input_set_abs_params(input_dev, ABS_PRESSURE, PRESSURE_MIN,
180 PRESSURE_MAX, 0, 0);
181
182 err = input_register_device(pcap_ts->input);
183 if (err)
184 goto fail_allocate;
185
186 err = request_irq(pcap_to_irq(pcap_ts->pcap, PCAP_IRQ_TS),
187 pcap_ts_event_touch, 0, "Touch Screen", pcap_ts);
188 if (err)
189 goto fail_register;
190
191 return 0;
192
193fail_register:
194 input_unregister_device(input_dev);
195 goto fail;
196fail_allocate:
197 input_free_device(input_dev);
198fail:
199 kfree(pcap_ts);
200
201 return err;
202}
203
204static int __devexit pcap_ts_remove(struct platform_device *pdev)
205{
206 struct pcap_ts *pcap_ts = platform_get_drvdata(pdev);
207
208 free_irq(pcap_to_irq(pcap_ts->pcap, PCAP_IRQ_TS), pcap_ts);
209 cancel_delayed_work_sync(&pcap_ts->work);
210
211 input_unregister_device(pcap_ts->input);
212
213 kfree(pcap_ts);
214
215 return 0;
216}
217
218#ifdef CONFIG_PM
219static int pcap_ts_suspend(struct device *dev)
220{
221 struct pcap_ts *pcap_ts = dev_get_drvdata(dev);
222
223 pcap_set_ts_bits(pcap_ts->pcap, PCAP_ADC_TS_REF_LOWPWR);
224 return 0;
225}
226
227static int pcap_ts_resume(struct device *dev)
228{
229 struct pcap_ts *pcap_ts = dev_get_drvdata(dev);
230
231 pcap_set_ts_bits(pcap_ts->pcap,
232 pcap_ts->read_state << PCAP_ADC_TS_M_SHIFT);
233 return 0;
234}
235
236static struct dev_pm_ops pcap_ts_pm_ops = {
237 .suspend = pcap_ts_suspend,
238 .resume = pcap_ts_resume,
239};
240#define PCAP_TS_PM_OPS (&pcap_ts_pm_ops)
241#else
242#define PCAP_TS_PM_OPS NULL
243#endif
244
245static struct platform_driver pcap_ts_driver = {
246 .probe = pcap_ts_probe,
247 .remove = __devexit_p(pcap_ts_remove),
248 .driver = {
249 .name = "pcap-ts",
250 .owner = THIS_MODULE,
251 .pm = PCAP_TS_PM_OPS,
252 },
253};
254
255static int __init pcap_ts_init(void)
256{
257 return platform_driver_register(&pcap_ts_driver);
258}
259
260static void __exit pcap_ts_exit(void)
261{
262 platform_driver_unregister(&pcap_ts_driver);
263}
264
265module_init(pcap_ts_init);
266module_exit(pcap_ts_exit);
267
268MODULE_DESCRIPTION("Motorola PCAP2 touchscreen driver");
269MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
270MODULE_LICENSE("GPL");
271MODULE_ALIAS("platform:pcap_ts");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 491ac0f800d2..570be139f9df 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -108,6 +108,19 @@ config TWL4030_CORE
108 high speed USB OTG transceiver, an audio codec (on most 108 high speed USB OTG transceiver, an audio codec (on most
109 versions) and many other features. 109 versions) and many other features.
110 110
111config TWL4030_POWER
112 bool "Support power resources on TWL4030 family chips"
113 depends on TWL4030_CORE && ARM
114 help
115 Say yes here if you want to use the power resources on the
116 TWL4030 family chips. Most of these resources are regulators,
117 which have a separate driver; some are control signals, such
118 as clock request handshaking.
119
120 This driver uses board-specific data to initialize the resources
121 and load scripts controling which resources are switched off/on
122 or reset when a sleep, wakeup or warm reset event occurs.
123
111config MFD_TMIO 124config MFD_TMIO
112 bool 125 bool
113 default n 126 default n
@@ -157,6 +170,16 @@ config MFD_WM8400
157 the device, additional drivers must be enabled in order to use 170 the device, additional drivers must be enabled in order to use
158 the functionality of the device. 171 the functionality of the device.
159 172
173config MFD_WM831X
174 tristate "Support Wolfson Microelectronics WM831x PMICs"
175 select MFD_CORE
176 depends on I2C
177 help
178 Support for the Wolfson Microelecronics WM831x PMICs. This
179 driver provides common support for accessing the device,
180 additional drivers must be enabled in order to use the
181 functionality of the device.
182
160config MFD_WM8350 183config MFD_WM8350
161 tristate 184 tristate
162 185
@@ -228,6 +251,16 @@ config MFD_PCF50633
228 facilities, and registers devices for the various functions 251 facilities, and registers devices for the various functions
229 so that function-specific drivers can bind to them. 252 so that function-specific drivers can bind to them.
230 253
254config MFD_MC13783
255 tristate "Support Freescale MC13783"
256 depends on SPI_MASTER
257 select MFD_CORE
258 help
259 Support for the Freescale (Atlas) MC13783 PMIC and audio CODEC.
260 This driver provides common support for accessing the device,
261 additional drivers must be enabled in order to use the
262 functionality of the device.
263
231config PCF50633_ADC 264config PCF50633_ADC
232 tristate "Support for NXP PCF50633 ADC" 265 tristate "Support for NXP PCF50633 ADC"
233 depends on MFD_PCF50633 266 depends on MFD_PCF50633
@@ -256,6 +289,15 @@ config AB3100_CORE
256 LEDs, vibrator, system power and temperature, power management 289 LEDs, vibrator, system power and temperature, power management
257 and ALSA sound. 290 and ALSA sound.
258 291
292config AB3100_OTP
293 tristate "ST-Ericsson AB3100 OTP functions"
294 depends on AB3100_CORE
295 default y if AB3100_CORE
296 help
297 Select this to enable the AB3100 Mixed Signal IC OTP (one-time
298 programmable memory) support. This exposes a sysfs file to read
299 out OTP values.
300
259config EZX_PCAP 301config EZX_PCAP
260 bool "PCAP Support" 302 bool "PCAP Support"
261 depends on GENERIC_HARDIRQS && SPI_MASTER 303 depends on GENERIC_HARDIRQS && SPI_MASTER
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6f8a9a1af20b..f3b277b90d40 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
15obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o 15obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
16 16
17obj-$(CONFIG_MFD_WM8400) += wm8400-core.o 17obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
18wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o
19obj-$(CONFIG_MFD_WM831X) += wm831x.o
18wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o 20wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o
19obj-$(CONFIG_MFD_WM8350) += wm8350.o 21obj-$(CONFIG_MFD_WM8350) += wm8350.o
20obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o 22obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
@@ -23,6 +25,9 @@ obj-$(CONFIG_TPS65010) += tps65010.o
23obj-$(CONFIG_MENELAUS) += menelaus.o 25obj-$(CONFIG_MENELAUS) += menelaus.o
24 26
25obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o 27obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
28obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o
29
30obj-$(CONFIG_MFD_MC13783) += mc13783-core.o
26 31
27obj-$(CONFIG_MFD_CORE) += mfd-core.o 32obj-$(CONFIG_MFD_CORE) += mfd-core.o
28 33
@@ -44,3 +49,4 @@ obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o
44obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o 49obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
45obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o 50obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
46obj-$(CONFIG_AB3100_CORE) += ab3100-core.o 51obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
52obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
index 13e7d7bfe85f..c533f86ff5ea 100644
--- a/drivers/mfd/ab3100-core.c
+++ b/drivers/mfd/ab3100-core.c
@@ -14,7 +14,6 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/workqueue.h>
18#include <linux/debugfs.h> 17#include <linux/debugfs.h>
19#include <linux/seq_file.h> 18#include <linux/seq_file.h>
20#include <linux/uaccess.h> 19#include <linux/uaccess.h>
@@ -77,7 +76,7 @@ u8 ab3100_get_chip_type(struct ab3100 *ab3100)
77} 76}
78EXPORT_SYMBOL(ab3100_get_chip_type); 77EXPORT_SYMBOL(ab3100_get_chip_type);
79 78
80int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval) 79int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval)
81{ 80{
82 u8 regandval[2] = {reg, regval}; 81 u8 regandval[2] = {reg, regval};
83 int err; 82 int err;
@@ -107,9 +106,10 @@ int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval)
107 err = 0; 106 err = 0;
108 } 107 }
109 mutex_unlock(&ab3100->access_mutex); 108 mutex_unlock(&ab3100->access_mutex);
110 return 0; 109 return err;
111} 110}
112EXPORT_SYMBOL(ab3100_set_register); 111EXPORT_SYMBOL(ab3100_set_register_interruptible);
112
113 113
114/* 114/*
115 * The test registers exist at an I2C bus address up one 115 * The test registers exist at an I2C bus address up one
@@ -118,7 +118,7 @@ EXPORT_SYMBOL(ab3100_set_register);
118 * anyway. It's currently only used from this file so declare 118 * anyway. It's currently only used from this file so declare
119 * it static and do not export. 119 * it static and do not export.
120 */ 120 */
121static int ab3100_set_test_register(struct ab3100 *ab3100, 121static int ab3100_set_test_register_interruptible(struct ab3100 *ab3100,
122 u8 reg, u8 regval) 122 u8 reg, u8 regval)
123{ 123{
124 u8 regandval[2] = {reg, regval}; 124 u8 regandval[2] = {reg, regval};
@@ -148,7 +148,8 @@ static int ab3100_set_test_register(struct ab3100 *ab3100,
148 return err; 148 return err;
149} 149}
150 150
151int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval) 151
152int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval)
152{ 153{
153 int err; 154 int err;
154 155
@@ -202,9 +203,10 @@ int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval)
202 mutex_unlock(&ab3100->access_mutex); 203 mutex_unlock(&ab3100->access_mutex);
203 return err; 204 return err;
204} 205}
205EXPORT_SYMBOL(ab3100_get_register); 206EXPORT_SYMBOL(ab3100_get_register_interruptible);
206 207
207int ab3100_get_register_page(struct ab3100 *ab3100, 208
209int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
208 u8 first_reg, u8 *regvals, u8 numregs) 210 u8 first_reg, u8 *regvals, u8 numregs)
209{ 211{
210 int err; 212 int err;
@@ -258,9 +260,10 @@ int ab3100_get_register_page(struct ab3100 *ab3100,
258 mutex_unlock(&ab3100->access_mutex); 260 mutex_unlock(&ab3100->access_mutex);
259 return err; 261 return err;
260} 262}
261EXPORT_SYMBOL(ab3100_get_register_page); 263EXPORT_SYMBOL(ab3100_get_register_page_interruptible);
264
262 265
263int ab3100_mask_and_set_register(struct ab3100 *ab3100, 266int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
264 u8 reg, u8 andmask, u8 ormask) 267 u8 reg, u8 andmask, u8 ormask)
265{ 268{
266 u8 regandval[2] = {reg, 0}; 269 u8 regandval[2] = {reg, 0};
@@ -328,7 +331,8 @@ int ab3100_mask_and_set_register(struct ab3100 *ab3100,
328 mutex_unlock(&ab3100->access_mutex); 331 mutex_unlock(&ab3100->access_mutex);
329 return err; 332 return err;
330} 333}
331EXPORT_SYMBOL(ab3100_mask_and_set_register); 334EXPORT_SYMBOL(ab3100_mask_and_set_register_interruptible);
335
332 336
333/* 337/*
334 * Register a simple callback for handling any AB3100 events. 338 * Register a simple callback for handling any AB3100 events.
@@ -371,7 +375,7 @@ static void ab3100_work(struct work_struct *work)
371 u32 fatevent; 375 u32 fatevent;
372 int err; 376 int err;
373 377
374 err = ab3100_get_register_page(ab3100, AB3100_EVENTA1, 378 err = ab3100_get_register_page_interruptible(ab3100, AB3100_EVENTA1,
375 event_regs, 3); 379 event_regs, 3);
376 if (err) 380 if (err)
377 goto err_event_wq; 381 goto err_event_wq;
@@ -417,7 +421,7 @@ static irqreturn_t ab3100_irq_handler(int irq, void *data)
417 * stuff and we will re-enable the interrupts once th 421 * stuff and we will re-enable the interrupts once th
418 * worker has finished. 422 * worker has finished.
419 */ 423 */
420 disable_irq(ab3100->i2c_client->irq); 424 disable_irq_nosync(irq);
421 schedule_work(&ab3100->work); 425 schedule_work(&ab3100->work);
422 return IRQ_HANDLED; 426 return IRQ_HANDLED;
423} 427}
@@ -435,7 +439,7 @@ static int ab3100_registers_print(struct seq_file *s, void *p)
435 seq_printf(s, "AB3100 registers:\n"); 439 seq_printf(s, "AB3100 registers:\n");
436 440
437 for (reg = 0; reg < 0xff; reg++) { 441 for (reg = 0; reg < 0xff; reg++) {
438 ab3100_get_register(ab3100, reg, &value); 442 ab3100_get_register_interruptible(ab3100, reg, &value);
439 seq_printf(s, "[0x%x]: 0x%x\n", reg, value); 443 seq_printf(s, "[0x%x]: 0x%x\n", reg, value);
440 } 444 }
441 return 0; 445 return 0;
@@ -465,14 +469,14 @@ static int ab3100_get_set_reg_open_file(struct inode *inode, struct file *file)
465 return 0; 469 return 0;
466} 470}
467 471
468static int ab3100_get_set_reg(struct file *file, 472static ssize_t ab3100_get_set_reg(struct file *file,
469 const char __user *user_buf, 473 const char __user *user_buf,
470 size_t count, loff_t *ppos) 474 size_t count, loff_t *ppos)
471{ 475{
472 struct ab3100_get_set_reg_priv *priv = file->private_data; 476 struct ab3100_get_set_reg_priv *priv = file->private_data;
473 struct ab3100 *ab3100 = priv->ab3100; 477 struct ab3100 *ab3100 = priv->ab3100;
474 char buf[32]; 478 char buf[32];
475 int buf_size; 479 ssize_t buf_size;
476 int regp; 480 int regp;
477 unsigned long user_reg; 481 unsigned long user_reg;
478 int err; 482 int err;
@@ -515,7 +519,7 @@ static int ab3100_get_set_reg(struct file *file,
515 u8 reg = (u8) user_reg; 519 u8 reg = (u8) user_reg;
516 u8 regvalue; 520 u8 regvalue;
517 521
518 ab3100_get_register(ab3100, reg, &regvalue); 522 ab3100_get_register_interruptible(ab3100, reg, &regvalue);
519 523
520 dev_info(ab3100->dev, 524 dev_info(ab3100->dev,
521 "debug read AB3100 reg[0x%02x]: 0x%02x\n", 525 "debug read AB3100 reg[0x%02x]: 0x%02x\n",
@@ -547,8 +551,8 @@ static int ab3100_get_set_reg(struct file *file,
547 return -EINVAL; 551 return -EINVAL;
548 552
549 value = (u8) user_value; 553 value = (u8) user_value;
550 ab3100_set_register(ab3100, reg, value); 554 ab3100_set_register_interruptible(ab3100, reg, value);
551 ab3100_get_register(ab3100, reg, &regvalue); 555 ab3100_get_register_interruptible(ab3100, reg, &regvalue);
552 556
553 dev_info(ab3100->dev, 557 dev_info(ab3100->dev,
554 "debug write reg[0x%02x] with 0x%02x, " 558 "debug write reg[0x%02x] with 0x%02x, "
@@ -662,7 +666,7 @@ ab3100_init_settings[] = {
662 .setting = 0x01 666 .setting = 0x01
663 }, { 667 }, {
664 .abreg = AB3100_IMRB1, 668 .abreg = AB3100_IMRB1,
665 .setting = 0xFF 669 .setting = 0xBF
666 }, { 670 }, {
667 .abreg = AB3100_IMRB2, 671 .abreg = AB3100_IMRB2,
668 .setting = 0xFF 672 .setting = 0xFF
@@ -696,7 +700,7 @@ static int __init ab3100_setup(struct ab3100 *ab3100)
696 int i; 700 int i;
697 701
698 for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) { 702 for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) {
699 err = ab3100_set_register(ab3100, 703 err = ab3100_set_register_interruptible(ab3100,
700 ab3100_init_settings[i].abreg, 704 ab3100_init_settings[i].abreg,
701 ab3100_init_settings[i].setting); 705 ab3100_init_settings[i].setting);
702 if (err) 706 if (err)
@@ -705,14 +709,14 @@ static int __init ab3100_setup(struct ab3100 *ab3100)
705 709
706 /* 710 /*
707 * Special trick to make the AB3100 use the 32kHz clock (RTC) 711 * Special trick to make the AB3100 use the 32kHz clock (RTC)
708 * bit 3 in test registe 0x02 is a special, undocumented test 712 * bit 3 in test register 0x02 is a special, undocumented test
709 * register bit that only exist in AB3100 P1E 713 * register bit that only exist in AB3100 P1E
710 */ 714 */
711 if (ab3100->chip_id == 0xc4) { 715 if (ab3100->chip_id == 0xc4) {
712 dev_warn(ab3100->dev, 716 dev_warn(ab3100->dev,
713 "AB3100 P1E variant detected, " 717 "AB3100 P1E variant detected, "
714 "forcing chip to 32KHz\n"); 718 "forcing chip to 32KHz\n");
715 err = ab3100_set_test_register(ab3100, 0x02, 0x08); 719 err = ab3100_set_test_register_interruptible(ab3100, 0x02, 0x08);
716 } 720 }
717 721
718 exit_no_setup: 722 exit_no_setup:
@@ -833,6 +837,8 @@ static int __init ab3100_probe(struct i2c_client *client,
833 const struct i2c_device_id *id) 837 const struct i2c_device_id *id)
834{ 838{
835 struct ab3100 *ab3100; 839 struct ab3100 *ab3100;
840 struct ab3100_platform_data *ab3100_plf_data =
841 client->dev.platform_data;
836 int err; 842 int err;
837 int i; 843 int i;
838 844
@@ -852,8 +858,8 @@ static int __init ab3100_probe(struct i2c_client *client,
852 i2c_set_clientdata(client, ab3100); 858 i2c_set_clientdata(client, ab3100);
853 859
854 /* Read chip ID register */ 860 /* Read chip ID register */
855 err = ab3100_get_register(ab3100, AB3100_CID, 861 err = ab3100_get_register_interruptible(ab3100, AB3100_CID,
856 &ab3100->chip_id); 862 &ab3100->chip_id);
857 if (err) { 863 if (err) {
858 dev_err(&client->dev, 864 dev_err(&client->dev,
859 "could not communicate with the AB3100 analog " 865 "could not communicate with the AB3100 analog "
@@ -916,6 +922,8 @@ static int __init ab3100_probe(struct i2c_client *client,
916 for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) { 922 for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) {
917 ab3100_platform_devs[i]->dev.parent = 923 ab3100_platform_devs[i]->dev.parent =
918 &client->dev; 924 &client->dev;
925 ab3100_platform_devs[i]->dev.platform_data =
926 ab3100_plf_data;
919 platform_set_drvdata(ab3100_platform_devs[i], ab3100); 927 platform_set_drvdata(ab3100_platform_devs[i], ab3100);
920 } 928 }
921 929
diff --git a/drivers/mfd/ab3100-otp.c b/drivers/mfd/ab3100-otp.c
new file mode 100644
index 000000000000..0499b2031a2c
--- /dev/null
+++ b/drivers/mfd/ab3100-otp.c
@@ -0,0 +1,268 @@
1/*
2 * drivers/mfd/ab3100_otp.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * Driver to read out OTP from the AB3100 Mixed-signal circuit
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/ab3100.h>
15#include <linux/debugfs.h>
16
17/* The OTP registers */
18#define AB3100_OTP0 0xb0
19#define AB3100_OTP1 0xb1
20#define AB3100_OTP2 0xb2
21#define AB3100_OTP3 0xb3
22#define AB3100_OTP4 0xb4
23#define AB3100_OTP5 0xb5
24#define AB3100_OTP6 0xb6
25#define AB3100_OTP7 0xb7
26#define AB3100_OTPP 0xbf
27
28/**
29 * struct ab3100_otp
30 * @dev containing device
31 * @ab3100 a pointer to the parent ab3100 device struct
32 * @locked whether the OTP is locked, after locking, no more bits
33 * can be changed but before locking it is still possible
34 * to change bits from 1->0.
35 * @freq clocking frequency for the OTP, this frequency is either
36 * 32768Hz or 1MHz/30
37 * @paf product activation flag, indicates whether this is a real
38 * product (paf true) or a lab board etc (paf false)
39 * @imeich if this is set it is possible to override the
40 * IMEI number found in the tac, fac and svn fields with
41 * (secured) software
42 * @cid customer ID
43 * @tac type allocation code of the IMEI
44 * @fac final assembly code of the IMEI
45 * @svn software version number of the IMEI
46 * @debugfs a debugfs file used when dumping to file
47 */
48struct ab3100_otp {
49 struct device *dev;
50 struct ab3100 *ab3100;
51 bool locked;
52 u32 freq;
53 bool paf;
54 bool imeich;
55 u16 cid:14;
56 u32 tac:20;
57 u8 fac;
58 u32 svn:20;
59 struct dentry *debugfs;
60};
61
62static int __init ab3100_otp_read(struct ab3100_otp *otp)
63{
64 struct ab3100 *ab = otp->ab3100;
65 u8 otpval[8];
66 u8 otpp;
67 int err;
68
69 err = ab3100_get_register_interruptible(ab, AB3100_OTPP, &otpp);
70 if (err) {
71 dev_err(otp->dev, "unable to read OTPP register\n");
72 return err;
73 }
74
75 err = ab3100_get_register_page_interruptible(ab, AB3100_OTP0,
76 otpval, 8);
77 if (err) {
78 dev_err(otp->dev, "unable to read OTP register page\n");
79 return err;
80 }
81
82 /* Cache OTP properties, they never change by nature */
83 otp->locked = (otpp & 0x80);
84 otp->freq = (otpp & 0x40) ? 32768 : 34100;
85 otp->paf = (otpval[1] & 0x80);
86 otp->imeich = (otpval[1] & 0x40);
87 otp->cid = ((otpval[1] << 8) | otpval[0]) & 0x3fff;
88 otp->tac = ((otpval[4] & 0x0f) << 16) | (otpval[3] << 8) | otpval[2];
89 otp->fac = ((otpval[5] & 0x0f) << 4) | (otpval[4] >> 4);
90 otp->svn = (otpval[7] << 12) | (otpval[6] << 4) | (otpval[5] >> 4);
91 return 0;
92}
93
94/*
95 * This is a simple debugfs human-readable file that dumps out
96 * the contents of the OTP.
97 */
98#ifdef CONFIG_DEBUGFS
99static int show_otp(struct seq_file *s, void *v)
100{
101 struct ab3100_otp *otp = s->private;
102 int err;
103
104 seq_printf(s, "OTP is %s\n", otp->locked ? "LOCKED" : "UNLOCKED");
105 seq_printf(s, "OTP clock switch startup is %uHz\n", otp->freq);
106 seq_printf(s, "PAF is %s\n", otp->paf ? "SET" : "NOT SET");
107 seq_printf(s, "IMEI is %s\n", otp->imeich ?
108 "CHANGEABLE" : "NOT CHANGEABLE");
109 seq_printf(s, "CID: 0x%04x (decimal: %d)\n", otp->cid, otp->cid);
110 seq_printf(s, "IMEI: %u-%u-%u\n", otp->tac, otp->fac, otp->svn);
111 return 0;
112}
113
114static int ab3100_otp_open(struct inode *inode, struct file *file)
115{
116 return single_open(file, ab3100_otp_show, inode->i_private);
117}
118
119static const struct file_operations ab3100_otp_operations = {
120 .open = ab3100_otp_open,
121 .read = seq_read,
122 .llseek = seq_lseek,
123 .release = single_release,
124};
125
126static int __init ab3100_otp_init_debugfs(struct device *dev,
127 struct ab3100_otp *otp)
128{
129 otp->debugfs = debugfs_create_file("ab3100_otp", S_IFREG | S_IRUGO,
130 NULL, otp,
131 &ab3100_otp_operations);
132 if (!otp->debugfs) {
133 dev_err(dev, "AB3100 debugfs OTP file registration failed!\n");
134 return err;
135 }
136}
137
138static void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp)
139{
140 debugfs_remove_file(otp->debugfs);
141}
142#else
143/* Compile this out if debugfs not selected */
144static inline int __init ab3100_otp_init_debugfs(struct device *dev,
145 struct ab3100_otp *otp)
146{
147 return 0;
148}
149
150static inline void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp)
151{
152}
153#endif
154
155#define SHOW_AB3100_ATTR(name) \
156static ssize_t ab3100_otp_##name##_show(struct device *dev, \
157 struct device_attribute *attr, \
158 char *buf) \
159{\
160 struct ab3100_otp *otp = dev_get_drvdata(dev); \
161 return sprintf(buf, "%u\n", otp->name); \
162}
163
164SHOW_AB3100_ATTR(locked)
165SHOW_AB3100_ATTR(freq)
166SHOW_AB3100_ATTR(paf)
167SHOW_AB3100_ATTR(imeich)
168SHOW_AB3100_ATTR(cid)
169SHOW_AB3100_ATTR(fac)
170SHOW_AB3100_ATTR(tac)
171SHOW_AB3100_ATTR(svn)
172
173static struct device_attribute ab3100_otp_attrs[] = {
174 __ATTR(locked, S_IRUGO, ab3100_otp_locked_show, NULL),
175 __ATTR(freq, S_IRUGO, ab3100_otp_freq_show, NULL),
176 __ATTR(paf, S_IRUGO, ab3100_otp_paf_show, NULL),
177 __ATTR(imeich, S_IRUGO, ab3100_otp_imeich_show, NULL),
178 __ATTR(cid, S_IRUGO, ab3100_otp_cid_show, NULL),
179 __ATTR(fac, S_IRUGO, ab3100_otp_fac_show, NULL),
180 __ATTR(tac, S_IRUGO, ab3100_otp_tac_show, NULL),
181 __ATTR(svn, S_IRUGO, ab3100_otp_svn_show, NULL),
182};
183
184static int __init ab3100_otp_probe(struct platform_device *pdev)
185{
186 struct ab3100_otp *otp;
187 int err = 0;
188 int i;
189
190 otp = kzalloc(sizeof(struct ab3100_otp), GFP_KERNEL);
191 if (!otp) {
192 dev_err(&pdev->dev, "could not allocate AB3100 OTP device\n");
193 return -ENOMEM;
194 }
195 otp->dev = &pdev->dev;
196
197 /* Replace platform data coming in with a local struct */
198 otp->ab3100 = platform_get_drvdata(pdev);
199 platform_set_drvdata(pdev, otp);
200
201 err = ab3100_otp_read(otp);
202 if (err)
203 return err;
204
205 dev_info(&pdev->dev, "AB3100 OTP readout registered\n");
206
207 /* sysfs entries */
208 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++) {
209 err = device_create_file(&pdev->dev,
210 &ab3100_otp_attrs[i]);
211 if (err)
212 goto out_no_sysfs;
213 }
214
215 /* debugfs entries */
216 err = ab3100_otp_init_debugfs(&pdev->dev, otp);
217 if (err)
218 goto out_no_debugfs;
219
220 return 0;
221
222out_no_sysfs:
223 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++)
224 device_remove_file(&pdev->dev,
225 &ab3100_otp_attrs[i]);
226out_no_debugfs:
227 kfree(otp);
228 return err;
229}
230
231static int __exit ab3100_otp_remove(struct platform_device *pdev)
232{
233 struct ab3100_otp *otp = platform_get_drvdata(pdev);
234 int i;
235
236 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++)
237 device_remove_file(&pdev->dev,
238 &ab3100_otp_attrs[i]);
239 ab3100_otp_exit_debugfs(otp);
240 kfree(otp);
241 return 0;
242}
243
244static struct platform_driver ab3100_otp_driver = {
245 .driver = {
246 .name = "ab3100-otp",
247 .owner = THIS_MODULE,
248 },
249 .remove = __exit_p(ab3100_otp_remove),
250};
251
252static int __init ab3100_otp_init(void)
253{
254 return platform_driver_probe(&ab3100_otp_driver,
255 ab3100_otp_probe);
256}
257
258static void __exit ab3100_otp_exit(void)
259{
260 platform_driver_unregister(&ab3100_otp_driver);
261}
262
263module_init(ab3100_otp_init);
264module_exit(ab3100_otp_exit);
265
266MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
267MODULE_DESCRIPTION("AB3100 OTP Readout Driver");
268MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c
index 5b6e58a3ba46..3d4a861976ca 100644
--- a/drivers/mfd/dm355evm_msp.c
+++ b/drivers/mfd/dm355evm_msp.c
@@ -107,8 +107,16 @@ static const u8 msp_gpios[] = {
107 MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1), 107 MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1),
108 MSP_GPIO(4, SWITCH1), 108 MSP_GPIO(4, SWITCH1),
109 /* switches on MMC/SD sockets */ 109 /* switches on MMC/SD sockets */
110 MSP_GPIO(1, SDMMC), MSP_GPIO(2, SDMMC), /* mmc0 WP, nCD */ 110 /*
111 MSP_GPIO(3, SDMMC), MSP_GPIO(4, SDMMC), /* mmc1 WP, nCD */ 111 * Note: EVMDM355_ECP_VA4.pdf suggests that Bit 2 and 4 should be
112 * checked for card detection. However on the EVM bit 1 and 3 gives
113 * this status, for 0 and 1 instance respectively. The pdf also
114 * suggests that Bit 1 and 3 should be checked for write protection.
115 * However on the EVM bit 2 and 4 gives this status,for 0 and 1
116 * instance respectively.
117 */
118 MSP_GPIO(2, SDMMC), MSP_GPIO(1, SDMMC), /* mmc0 WP, nCD */
119 MSP_GPIO(4, SDMMC), MSP_GPIO(3, SDMMC), /* mmc1 WP, nCD */
112}; 120};
113 121
114#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3) 122#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3)
diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
index c1de4afa89a6..016be4938e4c 100644
--- a/drivers/mfd/ezx-pcap.c
+++ b/drivers/mfd/ezx-pcap.c
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/mfd/ezx-pcap.h> 18#include <linux/mfd/ezx-pcap.h>
19#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
20 21
21#define PCAP_ADC_MAXQ 8 22#define PCAP_ADC_MAXQ 8
22struct pcap_adc_request { 23struct pcap_adc_request {
@@ -106,11 +107,35 @@ int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
106} 107}
107EXPORT_SYMBOL_GPL(ezx_pcap_read); 108EXPORT_SYMBOL_GPL(ezx_pcap_read);
108 109
110int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
111{
112 int ret;
113 u32 tmp = PCAP_REGISTER_READ_OP_BIT |
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
115
116 mutex_lock(&pcap->io_mutex);
117 ret = ezx_pcap_putget(pcap, &tmp);
118 if (ret)
119 goto out_unlock;
120
121 tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
122 tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
124
125 ret = ezx_pcap_putget(pcap, &tmp);
126out_unlock:
127 mutex_unlock(&pcap->io_mutex);
128
129 return ret;
130}
131EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
132
109/* IRQ */ 133/* IRQ */
110static inline unsigned int irq2pcap(struct pcap_chip *pcap, int irq) 134int irq_to_pcap(struct pcap_chip *pcap, int irq)
111{ 135{
112 return 1 << (irq - pcap->irq_base); 136 return irq - pcap->irq_base;
113} 137}
138EXPORT_SYMBOL_GPL(irq_to_pcap);
114 139
115int pcap_to_irq(struct pcap_chip *pcap, int irq) 140int pcap_to_irq(struct pcap_chip *pcap, int irq)
116{ 141{
@@ -122,7 +147,7 @@ static void pcap_mask_irq(unsigned int irq)
122{ 147{
123 struct pcap_chip *pcap = get_irq_chip_data(irq); 148 struct pcap_chip *pcap = get_irq_chip_data(irq);
124 149
125 pcap->msr |= irq2pcap(pcap, irq); 150 pcap->msr |= 1 << irq_to_pcap(pcap, irq);
126 queue_work(pcap->workqueue, &pcap->msr_work); 151 queue_work(pcap->workqueue, &pcap->msr_work);
127} 152}
128 153
@@ -130,7 +155,7 @@ static void pcap_unmask_irq(unsigned int irq)
130{ 155{
131 struct pcap_chip *pcap = get_irq_chip_data(irq); 156 struct pcap_chip *pcap = get_irq_chip_data(irq);
132 157
133 pcap->msr &= ~irq2pcap(pcap, irq); 158 pcap->msr &= ~(1 << irq_to_pcap(pcap, irq));
134 queue_work(pcap->workqueue, &pcap->msr_work); 159 queue_work(pcap->workqueue, &pcap->msr_work);
135} 160}
136 161
@@ -154,34 +179,38 @@ static void pcap_isr_work(struct work_struct *work)
154 u32 msr, isr, int_sel, service; 179 u32 msr, isr, int_sel, service;
155 int irq; 180 int irq;
156 181
157 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); 182 do {
158 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); 183 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
184 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
159 185
160 /* We cant service/ack irqs that are assigned to port 2 */ 186 /* We cant service/ack irqs that are assigned to port 2 */
161 if (!(pdata->config & PCAP_SECOND_PORT)) { 187 if (!(pdata->config & PCAP_SECOND_PORT)) {
162 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); 188 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
163 isr &= ~int_sel; 189 isr &= ~int_sel;
164 } 190 }
165 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
166 191
167 local_irq_disable(); 192 ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
168 service = isr & ~msr; 193 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
169 194
170 for (irq = pcap->irq_base; service; service >>= 1, irq++) { 195 local_irq_disable();
171 if (service & 1) { 196 service = isr & ~msr;
172 struct irq_desc *desc = irq_to_desc(irq); 197 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
198 if (service & 1) {
199 struct irq_desc *desc = irq_to_desc(irq);
173 200
174 if (WARN(!desc, KERN_WARNING 201 if (WARN(!desc, KERN_WARNING
175 "Invalid PCAP IRQ %d\n", irq)) 202 "Invalid PCAP IRQ %d\n", irq))
176 break; 203 break;
177 204
178 if (desc->status & IRQ_DISABLED) 205 if (desc->status & IRQ_DISABLED)
179 note_interrupt(irq, desc, IRQ_NONE); 206 note_interrupt(irq, desc, IRQ_NONE);
180 else 207 else
181 desc->handle_irq(irq, desc); 208 desc->handle_irq(irq, desc);
209 }
182 } 210 }
183 } 211 local_irq_enable();
184 local_irq_enable(); 212 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
213 } while (gpio_get_value(irq_to_gpio(pcap->spi->irq)));
185} 214}
186 215
187static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc) 216static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -194,6 +223,19 @@ static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
194} 223}
195 224
196/* ADC */ 225/* ADC */
226void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
227{
228 u32 tmp;
229
230 mutex_lock(&pcap->adc_mutex);
231 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
232 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
233 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
234 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
235 mutex_unlock(&pcap->adc_mutex);
236}
237EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
238
197static void pcap_disable_adc(struct pcap_chip *pcap) 239static void pcap_disable_adc(struct pcap_chip *pcap)
198{ 240{
199 u32 tmp; 241 u32 tmp;
@@ -216,15 +258,16 @@ static void pcap_adc_trigger(struct pcap_chip *pcap)
216 mutex_unlock(&pcap->adc_mutex); 258 mutex_unlock(&pcap->adc_mutex);
217 return; 259 return;
218 } 260 }
219 mutex_unlock(&pcap->adc_mutex); 261 /* start conversion on requested bank, save TS_M bits */
220 262 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
221 /* start conversion on requested bank */ 263 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
222 tmp = pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; 264 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
223 265
224 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) 266 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
225 tmp |= PCAP_ADC_AD_SEL1; 267 tmp |= PCAP_ADC_AD_SEL1;
226 268
227 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); 269 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
270 mutex_unlock(&pcap->adc_mutex);
228 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); 271 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
229} 272}
230 273
@@ -499,7 +542,7 @@ static void __exit ezx_pcap_exit(void)
499 spi_unregister_driver(&ezxpcap_driver); 542 spi_unregister_driver(&ezxpcap_driver);
500} 543}
501 544
502module_init(ezx_pcap_init); 545subsys_initcall(ezx_pcap_init);
503module_exit(ezx_pcap_exit); 546module_exit(ezx_pcap_exit);
504 547
505MODULE_LICENSE("GPL"); 548MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c
new file mode 100644
index 000000000000..e354d2912ef1
--- /dev/null
+++ b/drivers/mfd/mc13783-core.c
@@ -0,0 +1,427 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This code is in parts based on wm8350-core.c and pcf50633-core.c
5 *
6 * Initial development of this code was funded by
7 * Phytec Messtechnik GmbH, http://www.phytec.de
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/mfd/mc13783-private.h>
25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/completion.h>
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30#include <linux/spi/spi.h>
31#include <linux/uaccess.h>
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/slab.h>
36#include <linux/irq.h>
37
38#define MC13783_MAX_REG_NUM 0x3f
39#define MC13783_FRAME_MASK 0x00ffffff
40#define MC13783_MAX_REG_NUM 0x3f
41#define MC13783_REG_NUM_SHIFT 0x19
42#define MC13783_WRITE_BIT_SHIFT 31
43
44static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
45{
46 struct spi_transfer t = {
47 .tx_buf = (const void *)buf,
48 .rx_buf = buf,
49 .len = len,
50 .cs_change = 0,
51 .delay_usecs = 0,
52 };
53 struct spi_message m;
54
55 spi_message_init(&m);
56 spi_message_add_tail(&t, &m);
57 if (spi_sync(spi, &m) != 0 || m.status != 0)
58 return -EINVAL;
59 return len - m.actual_length;
60}
61
62static int mc13783_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
63{
64 unsigned int frame = 0;
65 int ret = 0;
66
67 if (reg_num > MC13783_MAX_REG_NUM)
68 return -EINVAL;
69
70 frame |= reg_num << MC13783_REG_NUM_SHIFT;
71
72 ret = spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
73
74 *reg_val = frame & MC13783_FRAME_MASK;
75
76 return ret;
77}
78
79static int mc13783_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
80{
81 unsigned int frame = 0;
82
83 if (reg_num > MC13783_MAX_REG_NUM)
84 return -EINVAL;
85
86 frame |= (1 << MC13783_WRITE_BIT_SHIFT);
87 frame |= reg_num << MC13783_REG_NUM_SHIFT;
88 frame |= reg_val & MC13783_FRAME_MASK;
89
90 return spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
91}
92
93int mc13783_reg_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
94{
95 int ret;
96
97 mutex_lock(&mc13783->io_lock);
98 ret = mc13783_read(mc13783, reg_num, reg_val);
99 mutex_unlock(&mc13783->io_lock);
100
101 return ret;
102}
103EXPORT_SYMBOL_GPL(mc13783_reg_read);
104
105int mc13783_reg_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
106{
107 int ret;
108
109 mutex_lock(&mc13783->io_lock);
110 ret = mc13783_write(mc13783, reg_num, reg_val);
111 mutex_unlock(&mc13783->io_lock);
112
113 return ret;
114}
115EXPORT_SYMBOL_GPL(mc13783_reg_write);
116
117/**
118 * mc13783_set_bits - Bitmask write
119 *
120 * @mc13783: Pointer to mc13783 control structure
121 * @reg: Register to access
122 * @mask: Mask of bits to change
123 * @val: Value to set for masked bits
124 */
125int mc13783_set_bits(struct mc13783 *mc13783, int reg, u32 mask, u32 val)
126{
127 u32 tmp;
128 int ret;
129
130 mutex_lock(&mc13783->io_lock);
131
132 ret = mc13783_read(mc13783, reg, &tmp);
133 tmp = (tmp & ~mask) | val;
134 if (ret == 0)
135 ret = mc13783_write(mc13783, reg, tmp);
136
137 mutex_unlock(&mc13783->io_lock);
138
139 return ret;
140}
141EXPORT_SYMBOL_GPL(mc13783_set_bits);
142
143int mc13783_register_irq(struct mc13783 *mc13783, int irq,
144 void (*handler) (int, void *), void *data)
145{
146 if (irq < 0 || irq > MC13783_NUM_IRQ || !handler)
147 return -EINVAL;
148
149 if (WARN_ON(mc13783->irq_handler[irq].handler))
150 return -EBUSY;
151
152 mutex_lock(&mc13783->io_lock);
153 mc13783->irq_handler[irq].handler = handler;
154 mc13783->irq_handler[irq].data = data;
155 mutex_unlock(&mc13783->io_lock);
156
157 return 0;
158}
159EXPORT_SYMBOL_GPL(mc13783_register_irq);
160
161int mc13783_free_irq(struct mc13783 *mc13783, int irq)
162{
163 if (irq < 0 || irq > MC13783_NUM_IRQ)
164 return -EINVAL;
165
166 mutex_lock(&mc13783->io_lock);
167 mc13783->irq_handler[irq].handler = NULL;
168 mutex_unlock(&mc13783->io_lock);
169
170 return 0;
171}
172EXPORT_SYMBOL_GPL(mc13783_free_irq);
173
174static void mc13783_irq_work(struct work_struct *work)
175{
176 struct mc13783 *mc13783 = container_of(work, struct mc13783, work);
177 int i;
178 unsigned int adc_sts;
179
180 /* check if the adc has finished any completion */
181 mc13783_reg_read(mc13783, MC13783_REG_INTERRUPT_STATUS_0, &adc_sts);
182 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0,
183 adc_sts & MC13783_INT_STAT_ADCDONEI);
184
185 if (adc_sts & MC13783_INT_STAT_ADCDONEI)
186 complete_all(&mc13783->adc_done);
187
188 for (i = 0; i < MC13783_NUM_IRQ; i++)
189 if (mc13783->irq_handler[i].handler)
190 mc13783->irq_handler[i].handler(i,
191 mc13783->irq_handler[i].data);
192 enable_irq(mc13783->irq);
193}
194
195static irqreturn_t mc13783_interrupt(int irq, void *dev_id)
196{
197 struct mc13783 *mc13783 = dev_id;
198
199 disable_irq_nosync(irq);
200
201 schedule_work(&mc13783->work);
202 return IRQ_HANDLED;
203}
204
205/* set adc to ts interrupt mode, which generates touchscreen wakeup interrupt */
206static inline void mc13783_adc_set_ts_irq_mode(struct mc13783 *mc13783)
207{
208 unsigned int reg_adc0, reg_adc1;
209
210 reg_adc0 = MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
211 | MC13783_ADC0_TSMOD0;
212 reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN;
213
214 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
215 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
216}
217
218int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
219 unsigned int channel, unsigned int *sample)
220{
221 unsigned int reg_adc0, reg_adc1;
222 int i;
223
224 mutex_lock(&mc13783->adc_conv_lock);
225
226 /* set up auto incrementing anyway to make quick read */
227 reg_adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
228 /* enable the adc, ignore external triggering and set ASC to trigger
229 * conversion */
230 reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN
231 | MC13783_ADC1_ASC;
232
233 /* setup channel number */
234 if (channel > 7)
235 reg_adc1 |= MC13783_ADC1_ADSEL;
236
237 switch (mode) {
238 case MC13783_ADC_MODE_TS:
239 /* enables touch screen reference mode and set touchscreen mode
240 * to position mode */
241 reg_adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
242 | MC13783_ADC0_TSMOD0 | MC13783_ADC0_TSMOD1;
243 reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
244 break;
245 case MC13783_ADC_MODE_SINGLE_CHAN:
246 reg_adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
247 reg_adc1 |= MC13783_ADC1_RAND;
248 break;
249 case MC13783_ADC_MODE_MULT_CHAN:
250 reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
251 break;
252 default:
253 return -EINVAL;
254 }
255
256 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
257 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
258
259 wait_for_completion_interruptible(&mc13783->adc_done);
260
261 for (i = 0; i < 4; i++)
262 mc13783_reg_read(mc13783, MC13783_REG_ADC_2, &sample[i]);
263
264 if (mc13783->ts_active)
265 mc13783_adc_set_ts_irq_mode(mc13783);
266
267 mutex_unlock(&mc13783->adc_conv_lock);
268
269 return 0;
270}
271EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
272
273void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status)
274{
275 mc13783->ts_active = status;
276}
277EXPORT_SYMBOL_GPL(mc13783_adc_set_ts_status);
278
279static int mc13783_check_revision(struct mc13783 *mc13783)
280{
281 u32 rev_id, rev1, rev2, finid, icid;
282
283 mc13783_read(mc13783, MC13783_REG_REVISION, &rev_id);
284
285 rev1 = (rev_id & 0x018) >> 3;
286 rev2 = (rev_id & 0x007);
287 icid = (rev_id & 0x01C0) >> 6;
288 finid = (rev_id & 0x01E00) >> 9;
289
290 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
291 if ((rev1 == 0) && (rev2 == 2))
292 rev1 = 3;
293
294 if (rev1 == 0 || icid != 2) {
295 dev_err(mc13783->dev, "No MC13783 detected.\n");
296 return -ENODEV;
297 }
298
299 mc13783->revision = ((rev1 * 10) + rev2);
300 dev_info(mc13783->dev, "MC13783 Rev %d.%d FinVer %x detected\n", rev1,
301 rev2, finid);
302
303 return 0;
304}
305
306/*
307 * Register a client device. This is non-fatal since there is no need to
308 * fail the entire device init due to a single platform device failing.
309 */
310static void mc13783_client_dev_register(struct mc13783 *mc13783,
311 const char *name)
312{
313 struct mfd_cell cell = {};
314
315 cell.name = name;
316
317 mfd_add_devices(mc13783->dev, -1, &cell, 1, NULL, 0);
318}
319
320static int __devinit mc13783_probe(struct spi_device *spi)
321{
322 struct mc13783 *mc13783;
323 struct mc13783_platform_data *pdata = spi->dev.platform_data;
324 int ret;
325
326 mc13783 = kzalloc(sizeof(struct mc13783), GFP_KERNEL);
327 if (!mc13783)
328 return -ENOMEM;
329
330 dev_set_drvdata(&spi->dev, mc13783);
331 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
332 spi->bits_per_word = 32;
333 spi_setup(spi);
334
335 mc13783->spi_device = spi;
336 mc13783->dev = &spi->dev;
337 mc13783->irq = spi->irq;
338
339 INIT_WORK(&mc13783->work, mc13783_irq_work);
340 mutex_init(&mc13783->io_lock);
341 mutex_init(&mc13783->adc_conv_lock);
342 init_completion(&mc13783->adc_done);
343
344 if (pdata) {
345 mc13783->flags = pdata->flags;
346 mc13783->regulators = pdata->regulators;
347 mc13783->num_regulators = pdata->num_regulators;
348 }
349
350 if (mc13783_check_revision(mc13783)) {
351 ret = -ENODEV;
352 goto err_out;
353 }
354
355 /* clear and mask all interrupts */
356 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0, 0x00ffffff);
357 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_0, 0x00ffffff);
358 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_1, 0x00ffffff);
359 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_1, 0x00ffffff);
360
361 /* unmask adcdone interrupts */
362 mc13783_set_bits(mc13783, MC13783_REG_INTERRUPT_MASK_0,
363 MC13783_INT_MASK_ADCDONEM, 0);
364
365 ret = request_irq(mc13783->irq, mc13783_interrupt,
366 IRQF_DISABLED | IRQF_TRIGGER_HIGH, "mc13783",
367 mc13783);
368 if (ret)
369 goto err_out;
370
371 if (mc13783->flags & MC13783_USE_CODEC)
372 mc13783_client_dev_register(mc13783, "mc13783-codec");
373 if (mc13783->flags & MC13783_USE_ADC)
374 mc13783_client_dev_register(mc13783, "mc13783-adc");
375 if (mc13783->flags & MC13783_USE_RTC)
376 mc13783_client_dev_register(mc13783, "mc13783-rtc");
377 if (mc13783->flags & MC13783_USE_REGULATOR)
378 mc13783_client_dev_register(mc13783, "mc13783-regulator");
379 if (mc13783->flags & MC13783_USE_TOUCHSCREEN)
380 mc13783_client_dev_register(mc13783, "mc13783-ts");
381
382 return 0;
383
384err_out:
385 kfree(mc13783);
386 return ret;
387}
388
389static int __devexit mc13783_remove(struct spi_device *spi)
390{
391 struct mc13783 *mc13783;
392
393 mc13783 = dev_get_drvdata(&spi->dev);
394
395 free_irq(mc13783->irq, mc13783);
396
397 mfd_remove_devices(&spi->dev);
398
399 return 0;
400}
401
402static struct spi_driver pmic_driver = {
403 .driver = {
404 .name = "mc13783",
405 .bus = &spi_bus_type,
406 .owner = THIS_MODULE,
407 },
408 .probe = mc13783_probe,
409 .remove = __devexit_p(mc13783_remove),
410};
411
412static int __init pmic_init(void)
413{
414 return spi_register_driver(&pmic_driver);
415}
416subsys_initcall(pmic_init);
417
418static void __exit pmic_exit(void)
419{
420 spi_unregister_driver(&pmic_driver);
421}
422module_exit(pmic_exit);
423
424MODULE_DESCRIPTION("Core/Protocol driver for Freescale MC13783 PMIC");
425MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
426MODULE_LICENSE("GPL");
427
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 54ddf3772e0c..ae15e495e20e 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -25,7 +25,7 @@ static int mfd_add_device(struct device *parent, int id,
25 int ret = -ENOMEM; 25 int ret = -ENOMEM;
26 int r; 26 int r;
27 27
28 pdev = platform_device_alloc(cell->name, id); 28 pdev = platform_device_alloc(cell->name, id + cell->id);
29 if (!pdev) 29 if (!pdev)
30 goto fail_alloc; 30 goto fail_alloc;
31 31
diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c
index c2d05becfa97..3d31e97d6a45 100644
--- a/drivers/mfd/pcf50633-adc.c
+++ b/drivers/mfd/pcf50633-adc.c
@@ -73,15 +73,10 @@ static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
73 struct pcf50633_adc *adc = __to_adc(pcf); 73 struct pcf50633_adc *adc = __to_adc(pcf);
74 int head; 74 int head;
75 75
76 mutex_lock(&adc->queue_mutex);
77
78 head = adc->queue_head; 76 head = adc->queue_head;
79 77
80 if (!adc->queue[head]) { 78 if (!adc->queue[head])
81 mutex_unlock(&adc->queue_mutex);
82 return; 79 return;
83 }
84 mutex_unlock(&adc->queue_mutex);
85 80
86 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); 81 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg);
87} 82}
@@ -99,16 +94,17 @@ adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
99 94
100 if (adc->queue[tail]) { 95 if (adc->queue[tail]) {
101 mutex_unlock(&adc->queue_mutex); 96 mutex_unlock(&adc->queue_mutex);
97 dev_err(pcf->dev, "ADC queue is full, dropping request\n");
102 return -EBUSY; 98 return -EBUSY;
103 } 99 }
104 100
105 adc->queue[tail] = req; 101 adc->queue[tail] = req;
102 if (head == tail)
103 trigger_next_adc_job_if_any(pcf);
106 adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1); 104 adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
107 105
108 mutex_unlock(&adc->queue_mutex); 106 mutex_unlock(&adc->queue_mutex);
109 107
110 trigger_next_adc_job_if_any(pcf);
111
112 return 0; 108 return 0;
113} 109}
114 110
@@ -124,6 +120,7 @@ pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result)
124int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) 120int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
125{ 121{
126 struct pcf50633_adc_request *req; 122 struct pcf50633_adc_request *req;
123 int err;
127 124
128 /* req is freed when the result is ready, in interrupt handler */ 125 /* req is freed when the result is ready, in interrupt handler */
129 req = kzalloc(sizeof(*req), GFP_KERNEL); 126 req = kzalloc(sizeof(*req), GFP_KERNEL);
@@ -136,9 +133,13 @@ int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
136 req->callback_param = req; 133 req->callback_param = req;
137 134
138 init_completion(&req->completion); 135 init_completion(&req->completion);
139 adc_enqueue_request(pcf, req); 136 err = adc_enqueue_request(pcf, req);
137 if (err)
138 return err;
139
140 wait_for_completion(&req->completion); 140 wait_for_completion(&req->completion);
141 141
142 /* FIXME by this time req might be already freed */
142 return req->result; 143 return req->result;
143} 144}
144EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read); 145EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
@@ -159,9 +160,7 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
159 req->callback = callback; 160 req->callback = callback;
160 req->callback_param = callback_param; 161 req->callback_param = callback_param;
161 162
162 adc_enqueue_request(pcf, req); 163 return adc_enqueue_request(pcf, req);
163
164 return 0;
165} 164}
166EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); 165EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
167 166
@@ -184,7 +183,7 @@ static void pcf50633_adc_irq(int irq, void *data)
184 struct pcf50633_adc *adc = data; 183 struct pcf50633_adc *adc = data;
185 struct pcf50633 *pcf = adc->pcf; 184 struct pcf50633 *pcf = adc->pcf;
186 struct pcf50633_adc_request *req; 185 struct pcf50633_adc_request *req;
187 int head; 186 int head, res;
188 187
189 mutex_lock(&adc->queue_mutex); 188 mutex_lock(&adc->queue_mutex);
190 head = adc->queue_head; 189 head = adc->queue_head;
@@ -199,12 +198,13 @@ static void pcf50633_adc_irq(int irq, void *data)
199 adc->queue_head = (head + 1) & 198 adc->queue_head = (head + 1) &
200 (PCF50633_MAX_ADC_FIFO_DEPTH - 1); 199 (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
201 200
201 res = adc_result(pcf);
202 trigger_next_adc_job_if_any(pcf);
203
202 mutex_unlock(&adc->queue_mutex); 204 mutex_unlock(&adc->queue_mutex);
203 205
204 req->callback(pcf, req->callback_param, adc_result(pcf)); 206 req->callback(pcf, req->callback_param, res);
205 kfree(req); 207 kfree(req);
206
207 trigger_next_adc_job_if_any(pcf);
208} 208}
209 209
210static int __devinit pcf50633_adc_probe(struct platform_device *pdev) 210static int __devinit pcf50633_adc_probe(struct platform_device *pdev)
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 8d3c38bf9714..d26d7747175e 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -444,7 +444,7 @@ static irqreturn_t pcf50633_irq(int irq, void *data)
444 444
445 get_device(pcf->dev); 445 get_device(pcf->dev);
446 disable_irq_nosync(pcf->irq); 446 disable_irq_nosync(pcf->irq);
447 schedule_work(&pcf->irq_work); 447 queue_work(pcf->work_queue, &pcf->irq_work);
448 448
449 return IRQ_HANDLED; 449 return IRQ_HANDLED;
450} 450}
@@ -575,6 +575,7 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
575 pcf->dev = &client->dev; 575 pcf->dev = &client->dev;
576 pcf->i2c_client = client; 576 pcf->i2c_client = client;
577 pcf->irq = client->irq; 577 pcf->irq = client->irq;
578 pcf->work_queue = create_singlethread_workqueue("pcf50633");
578 579
579 INIT_WORK(&pcf->irq_work, pcf50633_irq_worker); 580 INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
580 581
@@ -651,6 +652,7 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
651 return 0; 652 return 0;
652 653
653err: 654err:
655 destroy_workqueue(pcf->work_queue);
654 kfree(pcf); 656 kfree(pcf);
655 return ret; 657 return ret;
656} 658}
@@ -661,6 +663,7 @@ static int __devexit pcf50633_remove(struct i2c_client *client)
661 int i; 663 int i;
662 664
663 free_irq(pcf->irq, pcf); 665 free_irq(pcf->irq, pcf);
666 destroy_workqueue(pcf->work_queue);
664 667
665 platform_device_unregister(pcf->input_pdev); 668 platform_device_unregister(pcf->input_pdev);
666 platform_device_unregister(pcf->rtc_pdev); 669 platform_device_unregister(pcf->rtc_pdev);
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
index ca54996ffd0e..e424cf6d8e9e 100644
--- a/drivers/mfd/twl4030-core.c
+++ b/drivers/mfd/twl4030-core.c
@@ -89,6 +89,12 @@
89#define twl_has_madc() false 89#define twl_has_madc() false
90#endif 90#endif
91 91
92#ifdef CONFIG_TWL4030_POWER
93#define twl_has_power() true
94#else
95#define twl_has_power() false
96#endif
97
92#if defined(CONFIG_RTC_DRV_TWL4030) || defined(CONFIG_RTC_DRV_TWL4030_MODULE) 98#if defined(CONFIG_RTC_DRV_TWL4030) || defined(CONFIG_RTC_DRV_TWL4030_MODULE)
93#define twl_has_rtc() true 99#define twl_has_rtc() true
94#else 100#else
@@ -115,6 +121,12 @@
115 121
116#define TWL4030_NUM_SLAVES 4 122#define TWL4030_NUM_SLAVES 4
117 123
124#if defined(CONFIG_INPUT_TWL4030_PWRBUTTON) \
125 || defined(CONFIG_INPUT_TWL4030_PWBUTTON_MODULE)
126#define twl_has_pwrbutton() true
127#else
128#define twl_has_pwrbutton() false
129#endif
118 130
119/* Base Address defns for twl4030_map[] */ 131/* Base Address defns for twl4030_map[] */
120 132
@@ -538,6 +550,13 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
538 return PTR_ERR(child); 550 return PTR_ERR(child);
539 } 551 }
540 552
553 if (twl_has_pwrbutton()) {
554 child = add_child(1, "twl4030_pwrbutton",
555 NULL, 0, true, pdata->irq_base + 8 + 0, 0);
556 if (IS_ERR(child))
557 return PTR_ERR(child);
558 }
559
541 if (twl_has_regulator()) { 560 if (twl_has_regulator()) {
542 /* 561 /*
543 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1); 562 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1);
@@ -788,6 +807,10 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id)
788 /* setup clock framework */ 807 /* setup clock framework */
789 clocks_init(&client->dev); 808 clocks_init(&client->dev);
790 809
810 /* load power event scripts */
811 if (twl_has_power() && pdata->power)
812 twl4030_power_init(pdata->power);
813
791 /* Maybe init the T2 Interrupt subsystem */ 814 /* Maybe init the T2 Interrupt subsystem */
792 if (client->irq 815 if (client->irq
793 && pdata->irq_base 816 && pdata->irq_base
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index 7d430835655f..fb194fe244c1 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -424,7 +424,7 @@ static void twl4030_sih_do_edge(struct work_struct *work)
424 /* see what work we have */ 424 /* see what work we have */
425 spin_lock_irq(&sih_agent_lock); 425 spin_lock_irq(&sih_agent_lock);
426 edge_change = agent->edge_change; 426 edge_change = agent->edge_change;
427 agent->edge_change = 0;; 427 agent->edge_change = 0;
428 sih = edge_change ? agent->sih : NULL; 428 sih = edge_change ? agent->sih : NULL;
429 spin_unlock_irq(&sih_agent_lock); 429 spin_unlock_irq(&sih_agent_lock);
430 if (!sih) 430 if (!sih)
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
new file mode 100644
index 000000000000..d423e0c4176b
--- /dev/null
+++ b/drivers/mfd/twl4030-power.c
@@ -0,0 +1,472 @@
1/*
2 * linux/drivers/i2c/chips/twl4030-power.c
3 *
4 * Handle TWL4030 Power initialization
5 *
6 * Copyright (C) 2008 Nokia Corporation
7 * Copyright (C) 2006 Texas Instruments, Inc
8 *
9 * Written by Kalle Jokiniemi
10 * Peter De Schrijver <peter.de-schrijver@nokia.com>
11 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file "COPYING" in the main directory of this
15 * archive for more details.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <linux/module.h>
28#include <linux/pm.h>
29#include <linux/i2c/twl4030.h>
30#include <linux/platform_device.h>
31
32#include <asm/mach-types.h>
33
34static u8 twl4030_start_script_address = 0x2b;
35
36#define PWR_P1_SW_EVENTS 0x10
37#define PWR_DEVOFF (1<<0)
38
39#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
40#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
41
42/* resource - hfclk */
43#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
44
45/* PM events */
46#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
47#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
48#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
49#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
50#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
51#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
52
53#define LVL_WAKEUP 0x08
54
55#define ENABLE_WARMRESET (1<<4)
56
57#define END_OF_SCRIPT 0x3f
58
59#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
60#define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
61#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
62#define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
63#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
64#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
65
66#define R_PROTECT_KEY 0x0E
67#define R_KEY_1 0xC0
68#define R_KEY_2 0x0C
69
70/* resource configuration registers */
71
72#define DEVGROUP_OFFSET 0
73#define TYPE_OFFSET 1
74
75/* Bit positions */
76#define DEVGROUP_SHIFT 5
77#define DEVGROUP_MASK (7 << DEVGROUP_SHIFT)
78#define TYPE_SHIFT 0
79#define TYPE_MASK (7 << TYPE_SHIFT)
80#define TYPE2_SHIFT 3
81#define TYPE2_MASK (3 << TYPE2_SHIFT)
82
83static u8 res_config_addrs[] = {
84 [RES_VAUX1] = 0x17,
85 [RES_VAUX2] = 0x1b,
86 [RES_VAUX3] = 0x1f,
87 [RES_VAUX4] = 0x23,
88 [RES_VMMC1] = 0x27,
89 [RES_VMMC2] = 0x2b,
90 [RES_VPLL1] = 0x2f,
91 [RES_VPLL2] = 0x33,
92 [RES_VSIM] = 0x37,
93 [RES_VDAC] = 0x3b,
94 [RES_VINTANA1] = 0x3f,
95 [RES_VINTANA2] = 0x43,
96 [RES_VINTDIG] = 0x47,
97 [RES_VIO] = 0x4b,
98 [RES_VDD1] = 0x55,
99 [RES_VDD2] = 0x63,
100 [RES_VUSB_1V5] = 0x71,
101 [RES_VUSB_1V8] = 0x74,
102 [RES_VUSB_3V1] = 0x77,
103 [RES_VUSBCP] = 0x7a,
104 [RES_REGEN] = 0x7f,
105 [RES_NRES_PWRON] = 0x82,
106 [RES_CLKEN] = 0x85,
107 [RES_SYSEN] = 0x88,
108 [RES_HFCLKOUT] = 0x8b,
109 [RES_32KCLKOUT] = 0x8e,
110 [RES_RESET] = 0x91,
111 [RES_Main_Ref] = 0x94,
112};
113
114static int __init twl4030_write_script_byte(u8 address, u8 byte)
115{
116 int err;
117
118 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
119 R_MEMORY_ADDRESS);
120 if (err)
121 goto out;
122 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
123 R_MEMORY_DATA);
124out:
125 return err;
126}
127
128static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
129 u8 delay, u8 next)
130{
131 int err;
132
133 address *= 4;
134 err = twl4030_write_script_byte(address++, pmb_message >> 8);
135 if (err)
136 goto out;
137 err = twl4030_write_script_byte(address++, pmb_message & 0xff);
138 if (err)
139 goto out;
140 err = twl4030_write_script_byte(address++, delay);
141 if (err)
142 goto out;
143 err = twl4030_write_script_byte(address++, next);
144out:
145 return err;
146}
147
148static int __init twl4030_write_script(u8 address, struct twl4030_ins *script,
149 int len)
150{
151 int err;
152
153 for (; len; len--, address++, script++) {
154 if (len == 1) {
155 err = twl4030_write_script_ins(address,
156 script->pmb_message,
157 script->delay,
158 END_OF_SCRIPT);
159 if (err)
160 break;
161 } else {
162 err = twl4030_write_script_ins(address,
163 script->pmb_message,
164 script->delay,
165 address + 1);
166 if (err)
167 break;
168 }
169 }
170 return err;
171}
172
173static int __init twl4030_config_wakeup3_sequence(u8 address)
174{
175 int err;
176 u8 data;
177
178 /* Set SLEEP to ACTIVE SEQ address for P3 */
179 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
180 R_SEQ_ADD_S2A3);
181 if (err)
182 goto out;
183
184 /* P3 LVL_WAKEUP should be on LEVEL */
185 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
186 R_P3_SW_EVENTS);
187 if (err)
188 goto out;
189 data |= LVL_WAKEUP;
190 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
191 R_P3_SW_EVENTS);
192out:
193 if (err)
194 pr_err("TWL4030 wakeup sequence for P3 config error\n");
195 return err;
196}
197
198static int __init twl4030_config_wakeup12_sequence(u8 address)
199{
200 int err = 0;
201 u8 data;
202
203 /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
204 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
205 R_SEQ_ADD_S2A12);
206 if (err)
207 goto out;
208
209 /* P1/P2 LVL_WAKEUP should be on LEVEL */
210 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
211 R_P1_SW_EVENTS);
212 if (err)
213 goto out;
214
215 data |= LVL_WAKEUP;
216 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
217 R_P1_SW_EVENTS);
218 if (err)
219 goto out;
220
221 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
222 R_P2_SW_EVENTS);
223 if (err)
224 goto out;
225
226 data |= LVL_WAKEUP;
227 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
228 R_P2_SW_EVENTS);
229 if (err)
230 goto out;
231
232 if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
233 /* Disabling AC charger effect on sleep-active transitions */
234 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
235 R_CFG_P1_TRANSITION);
236 if (err)
237 goto out;
238 data &= ~(1<<1);
239 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
240 R_CFG_P1_TRANSITION);
241 if (err)
242 goto out;
243 }
244
245out:
246 if (err)
247 pr_err("TWL4030 wakeup sequence for P1 and P2" \
248 "config error\n");
249 return err;
250}
251
252static int __init twl4030_config_sleep_sequence(u8 address)
253{
254 int err;
255
256 /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
257 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
258 R_SEQ_ADD_A2S);
259
260 if (err)
261 pr_err("TWL4030 sleep sequence config error\n");
262
263 return err;
264}
265
266static int __init twl4030_config_warmreset_sequence(u8 address)
267{
268 int err;
269 u8 rd_data;
270
271 /* Set WARM RESET SEQ address for P1 */
272 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
273 R_SEQ_ADD_WARM);
274 if (err)
275 goto out;
276
277 /* P1/P2/P3 enable WARMRESET */
278 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
279 R_P1_SW_EVENTS);
280 if (err)
281 goto out;
282
283 rd_data |= ENABLE_WARMRESET;
284 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
285 R_P1_SW_EVENTS);
286 if (err)
287 goto out;
288
289 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
290 R_P2_SW_EVENTS);
291 if (err)
292 goto out;
293
294 rd_data |= ENABLE_WARMRESET;
295 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
296 R_P2_SW_EVENTS);
297 if (err)
298 goto out;
299
300 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
301 R_P3_SW_EVENTS);
302 if (err)
303 goto out;
304
305 rd_data |= ENABLE_WARMRESET;
306 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
307 R_P3_SW_EVENTS);
308out:
309 if (err)
310 pr_err("TWL4030 warmreset seq config error\n");
311 return err;
312}
313
314static int __init twl4030_configure_resource(struct twl4030_resconfig *rconfig)
315{
316 int rconfig_addr;
317 int err;
318 u8 type;
319 u8 grp;
320
321 if (rconfig->resource > TOTAL_RESOURCES) {
322 pr_err("TWL4030 Resource %d does not exist\n",
323 rconfig->resource);
324 return -EINVAL;
325 }
326
327 rconfig_addr = res_config_addrs[rconfig->resource];
328
329 /* Set resource group */
330 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &grp,
331 rconfig_addr + DEVGROUP_OFFSET);
332 if (err) {
333 pr_err("TWL4030 Resource %d group could not be read\n",
334 rconfig->resource);
335 return err;
336 }
337
338 if (rconfig->devgroup >= 0) {
339 grp &= ~DEVGROUP_MASK;
340 grp |= rconfig->devgroup << DEVGROUP_SHIFT;
341 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
342 grp, rconfig_addr + DEVGROUP_OFFSET);
343 if (err < 0) {
344 pr_err("TWL4030 failed to program devgroup\n");
345 return err;
346 }
347 }
348
349 /* Set resource types */
350 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &type,
351 rconfig_addr + TYPE_OFFSET);
352 if (err < 0) {
353 pr_err("TWL4030 Resource %d type could not be read\n",
354 rconfig->resource);
355 return err;
356 }
357
358 if (rconfig->type >= 0) {
359 type &= ~TYPE_MASK;
360 type |= rconfig->type << TYPE_SHIFT;
361 }
362
363 if (rconfig->type2 >= 0) {
364 type &= ~TYPE2_MASK;
365 type |= rconfig->type2 << TYPE2_SHIFT;
366 }
367
368 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
369 type, rconfig_addr + TYPE_OFFSET);
370 if (err < 0) {
371 pr_err("TWL4030 failed to program resource type\n");
372 return err;
373 }
374
375 return 0;
376}
377
378static int __init load_twl4030_script(struct twl4030_script *tscript,
379 u8 address)
380{
381 int err;
382 static int order;
383
384 /* Make sure the script isn't going beyond last valid address (0x3f) */
385 if ((address + tscript->size) > END_OF_SCRIPT) {
386 pr_err("TWL4030 scripts too big error\n");
387 return -EINVAL;
388 }
389
390 err = twl4030_write_script(address, tscript->script, tscript->size);
391 if (err)
392 goto out;
393
394 if (tscript->flags & TWL4030_WRST_SCRIPT) {
395 err = twl4030_config_warmreset_sequence(address);
396 if (err)
397 goto out;
398 }
399 if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
400 err = twl4030_config_wakeup12_sequence(address);
401 if (err)
402 goto out;
403 order = 1;
404 }
405 if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
406 err = twl4030_config_wakeup3_sequence(address);
407 if (err)
408 goto out;
409 }
410 if (tscript->flags & TWL4030_SLEEP_SCRIPT)
411 if (order)
412 pr_warning("TWL4030: Bad order of scripts (sleep "\
413 "script before wakeup) Leads to boot"\
414 "failure on some boards\n");
415 err = twl4030_config_sleep_sequence(address);
416out:
417 return err;
418}
419
420void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
421{
422 int err = 0;
423 int i;
424 struct twl4030_resconfig *resconfig;
425 u8 address = twl4030_start_script_address;
426
427 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_1,
428 R_PROTECT_KEY);
429 if (err)
430 goto unlock;
431
432 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_2,
433 R_PROTECT_KEY);
434 if (err)
435 goto unlock;
436
437 for (i = 0; i < twl4030_scripts->num; i++) {
438 err = load_twl4030_script(twl4030_scripts->scripts[i], address);
439 if (err)
440 goto load;
441 address += twl4030_scripts->scripts[i]->size;
442 }
443
444 resconfig = twl4030_scripts->resource_config;
445 if (resconfig) {
446 while (resconfig->resource) {
447 err = twl4030_configure_resource(resconfig);
448 if (err)
449 goto resource;
450 resconfig++;
451
452 }
453 }
454
455 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
456 if (err)
457 pr_err("TWL4030 Unable to relock registers\n");
458 return;
459
460unlock:
461 if (err)
462 pr_err("TWL4030 Unable to unlock registers\n");
463 return;
464load:
465 if (err)
466 pr_err("TWL4030 failed to load scripts\n");
467 return;
468resource:
469 if (err)
470 pr_err("TWL4030 failed to configure resource\n");
471 return;
472}
diff --git a/drivers/mfd/wm831x-core.c b/drivers/mfd/wm831x-core.c
new file mode 100644
index 000000000000..49b7885c2702
--- /dev/null
+++ b/drivers/mfd/wm831x-core.c
@@ -0,0 +1,1549 @@
1/*
2 * wm831x-core.c -- Device access for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/bcd.h>
19#include <linux/delay.h>
20#include <linux/mfd/core.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/pdata.h>
24#include <linux/mfd/wm831x/irq.h>
25#include <linux/mfd/wm831x/auxadc.h>
26#include <linux/mfd/wm831x/otp.h>
27#include <linux/mfd/wm831x/regulator.h>
28
29/* Current settings - values are 2*2^(reg_val/4) microamps. These are
30 * exported since they are used by multiple drivers.
31 */
32int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL] = {
33 2,
34 2,
35 3,
36 3,
37 4,
38 5,
39 6,
40 7,
41 8,
42 10,
43 11,
44 13,
45 16,
46 19,
47 23,
48 27,
49 32,
50 38,
51 45,
52 54,
53 64,
54 76,
55 91,
56 108,
57 128,
58 152,
59 181,
60 215,
61 256,
62 304,
63 362,
64 431,
65 512,
66 609,
67 724,
68 861,
69 1024,
70 1218,
71 1448,
72 1722,
73 2048,
74 2435,
75 2896,
76 3444,
77 4096,
78 4871,
79 5793,
80 6889,
81 8192,
82 9742,
83 11585,
84 13777,
85 16384,
86 19484,
87 23170,
88 27554,
89};
90EXPORT_SYMBOL_GPL(wm831x_isinkv_values);
91
92enum wm831x_parent {
93 WM8310 = 0,
94 WM8311 = 1,
95 WM8312 = 2,
96};
97
98static int wm831x_reg_locked(struct wm831x *wm831x, unsigned short reg)
99{
100 if (!wm831x->locked)
101 return 0;
102
103 switch (reg) {
104 case WM831X_WATCHDOG:
105 case WM831X_DC4_CONTROL:
106 case WM831X_ON_PIN_CONTROL:
107 case WM831X_BACKUP_CHARGER_CONTROL:
108 case WM831X_CHARGER_CONTROL_1:
109 case WM831X_CHARGER_CONTROL_2:
110 return 1;
111
112 default:
113 return 0;
114 }
115}
116
117/**
118 * wm831x_reg_unlock: Unlock user keyed registers
119 *
120 * The WM831x has a user key preventing writes to particularly
121 * critical registers. This function locks those registers,
122 * allowing writes to them.
123 */
124void wm831x_reg_lock(struct wm831x *wm831x)
125{
126 int ret;
127
128 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
129 if (ret == 0) {
130 dev_vdbg(wm831x->dev, "Registers locked\n");
131
132 mutex_lock(&wm831x->io_lock);
133 WARN_ON(wm831x->locked);
134 wm831x->locked = 1;
135 mutex_unlock(&wm831x->io_lock);
136 } else {
137 dev_err(wm831x->dev, "Failed to lock registers: %d\n", ret);
138 }
139
140}
141EXPORT_SYMBOL_GPL(wm831x_reg_lock);
142
143/**
144 * wm831x_reg_unlock: Unlock user keyed registers
145 *
146 * The WM831x has a user key preventing writes to particularly
147 * critical registers. This function locks those registers,
148 * preventing spurious writes.
149 */
150int wm831x_reg_unlock(struct wm831x *wm831x)
151{
152 int ret;
153
154 /* 0x9716 is the value required to unlock the registers */
155 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0x9716);
156 if (ret == 0) {
157 dev_vdbg(wm831x->dev, "Registers unlocked\n");
158
159 mutex_lock(&wm831x->io_lock);
160 WARN_ON(!wm831x->locked);
161 wm831x->locked = 0;
162 mutex_unlock(&wm831x->io_lock);
163 }
164
165 return ret;
166}
167EXPORT_SYMBOL_GPL(wm831x_reg_unlock);
168
169static int wm831x_read(struct wm831x *wm831x, unsigned short reg,
170 int bytes, void *dest)
171{
172 int ret, i;
173 u16 *buf = dest;
174
175 BUG_ON(bytes % 2);
176 BUG_ON(bytes <= 0);
177
178 ret = wm831x->read_dev(wm831x, reg, bytes, dest);
179 if (ret < 0)
180 return ret;
181
182 for (i = 0; i < bytes / 2; i++) {
183 buf[i] = be16_to_cpu(buf[i]);
184
185 dev_vdbg(wm831x->dev, "Read %04x from R%d(0x%x)\n",
186 buf[i], reg + i, reg + i);
187 }
188
189 return 0;
190}
191
192/**
193 * wm831x_reg_read: Read a single WM831x register.
194 *
195 * @wm831x: Device to read from.
196 * @reg: Register to read.
197 */
198int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg)
199{
200 unsigned short val;
201 int ret;
202
203 mutex_lock(&wm831x->io_lock);
204
205 ret = wm831x_read(wm831x, reg, 2, &val);
206
207 mutex_unlock(&wm831x->io_lock);
208
209 if (ret < 0)
210 return ret;
211 else
212 return val;
213}
214EXPORT_SYMBOL_GPL(wm831x_reg_read);
215
216/**
217 * wm831x_bulk_read: Read multiple WM831x registers
218 *
219 * @wm831x: Device to read from
220 * @reg: First register
221 * @count: Number of registers
222 * @buf: Buffer to fill.
223 */
224int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
225 int count, u16 *buf)
226{
227 int ret;
228
229 mutex_lock(&wm831x->io_lock);
230
231 ret = wm831x_read(wm831x, reg, count * 2, buf);
232
233 mutex_unlock(&wm831x->io_lock);
234
235 return ret;
236}
237EXPORT_SYMBOL_GPL(wm831x_bulk_read);
238
239static int wm831x_write(struct wm831x *wm831x, unsigned short reg,
240 int bytes, void *src)
241{
242 u16 *buf = src;
243 int i;
244
245 BUG_ON(bytes % 2);
246 BUG_ON(bytes <= 0);
247
248 for (i = 0; i < bytes / 2; i++) {
249 if (wm831x_reg_locked(wm831x, reg))
250 return -EPERM;
251
252 dev_vdbg(wm831x->dev, "Write %04x to R%d(0x%x)\n",
253 buf[i], reg + i, reg + i);
254
255 buf[i] = cpu_to_be16(buf[i]);
256 }
257
258 return wm831x->write_dev(wm831x, reg, bytes, src);
259}
260
261/**
262 * wm831x_reg_write: Write a single WM831x register.
263 *
264 * @wm831x: Device to write to.
265 * @reg: Register to write to.
266 * @val: Value to write.
267 */
268int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
269 unsigned short val)
270{
271 int ret;
272
273 mutex_lock(&wm831x->io_lock);
274
275 ret = wm831x_write(wm831x, reg, 2, &val);
276
277 mutex_unlock(&wm831x->io_lock);
278
279 return ret;
280}
281EXPORT_SYMBOL_GPL(wm831x_reg_write);
282
283/**
284 * wm831x_set_bits: Set the value of a bitfield in a WM831x register
285 *
286 * @wm831x: Device to write to.
287 * @reg: Register to write to.
288 * @mask: Mask of bits to set.
289 * @val: Value to set (unshifted)
290 */
291int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
292 unsigned short mask, unsigned short val)
293{
294 int ret;
295 u16 r;
296
297 mutex_lock(&wm831x->io_lock);
298
299 ret = wm831x_read(wm831x, reg, 2, &r);
300 if (ret < 0)
301 goto out;
302
303 r &= ~mask;
304 r |= val;
305
306 ret = wm831x_write(wm831x, reg, 2, &r);
307
308out:
309 mutex_unlock(&wm831x->io_lock);
310
311 return ret;
312}
313EXPORT_SYMBOL_GPL(wm831x_set_bits);
314
315/**
316 * wm831x_auxadc_read: Read a value from the WM831x AUXADC
317 *
318 * @wm831x: Device to read from.
319 * @input: AUXADC input to read.
320 */
321int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input)
322{
323 int tries = 10;
324 int ret, src;
325
326 mutex_lock(&wm831x->auxadc_lock);
327
328 ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
329 WM831X_AUX_ENA, WM831X_AUX_ENA);
330 if (ret < 0) {
331 dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n", ret);
332 goto out;
333 }
334
335 /* We force a single source at present */
336 src = input;
337 ret = wm831x_reg_write(wm831x, WM831X_AUXADC_SOURCE,
338 1 << src);
339 if (ret < 0) {
340 dev_err(wm831x->dev, "Failed to set AUXADC source: %d\n", ret);
341 goto out;
342 }
343
344 ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
345 WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA);
346 if (ret < 0) {
347 dev_err(wm831x->dev, "Failed to start AUXADC: %d\n", ret);
348 goto disable;
349 }
350
351 do {
352 msleep(1);
353
354 ret = wm831x_reg_read(wm831x, WM831X_AUXADC_CONTROL);
355 if (ret < 0)
356 ret = WM831X_AUX_CVT_ENA;
357 } while ((ret & WM831X_AUX_CVT_ENA) && --tries);
358
359 if (ret & WM831X_AUX_CVT_ENA) {
360 dev_err(wm831x->dev, "Timed out reading AUXADC\n");
361 ret = -EBUSY;
362 goto disable;
363 }
364
365 ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
366 if (ret < 0) {
367 dev_err(wm831x->dev, "Failed to read AUXADC data: %d\n", ret);
368 } else {
369 src = ((ret & WM831X_AUX_DATA_SRC_MASK)
370 >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
371
372 if (src == 14)
373 src = WM831X_AUX_CAL;
374
375 if (src != input) {
376 dev_err(wm831x->dev, "Data from source %d not %d\n",
377 src, input);
378 ret = -EINVAL;
379 } else {
380 ret &= WM831X_AUX_DATA_MASK;
381 }
382 }
383
384disable:
385 wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, WM831X_AUX_ENA, 0);
386out:
387 mutex_unlock(&wm831x->auxadc_lock);
388 return ret;
389}
390EXPORT_SYMBOL_GPL(wm831x_auxadc_read);
391
392/**
393 * wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC
394 *
395 * @wm831x: Device to read from.
396 * @input: AUXADC input to read.
397 */
398int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input)
399{
400 int ret;
401
402 ret = wm831x_auxadc_read(wm831x, input);
403 if (ret < 0)
404 return ret;
405
406 ret *= 1465;
407
408 return ret;
409}
410EXPORT_SYMBOL_GPL(wm831x_auxadc_read_uv);
411
412static struct resource wm831x_dcdc1_resources[] = {
413 {
414 .start = WM831X_DC1_CONTROL_1,
415 .end = WM831X_DC1_DVS_CONTROL,
416 .flags = IORESOURCE_IO,
417 },
418 {
419 .name = "UV",
420 .start = WM831X_IRQ_UV_DC1,
421 .end = WM831X_IRQ_UV_DC1,
422 .flags = IORESOURCE_IRQ,
423 },
424 {
425 .name = "HC",
426 .start = WM831X_IRQ_HC_DC1,
427 .end = WM831X_IRQ_HC_DC1,
428 .flags = IORESOURCE_IRQ,
429 },
430};
431
432
433static struct resource wm831x_dcdc2_resources[] = {
434 {
435 .start = WM831X_DC2_CONTROL_1,
436 .end = WM831X_DC2_DVS_CONTROL,
437 .flags = IORESOURCE_IO,
438 },
439 {
440 .name = "UV",
441 .start = WM831X_IRQ_UV_DC2,
442 .end = WM831X_IRQ_UV_DC2,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .name = "HC",
447 .start = WM831X_IRQ_HC_DC2,
448 .end = WM831X_IRQ_HC_DC2,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static struct resource wm831x_dcdc3_resources[] = {
454 {
455 .start = WM831X_DC3_CONTROL_1,
456 .end = WM831X_DC3_SLEEP_CONTROL,
457 .flags = IORESOURCE_IO,
458 },
459 {
460 .name = "UV",
461 .start = WM831X_IRQ_UV_DC3,
462 .end = WM831X_IRQ_UV_DC3,
463 .flags = IORESOURCE_IRQ,
464 },
465};
466
467static struct resource wm831x_dcdc4_resources[] = {
468 {
469 .start = WM831X_DC4_CONTROL,
470 .end = WM831X_DC4_SLEEP_CONTROL,
471 .flags = IORESOURCE_IO,
472 },
473 {
474 .name = "UV",
475 .start = WM831X_IRQ_UV_DC4,
476 .end = WM831X_IRQ_UV_DC4,
477 .flags = IORESOURCE_IRQ,
478 },
479};
480
481static struct resource wm831x_gpio_resources[] = {
482 {
483 .start = WM831X_IRQ_GPIO_1,
484 .end = WM831X_IRQ_GPIO_16,
485 .flags = IORESOURCE_IRQ,
486 },
487};
488
489static struct resource wm831x_isink1_resources[] = {
490 {
491 .start = WM831X_CURRENT_SINK_1,
492 .end = WM831X_CURRENT_SINK_1,
493 .flags = IORESOURCE_IO,
494 },
495 {
496 .start = WM831X_IRQ_CS1,
497 .end = WM831X_IRQ_CS1,
498 .flags = IORESOURCE_IRQ,
499 },
500};
501
502static struct resource wm831x_isink2_resources[] = {
503 {
504 .start = WM831X_CURRENT_SINK_2,
505 .end = WM831X_CURRENT_SINK_2,
506 .flags = IORESOURCE_IO,
507 },
508 {
509 .start = WM831X_IRQ_CS2,
510 .end = WM831X_IRQ_CS2,
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct resource wm831x_ldo1_resources[] = {
516 {
517 .start = WM831X_LDO1_CONTROL,
518 .end = WM831X_LDO1_SLEEP_CONTROL,
519 .flags = IORESOURCE_IO,
520 },
521 {
522 .name = "UV",
523 .start = WM831X_IRQ_UV_LDO1,
524 .end = WM831X_IRQ_UV_LDO1,
525 .flags = IORESOURCE_IRQ,
526 },
527};
528
529static struct resource wm831x_ldo2_resources[] = {
530 {
531 .start = WM831X_LDO2_CONTROL,
532 .end = WM831X_LDO2_SLEEP_CONTROL,
533 .flags = IORESOURCE_IO,
534 },
535 {
536 .name = "UV",
537 .start = WM831X_IRQ_UV_LDO2,
538 .end = WM831X_IRQ_UV_LDO2,
539 .flags = IORESOURCE_IRQ,
540 },
541};
542
543static struct resource wm831x_ldo3_resources[] = {
544 {
545 .start = WM831X_LDO3_CONTROL,
546 .end = WM831X_LDO3_SLEEP_CONTROL,
547 .flags = IORESOURCE_IO,
548 },
549 {
550 .name = "UV",
551 .start = WM831X_IRQ_UV_LDO3,
552 .end = WM831X_IRQ_UV_LDO3,
553 .flags = IORESOURCE_IRQ,
554 },
555};
556
557static struct resource wm831x_ldo4_resources[] = {
558 {
559 .start = WM831X_LDO4_CONTROL,
560 .end = WM831X_LDO4_SLEEP_CONTROL,
561 .flags = IORESOURCE_IO,
562 },
563 {
564 .name = "UV",
565 .start = WM831X_IRQ_UV_LDO4,
566 .end = WM831X_IRQ_UV_LDO4,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
571static struct resource wm831x_ldo5_resources[] = {
572 {
573 .start = WM831X_LDO5_CONTROL,
574 .end = WM831X_LDO5_SLEEP_CONTROL,
575 .flags = IORESOURCE_IO,
576 },
577 {
578 .name = "UV",
579 .start = WM831X_IRQ_UV_LDO5,
580 .end = WM831X_IRQ_UV_LDO5,
581 .flags = IORESOURCE_IRQ,
582 },
583};
584
585static struct resource wm831x_ldo6_resources[] = {
586 {
587 .start = WM831X_LDO6_CONTROL,
588 .end = WM831X_LDO6_SLEEP_CONTROL,
589 .flags = IORESOURCE_IO,
590 },
591 {
592 .name = "UV",
593 .start = WM831X_IRQ_UV_LDO6,
594 .end = WM831X_IRQ_UV_LDO6,
595 .flags = IORESOURCE_IRQ,
596 },
597};
598
599static struct resource wm831x_ldo7_resources[] = {
600 {
601 .start = WM831X_LDO7_CONTROL,
602 .end = WM831X_LDO7_SLEEP_CONTROL,
603 .flags = IORESOURCE_IO,
604 },
605 {
606 .name = "UV",
607 .start = WM831X_IRQ_UV_LDO7,
608 .end = WM831X_IRQ_UV_LDO7,
609 .flags = IORESOURCE_IRQ,
610 },
611};
612
613static struct resource wm831x_ldo8_resources[] = {
614 {
615 .start = WM831X_LDO8_CONTROL,
616 .end = WM831X_LDO8_SLEEP_CONTROL,
617 .flags = IORESOURCE_IO,
618 },
619 {
620 .name = "UV",
621 .start = WM831X_IRQ_UV_LDO8,
622 .end = WM831X_IRQ_UV_LDO8,
623 .flags = IORESOURCE_IRQ,
624 },
625};
626
627static struct resource wm831x_ldo9_resources[] = {
628 {
629 .start = WM831X_LDO9_CONTROL,
630 .end = WM831X_LDO9_SLEEP_CONTROL,
631 .flags = IORESOURCE_IO,
632 },
633 {
634 .name = "UV",
635 .start = WM831X_IRQ_UV_LDO9,
636 .end = WM831X_IRQ_UV_LDO9,
637 .flags = IORESOURCE_IRQ,
638 },
639};
640
641static struct resource wm831x_ldo10_resources[] = {
642 {
643 .start = WM831X_LDO10_CONTROL,
644 .end = WM831X_LDO10_SLEEP_CONTROL,
645 .flags = IORESOURCE_IO,
646 },
647 {
648 .name = "UV",
649 .start = WM831X_IRQ_UV_LDO10,
650 .end = WM831X_IRQ_UV_LDO10,
651 .flags = IORESOURCE_IRQ,
652 },
653};
654
655static struct resource wm831x_ldo11_resources[] = {
656 {
657 .start = WM831X_LDO11_ON_CONTROL,
658 .end = WM831X_LDO11_SLEEP_CONTROL,
659 .flags = IORESOURCE_IO,
660 },
661};
662
663static struct resource wm831x_on_resources[] = {
664 {
665 .start = WM831X_IRQ_ON,
666 .end = WM831X_IRQ_ON,
667 .flags = IORESOURCE_IRQ,
668 },
669};
670
671
672static struct resource wm831x_power_resources[] = {
673 {
674 .name = "SYSLO",
675 .start = WM831X_IRQ_PPM_SYSLO,
676 .end = WM831X_IRQ_PPM_SYSLO,
677 .flags = IORESOURCE_IRQ,
678 },
679 {
680 .name = "PWR SRC",
681 .start = WM831X_IRQ_PPM_PWR_SRC,
682 .end = WM831X_IRQ_PPM_PWR_SRC,
683 .flags = IORESOURCE_IRQ,
684 },
685 {
686 .name = "USB CURR",
687 .start = WM831X_IRQ_PPM_USB_CURR,
688 .end = WM831X_IRQ_PPM_USB_CURR,
689 .flags = IORESOURCE_IRQ,
690 },
691 {
692 .name = "BATT HOT",
693 .start = WM831X_IRQ_CHG_BATT_HOT,
694 .end = WM831X_IRQ_CHG_BATT_HOT,
695 .flags = IORESOURCE_IRQ,
696 },
697 {
698 .name = "BATT COLD",
699 .start = WM831X_IRQ_CHG_BATT_COLD,
700 .end = WM831X_IRQ_CHG_BATT_COLD,
701 .flags = IORESOURCE_IRQ,
702 },
703 {
704 .name = "BATT FAIL",
705 .start = WM831X_IRQ_CHG_BATT_FAIL,
706 .end = WM831X_IRQ_CHG_BATT_FAIL,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .name = "OV",
711 .start = WM831X_IRQ_CHG_OV,
712 .end = WM831X_IRQ_CHG_OV,
713 .flags = IORESOURCE_IRQ,
714 },
715 {
716 .name = "END",
717 .start = WM831X_IRQ_CHG_END,
718 .end = WM831X_IRQ_CHG_END,
719 .flags = IORESOURCE_IRQ,
720 },
721 {
722 .name = "TO",
723 .start = WM831X_IRQ_CHG_TO,
724 .end = WM831X_IRQ_CHG_TO,
725 .flags = IORESOURCE_IRQ,
726 },
727 {
728 .name = "MODE",
729 .start = WM831X_IRQ_CHG_MODE,
730 .end = WM831X_IRQ_CHG_MODE,
731 .flags = IORESOURCE_IRQ,
732 },
733 {
734 .name = "START",
735 .start = WM831X_IRQ_CHG_START,
736 .end = WM831X_IRQ_CHG_START,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct resource wm831x_rtc_resources[] = {
742 {
743 .name = "PER",
744 .start = WM831X_IRQ_RTC_PER,
745 .end = WM831X_IRQ_RTC_PER,
746 .flags = IORESOURCE_IRQ,
747 },
748 {
749 .name = "ALM",
750 .start = WM831X_IRQ_RTC_ALM,
751 .end = WM831X_IRQ_RTC_ALM,
752 .flags = IORESOURCE_IRQ,
753 },
754};
755
756static struct resource wm831x_status1_resources[] = {
757 {
758 .start = WM831X_STATUS_LED_1,
759 .end = WM831X_STATUS_LED_1,
760 .flags = IORESOURCE_IO,
761 },
762};
763
764static struct resource wm831x_status2_resources[] = {
765 {
766 .start = WM831X_STATUS_LED_2,
767 .end = WM831X_STATUS_LED_2,
768 .flags = IORESOURCE_IO,
769 },
770};
771
772static struct resource wm831x_touch_resources[] = {
773 {
774 .name = "TCHPD",
775 .start = WM831X_IRQ_TCHPD,
776 .end = WM831X_IRQ_TCHPD,
777 .flags = IORESOURCE_IRQ,
778 },
779 {
780 .name = "TCHDATA",
781 .start = WM831X_IRQ_TCHDATA,
782 .end = WM831X_IRQ_TCHDATA,
783 .flags = IORESOURCE_IRQ,
784 },
785};
786
787static struct resource wm831x_wdt_resources[] = {
788 {
789 .start = WM831X_IRQ_WDOG_TO,
790 .end = WM831X_IRQ_WDOG_TO,
791 .flags = IORESOURCE_IRQ,
792 },
793};
794
795static struct mfd_cell wm8310_devs[] = {
796 {
797 .name = "wm831x-buckv",
798 .id = 1,
799 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
800 .resources = wm831x_dcdc1_resources,
801 },
802 {
803 .name = "wm831x-buckv",
804 .id = 2,
805 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
806 .resources = wm831x_dcdc2_resources,
807 },
808 {
809 .name = "wm831x-buckp",
810 .id = 3,
811 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
812 .resources = wm831x_dcdc3_resources,
813 },
814 {
815 .name = "wm831x-boostp",
816 .id = 4,
817 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
818 .resources = wm831x_dcdc4_resources,
819 },
820 {
821 .name = "wm831x-epe",
822 .id = 1,
823 },
824 {
825 .name = "wm831x-epe",
826 .id = 2,
827 },
828 {
829 .name = "wm831x-gpio",
830 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
831 .resources = wm831x_gpio_resources,
832 },
833 {
834 .name = "wm831x-hwmon",
835 },
836 {
837 .name = "wm831x-isink",
838 .id = 1,
839 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
840 .resources = wm831x_isink1_resources,
841 },
842 {
843 .name = "wm831x-isink",
844 .id = 2,
845 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
846 .resources = wm831x_isink2_resources,
847 },
848 {
849 .name = "wm831x-ldo",
850 .id = 1,
851 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
852 .resources = wm831x_ldo1_resources,
853 },
854 {
855 .name = "wm831x-ldo",
856 .id = 2,
857 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
858 .resources = wm831x_ldo2_resources,
859 },
860 {
861 .name = "wm831x-ldo",
862 .id = 3,
863 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
864 .resources = wm831x_ldo3_resources,
865 },
866 {
867 .name = "wm831x-ldo",
868 .id = 4,
869 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
870 .resources = wm831x_ldo4_resources,
871 },
872 {
873 .name = "wm831x-ldo",
874 .id = 5,
875 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
876 .resources = wm831x_ldo5_resources,
877 },
878 {
879 .name = "wm831x-ldo",
880 .id = 6,
881 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
882 .resources = wm831x_ldo6_resources,
883 },
884 {
885 .name = "wm831x-aldo",
886 .id = 7,
887 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
888 .resources = wm831x_ldo7_resources,
889 },
890 {
891 .name = "wm831x-aldo",
892 .id = 8,
893 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
894 .resources = wm831x_ldo8_resources,
895 },
896 {
897 .name = "wm831x-aldo",
898 .id = 9,
899 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
900 .resources = wm831x_ldo9_resources,
901 },
902 {
903 .name = "wm831x-aldo",
904 .id = 10,
905 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
906 .resources = wm831x_ldo10_resources,
907 },
908 {
909 .name = "wm831x-alive-ldo",
910 .id = 11,
911 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
912 .resources = wm831x_ldo11_resources,
913 },
914 {
915 .name = "wm831x-on",
916 .num_resources = ARRAY_SIZE(wm831x_on_resources),
917 .resources = wm831x_on_resources,
918 },
919 {
920 .name = "wm831x-power",
921 .num_resources = ARRAY_SIZE(wm831x_power_resources),
922 .resources = wm831x_power_resources,
923 },
924 {
925 .name = "wm831x-rtc",
926 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
927 .resources = wm831x_rtc_resources,
928 },
929 {
930 .name = "wm831x-status",
931 .id = 1,
932 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
933 .resources = wm831x_status1_resources,
934 },
935 {
936 .name = "wm831x-status",
937 .id = 2,
938 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
939 .resources = wm831x_status2_resources,
940 },
941 {
942 .name = "wm831x-watchdog",
943 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
944 .resources = wm831x_wdt_resources,
945 },
946};
947
948static struct mfd_cell wm8311_devs[] = {
949 {
950 .name = "wm831x-buckv",
951 .id = 1,
952 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
953 .resources = wm831x_dcdc1_resources,
954 },
955 {
956 .name = "wm831x-buckv",
957 .id = 2,
958 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
959 .resources = wm831x_dcdc2_resources,
960 },
961 {
962 .name = "wm831x-buckp",
963 .id = 3,
964 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
965 .resources = wm831x_dcdc3_resources,
966 },
967 {
968 .name = "wm831x-boostp",
969 .id = 4,
970 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
971 .resources = wm831x_dcdc4_resources,
972 },
973 {
974 .name = "wm831x-epe",
975 .id = 1,
976 },
977 {
978 .name = "wm831x-epe",
979 .id = 2,
980 },
981 {
982 .name = "wm831x-gpio",
983 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
984 .resources = wm831x_gpio_resources,
985 },
986 {
987 .name = "wm831x-hwmon",
988 },
989 {
990 .name = "wm831x-isink",
991 .id = 1,
992 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
993 .resources = wm831x_isink1_resources,
994 },
995 {
996 .name = "wm831x-isink",
997 .id = 2,
998 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
999 .resources = wm831x_isink2_resources,
1000 },
1001 {
1002 .name = "wm831x-ldo",
1003 .id = 1,
1004 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1005 .resources = wm831x_ldo1_resources,
1006 },
1007 {
1008 .name = "wm831x-ldo",
1009 .id = 2,
1010 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1011 .resources = wm831x_ldo2_resources,
1012 },
1013 {
1014 .name = "wm831x-ldo",
1015 .id = 3,
1016 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1017 .resources = wm831x_ldo3_resources,
1018 },
1019 {
1020 .name = "wm831x-ldo",
1021 .id = 4,
1022 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1023 .resources = wm831x_ldo4_resources,
1024 },
1025 {
1026 .name = "wm831x-ldo",
1027 .id = 5,
1028 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1029 .resources = wm831x_ldo5_resources,
1030 },
1031 {
1032 .name = "wm831x-aldo",
1033 .id = 7,
1034 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1035 .resources = wm831x_ldo7_resources,
1036 },
1037 {
1038 .name = "wm831x-alive-ldo",
1039 .id = 11,
1040 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1041 .resources = wm831x_ldo11_resources,
1042 },
1043 {
1044 .name = "wm831x-on",
1045 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1046 .resources = wm831x_on_resources,
1047 },
1048 {
1049 .name = "wm831x-power",
1050 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1051 .resources = wm831x_power_resources,
1052 },
1053 {
1054 .name = "wm831x-rtc",
1055 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
1056 .resources = wm831x_rtc_resources,
1057 },
1058 {
1059 .name = "wm831x-status",
1060 .id = 1,
1061 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1062 .resources = wm831x_status1_resources,
1063 },
1064 {
1065 .name = "wm831x-status",
1066 .id = 2,
1067 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1068 .resources = wm831x_status2_resources,
1069 },
1070 {
1071 .name = "wm831x-touch",
1072 .num_resources = ARRAY_SIZE(wm831x_touch_resources),
1073 .resources = wm831x_touch_resources,
1074 },
1075 {
1076 .name = "wm831x-watchdog",
1077 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1078 .resources = wm831x_wdt_resources,
1079 },
1080};
1081
1082static struct mfd_cell wm8312_devs[] = {
1083 {
1084 .name = "wm831x-buckv",
1085 .id = 1,
1086 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1087 .resources = wm831x_dcdc1_resources,
1088 },
1089 {
1090 .name = "wm831x-buckv",
1091 .id = 2,
1092 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1093 .resources = wm831x_dcdc2_resources,
1094 },
1095 {
1096 .name = "wm831x-buckp",
1097 .id = 3,
1098 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1099 .resources = wm831x_dcdc3_resources,
1100 },
1101 {
1102 .name = "wm831x-boostp",
1103 .id = 4,
1104 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
1105 .resources = wm831x_dcdc4_resources,
1106 },
1107 {
1108 .name = "wm831x-epe",
1109 .id = 1,
1110 },
1111 {
1112 .name = "wm831x-epe",
1113 .id = 2,
1114 },
1115 {
1116 .name = "wm831x-gpio",
1117 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1118 .resources = wm831x_gpio_resources,
1119 },
1120 {
1121 .name = "wm831x-hwmon",
1122 },
1123 {
1124 .name = "wm831x-isink",
1125 .id = 1,
1126 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
1127 .resources = wm831x_isink1_resources,
1128 },
1129 {
1130 .name = "wm831x-isink",
1131 .id = 2,
1132 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
1133 .resources = wm831x_isink2_resources,
1134 },
1135 {
1136 .name = "wm831x-ldo",
1137 .id = 1,
1138 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1139 .resources = wm831x_ldo1_resources,
1140 },
1141 {
1142 .name = "wm831x-ldo",
1143 .id = 2,
1144 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1145 .resources = wm831x_ldo2_resources,
1146 },
1147 {
1148 .name = "wm831x-ldo",
1149 .id = 3,
1150 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1151 .resources = wm831x_ldo3_resources,
1152 },
1153 {
1154 .name = "wm831x-ldo",
1155 .id = 4,
1156 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1157 .resources = wm831x_ldo4_resources,
1158 },
1159 {
1160 .name = "wm831x-ldo",
1161 .id = 5,
1162 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1163 .resources = wm831x_ldo5_resources,
1164 },
1165 {
1166 .name = "wm831x-ldo",
1167 .id = 6,
1168 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
1169 .resources = wm831x_ldo6_resources,
1170 },
1171 {
1172 .name = "wm831x-aldo",
1173 .id = 7,
1174 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1175 .resources = wm831x_ldo7_resources,
1176 },
1177 {
1178 .name = "wm831x-aldo",
1179 .id = 8,
1180 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
1181 .resources = wm831x_ldo8_resources,
1182 },
1183 {
1184 .name = "wm831x-aldo",
1185 .id = 9,
1186 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
1187 .resources = wm831x_ldo9_resources,
1188 },
1189 {
1190 .name = "wm831x-aldo",
1191 .id = 10,
1192 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
1193 .resources = wm831x_ldo10_resources,
1194 },
1195 {
1196 .name = "wm831x-alive-ldo",
1197 .id = 11,
1198 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1199 .resources = wm831x_ldo11_resources,
1200 },
1201 {
1202 .name = "wm831x-on",
1203 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1204 .resources = wm831x_on_resources,
1205 },
1206 {
1207 .name = "wm831x-power",
1208 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1209 .resources = wm831x_power_resources,
1210 },
1211 {
1212 .name = "wm831x-rtc",
1213 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
1214 .resources = wm831x_rtc_resources,
1215 },
1216 {
1217 .name = "wm831x-status",
1218 .id = 1,
1219 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1220 .resources = wm831x_status1_resources,
1221 },
1222 {
1223 .name = "wm831x-status",
1224 .id = 2,
1225 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1226 .resources = wm831x_status2_resources,
1227 },
1228 {
1229 .name = "wm831x-touch",
1230 .num_resources = ARRAY_SIZE(wm831x_touch_resources),
1231 .resources = wm831x_touch_resources,
1232 },
1233 {
1234 .name = "wm831x-watchdog",
1235 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1236 .resources = wm831x_wdt_resources,
1237 },
1238};
1239
1240static struct mfd_cell backlight_devs[] = {
1241 {
1242 .name = "wm831x-backlight",
1243 },
1244};
1245
1246/*
1247 * Instantiate the generic non-control parts of the device.
1248 */
1249static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq)
1250{
1251 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
1252 int rev;
1253 enum wm831x_parent parent;
1254 int ret;
1255
1256 mutex_init(&wm831x->io_lock);
1257 mutex_init(&wm831x->key_lock);
1258 mutex_init(&wm831x->auxadc_lock);
1259 dev_set_drvdata(wm831x->dev, wm831x);
1260
1261 ret = wm831x_reg_read(wm831x, WM831X_PARENT_ID);
1262 if (ret < 0) {
1263 dev_err(wm831x->dev, "Failed to read parent ID: %d\n", ret);
1264 goto err;
1265 }
1266 if (ret != 0x6204) {
1267 dev_err(wm831x->dev, "Device is not a WM831x: ID %x\n", ret);
1268 ret = -EINVAL;
1269 goto err;
1270 }
1271
1272 ret = wm831x_reg_read(wm831x, WM831X_REVISION);
1273 if (ret < 0) {
1274 dev_err(wm831x->dev, "Failed to read revision: %d\n", ret);
1275 goto err;
1276 }
1277 rev = (ret & WM831X_PARENT_REV_MASK) >> WM831X_PARENT_REV_SHIFT;
1278
1279 ret = wm831x_reg_read(wm831x, WM831X_RESET_ID);
1280 if (ret < 0) {
1281 dev_err(wm831x->dev, "Failed to read device ID: %d\n", ret);
1282 goto err;
1283 }
1284
1285 switch (ret) {
1286 case 0x8310:
1287 parent = WM8310;
1288 switch (rev) {
1289 case 0:
1290 dev_info(wm831x->dev, "WM8310 revision %c\n",
1291 'A' + rev);
1292 break;
1293 }
1294 break;
1295
1296 case 0x8311:
1297 parent = WM8311;
1298 switch (rev) {
1299 case 0:
1300 dev_info(wm831x->dev, "WM8311 revision %c\n",
1301 'A' + rev);
1302 break;
1303 }
1304 break;
1305
1306 case 0x8312:
1307 parent = WM8312;
1308 switch (rev) {
1309 case 0:
1310 dev_info(wm831x->dev, "WM8312 revision %c\n",
1311 'A' + rev);
1312 break;
1313 }
1314 break;
1315
1316 case 0:
1317 /* Some engineering samples do not have the ID set,
1318 * rely on the device being registered correctly.
1319 * This will need revisiting for future devices with
1320 * multiple dies.
1321 */
1322 parent = id;
1323 switch (rev) {
1324 case 0:
1325 dev_info(wm831x->dev, "WM831%d ES revision %c\n",
1326 parent, 'A' + rev);
1327 break;
1328 }
1329 break;
1330
1331 default:
1332 dev_err(wm831x->dev, "Unknown WM831x device %04x\n", ret);
1333 ret = -EINVAL;
1334 goto err;
1335 }
1336
1337 /* This will need revisiting in future but is OK for all
1338 * current parts.
1339 */
1340 if (parent != id)
1341 dev_warn(wm831x->dev, "Device was registered as a WM831%lu\n",
1342 id);
1343
1344 /* Bootstrap the user key */
1345 ret = wm831x_reg_read(wm831x, WM831X_SECURITY_KEY);
1346 if (ret < 0) {
1347 dev_err(wm831x->dev, "Failed to read security key: %d\n", ret);
1348 goto err;
1349 }
1350 if (ret != 0) {
1351 dev_warn(wm831x->dev, "Security key had non-zero value %x\n",
1352 ret);
1353 wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
1354 }
1355 wm831x->locked = 1;
1356
1357 if (pdata && pdata->pre_init) {
1358 ret = pdata->pre_init(wm831x);
1359 if (ret != 0) {
1360 dev_err(wm831x->dev, "pre_init() failed: %d\n", ret);
1361 goto err;
1362 }
1363 }
1364
1365 ret = wm831x_irq_init(wm831x, irq);
1366 if (ret != 0)
1367 goto err;
1368
1369 /* The core device is up, instantiate the subdevices. */
1370 switch (parent) {
1371 case WM8310:
1372 ret = mfd_add_devices(wm831x->dev, -1,
1373 wm8310_devs, ARRAY_SIZE(wm8310_devs),
1374 NULL, 0);
1375 break;
1376
1377 case WM8311:
1378 ret = mfd_add_devices(wm831x->dev, -1,
1379 wm8311_devs, ARRAY_SIZE(wm8311_devs),
1380 NULL, 0);
1381 break;
1382
1383 case WM8312:
1384 ret = mfd_add_devices(wm831x->dev, -1,
1385 wm8312_devs, ARRAY_SIZE(wm8312_devs),
1386 NULL, 0);
1387 break;
1388
1389 default:
1390 /* If this happens the bus probe function is buggy */
1391 BUG();
1392 }
1393
1394 if (ret != 0) {
1395 dev_err(wm831x->dev, "Failed to add children\n");
1396 goto err_irq;
1397 }
1398
1399 if (pdata && pdata->backlight) {
1400 /* Treat errors as non-critical */
1401 ret = mfd_add_devices(wm831x->dev, -1, backlight_devs,
1402 ARRAY_SIZE(backlight_devs), NULL, 0);
1403 if (ret < 0)
1404 dev_err(wm831x->dev, "Failed to add backlight: %d\n",
1405 ret);
1406 }
1407
1408 wm831x_otp_init(wm831x);
1409
1410 if (pdata && pdata->post_init) {
1411 ret = pdata->post_init(wm831x);
1412 if (ret != 0) {
1413 dev_err(wm831x->dev, "post_init() failed: %d\n", ret);
1414 goto err_irq;
1415 }
1416 }
1417
1418 return 0;
1419
1420err_irq:
1421 wm831x_irq_exit(wm831x);
1422err:
1423 mfd_remove_devices(wm831x->dev);
1424 kfree(wm831x);
1425 return ret;
1426}
1427
1428static void wm831x_device_exit(struct wm831x *wm831x)
1429{
1430 wm831x_otp_exit(wm831x);
1431 mfd_remove_devices(wm831x->dev);
1432 wm831x_irq_exit(wm831x);
1433 kfree(wm831x);
1434}
1435
1436static int wm831x_i2c_read_device(struct wm831x *wm831x, unsigned short reg,
1437 int bytes, void *dest)
1438{
1439 struct i2c_client *i2c = wm831x->control_data;
1440 int ret;
1441 u16 r = cpu_to_be16(reg);
1442
1443 ret = i2c_master_send(i2c, (unsigned char *)&r, 2);
1444 if (ret < 0)
1445 return ret;
1446 if (ret != 2)
1447 return -EIO;
1448
1449 ret = i2c_master_recv(i2c, dest, bytes);
1450 if (ret < 0)
1451 return ret;
1452 if (ret != bytes)
1453 return -EIO;
1454 return 0;
1455}
1456
1457/* Currently we allocate the write buffer on the stack; this is OK for
1458 * small writes - if we need to do large writes this will need to be
1459 * revised.
1460 */
1461static int wm831x_i2c_write_device(struct wm831x *wm831x, unsigned short reg,
1462 int bytes, void *src)
1463{
1464 struct i2c_client *i2c = wm831x->control_data;
1465 unsigned char msg[bytes + 2];
1466 int ret;
1467
1468 reg = cpu_to_be16(reg);
1469 memcpy(&msg[0], &reg, 2);
1470 memcpy(&msg[2], src, bytes);
1471
1472 ret = i2c_master_send(i2c, msg, bytes + 2);
1473 if (ret < 0)
1474 return ret;
1475 if (ret < bytes + 2)
1476 return -EIO;
1477
1478 return 0;
1479}
1480
1481static int wm831x_i2c_probe(struct i2c_client *i2c,
1482 const struct i2c_device_id *id)
1483{
1484 struct wm831x *wm831x;
1485
1486 wm831x = kzalloc(sizeof(struct wm831x), GFP_KERNEL);
1487 if (wm831x == NULL) {
1488 kfree(i2c);
1489 return -ENOMEM;
1490 }
1491
1492 i2c_set_clientdata(i2c, wm831x);
1493 wm831x->dev = &i2c->dev;
1494 wm831x->control_data = i2c;
1495 wm831x->read_dev = wm831x_i2c_read_device;
1496 wm831x->write_dev = wm831x_i2c_write_device;
1497
1498 return wm831x_device_init(wm831x, id->driver_data, i2c->irq);
1499}
1500
1501static int wm831x_i2c_remove(struct i2c_client *i2c)
1502{
1503 struct wm831x *wm831x = i2c_get_clientdata(i2c);
1504
1505 wm831x_device_exit(wm831x);
1506
1507 return 0;
1508}
1509
1510static const struct i2c_device_id wm831x_i2c_id[] = {
1511 { "wm8310", WM8310 },
1512 { "wm8311", WM8311 },
1513 { "wm8312", WM8312 },
1514 { }
1515};
1516MODULE_DEVICE_TABLE(i2c, wm831x_i2c_id);
1517
1518
1519static struct i2c_driver wm831x_i2c_driver = {
1520 .driver = {
1521 .name = "wm831x",
1522 .owner = THIS_MODULE,
1523 },
1524 .probe = wm831x_i2c_probe,
1525 .remove = wm831x_i2c_remove,
1526 .id_table = wm831x_i2c_id,
1527};
1528
1529static int __init wm831x_i2c_init(void)
1530{
1531 int ret;
1532
1533 ret = i2c_add_driver(&wm831x_i2c_driver);
1534 if (ret != 0)
1535 pr_err("Failed to register wm831x I2C driver: %d\n", ret);
1536
1537 return ret;
1538}
1539subsys_initcall(wm831x_i2c_init);
1540
1541static void __exit wm831x_i2c_exit(void)
1542{
1543 i2c_del_driver(&wm831x_i2c_driver);
1544}
1545module_exit(wm831x_i2c_exit);
1546
1547MODULE_DESCRIPTION("I2C support for the WM831X AudioPlus PMIC");
1548MODULE_LICENSE("GPL");
1549MODULE_AUTHOR("Mark Brown");
diff --git a/drivers/mfd/wm831x-irq.c b/drivers/mfd/wm831x-irq.c
new file mode 100644
index 000000000000..d3015dfb9134
--- /dev/null
+++ b/drivers/mfd/wm831x-irq.c
@@ -0,0 +1,559 @@
1/*
2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/mfd/core.h>
19#include <linux/interrupt.h>
20
21#include <linux/mfd/wm831x/core.h>
22#include <linux/mfd/wm831x/pdata.h>
23#include <linux/mfd/wm831x/irq.h>
24
25#include <linux/delay.h>
26
27/*
28 * Since generic IRQs don't currently support interrupt controllers on
29 * interrupt driven buses we don't use genirq but instead provide an
30 * interface that looks very much like the standard ones. This leads
31 * to some bodges, including storing interrupt handler information in
32 * the static irq_data table we use to look up the data for individual
33 * interrupts, but hopefully won't last too long.
34 */
35
36struct wm831x_irq_data {
37 int primary;
38 int reg;
39 int mask;
40 irq_handler_t handler;
41 void *handler_data;
42};
43
44static struct wm831x_irq_data wm831x_irqs[] = {
45 [WM831X_IRQ_TEMP_THW] = {
46 .primary = WM831X_TEMP_INT,
47 .reg = 1,
48 .mask = WM831X_TEMP_THW_EINT,
49 },
50 [WM831X_IRQ_GPIO_1] = {
51 .primary = WM831X_GP_INT,
52 .reg = 5,
53 .mask = WM831X_GP1_EINT,
54 },
55 [WM831X_IRQ_GPIO_2] = {
56 .primary = WM831X_GP_INT,
57 .reg = 5,
58 .mask = WM831X_GP2_EINT,
59 },
60 [WM831X_IRQ_GPIO_3] = {
61 .primary = WM831X_GP_INT,
62 .reg = 5,
63 .mask = WM831X_GP3_EINT,
64 },
65 [WM831X_IRQ_GPIO_4] = {
66 .primary = WM831X_GP_INT,
67 .reg = 5,
68 .mask = WM831X_GP4_EINT,
69 },
70 [WM831X_IRQ_GPIO_5] = {
71 .primary = WM831X_GP_INT,
72 .reg = 5,
73 .mask = WM831X_GP5_EINT,
74 },
75 [WM831X_IRQ_GPIO_6] = {
76 .primary = WM831X_GP_INT,
77 .reg = 5,
78 .mask = WM831X_GP6_EINT,
79 },
80 [WM831X_IRQ_GPIO_7] = {
81 .primary = WM831X_GP_INT,
82 .reg = 5,
83 .mask = WM831X_GP7_EINT,
84 },
85 [WM831X_IRQ_GPIO_8] = {
86 .primary = WM831X_GP_INT,
87 .reg = 5,
88 .mask = WM831X_GP8_EINT,
89 },
90 [WM831X_IRQ_GPIO_9] = {
91 .primary = WM831X_GP_INT,
92 .reg = 5,
93 .mask = WM831X_GP9_EINT,
94 },
95 [WM831X_IRQ_GPIO_10] = {
96 .primary = WM831X_GP_INT,
97 .reg = 5,
98 .mask = WM831X_GP10_EINT,
99 },
100 [WM831X_IRQ_GPIO_11] = {
101 .primary = WM831X_GP_INT,
102 .reg = 5,
103 .mask = WM831X_GP11_EINT,
104 },
105 [WM831X_IRQ_GPIO_12] = {
106 .primary = WM831X_GP_INT,
107 .reg = 5,
108 .mask = WM831X_GP12_EINT,
109 },
110 [WM831X_IRQ_GPIO_13] = {
111 .primary = WM831X_GP_INT,
112 .reg = 5,
113 .mask = WM831X_GP13_EINT,
114 },
115 [WM831X_IRQ_GPIO_14] = {
116 .primary = WM831X_GP_INT,
117 .reg = 5,
118 .mask = WM831X_GP14_EINT,
119 },
120 [WM831X_IRQ_GPIO_15] = {
121 .primary = WM831X_GP_INT,
122 .reg = 5,
123 .mask = WM831X_GP15_EINT,
124 },
125 [WM831X_IRQ_GPIO_16] = {
126 .primary = WM831X_GP_INT,
127 .reg = 5,
128 .mask = WM831X_GP16_EINT,
129 },
130 [WM831X_IRQ_ON] = {
131 .primary = WM831X_ON_PIN_INT,
132 .reg = 1,
133 .mask = WM831X_ON_PIN_EINT,
134 },
135 [WM831X_IRQ_PPM_SYSLO] = {
136 .primary = WM831X_PPM_INT,
137 .reg = 1,
138 .mask = WM831X_PPM_SYSLO_EINT,
139 },
140 [WM831X_IRQ_PPM_PWR_SRC] = {
141 .primary = WM831X_PPM_INT,
142 .reg = 1,
143 .mask = WM831X_PPM_PWR_SRC_EINT,
144 },
145 [WM831X_IRQ_PPM_USB_CURR] = {
146 .primary = WM831X_PPM_INT,
147 .reg = 1,
148 .mask = WM831X_PPM_USB_CURR_EINT,
149 },
150 [WM831X_IRQ_WDOG_TO] = {
151 .primary = WM831X_WDOG_INT,
152 .reg = 1,
153 .mask = WM831X_WDOG_TO_EINT,
154 },
155 [WM831X_IRQ_RTC_PER] = {
156 .primary = WM831X_RTC_INT,
157 .reg = 1,
158 .mask = WM831X_RTC_PER_EINT,
159 },
160 [WM831X_IRQ_RTC_ALM] = {
161 .primary = WM831X_RTC_INT,
162 .reg = 1,
163 .mask = WM831X_RTC_ALM_EINT,
164 },
165 [WM831X_IRQ_CHG_BATT_HOT] = {
166 .primary = WM831X_CHG_INT,
167 .reg = 2,
168 .mask = WM831X_CHG_BATT_HOT_EINT,
169 },
170 [WM831X_IRQ_CHG_BATT_COLD] = {
171 .primary = WM831X_CHG_INT,
172 .reg = 2,
173 .mask = WM831X_CHG_BATT_COLD_EINT,
174 },
175 [WM831X_IRQ_CHG_BATT_FAIL] = {
176 .primary = WM831X_CHG_INT,
177 .reg = 2,
178 .mask = WM831X_CHG_BATT_FAIL_EINT,
179 },
180 [WM831X_IRQ_CHG_OV] = {
181 .primary = WM831X_CHG_INT,
182 .reg = 2,
183 .mask = WM831X_CHG_OV_EINT,
184 },
185 [WM831X_IRQ_CHG_END] = {
186 .primary = WM831X_CHG_INT,
187 .reg = 2,
188 .mask = WM831X_CHG_END_EINT,
189 },
190 [WM831X_IRQ_CHG_TO] = {
191 .primary = WM831X_CHG_INT,
192 .reg = 2,
193 .mask = WM831X_CHG_TO_EINT,
194 },
195 [WM831X_IRQ_CHG_MODE] = {
196 .primary = WM831X_CHG_INT,
197 .reg = 2,
198 .mask = WM831X_CHG_MODE_EINT,
199 },
200 [WM831X_IRQ_CHG_START] = {
201 .primary = WM831X_CHG_INT,
202 .reg = 2,
203 .mask = WM831X_CHG_START_EINT,
204 },
205 [WM831X_IRQ_TCHDATA] = {
206 .primary = WM831X_TCHDATA_INT,
207 .reg = 1,
208 .mask = WM831X_TCHDATA_EINT,
209 },
210 [WM831X_IRQ_TCHPD] = {
211 .primary = WM831X_TCHPD_INT,
212 .reg = 1,
213 .mask = WM831X_TCHPD_EINT,
214 },
215 [WM831X_IRQ_AUXADC_DATA] = {
216 .primary = WM831X_AUXADC_INT,
217 .reg = 1,
218 .mask = WM831X_AUXADC_DATA_EINT,
219 },
220 [WM831X_IRQ_AUXADC_DCOMP1] = {
221 .primary = WM831X_AUXADC_INT,
222 .reg = 1,
223 .mask = WM831X_AUXADC_DCOMP1_EINT,
224 },
225 [WM831X_IRQ_AUXADC_DCOMP2] = {
226 .primary = WM831X_AUXADC_INT,
227 .reg = 1,
228 .mask = WM831X_AUXADC_DCOMP2_EINT,
229 },
230 [WM831X_IRQ_AUXADC_DCOMP3] = {
231 .primary = WM831X_AUXADC_INT,
232 .reg = 1,
233 .mask = WM831X_AUXADC_DCOMP3_EINT,
234 },
235 [WM831X_IRQ_AUXADC_DCOMP4] = {
236 .primary = WM831X_AUXADC_INT,
237 .reg = 1,
238 .mask = WM831X_AUXADC_DCOMP4_EINT,
239 },
240 [WM831X_IRQ_CS1] = {
241 .primary = WM831X_CS_INT,
242 .reg = 2,
243 .mask = WM831X_CS1_EINT,
244 },
245 [WM831X_IRQ_CS2] = {
246 .primary = WM831X_CS_INT,
247 .reg = 2,
248 .mask = WM831X_CS2_EINT,
249 },
250 [WM831X_IRQ_HC_DC1] = {
251 .primary = WM831X_HC_INT,
252 .reg = 4,
253 .mask = WM831X_HC_DC1_EINT,
254 },
255 [WM831X_IRQ_HC_DC2] = {
256 .primary = WM831X_HC_INT,
257 .reg = 4,
258 .mask = WM831X_HC_DC2_EINT,
259 },
260 [WM831X_IRQ_UV_LDO1] = {
261 .primary = WM831X_UV_INT,
262 .reg = 3,
263 .mask = WM831X_UV_LDO1_EINT,
264 },
265 [WM831X_IRQ_UV_LDO2] = {
266 .primary = WM831X_UV_INT,
267 .reg = 3,
268 .mask = WM831X_UV_LDO2_EINT,
269 },
270 [WM831X_IRQ_UV_LDO3] = {
271 .primary = WM831X_UV_INT,
272 .reg = 3,
273 .mask = WM831X_UV_LDO3_EINT,
274 },
275 [WM831X_IRQ_UV_LDO4] = {
276 .primary = WM831X_UV_INT,
277 .reg = 3,
278 .mask = WM831X_UV_LDO4_EINT,
279 },
280 [WM831X_IRQ_UV_LDO5] = {
281 .primary = WM831X_UV_INT,
282 .reg = 3,
283 .mask = WM831X_UV_LDO5_EINT,
284 },
285 [WM831X_IRQ_UV_LDO6] = {
286 .primary = WM831X_UV_INT,
287 .reg = 3,
288 .mask = WM831X_UV_LDO6_EINT,
289 },
290 [WM831X_IRQ_UV_LDO7] = {
291 .primary = WM831X_UV_INT,
292 .reg = 3,
293 .mask = WM831X_UV_LDO7_EINT,
294 },
295 [WM831X_IRQ_UV_LDO8] = {
296 .primary = WM831X_UV_INT,
297 .reg = 3,
298 .mask = WM831X_UV_LDO8_EINT,
299 },
300 [WM831X_IRQ_UV_LDO9] = {
301 .primary = WM831X_UV_INT,
302 .reg = 3,
303 .mask = WM831X_UV_LDO9_EINT,
304 },
305 [WM831X_IRQ_UV_LDO10] = {
306 .primary = WM831X_UV_INT,
307 .reg = 3,
308 .mask = WM831X_UV_LDO10_EINT,
309 },
310 [WM831X_IRQ_UV_DC1] = {
311 .primary = WM831X_UV_INT,
312 .reg = 4,
313 .mask = WM831X_UV_DC1_EINT,
314 },
315 [WM831X_IRQ_UV_DC2] = {
316 .primary = WM831X_UV_INT,
317 .reg = 4,
318 .mask = WM831X_UV_DC2_EINT,
319 },
320 [WM831X_IRQ_UV_DC3] = {
321 .primary = WM831X_UV_INT,
322 .reg = 4,
323 .mask = WM831X_UV_DC3_EINT,
324 },
325 [WM831X_IRQ_UV_DC4] = {
326 .primary = WM831X_UV_INT,
327 .reg = 4,
328 .mask = WM831X_UV_DC4_EINT,
329 },
330};
331
332static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
333{
334 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
335}
336
337static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
338{
339 return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
340}
341
342static void __wm831x_enable_irq(struct wm831x *wm831x, int irq)
343{
344 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
345
346 wm831x->irq_masks[irq_data->reg - 1] &= ~irq_data->mask;
347 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
348 wm831x->irq_masks[irq_data->reg - 1]);
349}
350
351void wm831x_enable_irq(struct wm831x *wm831x, int irq)
352{
353 mutex_lock(&wm831x->irq_lock);
354 __wm831x_enable_irq(wm831x, irq);
355 mutex_unlock(&wm831x->irq_lock);
356}
357EXPORT_SYMBOL_GPL(wm831x_enable_irq);
358
359static void __wm831x_disable_irq(struct wm831x *wm831x, int irq)
360{
361 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
362
363 wm831x->irq_masks[irq_data->reg - 1] |= irq_data->mask;
364 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
365 wm831x->irq_masks[irq_data->reg - 1]);
366}
367
368void wm831x_disable_irq(struct wm831x *wm831x, int irq)
369{
370 mutex_lock(&wm831x->irq_lock);
371 __wm831x_disable_irq(wm831x, irq);
372 mutex_unlock(&wm831x->irq_lock);
373}
374EXPORT_SYMBOL_GPL(wm831x_disable_irq);
375
376int wm831x_request_irq(struct wm831x *wm831x,
377 unsigned int irq, irq_handler_t handler,
378 unsigned long flags, const char *name,
379 void *dev)
380{
381 int ret = 0;
382
383 if (irq < 0 || irq >= WM831X_NUM_IRQS)
384 return -EINVAL;
385
386 mutex_lock(&wm831x->irq_lock);
387
388 if (wm831x_irqs[irq].handler) {
389 dev_err(wm831x->dev, "Already have handler for IRQ %d\n", irq);
390 ret = -EINVAL;
391 goto out;
392 }
393
394 wm831x_irqs[irq].handler = handler;
395 wm831x_irqs[irq].handler_data = dev;
396
397 __wm831x_enable_irq(wm831x, irq);
398
399out:
400 mutex_unlock(&wm831x->irq_lock);
401
402 return ret;
403}
404EXPORT_SYMBOL_GPL(wm831x_request_irq);
405
406void wm831x_free_irq(struct wm831x *wm831x, unsigned int irq, void *data)
407{
408 if (irq < 0 || irq >= WM831X_NUM_IRQS)
409 return;
410
411 mutex_lock(&wm831x->irq_lock);
412
413 wm831x_irqs[irq].handler = NULL;
414 wm831x_irqs[irq].handler_data = NULL;
415
416 __wm831x_disable_irq(wm831x, irq);
417
418 mutex_unlock(&wm831x->irq_lock);
419}
420EXPORT_SYMBOL_GPL(wm831x_free_irq);
421
422
423static void wm831x_handle_irq(struct wm831x *wm831x, int irq, int status)
424{
425 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
426
427 if (irq_data->handler) {
428 irq_data->handler(irq, irq_data->handler_data);
429 wm831x_reg_write(wm831x, irq_data_to_status_reg(irq_data),
430 irq_data->mask);
431 } else {
432 dev_err(wm831x->dev, "Unhandled IRQ %d, masking\n", irq);
433 __wm831x_disable_irq(wm831x, irq);
434 }
435}
436
437/* Main interrupt handling occurs in a workqueue since we need
438 * interrupts enabled to interact with the chip. */
439static void wm831x_irq_worker(struct work_struct *work)
440{
441 struct wm831x *wm831x = container_of(work, struct wm831x, irq_work);
442 unsigned int i;
443 int primary;
444 int status_regs[5];
445 int read[5] = { 0 };
446 int *status;
447
448 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
449 if (primary < 0) {
450 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
451 primary);
452 goto out;
453 }
454
455 mutex_lock(&wm831x->irq_lock);
456
457 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
458 int offset = wm831x_irqs[i].reg - 1;
459
460 if (!(primary & wm831x_irqs[i].primary))
461 continue;
462
463 status = &status_regs[offset];
464
465 /* Hopefully there should only be one register to read
466 * each time otherwise we ought to do a block read. */
467 if (!read[offset]) {
468 *status = wm831x_reg_read(wm831x,
469 irq_data_to_status_reg(&wm831x_irqs[i]));
470 if (*status < 0) {
471 dev_err(wm831x->dev,
472 "Failed to read IRQ status: %d\n",
473 *status);
474 goto out_lock;
475 }
476
477 /* Mask out the disabled IRQs */
478 *status &= ~wm831x->irq_masks[offset];
479 read[offset] = 1;
480 }
481
482 if (*status & wm831x_irqs[i].mask)
483 wm831x_handle_irq(wm831x, i, *status);
484 }
485
486out_lock:
487 mutex_unlock(&wm831x->irq_lock);
488out:
489 enable_irq(wm831x->irq);
490}
491
492
493static irqreturn_t wm831x_cpu_irq(int irq, void *data)
494{
495 struct wm831x *wm831x = data;
496
497 /* Shut the interrupt to the CPU up and schedule the actual
498 * handler; we can't check that the IRQ is asserted. */
499 disable_irq_nosync(irq);
500
501 queue_work(wm831x->irq_wq, &wm831x->irq_work);
502
503 return IRQ_HANDLED;
504}
505
506int wm831x_irq_init(struct wm831x *wm831x, int irq)
507{
508 int i, ret;
509
510 if (!irq) {
511 dev_warn(wm831x->dev,
512 "No interrupt specified - functionality limited\n");
513 return 0;
514 }
515
516
517 wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq");
518 if (!wm831x->irq_wq) {
519 dev_err(wm831x->dev, "Failed to allocate IRQ worker\n");
520 return -ESRCH;
521 }
522
523 wm831x->irq = irq;
524 mutex_init(&wm831x->irq_lock);
525 INIT_WORK(&wm831x->irq_work, wm831x_irq_worker);
526
527 /* Mask the individual interrupt sources */
528 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks); i++) {
529 wm831x->irq_masks[i] = 0xffff;
530 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
531 0xffff);
532 }
533
534 /* Enable top level interrupts, we mask at secondary level */
535 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
536
537 /* We're good to go. We set IRQF_SHARED since there's a
538 * chance the driver will interoperate with another driver but
539 * the need to disable the IRQ while handing via I2C/SPI means
540 * that this may break and performance will be impacted. If
541 * this does happen it's a hardware design issue and the only
542 * other alternative would be polling.
543 */
544 ret = request_irq(irq, wm831x_cpu_irq, IRQF_TRIGGER_LOW | IRQF_SHARED,
545 "wm831x", wm831x);
546 if (ret != 0) {
547 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
548 irq, ret);
549 return ret;
550 }
551
552 return 0;
553}
554
555void wm831x_irq_exit(struct wm831x *wm831x)
556{
557 if (wm831x->irq)
558 free_irq(wm831x->irq, wm831x);
559}
diff --git a/drivers/mfd/wm831x-otp.c b/drivers/mfd/wm831x-otp.c
new file mode 100644
index 000000000000..f742745ff354
--- /dev/null
+++ b/drivers/mfd/wm831x-otp.c
@@ -0,0 +1,83 @@
1/*
2 * wm831x-otp.c -- OTP for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/bcd.h>
19#include <linux/delay.h>
20#include <linux/mfd/core.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/otp.h>
24
25/* In bytes */
26#define WM831X_UNIQUE_ID_LEN 16
27
28/* Read the unique ID from the chip into id */
29static int wm831x_unique_id_read(struct wm831x *wm831x, char *id)
30{
31 int i, val;
32
33 for (i = 0; i < WM831X_UNIQUE_ID_LEN / 2; i++) {
34 val = wm831x_reg_read(wm831x, WM831X_UNIQUE_ID_1 + i);
35 if (val < 0)
36 return val;
37
38 id[i * 2] = (val >> 8) & 0xff;
39 id[(i * 2) + 1] = val & 0xff;
40 }
41
42 return 0;
43}
44
45static ssize_t wm831x_unique_id_show(struct device *dev,
46 struct device_attribute *attr, char *buf)
47{
48 struct wm831x *wm831x = dev_get_drvdata(dev);
49 int i, rval;
50 char id[WM831X_UNIQUE_ID_LEN];
51 ssize_t ret = 0;
52
53 rval = wm831x_unique_id_read(wm831x, id);
54 if (rval < 0)
55 return 0;
56
57 for (i = 0; i < WM831X_UNIQUE_ID_LEN; i++)
58 ret += sprintf(&buf[ret], "%02x", buf[i]);
59
60 ret += sprintf(&buf[ret], "\n");
61
62 return ret;
63}
64
65static DEVICE_ATTR(unique_id, 0444, wm831x_unique_id_show, NULL);
66
67int wm831x_otp_init(struct wm831x *wm831x)
68{
69 int ret;
70
71 ret = device_create_file(wm831x->dev, &dev_attr_unique_id);
72 if (ret != 0)
73 dev_err(wm831x->dev, "Unique ID attribute not created: %d\n",
74 ret);
75
76 return ret;
77}
78
79void wm831x_otp_exit(struct wm831x *wm831x)
80{
81 device_remove_file(wm831x->dev, &dev_attr_unique_id);
82}
83
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index fe24079387c5..ba27c9dc1ad3 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -353,15 +353,15 @@ static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
353} 353}
354 354
355/* 355/*
356 * wm8350_irq_worker actually handles the interrupts. Since all 356 * This is a threaded IRQ handler so can access I2C/SPI. Since all
357 * interrupts are clear on read the IRQ line will be reasserted and 357 * interrupts are clear on read the IRQ line will be reasserted and
358 * the physical IRQ will be handled again if another interrupt is 358 * the physical IRQ will be handled again if another interrupt is
359 * asserted while we run - in the normal course of events this is a 359 * asserted while we run - in the normal course of events this is a
360 * rare occurrence so we save I2C/SPI reads. 360 * rare occurrence so we save I2C/SPI reads.
361 */ 361 */
362static void wm8350_irq_worker(struct work_struct *work) 362static irqreturn_t wm8350_irq(int irq, void *data)
363{ 363{
364 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work); 364 struct wm8350 *wm8350 = data;
365 u16 level_one, status1, status2, comp; 365 u16 level_one, status1, status2, comp;
366 366
367 /* TODO: Use block reads to improve performance? */ 367 /* TODO: Use block reads to improve performance? */
@@ -552,16 +552,6 @@ static void wm8350_irq_worker(struct work_struct *work)
552 } 552 }
553 } 553 }
554 554
555 enable_irq(wm8350->chip_irq);
556}
557
558static irqreturn_t wm8350_irq(int irq, void *data)
559{
560 struct wm8350 *wm8350 = data;
561
562 disable_irq_nosync(irq);
563 schedule_work(&wm8350->irq_work);
564
565 return IRQ_HANDLED; 555 return IRQ_HANDLED;
566} 556}
567 557
@@ -1428,9 +1418,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1428 1418
1429 mutex_init(&wm8350->auxadc_mutex); 1419 mutex_init(&wm8350->auxadc_mutex);
1430 mutex_init(&wm8350->irq_mutex); 1420 mutex_init(&wm8350->irq_mutex);
1431 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1432 if (irq) { 1421 if (irq) {
1433 int flags = 0; 1422 int flags = IRQF_ONESHOT;
1434 1423
1435 if (pdata && pdata->irq_high) { 1424 if (pdata && pdata->irq_high) {
1436 flags |= IRQF_TRIGGER_HIGH; 1425 flags |= IRQF_TRIGGER_HIGH;
@@ -1444,8 +1433,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1444 WM8350_IRQ_POL); 1433 WM8350_IRQ_POL);
1445 } 1434 }
1446 1435
1447 ret = request_irq(irq, wm8350_irq, flags, 1436 ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
1448 "wm8350", wm8350); 1437 "wm8350", wm8350);
1449 if (ret != 0) { 1438 if (ret != 0) {
1450 dev_err(wm8350->dev, "Failed to request IRQ: %d\n", 1439 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1451 ret); 1440 ret);
@@ -1472,6 +1461,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1472 &(wm8350->codec.pdev)); 1461 &(wm8350->codec.pdev));
1473 wm8350_client_dev_register(wm8350, "wm8350-gpio", 1462 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1474 &(wm8350->gpio.pdev)); 1463 &(wm8350->gpio.pdev));
1464 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
1465 &(wm8350->hwmon.pdev));
1475 wm8350_client_dev_register(wm8350, "wm8350-power", 1466 wm8350_client_dev_register(wm8350, "wm8350-power",
1476 &(wm8350->power.pdev)); 1467 &(wm8350->power.pdev));
1477 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev)); 1468 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
@@ -1498,11 +1489,11 @@ void wm8350_device_exit(struct wm8350 *wm8350)
1498 platform_device_unregister(wm8350->wdt.pdev); 1489 platform_device_unregister(wm8350->wdt.pdev);
1499 platform_device_unregister(wm8350->rtc.pdev); 1490 platform_device_unregister(wm8350->rtc.pdev);
1500 platform_device_unregister(wm8350->power.pdev); 1491 platform_device_unregister(wm8350->power.pdev);
1492 platform_device_unregister(wm8350->hwmon.pdev);
1501 platform_device_unregister(wm8350->gpio.pdev); 1493 platform_device_unregister(wm8350->gpio.pdev);
1502 platform_device_unregister(wm8350->codec.pdev); 1494 platform_device_unregister(wm8350->codec.pdev);
1503 1495
1504 free_irq(wm8350->chip_irq, wm8350); 1496 free_irq(wm8350->chip_irq, wm8350);
1505 flush_work(&wm8350->irq_work);
1506 kfree(wm8350->reg_cache); 1497 kfree(wm8350->reg_cache);
1507} 1498}
1508EXPORT_SYMBOL_GPL(wm8350_device_exit); 1499EXPORT_SYMBOL_GPL(wm8350_device_exit);
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index f4317798e47c..2dc42bbf6fe9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -82,6 +82,13 @@ config REGULATOR_TWL4030
82 This driver supports the voltage regulators provided by 82 This driver supports the voltage regulators provided by
83 this family of companion chips. 83 this family of companion chips.
84 84
85config REGULATOR_WM831X
86 tristate "Wolfson Microelcronics WM831x PMIC regulators"
87 depends on MFD_WM831X
88 help
89 Support the voltage and current regulators of the WM831x series
90 of PMIC devices.
91
85config REGULATOR_WM8350 92config REGULATOR_WM8350
86 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" 93 tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC"
87 depends on MFD_WM8350 94 depends on MFD_WM8350
@@ -117,4 +124,28 @@ config REGULATOR_LP3971
117 Say Y here to support the voltage regulators and convertors 124 Say Y here to support the voltage regulators and convertors
118 on National Semiconductors LP3971 PMIC 125 on National Semiconductors LP3971 PMIC
119 126
127config REGULATOR_PCAP
128 tristate "PCAP2 regulator driver"
129 depends on EZX_PCAP
130 help
131 This driver provides support for the voltage regulators of the
132 PCAP2 PMIC.
133
134config REGULATOR_MC13783
135 tristate "Support regulators on Freescale MC13783 PMIC"
136 depends on MFD_MC13783
137 help
138 Say y here to support the regulators found on the Freescale MC13783
139 PMIC.
140
141config REGULATOR_AB3100
142 tristate "ST-Ericsson AB3100 Regulator functions"
143 depends on AB3100_CORE
144 default y if AB3100_CORE
145 help
146 These regulators correspond to functionality in the
147 AB3100 analog baseband dealing with power regulators
148 for the system.
149
120endif 150endif
151
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4d762c4cccfd..768b3316d6eb 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -12,9 +12,15 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
12obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o 12obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o 13obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o 14obj-$(CONFIG_REGULATOR_TWL4030) += twl4030-regulator.o
15obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
16obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o
17obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
15obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o 18obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
16obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o 19obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
17obj-$(CONFIG_REGULATOR_DA903X) += da903x.o 20obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
18obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o 21obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
22obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
23obj-$(CONFIG_REGULATOR_MC13783) += mc13783.o
24obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
19 25
20ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG 26ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c
new file mode 100644
index 000000000000..49aeee823a25
--- /dev/null
+++ b/drivers/regulator/ab3100.c
@@ -0,0 +1,700 @@
1/*
2 * drivers/regulator/ab3100.c
3 *
4 * Copyright (C) 2008-2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * Low-level control of the AB3100 IC Low Dropout (LDO)
7 * regulators, external regulator and buck converter
8 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/driver.h>
19#include <linux/mfd/ab3100.h>
20
21/* LDO registers and some handy masking definitions for AB3100 */
22#define AB3100_LDO_A 0x40
23#define AB3100_LDO_C 0x41
24#define AB3100_LDO_D 0x42
25#define AB3100_LDO_E 0x43
26#define AB3100_LDO_E_SLEEP 0x44
27#define AB3100_LDO_F 0x45
28#define AB3100_LDO_G 0x46
29#define AB3100_LDO_H 0x47
30#define AB3100_LDO_H_SLEEP_MODE 0
31#define AB3100_LDO_H_SLEEP_EN 2
32#define AB3100_LDO_ON 4
33#define AB3100_LDO_H_VSEL_AC 5
34#define AB3100_LDO_K 0x48
35#define AB3100_LDO_EXT 0x49
36#define AB3100_BUCK 0x4A
37#define AB3100_BUCK_SLEEP 0x4B
38#define AB3100_REG_ON_MASK 0x10
39
40/**
41 * struct ab3100_regulator
42 * A struct passed around the individual regulator functions
43 * @platform_device: platform device holding this regulator
44 * @ab3100: handle to the AB3100 parent chip
45 * @plfdata: AB3100 platform data passed in at probe time
46 * @regreg: regulator register number in the AB3100
47 * @fixed_voltage: a fixed voltage for this regulator, if this
48 * 0 the voltages array is used instead.
49 * @typ_voltages: an array of available typical voltages for
50 * this regulator
51 * @voltages_len: length of the array of available voltages
52 */
53struct ab3100_regulator {
54 struct regulator_dev *rdev;
55 struct ab3100 *ab3100;
56 struct ab3100_platform_data *plfdata;
57 u8 regreg;
58 int fixed_voltage;
59 int const *typ_voltages;
60 u8 voltages_len;
61};
62
63/* The order in which registers are initialized */
64static const u8 ab3100_reg_init_order[AB3100_NUM_REGULATORS+2] = {
65 AB3100_LDO_A,
66 AB3100_LDO_C,
67 AB3100_LDO_E,
68 AB3100_LDO_E_SLEEP,
69 AB3100_LDO_F,
70 AB3100_LDO_G,
71 AB3100_LDO_H,
72 AB3100_LDO_K,
73 AB3100_LDO_EXT,
74 AB3100_BUCK,
75 AB3100_BUCK_SLEEP,
76 AB3100_LDO_D,
77};
78
79/* Preset (hardware defined) voltages for these regulators */
80#define LDO_A_VOLTAGE 2750000
81#define LDO_C_VOLTAGE 2650000
82#define LDO_D_VOLTAGE 2650000
83
84static const int const ldo_e_buck_typ_voltages[] = {
85 1800000,
86 1400000,
87 1300000,
88 1200000,
89 1100000,
90 1050000,
91 900000,
92};
93
94static const int const ldo_f_typ_voltages[] = {
95 1800000,
96 1400000,
97 1300000,
98 1200000,
99 1100000,
100 1050000,
101 2500000,
102 2650000,
103};
104
105static const int const ldo_g_typ_voltages[] = {
106 2850000,
107 2750000,
108 1800000,
109 1500000,
110};
111
112static const int const ldo_h_typ_voltages[] = {
113 2750000,
114 1800000,
115 1500000,
116 1200000,
117};
118
119static const int const ldo_k_typ_voltages[] = {
120 2750000,
121 1800000,
122};
123
124
125/* The regulator devices */
126static struct ab3100_regulator
127ab3100_regulators[AB3100_NUM_REGULATORS] = {
128 {
129 .regreg = AB3100_LDO_A,
130 .fixed_voltage = LDO_A_VOLTAGE,
131 },
132 {
133 .regreg = AB3100_LDO_C,
134 .fixed_voltage = LDO_C_VOLTAGE,
135 },
136 {
137 .regreg = AB3100_LDO_D,
138 .fixed_voltage = LDO_D_VOLTAGE,
139 },
140 {
141 .regreg = AB3100_LDO_E,
142 .typ_voltages = ldo_e_buck_typ_voltages,
143 .voltages_len = ARRAY_SIZE(ldo_e_buck_typ_voltages),
144 },
145 {
146 .regreg = AB3100_LDO_F,
147 .typ_voltages = ldo_f_typ_voltages,
148 .voltages_len = ARRAY_SIZE(ldo_f_typ_voltages),
149 },
150 {
151 .regreg = AB3100_LDO_G,
152 .typ_voltages = ldo_g_typ_voltages,
153 .voltages_len = ARRAY_SIZE(ldo_g_typ_voltages),
154 },
155 {
156 .regreg = AB3100_LDO_H,
157 .typ_voltages = ldo_h_typ_voltages,
158 .voltages_len = ARRAY_SIZE(ldo_h_typ_voltages),
159 },
160 {
161 .regreg = AB3100_LDO_K,
162 .typ_voltages = ldo_k_typ_voltages,
163 .voltages_len = ARRAY_SIZE(ldo_k_typ_voltages),
164 },
165 {
166 .regreg = AB3100_LDO_EXT,
167 /* No voltages for the external regulator */
168 },
169 {
170 .regreg = AB3100_BUCK,
171 .typ_voltages = ldo_e_buck_typ_voltages,
172 .voltages_len = ARRAY_SIZE(ldo_e_buck_typ_voltages),
173 },
174};
175
176/*
177 * General functions for enable, disable and is_enabled used for
178 * LDO: A,C,E,F,G,H,K,EXT and BUCK
179 */
180static int ab3100_enable_regulator(struct regulator_dev *reg)
181{
182 struct ab3100_regulator *abreg = reg->reg_data;
183 int err;
184 u8 regval;
185
186 err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg,
187 &regval);
188 if (err) {
189 dev_warn(&reg->dev, "failed to get regid %d value\n",
190 abreg->regreg);
191 return err;
192 }
193
194 /* The regulator is already on, no reason to go further */
195 if (regval & AB3100_REG_ON_MASK)
196 return 0;
197
198 regval |= AB3100_REG_ON_MASK;
199
200 err = ab3100_set_register_interruptible(abreg->ab3100, abreg->regreg,
201 regval);
202 if (err) {
203 dev_warn(&reg->dev, "failed to set regid %d value\n",
204 abreg->regreg);
205 return err;
206 }
207
208 /* Per-regulator power on delay from spec */
209 switch (abreg->regreg) {
210 case AB3100_LDO_A: /* Fallthrough */
211 case AB3100_LDO_C: /* Fallthrough */
212 case AB3100_LDO_D: /* Fallthrough */
213 case AB3100_LDO_E: /* Fallthrough */
214 case AB3100_LDO_H: /* Fallthrough */
215 case AB3100_LDO_K:
216 udelay(200);
217 break;
218 case AB3100_LDO_F:
219 udelay(600);
220 break;
221 case AB3100_LDO_G:
222 udelay(400);
223 break;
224 case AB3100_BUCK:
225 mdelay(1);
226 break;
227 default:
228 break;
229 }
230
231 return 0;
232}
233
234static int ab3100_disable_regulator(struct regulator_dev *reg)
235{
236 struct ab3100_regulator *abreg = reg->reg_data;
237 int err;
238 u8 regval;
239
240 /*
241 * LDO D is a special regulator. When it is disabled, the entire
242 * system is shut down. So this is handled specially.
243 */
244 if (abreg->regreg == AB3100_LDO_D) {
245 int i;
246
247 dev_info(&reg->dev, "disabling LDO D - shut down system\n");
248 /*
249 * Set regulators to default values, ignore any errors,
250 * we're going DOWN
251 */
252 for (i = 0; i < ARRAY_SIZE(ab3100_reg_init_order); i++) {
253 (void) ab3100_set_register_interruptible(abreg->ab3100,
254 ab3100_reg_init_order[i],
255 abreg->plfdata->reg_initvals[i]);
256 }
257
258 /* Setting LDO D to 0x00 cuts the power to the SoC */
259 return ab3100_set_register_interruptible(abreg->ab3100,
260 AB3100_LDO_D, 0x00U);
261
262 }
263
264 /*
265 * All other regulators are handled here
266 */
267 err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg,
268 &regval);
269 if (err) {
270 dev_err(&reg->dev, "unable to get register 0x%x\n",
271 abreg->regreg);
272 return err;
273 }
274 regval &= ~AB3100_REG_ON_MASK;
275 return ab3100_set_register_interruptible(abreg->ab3100, abreg->regreg,
276 regval);
277}
278
279static int ab3100_is_enabled_regulator(struct regulator_dev *reg)
280{
281 struct ab3100_regulator *abreg = reg->reg_data;
282 u8 regval;
283 int err;
284
285 err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg,
286 &regval);
287 if (err) {
288 dev_err(&reg->dev, "unable to get register 0x%x\n",
289 abreg->regreg);
290 return err;
291 }
292
293 return regval & AB3100_REG_ON_MASK;
294}
295
296static int ab3100_list_voltage_regulator(struct regulator_dev *reg,
297 unsigned selector)
298{
299 struct ab3100_regulator *abreg = reg->reg_data;
300
301 if (selector > abreg->voltages_len)
302 return -EINVAL;
303 return abreg->typ_voltages[selector];
304}
305
306static int ab3100_get_voltage_regulator(struct regulator_dev *reg)
307{
308 struct ab3100_regulator *abreg = reg->reg_data;
309 u8 regval;
310 int err;
311
312 /* Return the voltage for fixed regulators immediately */
313 if (abreg->fixed_voltage)
314 return abreg->fixed_voltage;
315
316 /*
317 * For variable types, read out setting and index into
318 * supplied voltage list.
319 */
320 err = ab3100_get_register_interruptible(abreg->ab3100,
321 abreg->regreg, &regval);
322 if (err) {
323 dev_warn(&reg->dev,
324 "failed to get regulator value in register %02x\n",
325 abreg->regreg);
326 return err;
327 }
328
329 /* The 3 highest bits index voltages */
330 regval &= 0xE0;
331 regval >>= 5;
332
333 if (regval > abreg->voltages_len) {
334 dev_err(&reg->dev,
335 "regulator register %02x contains an illegal voltage setting\n",
336 abreg->regreg);
337 return -EINVAL;
338 }
339
340 return abreg->typ_voltages[regval];
341}
342
343static int ab3100_get_best_voltage_index(struct regulator_dev *reg,
344 int min_uV, int max_uV)
345{
346 struct ab3100_regulator *abreg = reg->reg_data;
347 int i;
348 int bestmatch;
349 int bestindex;
350
351 /*
352 * Locate the minimum voltage fitting the criteria on
353 * this regulator. The switchable voltages are not
354 * in strict falling order so we need to check them
355 * all for the best match.
356 */
357 bestmatch = INT_MAX;
358 bestindex = -1;
359 for (i = 0; i < abreg->voltages_len; i++) {
360 if (abreg->typ_voltages[i] <= max_uV &&
361 abreg->typ_voltages[i] >= min_uV &&
362 abreg->typ_voltages[i] < bestmatch) {
363 bestmatch = abreg->typ_voltages[i];
364 bestindex = i;
365 }
366 }
367
368 if (bestindex < 0) {
369 dev_warn(&reg->dev, "requested %d<=x<=%d uV, out of range!\n",
370 min_uV, max_uV);
371 return -EINVAL;
372 }
373 return bestindex;
374}
375
376static int ab3100_set_voltage_regulator(struct regulator_dev *reg,
377 int min_uV, int max_uV)
378{
379 struct ab3100_regulator *abreg = reg->reg_data;
380 u8 regval;
381 int err;
382 int bestindex;
383
384 bestindex = ab3100_get_best_voltage_index(reg, min_uV, max_uV);
385 if (bestindex < 0)
386 return bestindex;
387
388 err = ab3100_get_register_interruptible(abreg->ab3100,
389 abreg->regreg, &regval);
390 if (err) {
391 dev_warn(&reg->dev,
392 "failed to get regulator register %02x\n",
393 abreg->regreg);
394 return err;
395 }
396
397 /* The highest three bits control the variable regulators */
398 regval &= ~0xE0;
399 regval |= (bestindex << 5);
400
401 err = ab3100_set_register_interruptible(abreg->ab3100,
402 abreg->regreg, regval);
403 if (err)
404 dev_warn(&reg->dev, "failed to set regulator register %02x\n",
405 abreg->regreg);
406
407 return err;
408}
409
410static int ab3100_set_suspend_voltage_regulator(struct regulator_dev *reg,
411 int uV)
412{
413 struct ab3100_regulator *abreg = reg->reg_data;
414 u8 regval;
415 int err;
416 int bestindex;
417 u8 targetreg;
418
419 if (abreg->regreg == AB3100_LDO_E)
420 targetreg = AB3100_LDO_E_SLEEP;
421 else if (abreg->regreg == AB3100_BUCK)
422 targetreg = AB3100_BUCK_SLEEP;
423 else
424 return -EINVAL;
425
426 /* LDO E and BUCK have special suspend voltages you can set */
427 bestindex = ab3100_get_best_voltage_index(reg, uV, uV);
428
429 err = ab3100_get_register_interruptible(abreg->ab3100,
430 targetreg, &regval);
431 if (err) {
432 dev_warn(&reg->dev,
433 "failed to get regulator register %02x\n",
434 targetreg);
435 return err;
436 }
437
438 /* The highest three bits control the variable regulators */
439 regval &= ~0xE0;
440 regval |= (bestindex << 5);
441
442 err = ab3100_set_register_interruptible(abreg->ab3100,
443 targetreg, regval);
444 if (err)
445 dev_warn(&reg->dev, "failed to set regulator register %02x\n",
446 abreg->regreg);
447
448 return err;
449}
450
451/*
452 * The external regulator can just define a fixed voltage.
453 */
454static int ab3100_get_voltage_regulator_external(struct regulator_dev *reg)
455{
456 struct ab3100_regulator *abreg = reg->reg_data;
457
458 return abreg->plfdata->external_voltage;
459}
460
461static struct regulator_ops regulator_ops_fixed = {
462 .enable = ab3100_enable_regulator,
463 .disable = ab3100_disable_regulator,
464 .is_enabled = ab3100_is_enabled_regulator,
465 .get_voltage = ab3100_get_voltage_regulator,
466};
467
468static struct regulator_ops regulator_ops_variable = {
469 .enable = ab3100_enable_regulator,
470 .disable = ab3100_disable_regulator,
471 .is_enabled = ab3100_is_enabled_regulator,
472 .get_voltage = ab3100_get_voltage_regulator,
473 .set_voltage = ab3100_set_voltage_regulator,
474 .list_voltage = ab3100_list_voltage_regulator,
475};
476
477static struct regulator_ops regulator_ops_variable_sleepable = {
478 .enable = ab3100_enable_regulator,
479 .disable = ab3100_disable_regulator,
480 .is_enabled = ab3100_is_enabled_regulator,
481 .get_voltage = ab3100_get_voltage_regulator,
482 .set_voltage = ab3100_set_voltage_regulator,
483 .set_suspend_voltage = ab3100_set_suspend_voltage_regulator,
484 .list_voltage = ab3100_list_voltage_regulator,
485};
486
487/*
488 * LDO EXT is an external regulator so it is really
489 * not possible to set any voltage locally here, AB3100
490 * is an on/off switch plain an simple. The external
491 * voltage is defined in the board set-up if any.
492 */
493static struct regulator_ops regulator_ops_external = {
494 .enable = ab3100_enable_regulator,
495 .disable = ab3100_disable_regulator,
496 .is_enabled = ab3100_is_enabled_regulator,
497 .get_voltage = ab3100_get_voltage_regulator_external,
498};
499
500static struct regulator_desc
501ab3100_regulator_desc[AB3100_NUM_REGULATORS] = {
502 {
503 .name = "LDO_A",
504 .id = AB3100_LDO_A,
505 .ops = &regulator_ops_fixed,
506 .type = REGULATOR_VOLTAGE,
507 },
508 {
509 .name = "LDO_C",
510 .id = AB3100_LDO_C,
511 .ops = &regulator_ops_fixed,
512 .type = REGULATOR_VOLTAGE,
513 },
514 {
515 .name = "LDO_D",
516 .id = AB3100_LDO_D,
517 .ops = &regulator_ops_fixed,
518 .type = REGULATOR_VOLTAGE,
519 },
520 {
521 .name = "LDO_E",
522 .id = AB3100_LDO_E,
523 .ops = &regulator_ops_variable_sleepable,
524 .n_voltages = ARRAY_SIZE(ldo_e_buck_typ_voltages),
525 .type = REGULATOR_VOLTAGE,
526 },
527 {
528 .name = "LDO_F",
529 .id = AB3100_LDO_F,
530 .ops = &regulator_ops_variable,
531 .n_voltages = ARRAY_SIZE(ldo_f_typ_voltages),
532 .type = REGULATOR_VOLTAGE,
533 },
534 {
535 .name = "LDO_G",
536 .id = AB3100_LDO_G,
537 .ops = &regulator_ops_variable,
538 .n_voltages = ARRAY_SIZE(ldo_g_typ_voltages),
539 .type = REGULATOR_VOLTAGE,
540 },
541 {
542 .name = "LDO_H",
543 .id = AB3100_LDO_H,
544 .ops = &regulator_ops_variable,
545 .n_voltages = ARRAY_SIZE(ldo_h_typ_voltages),
546 .type = REGULATOR_VOLTAGE,
547 },
548 {
549 .name = "LDO_K",
550 .id = AB3100_LDO_K,
551 .ops = &regulator_ops_variable,
552 .n_voltages = ARRAY_SIZE(ldo_k_typ_voltages),
553 .type = REGULATOR_VOLTAGE,
554 },
555 {
556 .name = "LDO_EXT",
557 .id = AB3100_LDO_EXT,
558 .ops = &regulator_ops_external,
559 .type = REGULATOR_VOLTAGE,
560 },
561 {
562 .name = "BUCK",
563 .id = AB3100_BUCK,
564 .ops = &regulator_ops_variable_sleepable,
565 .n_voltages = ARRAY_SIZE(ldo_e_buck_typ_voltages),
566 .type = REGULATOR_VOLTAGE,
567 },
568};
569
570/*
571 * NOTE: the following functions are regulators pluralis - it is the
572 * binding to the AB3100 core driver and the parent platform device
573 * for all the different regulators.
574 */
575
576static int __init ab3100_regulators_probe(struct platform_device *pdev)
577{
578 struct ab3100_platform_data *plfdata = pdev->dev.platform_data;
579 struct ab3100 *ab3100 = platform_get_drvdata(pdev);
580 int err = 0;
581 u8 data;
582 int i;
583
584 /* Check chip state */
585 err = ab3100_get_register_interruptible(ab3100,
586 AB3100_LDO_D, &data);
587 if (err) {
588 dev_err(&pdev->dev, "could not read initial status of LDO_D\n");
589 return err;
590 }
591 if (data & 0x10)
592 dev_notice(&pdev->dev,
593 "chip is already in active mode (Warm start)\n");
594 else
595 dev_notice(&pdev->dev,
596 "chip is in inactive mode (Cold start)\n");
597
598 /* Set up regulators */
599 for (i = 0; i < ARRAY_SIZE(ab3100_reg_init_order); i++) {
600 err = ab3100_set_register_interruptible(ab3100,
601 ab3100_reg_init_order[i],
602 plfdata->reg_initvals[i]);
603 if (err) {
604 dev_err(&pdev->dev, "regulator initialization failed with error %d\n",
605 err);
606 return err;
607 }
608 }
609
610 if (err) {
611 dev_err(&pdev->dev,
612 "LDO D regulator initialization failed with error %d\n",
613 err);
614 return err;
615 }
616
617 /* Register the regulators */
618 for (i = 0; i < AB3100_NUM_REGULATORS; i++) {
619 struct ab3100_regulator *reg = &ab3100_regulators[i];
620 struct regulator_dev *rdev;
621
622 /*
623 * Initialize per-regulator struct.
624 * Inherit platform data, this comes down from the
625 * i2c boarddata, from the machine. So if you want to
626 * see what it looks like for a certain machine, go
627 * into the machine I2C setup.
628 */
629 reg->ab3100 = ab3100;
630 reg->plfdata = plfdata;
631
632 /*
633 * Register the regulator, pass around
634 * the ab3100_regulator struct
635 */
636 rdev = regulator_register(&ab3100_regulator_desc[i],
637 &pdev->dev,
638 &plfdata->reg_constraints[i],
639 reg);
640
641 if (IS_ERR(rdev)) {
642 err = PTR_ERR(rdev);
643 dev_err(&pdev->dev,
644 "%s: failed to register regulator %s err %d\n",
645 __func__, ab3100_regulator_desc[i].name,
646 err);
647 i--;
648 /* remove the already registered regulators */
649 while (i > 0) {
650 regulator_unregister(ab3100_regulators[i].rdev);
651 i--;
652 }
653 return err;
654 }
655
656 /* Then set a pointer back to the registered regulator */
657 reg->rdev = rdev;
658 }
659
660 return 0;
661}
662
663static int __exit ab3100_regulators_remove(struct platform_device *pdev)
664{
665 int i;
666
667 for (i = 0; i < AB3100_NUM_REGULATORS; i++) {
668 struct ab3100_regulator *reg = &ab3100_regulators[i];
669
670 regulator_unregister(reg->rdev);
671 }
672 return 0;
673}
674
675static struct platform_driver ab3100_regulators_driver = {
676 .driver = {
677 .name = "ab3100-regulators",
678 .owner = THIS_MODULE,
679 },
680 .probe = ab3100_regulators_probe,
681 .remove = __exit_p(ab3100_regulators_remove),
682};
683
684static __init int ab3100_regulators_init(void)
685{
686 return platform_driver_register(&ab3100_regulators_driver);
687}
688
689static __exit void ab3100_regulators_exit(void)
690{
691 platform_driver_register(&ab3100_regulators_driver);
692}
693
694subsys_initcall(ab3100_regulators_init);
695module_exit(ab3100_regulators_exit);
696
697MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
698MODULE_DESCRIPTION("AB3100 Regulator driver");
699MODULE_LICENSE("GPL");
700MODULE_ALIAS("platform:ab3100-regulators");
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 98c3a74e9949..91ba9bfaa706 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1864,6 +1864,30 @@ int regulator_notifier_call_chain(struct regulator_dev *rdev,
1864} 1864}
1865EXPORT_SYMBOL_GPL(regulator_notifier_call_chain); 1865EXPORT_SYMBOL_GPL(regulator_notifier_call_chain);
1866 1866
1867/**
1868 * regulator_mode_to_status - convert a regulator mode into a status
1869 *
1870 * @mode: Mode to convert
1871 *
1872 * Convert a regulator mode into a status.
1873 */
1874int regulator_mode_to_status(unsigned int mode)
1875{
1876 switch (mode) {
1877 case REGULATOR_MODE_FAST:
1878 return REGULATOR_STATUS_FAST;
1879 case REGULATOR_MODE_NORMAL:
1880 return REGULATOR_STATUS_NORMAL;
1881 case REGULATOR_MODE_IDLE:
1882 return REGULATOR_STATUS_IDLE;
1883 case REGULATOR_STATUS_STANDBY:
1884 return REGULATOR_STATUS_STANDBY;
1885 default:
1886 return 0;
1887 }
1888}
1889EXPORT_SYMBOL_GPL(regulator_mode_to_status);
1890
1867/* 1891/*
1868 * To avoid cluttering sysfs (and memory) with useless state, only 1892 * To avoid cluttering sysfs (and memory) with useless state, only
1869 * create attributes that can be meaningfully displayed. 1893 * create attributes that can be meaningfully displayed.
diff --git a/drivers/regulator/mc13783.c b/drivers/regulator/mc13783.c
new file mode 100644
index 000000000000..710211f67449
--- /dev/null
+++ b/drivers/regulator/mc13783.c
@@ -0,0 +1,410 @@
1/*
2 * Regulator Driver for Freescale MC13783 PMIC
3 *
4 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/mfd/mc13783-private.h>
12#include <linux/regulator/machine.h>
13#include <linux/regulator/driver.h>
14#include <linux/platform_device.h>
15#include <linux/mfd/mc13783.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/err.h>
19
20struct mc13783_regulator {
21 struct regulator_desc desc;
22 int reg;
23 int enable_bit;
24};
25
26static struct regulator_ops mc13783_regulator_ops;
27
28static struct mc13783_regulator mc13783_regulators[] = {
29 [MC13783_SW_SW3] = {
30 .desc = {
31 .name = "SW_SW3",
32 .ops = &mc13783_regulator_ops,
33 .type = REGULATOR_VOLTAGE,
34 .id = MC13783_SW_SW3,
35 .owner = THIS_MODULE,
36 },
37 .reg = MC13783_REG_SWITCHERS_5,
38 .enable_bit = MC13783_SWCTRL_SW3_EN,
39 },
40 [MC13783_SW_PLL] = {
41 .desc = {
42 .name = "SW_PLL",
43 .ops = &mc13783_regulator_ops,
44 .type = REGULATOR_VOLTAGE,
45 .id = MC13783_SW_PLL,
46 .owner = THIS_MODULE,
47 },
48 .reg = MC13783_REG_SWITCHERS_4,
49 .enable_bit = MC13783_SWCTRL_PLL_EN,
50 },
51 [MC13783_REGU_VAUDIO] = {
52 .desc = {
53 .name = "REGU_VAUDIO",
54 .ops = &mc13783_regulator_ops,
55 .type = REGULATOR_VOLTAGE,
56 .id = MC13783_REGU_VAUDIO,
57 .owner = THIS_MODULE,
58 },
59 .reg = MC13783_REG_REGULATOR_MODE_0,
60 .enable_bit = MC13783_REGCTRL_VAUDIO_EN,
61 },
62 [MC13783_REGU_VIOHI] = {
63 .desc = {
64 .name = "REGU_VIOHI",
65 .ops = &mc13783_regulator_ops,
66 .type = REGULATOR_VOLTAGE,
67 .id = MC13783_REGU_VIOHI,
68 .owner = THIS_MODULE,
69 },
70 .reg = MC13783_REG_REGULATOR_MODE_0,
71 .enable_bit = MC13783_REGCTRL_VIOHI_EN,
72 },
73 [MC13783_REGU_VIOLO] = {
74 .desc = {
75 .name = "REGU_VIOLO",
76 .ops = &mc13783_regulator_ops,
77 .type = REGULATOR_VOLTAGE,
78 .id = MC13783_REGU_VIOLO,
79 .owner = THIS_MODULE,
80 },
81 .reg = MC13783_REG_REGULATOR_MODE_0,
82 .enable_bit = MC13783_REGCTRL_VIOLO_EN,
83 },
84 [MC13783_REGU_VDIG] = {
85 .desc = {
86 .name = "REGU_VDIG",
87 .ops = &mc13783_regulator_ops,
88 .type = REGULATOR_VOLTAGE,
89 .id = MC13783_REGU_VDIG,
90 .owner = THIS_MODULE,
91 },
92 .reg = MC13783_REG_REGULATOR_MODE_0,
93 .enable_bit = MC13783_REGCTRL_VDIG_EN,
94 },
95 [MC13783_REGU_VGEN] = {
96 .desc = {
97 .name = "REGU_VGEN",
98 .ops = &mc13783_regulator_ops,
99 .type = REGULATOR_VOLTAGE,
100 .id = MC13783_REGU_VGEN,
101 .owner = THIS_MODULE,
102 },
103 .reg = MC13783_REG_REGULATOR_MODE_0,
104 .enable_bit = MC13783_REGCTRL_VGEN_EN,
105 },
106 [MC13783_REGU_VRFDIG] = {
107 .desc = {
108 .name = "REGU_VRFDIG",
109 .ops = &mc13783_regulator_ops,
110 .type = REGULATOR_VOLTAGE,
111 .id = MC13783_REGU_VRFDIG,
112 .owner = THIS_MODULE,
113 },
114 .reg = MC13783_REG_REGULATOR_MODE_0,
115 .enable_bit = MC13783_REGCTRL_VRFDIG_EN,
116 },
117 [MC13783_REGU_VRFREF] = {
118 .desc = {
119 .name = "REGU_VRFREF",
120 .ops = &mc13783_regulator_ops,
121 .type = REGULATOR_VOLTAGE,
122 .id = MC13783_REGU_VRFREF,
123 .owner = THIS_MODULE,
124 },
125 .reg = MC13783_REG_REGULATOR_MODE_0,
126 .enable_bit = MC13783_REGCTRL_VRFREF_EN,
127 },
128 [MC13783_REGU_VRFCP] = {
129 .desc = {
130 .name = "REGU_VRFCP",
131 .ops = &mc13783_regulator_ops,
132 .type = REGULATOR_VOLTAGE,
133 .id = MC13783_REGU_VRFCP,
134 .owner = THIS_MODULE,
135 },
136 .reg = MC13783_REG_REGULATOR_MODE_0,
137 .enable_bit = MC13783_REGCTRL_VRFCP_EN,
138 },
139 [MC13783_REGU_VSIM] = {
140 .desc = {
141 .name = "REGU_VSIM",
142 .ops = &mc13783_regulator_ops,
143 .type = REGULATOR_VOLTAGE,
144 .id = MC13783_REGU_VSIM,
145 .owner = THIS_MODULE,
146 },
147 .reg = MC13783_REG_REGULATOR_MODE_1,
148 .enable_bit = MC13783_REGCTRL_VSIM_EN,
149 },
150 [MC13783_REGU_VESIM] = {
151 .desc = {
152 .name = "REGU_VESIM",
153 .ops = &mc13783_regulator_ops,
154 .type = REGULATOR_VOLTAGE,
155 .id = MC13783_REGU_VESIM,
156 .owner = THIS_MODULE,
157 },
158 .reg = MC13783_REG_REGULATOR_MODE_1,
159 .enable_bit = MC13783_REGCTRL_VESIM_EN,
160 },
161 [MC13783_REGU_VCAM] = {
162 .desc = {
163 .name = "REGU_VCAM",
164 .ops = &mc13783_regulator_ops,
165 .type = REGULATOR_VOLTAGE,
166 .id = MC13783_REGU_VCAM,
167 .owner = THIS_MODULE,
168 },
169 .reg = MC13783_REG_REGULATOR_MODE_1,
170 .enable_bit = MC13783_REGCTRL_VCAM_EN,
171 },
172 [MC13783_REGU_VRFBG] = {
173 .desc = {
174 .name = "REGU_VRFBG",
175 .ops = &mc13783_regulator_ops,
176 .type = REGULATOR_VOLTAGE,
177 .id = MC13783_REGU_VRFBG,
178 .owner = THIS_MODULE,
179 },
180 .reg = MC13783_REG_REGULATOR_MODE_1,
181 .enable_bit = MC13783_REGCTRL_VRFBG_EN,
182 },
183 [MC13783_REGU_VVIB] = {
184 .desc = {
185 .name = "REGU_VVIB",
186 .ops = &mc13783_regulator_ops,
187 .type = REGULATOR_VOLTAGE,
188 .id = MC13783_REGU_VVIB,
189 .owner = THIS_MODULE,
190 },
191 .reg = MC13783_REG_REGULATOR_MODE_1,
192 .enable_bit = MC13783_REGCTRL_VVIB_EN,
193 },
194 [MC13783_REGU_VRF1] = {
195 .desc = {
196 .name = "REGU_VRF1",
197 .ops = &mc13783_regulator_ops,
198 .type = REGULATOR_VOLTAGE,
199 .id = MC13783_REGU_VRF1,
200 .owner = THIS_MODULE,
201 },
202 .reg = MC13783_REG_REGULATOR_MODE_1,
203 .enable_bit = MC13783_REGCTRL_VRF1_EN,
204 },
205 [MC13783_REGU_VRF2] = {
206 .desc = {
207 .name = "REGU_VRF2",
208 .ops = &mc13783_regulator_ops,
209 .type = REGULATOR_VOLTAGE,
210 .id = MC13783_REGU_VRF2,
211 .owner = THIS_MODULE,
212 },
213 .reg = MC13783_REG_REGULATOR_MODE_1,
214 .enable_bit = MC13783_REGCTRL_VRF2_EN,
215 },
216 [MC13783_REGU_VMMC1] = {
217 .desc = {
218 .name = "REGU_VMMC1",
219 .ops = &mc13783_regulator_ops,
220 .type = REGULATOR_VOLTAGE,
221 .id = MC13783_REGU_VMMC1,
222 .owner = THIS_MODULE,
223 },
224 .reg = MC13783_REG_REGULATOR_MODE_1,
225 .enable_bit = MC13783_REGCTRL_VMMC1_EN,
226 },
227 [MC13783_REGU_VMMC2] = {
228 .desc = {
229 .name = "REGU_VMMC2",
230 .ops = &mc13783_regulator_ops,
231 .type = REGULATOR_VOLTAGE,
232 .id = MC13783_REGU_VMMC2,
233 .owner = THIS_MODULE,
234 },
235 .reg = MC13783_REG_REGULATOR_MODE_1,
236 .enable_bit = MC13783_REGCTRL_VMMC2_EN,
237 },
238 [MC13783_REGU_GPO1] = {
239 .desc = {
240 .name = "REGU_GPO1",
241 .ops = &mc13783_regulator_ops,
242 .type = REGULATOR_VOLTAGE,
243 .id = MC13783_REGU_GPO1,
244 .owner = THIS_MODULE,
245 },
246 .reg = MC13783_REG_POWER_MISCELLANEOUS,
247 .enable_bit = MC13783_REGCTRL_GPO1_EN,
248 },
249 [MC13783_REGU_GPO2] = {
250 .desc = {
251 .name = "REGU_GPO2",
252 .ops = &mc13783_regulator_ops,
253 .type = REGULATOR_VOLTAGE,
254 .id = MC13783_REGU_GPO2,
255 .owner = THIS_MODULE,
256 },
257 .reg = MC13783_REG_POWER_MISCELLANEOUS,
258 .enable_bit = MC13783_REGCTRL_GPO2_EN,
259 },
260 [MC13783_REGU_GPO3] = {
261 .desc = {
262 .name = "REGU_GPO3",
263 .ops = &mc13783_regulator_ops,
264 .type = REGULATOR_VOLTAGE,
265 .id = MC13783_REGU_GPO3,
266 .owner = THIS_MODULE,
267 },
268 .reg = MC13783_REG_POWER_MISCELLANEOUS,
269 .enable_bit = MC13783_REGCTRL_GPO3_EN,
270 },
271 [MC13783_REGU_GPO4] = {
272 .desc = {
273 .name = "REGU_GPO4",
274 .ops = &mc13783_regulator_ops,
275 .type = REGULATOR_VOLTAGE,
276 .id = MC13783_REGU_GPO4,
277 .owner = THIS_MODULE,
278 },
279 .reg = MC13783_REG_POWER_MISCELLANEOUS,
280 .enable_bit = MC13783_REGCTRL_GPO4_EN,
281 },
282};
283
284struct mc13783_priv {
285 struct regulator_desc desc[ARRAY_SIZE(mc13783_regulators)];
286 struct mc13783 *mc13783;
287 struct regulator_dev *regulators[0];
288};
289
290static int mc13783_enable(struct regulator_dev *rdev)
291{
292 struct mc13783_priv *priv = rdev_get_drvdata(rdev);
293 int id = rdev_get_id(rdev);
294
295 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
296
297 return mc13783_set_bits(priv->mc13783, mc13783_regulators[id].reg,
298 mc13783_regulators[id].enable_bit,
299 mc13783_regulators[id].enable_bit);
300}
301
302static int mc13783_disable(struct regulator_dev *rdev)
303{
304 struct mc13783_priv *priv = rdev_get_drvdata(rdev);
305 int id = rdev_get_id(rdev);
306
307 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
308
309 return mc13783_set_bits(priv->mc13783, mc13783_regulators[id].reg,
310 mc13783_regulators[id].enable_bit, 0);
311}
312
313static int mc13783_is_enabled(struct regulator_dev *rdev)
314{
315 struct mc13783_priv *priv = rdev_get_drvdata(rdev);
316 int ret, id = rdev_get_id(rdev);
317 unsigned int val;
318
319 ret = mc13783_reg_read(priv->mc13783, mc13783_regulators[id].reg, &val);
320 if (ret)
321 return ret;
322
323 return (val & mc13783_regulators[id].enable_bit) != 0;
324}
325
326static struct regulator_ops mc13783_regulator_ops = {
327 .enable = mc13783_enable,
328 .disable = mc13783_disable,
329 .is_enabled = mc13783_is_enabled,
330};
331
332static int __devinit mc13783_regulator_probe(struct platform_device *pdev)
333{
334 struct mc13783_priv *priv;
335 struct mc13783 *mc13783 = dev_get_drvdata(pdev->dev.parent);
336 struct mc13783_regulator_init_data *init_data;
337 int i, ret;
338
339 dev_dbg(&pdev->dev, "mc13783_regulator_probe id %d\n", pdev->id);
340
341 priv = kzalloc(sizeof(*priv) + mc13783->num_regulators * sizeof(void *),
342 GFP_KERNEL);
343 if (!priv)
344 return -ENOMEM;
345
346 priv->mc13783 = mc13783;
347
348 for (i = 0; i < mc13783->num_regulators; i++) {
349 init_data = &mc13783->regulators[i];
350 priv->regulators[i] = regulator_register(
351 &mc13783_regulators[init_data->id].desc,
352 &pdev->dev, init_data->init_data, priv);
353
354 if (IS_ERR(priv->regulators[i])) {
355 dev_err(&pdev->dev, "failed to register regulator %s\n",
356 mc13783_regulators[i].desc.name);
357 ret = PTR_ERR(priv->regulators[i]);
358 goto err;
359 }
360 }
361
362 platform_set_drvdata(pdev, priv);
363
364 return 0;
365err:
366 while (--i >= 0)
367 regulator_unregister(priv->regulators[i]);
368
369 kfree(priv);
370
371 return ret;
372}
373
374static int __devexit mc13783_regulator_remove(struct platform_device *pdev)
375{
376 struct mc13783_priv *priv = platform_get_drvdata(pdev);
377 struct mc13783 *mc13783 = priv->mc13783;
378 int i;
379
380 for (i = 0; i < mc13783->num_regulators; i++)
381 regulator_unregister(priv->regulators[i]);
382
383 return 0;
384}
385
386static struct platform_driver mc13783_regulator_driver = {
387 .driver = {
388 .name = "mc13783-regulator",
389 .owner = THIS_MODULE,
390 },
391 .remove = __devexit_p(mc13783_regulator_remove),
392};
393
394static int __init mc13783_regulator_init(void)
395{
396 return platform_driver_probe(&mc13783_regulator_driver,
397 mc13783_regulator_probe);
398}
399subsys_initcall(mc13783_regulator_init);
400
401static void __exit mc13783_regulator_exit(void)
402{
403 platform_driver_unregister(&mc13783_regulator_driver);
404}
405module_exit(mc13783_regulator_exit);
406
407MODULE_LICENSE("GPL");
408MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de");
409MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
410MODULE_ALIAS("platform:mc13783-regulator");
diff --git a/drivers/regulator/pcap-regulator.c b/drivers/regulator/pcap-regulator.c
new file mode 100644
index 000000000000..33d7d899e030
--- /dev/null
+++ b/drivers/regulator/pcap-regulator.c
@@ -0,0 +1,318 @@
1/*
2 * PCAP2 Regulator Driver
3 *
4 * Copyright (c) 2009 Daniel Ribeiro <drwyrm@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h>
19#include <linux/mfd/ezx-pcap.h>
20
21static const u16 V1_table[] = {
22 2775, 1275, 1600, 1725, 1825, 1925, 2075, 2275,
23};
24
25static const u16 V2_table[] = {
26 2500, 2775,
27};
28
29static const u16 V3_table[] = {
30 1075, 1275, 1550, 1725, 1876, 1950, 2075, 2275,
31};
32
33static const u16 V4_table[] = {
34 1275, 1550, 1725, 1875, 1950, 2075, 2275, 2775,
35};
36
37static const u16 V5_table[] = {
38 1875, 2275, 2475, 2775,
39};
40
41static const u16 V6_table[] = {
42 2475, 2775,
43};
44
45static const u16 V7_table[] = {
46 1875, 2775,
47};
48
49#define V8_table V4_table
50
51static const u16 V9_table[] = {
52 1575, 1875, 2475, 2775,
53};
54
55static const u16 V10_table[] = {
56 5000,
57};
58
59static const u16 VAUX1_table[] = {
60 1875, 2475, 2775, 3000,
61};
62
63#define VAUX2_table VAUX1_table
64
65static const u16 VAUX3_table[] = {
66 1200, 1200, 1200, 1200, 1400, 1600, 1800, 2000,
67 2200, 2400, 2600, 2800, 3000, 3200, 3400, 3600,
68};
69
70static const u16 VAUX4_table[] = {
71 1800, 1800, 3000, 5000,
72};
73
74static const u16 VSIM_table[] = {
75 1875, 3000,
76};
77
78static const u16 VSIM2_table[] = {
79 1875,
80};
81
82static const u16 VVIB_table[] = {
83 1300, 1800, 2000, 3000,
84};
85
86static const u16 SW1_table[] = {
87 900, 950, 1000, 1050, 1100, 1150, 1200, 1250,
88 1300, 1350, 1400, 1450, 1500, 1600, 1875, 2250,
89};
90
91#define SW2_table SW1_table
92
93static const u16 SW3_table[] = {
94 4000, 4500, 5000, 5500,
95};
96
97struct pcap_regulator {
98 const u8 reg;
99 const u8 en;
100 const u8 index;
101 const u8 stby;
102 const u8 lowpwr;
103 const u8 n_voltages;
104 const u16 *voltage_table;
105};
106
107#define NA 0xff
108
109#define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \
110 [_vreg] = { \
111 .reg = _reg, \
112 .en = _en, \
113 .index = _index, \
114 .stby = _stby, \
115 .lowpwr = _lowpwr, \
116 .n_voltages = ARRAY_SIZE(_vreg##_table), \
117 .voltage_table = _vreg##_table, \
118 }
119
120static struct pcap_regulator vreg_table[] = {
121 VREG_INFO(V1, PCAP_REG_VREG1, 1, 2, 18, 0),
122 VREG_INFO(V2, PCAP_REG_VREG1, 5, 6, 19, 22),
123 VREG_INFO(V3, PCAP_REG_VREG1, 7, 8, 20, 23),
124 VREG_INFO(V4, PCAP_REG_VREG1, 11, 12, 21, 24),
125 /* V5 STBY and LOWPWR are on PCAP_REG_VREG2 */
126 VREG_INFO(V5, PCAP_REG_VREG1, 15, 16, 12, 19),
127
128 VREG_INFO(V6, PCAP_REG_VREG2, 1, 2, 14, 20),
129 VREG_INFO(V7, PCAP_REG_VREG2, 3, 4, 15, 21),
130 VREG_INFO(V8, PCAP_REG_VREG2, 5, 6, 16, 22),
131 VREG_INFO(V9, PCAP_REG_VREG2, 9, 10, 17, 23),
132 VREG_INFO(V10, PCAP_REG_VREG2, 10, NA, 18, 24),
133
134 VREG_INFO(VAUX1, PCAP_REG_AUXVREG, 1, 2, 22, 23),
135 /* VAUX2 ... VSIM2 STBY and LOWPWR are on PCAP_REG_LOWPWR */
136 VREG_INFO(VAUX2, PCAP_REG_AUXVREG, 4, 5, 0, 1),
137 VREG_INFO(VAUX3, PCAP_REG_AUXVREG, 7, 8, 2, 3),
138 VREG_INFO(VAUX4, PCAP_REG_AUXVREG, 12, 13, 4, 5),
139 VREG_INFO(VSIM, PCAP_REG_AUXVREG, 17, 18, NA, 6),
140 VREG_INFO(VSIM2, PCAP_REG_AUXVREG, 16, NA, NA, 7),
141 VREG_INFO(VVIB, PCAP_REG_AUXVREG, 19, 20, NA, NA),
142
143 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
144 VREG_INFO(SW2, PCAP_REG_SWCTRL, 6, 7, NA, NA),
145 /* SW3 STBY is on PCAP_REG_AUXVREG */
146 VREG_INFO(SW3, PCAP_REG_SWCTRL, 11, 12, 24, NA),
147
148 /* SWxS used to control SWx voltage on standby */
149/* VREG_INFO(SW1S, PCAP_REG_LOWPWR, NA, 12, NA, NA),
150 VREG_INFO(SW2S, PCAP_REG_LOWPWR, NA, 20, NA, NA), */
151};
152
153static int pcap_regulator_set_voltage(struct regulator_dev *rdev,
154 int min_uV, int max_uV)
155{
156 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
157 void *pcap = rdev_get_drvdata(rdev);
158 int uV;
159 u8 i;
160
161 /* the regulator doesn't support voltage switching */
162 if (vreg->n_voltages == 1)
163 return -EINVAL;
164
165 for (i = 0; i < vreg->n_voltages; i++) {
166 /* For V1 the first is not the best match */
167 if (i == 0 && rdev_get_id(rdev) == V1)
168 i = 1;
169 else if (i + 1 == vreg->n_voltages && rdev_get_id(rdev) == V1)
170 i = 0;
171
172 uV = vreg->voltage_table[i] * 1000;
173 if (min_uV <= uV && uV <= max_uV)
174 return ezx_pcap_set_bits(pcap, vreg->reg,
175 (vreg->n_voltages - 1) << vreg->index,
176 i << vreg->index);
177
178 if (i == 0 && rdev_get_id(rdev) == V1)
179 i = vreg->n_voltages - 1;
180 }
181
182 /* the requested voltage range is not supported by this regulator */
183 return -EINVAL;
184}
185
186static int pcap_regulator_get_voltage(struct regulator_dev *rdev)
187{
188 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
189 void *pcap = rdev_get_drvdata(rdev);
190 u32 tmp;
191 int mV;
192
193 if (vreg->n_voltages == 1)
194 return vreg->voltage_table[0] * 1000;
195
196 ezx_pcap_read(pcap, vreg->reg, &tmp);
197 tmp = ((tmp >> vreg->index) & (vreg->n_voltages - 1));
198 mV = vreg->voltage_table[tmp];
199
200 return mV * 1000;
201}
202
203static int pcap_regulator_enable(struct regulator_dev *rdev)
204{
205 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
206 void *pcap = rdev_get_drvdata(rdev);
207
208 if (vreg->en == NA)
209 return -EINVAL;
210
211 return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 1 << vreg->en);
212}
213
214static int pcap_regulator_disable(struct regulator_dev *rdev)
215{
216 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
217 void *pcap = rdev_get_drvdata(rdev);
218
219 if (vreg->en == NA)
220 return -EINVAL;
221
222 return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 0);
223}
224
225static int pcap_regulator_is_enabled(struct regulator_dev *rdev)
226{
227 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
228 void *pcap = rdev_get_drvdata(rdev);
229 u32 tmp;
230
231 if (vreg->en == NA)
232 return -EINVAL;
233
234 ezx_pcap_read(pcap, vreg->reg, &tmp);
235 return (tmp >> vreg->en) & 1;
236}
237
238static int pcap_regulator_list_voltage(struct regulator_dev *rdev,
239 unsigned int index)
240{
241 struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
242
243 return vreg->voltage_table[index] * 1000;
244}
245
246static struct regulator_ops pcap_regulator_ops = {
247 .list_voltage = pcap_regulator_list_voltage,
248 .set_voltage = pcap_regulator_set_voltage,
249 .get_voltage = pcap_regulator_get_voltage,
250 .enable = pcap_regulator_enable,
251 .disable = pcap_regulator_disable,
252 .is_enabled = pcap_regulator_is_enabled,
253};
254
255#define VREG(_vreg) \
256 [_vreg] = { \
257 .name = #_vreg, \
258 .id = _vreg, \
259 .n_voltages = ARRAY_SIZE(_vreg##_table), \
260 .ops = &pcap_regulator_ops, \
261 .type = REGULATOR_VOLTAGE, \
262 .owner = THIS_MODULE, \
263 }
264
265static struct regulator_desc pcap_regulators[] = {
266 VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),
267 VREG(V8), VREG(V9), VREG(V10), VREG(VAUX1), VREG(VAUX2), VREG(VAUX3),
268 VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
269};
270
271static int __devinit pcap_regulator_probe(struct platform_device *pdev)
272{
273 struct regulator_dev *rdev;
274 void *pcap = dev_get_drvdata(pdev->dev.parent);
275
276 rdev = regulator_register(&pcap_regulators[pdev->id], &pdev->dev,
277 pdev->dev.platform_data, pcap);
278 if (IS_ERR(rdev))
279 return PTR_ERR(rdev);
280
281 platform_set_drvdata(pdev, rdev);
282
283 return 0;
284}
285
286static int __devexit pcap_regulator_remove(struct platform_device *pdev)
287{
288 struct regulator_dev *rdev = platform_get_drvdata(pdev);
289
290 regulator_unregister(rdev);
291
292 return 0;
293}
294
295static struct platform_driver pcap_regulator_driver = {
296 .driver = {
297 .name = "pcap-regulator",
298 },
299 .probe = pcap_regulator_probe,
300 .remove = __devexit_p(pcap_regulator_remove),
301};
302
303static int __init pcap_regulator_init(void)
304{
305 return platform_driver_register(&pcap_regulator_driver);
306}
307
308static void __exit pcap_regulator_exit(void)
309{
310 platform_driver_unregister(&pcap_regulator_driver);
311}
312
313subsys_initcall(pcap_regulator_init);
314module_exit(pcap_regulator_exit);
315
316MODULE_AUTHOR("Daniel Ribeiro <drwyrm@gmail.com>");
317MODULE_DESCRIPTION("PCAP2 Regulator Driver");
318MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c
new file mode 100644
index 000000000000..2eefc1a0cf08
--- /dev/null
+++ b/drivers/regulator/wm831x-dcdc.c
@@ -0,0 +1,862 @@
1/*
2 * wm831x-dcdc.c -- DC-DC buck convertor driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/regulator.h>
25#include <linux/mfd/wm831x/pdata.h>
26
27#define WM831X_BUCKV_MAX_SELECTOR 0x68
28#define WM831X_BUCKP_MAX_SELECTOR 0x66
29
30#define WM831X_DCDC_MODE_FAST 0
31#define WM831X_DCDC_MODE_NORMAL 1
32#define WM831X_DCDC_MODE_IDLE 2
33#define WM831X_DCDC_MODE_STANDBY 3
34
35#define WM831X_DCDC_MAX_NAME 6
36
37/* Register offsets in control block */
38#define WM831X_DCDC_CONTROL_1 0
39#define WM831X_DCDC_CONTROL_2 1
40#define WM831X_DCDC_ON_CONFIG 2
41#define WM831X_DCDC_SLEEP_CONTROL 3
42
43/*
44 * Shared
45 */
46
47struct wm831x_dcdc {
48 char name[WM831X_DCDC_MAX_NAME];
49 struct regulator_desc desc;
50 int base;
51 struct wm831x *wm831x;
52 struct regulator_dev *regulator;
53};
54
55static int wm831x_dcdc_is_enabled(struct regulator_dev *rdev)
56{
57 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
58 struct wm831x *wm831x = dcdc->wm831x;
59 int mask = 1 << rdev_get_id(rdev);
60 int reg;
61
62 reg = wm831x_reg_read(wm831x, WM831X_DCDC_ENABLE);
63 if (reg < 0)
64 return reg;
65
66 if (reg & mask)
67 return 1;
68 else
69 return 0;
70}
71
72static int wm831x_dcdc_enable(struct regulator_dev *rdev)
73{
74 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
75 struct wm831x *wm831x = dcdc->wm831x;
76 int mask = 1 << rdev_get_id(rdev);
77
78 return wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, mask, mask);
79}
80
81static int wm831x_dcdc_disable(struct regulator_dev *rdev)
82{
83 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
84 struct wm831x *wm831x = dcdc->wm831x;
85 int mask = 1 << rdev_get_id(rdev);
86
87 return wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, mask, 0);
88}
89
90static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
91
92{
93 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
94 struct wm831x *wm831x = dcdc->wm831x;
95 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
96 int val;
97
98 val = wm831x_reg_read(wm831x, reg);
99 if (val < 0)
100 return val;
101
102 val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT;
103
104 switch (val) {
105 case WM831X_DCDC_MODE_FAST:
106 return REGULATOR_MODE_FAST;
107 case WM831X_DCDC_MODE_NORMAL:
108 return REGULATOR_MODE_NORMAL;
109 case WM831X_DCDC_MODE_STANDBY:
110 return REGULATOR_MODE_STANDBY;
111 case WM831X_DCDC_MODE_IDLE:
112 return REGULATOR_MODE_IDLE;
113 default:
114 BUG();
115 }
116}
117
118static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg,
119 unsigned int mode)
120{
121 int val;
122
123 switch (mode) {
124 case REGULATOR_MODE_FAST:
125 val = WM831X_DCDC_MODE_FAST;
126 break;
127 case REGULATOR_MODE_NORMAL:
128 val = WM831X_DCDC_MODE_NORMAL;
129 break;
130 case REGULATOR_MODE_STANDBY:
131 val = WM831X_DCDC_MODE_STANDBY;
132 break;
133 case REGULATOR_MODE_IDLE:
134 val = WM831X_DCDC_MODE_IDLE;
135 break;
136 default:
137 return -EINVAL;
138 }
139
140 return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK,
141 val << WM831X_DC1_ON_MODE_SHIFT);
142}
143
144static int wm831x_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
145{
146 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
147 struct wm831x *wm831x = dcdc->wm831x;
148 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
149
150 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
151}
152
153static int wm831x_dcdc_set_suspend_mode(struct regulator_dev *rdev,
154 unsigned int mode)
155{
156 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
157 struct wm831x *wm831x = dcdc->wm831x;
158 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
159
160 return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
161}
162
163static int wm831x_dcdc_get_status(struct regulator_dev *rdev)
164{
165 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
166 struct wm831x *wm831x = dcdc->wm831x;
167 int ret;
168
169 /* First, check for errors */
170 ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
171 if (ret < 0)
172 return ret;
173
174 if (ret & (1 << rdev_get_id(rdev))) {
175 dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
176 rdev_get_id(rdev) + 1);
177 return REGULATOR_STATUS_ERROR;
178 }
179
180 /* DCDC1 and DCDC2 can additionally detect high voltage/current */
181 if (rdev_get_id(rdev) < 2) {
182 if (ret & (WM831X_DC1_OV_STS << rdev_get_id(rdev))) {
183 dev_dbg(wm831x->dev, "DCDC%d over voltage\n",
184 rdev_get_id(rdev) + 1);
185 return REGULATOR_STATUS_ERROR;
186 }
187
188 if (ret & (WM831X_DC1_HC_STS << rdev_get_id(rdev))) {
189 dev_dbg(wm831x->dev, "DCDC%d over current\n",
190 rdev_get_id(rdev) + 1);
191 return REGULATOR_STATUS_ERROR;
192 }
193 }
194
195 /* Is the regulator on? */
196 ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
197 if (ret < 0)
198 return ret;
199 if (!(ret & (1 << rdev_get_id(rdev))))
200 return REGULATOR_STATUS_OFF;
201
202 /* TODO: When we handle hardware control modes so we can report the
203 * current mode. */
204 return REGULATOR_STATUS_ON;
205}
206
207static irqreturn_t wm831x_dcdc_uv_irq(int irq, void *data)
208{
209 struct wm831x_dcdc *dcdc = data;
210
211 regulator_notifier_call_chain(dcdc->regulator,
212 REGULATOR_EVENT_UNDER_VOLTAGE,
213 NULL);
214
215 return IRQ_HANDLED;
216}
217
218static irqreturn_t wm831x_dcdc_oc_irq(int irq, void *data)
219{
220 struct wm831x_dcdc *dcdc = data;
221
222 regulator_notifier_call_chain(dcdc->regulator,
223 REGULATOR_EVENT_OVER_CURRENT,
224 NULL);
225
226 return IRQ_HANDLED;
227}
228
229/*
230 * BUCKV specifics
231 */
232
233static int wm831x_buckv_list_voltage(struct regulator_dev *rdev,
234 unsigned selector)
235{
236 if (selector <= 0x8)
237 return 600000;
238 if (selector <= WM831X_BUCKV_MAX_SELECTOR)
239 return 600000 + ((selector - 0x8) * 12500);
240 return -EINVAL;
241}
242
243static int wm831x_buckv_set_voltage_int(struct regulator_dev *rdev, int reg,
244 int min_uV, int max_uV)
245{
246 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
247 struct wm831x *wm831x = dcdc->wm831x;
248 u16 vsel;
249
250 if (min_uV < 600000)
251 vsel = 0;
252 else if (min_uV <= 1800000)
253 vsel = ((min_uV - 600000) / 12500) + 8;
254 else
255 return -EINVAL;
256
257 if (wm831x_buckv_list_voltage(rdev, vsel) > max_uV)
258 return -EINVAL;
259
260 return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_VSEL_MASK, vsel);
261}
262
263static int wm831x_buckv_set_voltage(struct regulator_dev *rdev,
264 int min_uV, int max_uV)
265{
266 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
267 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
268
269 return wm831x_buckv_set_voltage_int(rdev, reg, min_uV, max_uV);
270}
271
272static int wm831x_buckv_set_suspend_voltage(struct regulator_dev *rdev,
273 int uV)
274{
275 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
276 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
277
278 return wm831x_buckv_set_voltage_int(rdev, reg, uV, uV);
279}
280
281static int wm831x_buckv_get_voltage(struct regulator_dev *rdev)
282{
283 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
284 struct wm831x *wm831x = dcdc->wm831x;
285 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
286 int val;
287
288 val = wm831x_reg_read(wm831x, reg);
289 if (val < 0)
290 return val;
291
292 return wm831x_buckv_list_voltage(rdev, val & WM831X_DC1_ON_VSEL_MASK);
293}
294
295/* Current limit options */
296static u16 wm831x_dcdc_ilim[] = {
297 125, 250, 375, 500, 625, 750, 875, 1000
298};
299
300static int wm831x_buckv_set_current_limit(struct regulator_dev *rdev,
301 int min_uA, int max_uA)
302{
303 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
304 struct wm831x *wm831x = dcdc->wm831x;
305 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
306 int i;
307
308 for (i = 0; i < ARRAY_SIZE(wm831x_dcdc_ilim); i++) {
309 if (max_uA <= wm831x_dcdc_ilim[i])
310 break;
311 }
312 if (i == ARRAY_SIZE(wm831x_dcdc_ilim))
313 return -EINVAL;
314
315 return wm831x_set_bits(wm831x, reg, WM831X_DC1_HC_THR_MASK, i);
316}
317
318static int wm831x_buckv_get_current_limit(struct regulator_dev *rdev)
319{
320 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
321 struct wm831x *wm831x = dcdc->wm831x;
322 u16 reg = dcdc->base + WM831X_DCDC_CONTROL_2;
323 int val;
324
325 val = wm831x_reg_read(wm831x, reg);
326 if (val < 0)
327 return val;
328
329 return wm831x_dcdc_ilim[val & WM831X_DC1_HC_THR_MASK];
330}
331
332static struct regulator_ops wm831x_buckv_ops = {
333 .set_voltage = wm831x_buckv_set_voltage,
334 .get_voltage = wm831x_buckv_get_voltage,
335 .list_voltage = wm831x_buckv_list_voltage,
336 .set_suspend_voltage = wm831x_buckv_set_suspend_voltage,
337 .set_current_limit = wm831x_buckv_set_current_limit,
338 .get_current_limit = wm831x_buckv_get_current_limit,
339
340 .is_enabled = wm831x_dcdc_is_enabled,
341 .enable = wm831x_dcdc_enable,
342 .disable = wm831x_dcdc_disable,
343 .get_status = wm831x_dcdc_get_status,
344 .get_mode = wm831x_dcdc_get_mode,
345 .set_mode = wm831x_dcdc_set_mode,
346 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
347};
348
349static __devinit int wm831x_buckv_probe(struct platform_device *pdev)
350{
351 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
352 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
353 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
354 struct wm831x_dcdc *dcdc;
355 struct resource *res;
356 int ret, irq;
357
358 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
359
360 if (pdata == NULL || pdata->dcdc[id] == NULL)
361 return -ENODEV;
362
363 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
364 if (dcdc == NULL) {
365 dev_err(&pdev->dev, "Unable to allocate private data\n");
366 return -ENOMEM;
367 }
368
369 dcdc->wm831x = wm831x;
370
371 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
372 if (res == NULL) {
373 dev_err(&pdev->dev, "No I/O resource\n");
374 ret = -EINVAL;
375 goto err;
376 }
377 dcdc->base = res->start;
378
379 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
380 dcdc->desc.name = dcdc->name;
381 dcdc->desc.id = id;
382 dcdc->desc.type = REGULATOR_VOLTAGE;
383 dcdc->desc.n_voltages = WM831X_BUCKV_MAX_SELECTOR + 1;
384 dcdc->desc.ops = &wm831x_buckv_ops;
385 dcdc->desc.owner = THIS_MODULE;
386
387 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
388 pdata->dcdc[id], dcdc);
389 if (IS_ERR(dcdc->regulator)) {
390 ret = PTR_ERR(dcdc->regulator);
391 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
392 id + 1, ret);
393 goto err;
394 }
395
396 irq = platform_get_irq_byname(pdev, "UV");
397 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_uv_irq,
398 IRQF_TRIGGER_RISING, dcdc->name,
399 dcdc);
400 if (ret != 0) {
401 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
402 irq, ret);
403 goto err_regulator;
404 }
405
406 irq = platform_get_irq_byname(pdev, "HC");
407 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_oc_irq,
408 IRQF_TRIGGER_RISING, dcdc->name,
409 dcdc);
410 if (ret != 0) {
411 dev_err(&pdev->dev, "Failed to request HC IRQ %d: %d\n",
412 irq, ret);
413 goto err_uv;
414 }
415
416 platform_set_drvdata(pdev, dcdc);
417
418 return 0;
419
420err_uv:
421 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
422err_regulator:
423 regulator_unregister(dcdc->regulator);
424err:
425 kfree(dcdc);
426 return ret;
427}
428
429static __devexit int wm831x_buckv_remove(struct platform_device *pdev)
430{
431 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
432 struct wm831x *wm831x = dcdc->wm831x;
433
434 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "HC"), dcdc);
435 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
436 regulator_unregister(dcdc->regulator);
437 kfree(dcdc);
438
439 return 0;
440}
441
442static struct platform_driver wm831x_buckv_driver = {
443 .probe = wm831x_buckv_probe,
444 .remove = __devexit_p(wm831x_buckv_remove),
445 .driver = {
446 .name = "wm831x-buckv",
447 },
448};
449
450/*
451 * BUCKP specifics
452 */
453
454static int wm831x_buckp_list_voltage(struct regulator_dev *rdev,
455 unsigned selector)
456{
457 if (selector <= WM831X_BUCKP_MAX_SELECTOR)
458 return 850000 + (selector * 25000);
459 else
460 return -EINVAL;
461}
462
463static int wm831x_buckp_set_voltage_int(struct regulator_dev *rdev, int reg,
464 int min_uV, int max_uV)
465{
466 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
467 struct wm831x *wm831x = dcdc->wm831x;
468 u16 vsel;
469
470 if (min_uV <= 34000000)
471 vsel = (min_uV - 850000) / 25000;
472 else
473 return -EINVAL;
474
475 if (wm831x_buckp_list_voltage(rdev, vsel) > max_uV)
476 return -EINVAL;
477
478 return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, vsel);
479}
480
481static int wm831x_buckp_set_voltage(struct regulator_dev *rdev,
482 int min_uV, int max_uV)
483{
484 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
485 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
486
487 return wm831x_buckp_set_voltage_int(rdev, reg, min_uV, max_uV);
488}
489
490static int wm831x_buckp_set_suspend_voltage(struct regulator_dev *rdev,
491 int uV)
492{
493 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
494 u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
495
496 return wm831x_buckp_set_voltage_int(rdev, reg, uV, uV);
497}
498
499static int wm831x_buckp_get_voltage(struct regulator_dev *rdev)
500{
501 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
502 struct wm831x *wm831x = dcdc->wm831x;
503 u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
504 int val;
505
506 val = wm831x_reg_read(wm831x, reg);
507 if (val < 0)
508 return val;
509
510 return wm831x_buckp_list_voltage(rdev, val & WM831X_DC3_ON_VSEL_MASK);
511}
512
513static struct regulator_ops wm831x_buckp_ops = {
514 .set_voltage = wm831x_buckp_set_voltage,
515 .get_voltage = wm831x_buckp_get_voltage,
516 .list_voltage = wm831x_buckp_list_voltage,
517 .set_suspend_voltage = wm831x_buckp_set_suspend_voltage,
518
519 .is_enabled = wm831x_dcdc_is_enabled,
520 .enable = wm831x_dcdc_enable,
521 .disable = wm831x_dcdc_disable,
522 .get_status = wm831x_dcdc_get_status,
523 .get_mode = wm831x_dcdc_get_mode,
524 .set_mode = wm831x_dcdc_set_mode,
525 .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
526};
527
528static __devinit int wm831x_buckp_probe(struct platform_device *pdev)
529{
530 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
531 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
532 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
533 struct wm831x_dcdc *dcdc;
534 struct resource *res;
535 int ret, irq;
536
537 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
538
539 if (pdata == NULL || pdata->dcdc[id] == NULL)
540 return -ENODEV;
541
542 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
543 if (dcdc == NULL) {
544 dev_err(&pdev->dev, "Unable to allocate private data\n");
545 return -ENOMEM;
546 }
547
548 dcdc->wm831x = wm831x;
549
550 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
551 if (res == NULL) {
552 dev_err(&pdev->dev, "No I/O resource\n");
553 ret = -EINVAL;
554 goto err;
555 }
556 dcdc->base = res->start;
557
558 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
559 dcdc->desc.name = dcdc->name;
560 dcdc->desc.id = id;
561 dcdc->desc.type = REGULATOR_VOLTAGE;
562 dcdc->desc.n_voltages = WM831X_BUCKP_MAX_SELECTOR + 1;
563 dcdc->desc.ops = &wm831x_buckp_ops;
564 dcdc->desc.owner = THIS_MODULE;
565
566 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
567 pdata->dcdc[id], dcdc);
568 if (IS_ERR(dcdc->regulator)) {
569 ret = PTR_ERR(dcdc->regulator);
570 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
571 id + 1, ret);
572 goto err;
573 }
574
575 irq = platform_get_irq_byname(pdev, "UV");
576 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_uv_irq,
577 IRQF_TRIGGER_RISING, dcdc->name,
578 dcdc);
579 if (ret != 0) {
580 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
581 irq, ret);
582 goto err_regulator;
583 }
584
585 platform_set_drvdata(pdev, dcdc);
586
587 return 0;
588
589err_regulator:
590 regulator_unregister(dcdc->regulator);
591err:
592 kfree(dcdc);
593 return ret;
594}
595
596static __devexit int wm831x_buckp_remove(struct platform_device *pdev)
597{
598 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
599 struct wm831x *wm831x = dcdc->wm831x;
600
601 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
602 regulator_unregister(dcdc->regulator);
603 kfree(dcdc);
604
605 return 0;
606}
607
608static struct platform_driver wm831x_buckp_driver = {
609 .probe = wm831x_buckp_probe,
610 .remove = __devexit_p(wm831x_buckp_remove),
611 .driver = {
612 .name = "wm831x-buckp",
613 },
614};
615
616/*
617 * DCDC boost convertors
618 */
619
620static int wm831x_boostp_get_status(struct regulator_dev *rdev)
621{
622 struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
623 struct wm831x *wm831x = dcdc->wm831x;
624 int ret;
625
626 /* First, check for errors */
627 ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
628 if (ret < 0)
629 return ret;
630
631 if (ret & (1 << rdev_get_id(rdev))) {
632 dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
633 rdev_get_id(rdev) + 1);
634 return REGULATOR_STATUS_ERROR;
635 }
636
637 /* Is the regulator on? */
638 ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
639 if (ret < 0)
640 return ret;
641 if (ret & (1 << rdev_get_id(rdev)))
642 return REGULATOR_STATUS_ON;
643 else
644 return REGULATOR_STATUS_OFF;
645}
646
647static struct regulator_ops wm831x_boostp_ops = {
648 .get_status = wm831x_boostp_get_status,
649
650 .is_enabled = wm831x_dcdc_is_enabled,
651 .enable = wm831x_dcdc_enable,
652 .disable = wm831x_dcdc_disable,
653};
654
655static __devinit int wm831x_boostp_probe(struct platform_device *pdev)
656{
657 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
658 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
659 int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
660 struct wm831x_dcdc *dcdc;
661 struct resource *res;
662 int ret, irq;
663
664 dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
665
666 if (pdata == NULL || pdata->dcdc[id] == NULL)
667 return -ENODEV;
668
669 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
670 if (dcdc == NULL) {
671 dev_err(&pdev->dev, "Unable to allocate private data\n");
672 return -ENOMEM;
673 }
674
675 dcdc->wm831x = wm831x;
676
677 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
678 if (res == NULL) {
679 dev_err(&pdev->dev, "No I/O resource\n");
680 ret = -EINVAL;
681 goto err;
682 }
683 dcdc->base = res->start;
684
685 snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
686 dcdc->desc.name = dcdc->name;
687 dcdc->desc.id = id;
688 dcdc->desc.type = REGULATOR_VOLTAGE;
689 dcdc->desc.ops = &wm831x_boostp_ops;
690 dcdc->desc.owner = THIS_MODULE;
691
692 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
693 pdata->dcdc[id], dcdc);
694 if (IS_ERR(dcdc->regulator)) {
695 ret = PTR_ERR(dcdc->regulator);
696 dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
697 id + 1, ret);
698 goto err;
699 }
700
701 irq = platform_get_irq_byname(pdev, "UV");
702 ret = wm831x_request_irq(wm831x, irq, wm831x_dcdc_uv_irq,
703 IRQF_TRIGGER_RISING, dcdc->name,
704 dcdc);
705 if (ret != 0) {
706 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
707 irq, ret);
708 goto err_regulator;
709 }
710
711 platform_set_drvdata(pdev, dcdc);
712
713 return 0;
714
715err_regulator:
716 regulator_unregister(dcdc->regulator);
717err:
718 kfree(dcdc);
719 return ret;
720}
721
722static __devexit int wm831x_boostp_remove(struct platform_device *pdev)
723{
724 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
725 struct wm831x *wm831x = dcdc->wm831x;
726
727 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc);
728 regulator_unregister(dcdc->regulator);
729 kfree(dcdc);
730
731 return 0;
732}
733
734static struct platform_driver wm831x_boostp_driver = {
735 .probe = wm831x_boostp_probe,
736 .remove = __devexit_p(wm831x_boostp_remove),
737 .driver = {
738 .name = "wm831x-boostp",
739 },
740};
741
742/*
743 * External Power Enable
744 *
745 * These aren't actually DCDCs but look like them in hardware so share
746 * code.
747 */
748
749#define WM831X_EPE_BASE 6
750
751static struct regulator_ops wm831x_epe_ops = {
752 .is_enabled = wm831x_dcdc_is_enabled,
753 .enable = wm831x_dcdc_enable,
754 .disable = wm831x_dcdc_disable,
755 .get_status = wm831x_dcdc_get_status,
756};
757
758static __devinit int wm831x_epe_probe(struct platform_device *pdev)
759{
760 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
761 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
762 int id = pdev->id % ARRAY_SIZE(pdata->epe);
763 struct wm831x_dcdc *dcdc;
764 int ret;
765
766 dev_dbg(&pdev->dev, "Probing EPE%d\n", id + 1);
767
768 if (pdata == NULL || pdata->epe[id] == NULL)
769 return -ENODEV;
770
771 dcdc = kzalloc(sizeof(struct wm831x_dcdc), GFP_KERNEL);
772 if (dcdc == NULL) {
773 dev_err(&pdev->dev, "Unable to allocate private data\n");
774 return -ENOMEM;
775 }
776
777 dcdc->wm831x = wm831x;
778
779 /* For current parts this is correct; probably need to revisit
780 * in future.
781 */
782 snprintf(dcdc->name, sizeof(dcdc->name), "EPE%d", id + 1);
783 dcdc->desc.name = dcdc->name;
784 dcdc->desc.id = id + WM831X_EPE_BASE; /* Offset in DCDC registers */
785 dcdc->desc.ops = &wm831x_epe_ops;
786 dcdc->desc.type = REGULATOR_VOLTAGE;
787 dcdc->desc.owner = THIS_MODULE;
788
789 dcdc->regulator = regulator_register(&dcdc->desc, &pdev->dev,
790 pdata->epe[id], dcdc);
791 if (IS_ERR(dcdc->regulator)) {
792 ret = PTR_ERR(dcdc->regulator);
793 dev_err(wm831x->dev, "Failed to register EPE%d: %d\n",
794 id + 1, ret);
795 goto err;
796 }
797
798 platform_set_drvdata(pdev, dcdc);
799
800 return 0;
801
802err:
803 kfree(dcdc);
804 return ret;
805}
806
807static __devexit int wm831x_epe_remove(struct platform_device *pdev)
808{
809 struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev);
810
811 regulator_unregister(dcdc->regulator);
812 kfree(dcdc);
813
814 return 0;
815}
816
817static struct platform_driver wm831x_epe_driver = {
818 .probe = wm831x_epe_probe,
819 .remove = __devexit_p(wm831x_epe_remove),
820 .driver = {
821 .name = "wm831x-epe",
822 },
823};
824
825static int __init wm831x_dcdc_init(void)
826{
827 int ret;
828 ret = platform_driver_register(&wm831x_buckv_driver);
829 if (ret != 0)
830 pr_err("Failed to register WM831x BUCKV driver: %d\n", ret);
831
832 ret = platform_driver_register(&wm831x_buckp_driver);
833 if (ret != 0)
834 pr_err("Failed to register WM831x BUCKP driver: %d\n", ret);
835
836 ret = platform_driver_register(&wm831x_boostp_driver);
837 if (ret != 0)
838 pr_err("Failed to register WM831x BOOST driver: %d\n", ret);
839
840 ret = platform_driver_register(&wm831x_epe_driver);
841 if (ret != 0)
842 pr_err("Failed to register WM831x EPE driver: %d\n", ret);
843
844 return 0;
845}
846subsys_initcall(wm831x_dcdc_init);
847
848static void __exit wm831x_dcdc_exit(void)
849{
850 platform_driver_unregister(&wm831x_epe_driver);
851 platform_driver_unregister(&wm831x_boostp_driver);
852 platform_driver_unregister(&wm831x_buckp_driver);
853 platform_driver_unregister(&wm831x_buckv_driver);
854}
855module_exit(wm831x_dcdc_exit);
856
857/* Module information */
858MODULE_AUTHOR("Mark Brown");
859MODULE_DESCRIPTION("WM831x DC-DC convertor driver");
860MODULE_LICENSE("GPL");
861MODULE_ALIAS("platform:wm831x-buckv");
862MODULE_ALIAS("platform:wm831x-buckp");
diff --git a/drivers/regulator/wm831x-isink.c b/drivers/regulator/wm831x-isink.c
new file mode 100644
index 000000000000..1d8d9879d3a1
--- /dev/null
+++ b/drivers/regulator/wm831x-isink.c
@@ -0,0 +1,260 @@
1/*
2 * wm831x-isink.c -- Current sink driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/regulator.h>
25#include <linux/mfd/wm831x/pdata.h>
26
27#define WM831X_ISINK_MAX_NAME 7
28
29struct wm831x_isink {
30 char name[WM831X_ISINK_MAX_NAME];
31 struct regulator_desc desc;
32 int reg;
33 struct wm831x *wm831x;
34 struct regulator_dev *regulator;
35};
36
37static int wm831x_isink_enable(struct regulator_dev *rdev)
38{
39 struct wm831x_isink *isink = rdev_get_drvdata(rdev);
40 struct wm831x *wm831x = isink->wm831x;
41 int ret;
42
43 /* We have a two stage enable: first start the ISINK... */
44 ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA,
45 WM831X_CS1_ENA);
46 if (ret != 0)
47 return ret;
48
49 /* ...then enable drive */
50 ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_DRIVE,
51 WM831X_CS1_DRIVE);
52 if (ret != 0)
53 wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA, 0);
54
55 return ret;
56
57}
58
59static int wm831x_isink_disable(struct regulator_dev *rdev)
60{
61 struct wm831x_isink *isink = rdev_get_drvdata(rdev);
62 struct wm831x *wm831x = isink->wm831x;
63 int ret;
64
65 ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_DRIVE, 0);
66 if (ret < 0)
67 return ret;
68
69 ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA, 0);
70 if (ret < 0)
71 return ret;
72
73 return ret;
74
75}
76
77static int wm831x_isink_is_enabled(struct regulator_dev *rdev)
78{
79 struct wm831x_isink *isink = rdev_get_drvdata(rdev);
80 struct wm831x *wm831x = isink->wm831x;
81 int ret;
82
83 ret = wm831x_reg_read(wm831x, isink->reg);
84 if (ret < 0)
85 return ret;
86
87 if ((ret & (WM831X_CS1_ENA | WM831X_CS1_DRIVE)) ==
88 (WM831X_CS1_ENA | WM831X_CS1_DRIVE))
89 return 1;
90 else
91 return 0;
92}
93
94static int wm831x_isink_set_current(struct regulator_dev *rdev,
95 int min_uA, int max_uA)
96{
97 struct wm831x_isink *isink = rdev_get_drvdata(rdev);
98 struct wm831x *wm831x = isink->wm831x;
99 int ret, i;
100
101 for (i = 0; i < ARRAY_SIZE(wm831x_isinkv_values); i++) {
102 int val = wm831x_isinkv_values[i];
103 if (min_uA >= val && val <= max_uA) {
104 ret = wm831x_set_bits(wm831x, isink->reg,
105 WM831X_CS1_ISEL_MASK, i);
106 return ret;
107 }
108 }
109
110 return -EINVAL;
111}
112
113static int wm831x_isink_get_current(struct regulator_dev *rdev)
114{
115 struct wm831x_isink *isink = rdev_get_drvdata(rdev);
116 struct wm831x *wm831x = isink->wm831x;
117 int ret;
118
119 ret = wm831x_reg_read(wm831x, isink->reg);
120 if (ret < 0)
121 return ret;
122
123 ret &= WM831X_CS1_ISEL_MASK;
124 if (ret > WM831X_ISINK_MAX_ISEL)
125 ret = WM831X_ISINK_MAX_ISEL;
126
127 return wm831x_isinkv_values[ret];
128}
129
130static struct regulator_ops wm831x_isink_ops = {
131 .is_enabled = wm831x_isink_is_enabled,
132 .enable = wm831x_isink_enable,
133 .disable = wm831x_isink_disable,
134 .set_current_limit = wm831x_isink_set_current,
135 .get_current_limit = wm831x_isink_get_current,
136};
137
138static irqreturn_t wm831x_isink_irq(int irq, void *data)
139{
140 struct wm831x_isink *isink = data;
141
142 regulator_notifier_call_chain(isink->regulator,
143 REGULATOR_EVENT_OVER_CURRENT,
144 NULL);
145
146 return IRQ_HANDLED;
147}
148
149
150static __devinit int wm831x_isink_probe(struct platform_device *pdev)
151{
152 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
153 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
154 struct wm831x_isink *isink;
155 int id = pdev->id % ARRAY_SIZE(pdata->isink);
156 struct resource *res;
157 int ret, irq;
158
159 dev_dbg(&pdev->dev, "Probing ISINK%d\n", id + 1);
160
161 if (pdata == NULL || pdata->isink[id] == NULL)
162 return -ENODEV;
163
164 isink = kzalloc(sizeof(struct wm831x_isink), GFP_KERNEL);
165 if (isink == NULL) {
166 dev_err(&pdev->dev, "Unable to allocate private data\n");
167 return -ENOMEM;
168 }
169
170 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
171 if (res == NULL) {
172 dev_err(&pdev->dev, "No I/O resource\n");
173 ret = -EINVAL;
174 goto err;
175 }
176 isink->reg = res->start;
177
178 /* For current parts this is correct; probably need to revisit
179 * in future.
180 */
181 snprintf(isink->name, sizeof(isink->name), "ISINK%d", id + 1);
182 isink->desc.name = isink->name;
183 isink->desc.id = id;
184 isink->desc.ops = &wm831x_isink_ops;
185 isink->desc.type = REGULATOR_CURRENT;
186 isink->desc.owner = THIS_MODULE;
187
188 isink->regulator = regulator_register(&isink->desc, &pdev->dev,
189 pdata->isink[id], isink);
190 if (IS_ERR(isink->regulator)) {
191 ret = PTR_ERR(isink->regulator);
192 dev_err(wm831x->dev, "Failed to register ISINK%d: %d\n",
193 id + 1, ret);
194 goto err;
195 }
196
197 irq = platform_get_irq(pdev, 0);
198 ret = wm831x_request_irq(wm831x, irq, wm831x_isink_irq,
199 IRQF_TRIGGER_RISING, isink->name,
200 isink);
201 if (ret != 0) {
202 dev_err(&pdev->dev, "Failed to request ISINK IRQ %d: %d\n",
203 irq, ret);
204 goto err_regulator;
205 }
206
207 platform_set_drvdata(pdev, isink);
208
209 return 0;
210
211err_regulator:
212 regulator_unregister(isink->regulator);
213err:
214 kfree(isink);
215 return ret;
216}
217
218static __devexit int wm831x_isink_remove(struct platform_device *pdev)
219{
220 struct wm831x_isink *isink = platform_get_drvdata(pdev);
221 struct wm831x *wm831x = isink->wm831x;
222
223 wm831x_free_irq(wm831x, platform_get_irq(pdev, 0), isink);
224
225 regulator_unregister(isink->regulator);
226 kfree(isink);
227
228 return 0;
229}
230
231static struct platform_driver wm831x_isink_driver = {
232 .probe = wm831x_isink_probe,
233 .remove = __devexit_p(wm831x_isink_remove),
234 .driver = {
235 .name = "wm831x-isink",
236 },
237};
238
239static int __init wm831x_isink_init(void)
240{
241 int ret;
242 ret = platform_driver_register(&wm831x_isink_driver);
243 if (ret != 0)
244 pr_err("Failed to register WM831x ISINK driver: %d\n", ret);
245
246 return ret;
247}
248subsys_initcall(wm831x_isink_init);
249
250static void __exit wm831x_isink_exit(void)
251{
252 platform_driver_unregister(&wm831x_isink_driver);
253}
254module_exit(wm831x_isink_exit);
255
256/* Module information */
257MODULE_AUTHOR("Mark Brown");
258MODULE_DESCRIPTION("WM831x current sink driver");
259MODULE_LICENSE("GPL");
260MODULE_ALIAS("platform:wm831x-isink");
diff --git a/drivers/regulator/wm831x-ldo.c b/drivers/regulator/wm831x-ldo.c
new file mode 100644
index 000000000000..bb61aede4801
--- /dev/null
+++ b/drivers/regulator/wm831x-ldo.c
@@ -0,0 +1,852 @@
1/*
2 * wm831x-ldo.c -- LDO driver for the WM831x series
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22
23#include <linux/mfd/wm831x/core.h>
24#include <linux/mfd/wm831x/regulator.h>
25#include <linux/mfd/wm831x/pdata.h>
26
27#define WM831X_LDO_MAX_NAME 6
28
29#define WM831X_LDO_CONTROL 0
30#define WM831X_LDO_ON_CONTROL 1
31#define WM831X_LDO_SLEEP_CONTROL 2
32
33#define WM831X_ALIVE_LDO_ON_CONTROL 0
34#define WM831X_ALIVE_LDO_SLEEP_CONTROL 1
35
36struct wm831x_ldo {
37 char name[WM831X_LDO_MAX_NAME];
38 struct regulator_desc desc;
39 int base;
40 struct wm831x *wm831x;
41 struct regulator_dev *regulator;
42};
43
44/*
45 * Shared
46 */
47
48static int wm831x_ldo_is_enabled(struct regulator_dev *rdev)
49{
50 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
51 struct wm831x *wm831x = ldo->wm831x;
52 int mask = 1 << rdev_get_id(rdev);
53 int reg;
54
55 reg = wm831x_reg_read(wm831x, WM831X_LDO_ENABLE);
56 if (reg < 0)
57 return reg;
58
59 if (reg & mask)
60 return 1;
61 else
62 return 0;
63}
64
65static int wm831x_ldo_enable(struct regulator_dev *rdev)
66{
67 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
68 struct wm831x *wm831x = ldo->wm831x;
69 int mask = 1 << rdev_get_id(rdev);
70
71 return wm831x_set_bits(wm831x, WM831X_LDO_ENABLE, mask, mask);
72}
73
74static int wm831x_ldo_disable(struct regulator_dev *rdev)
75{
76 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
77 struct wm831x *wm831x = ldo->wm831x;
78 int mask = 1 << rdev_get_id(rdev);
79
80 return wm831x_set_bits(wm831x, WM831X_LDO_ENABLE, mask, 0);
81}
82
83static irqreturn_t wm831x_ldo_uv_irq(int irq, void *data)
84{
85 struct wm831x_ldo *ldo = data;
86
87 regulator_notifier_call_chain(ldo->regulator,
88 REGULATOR_EVENT_UNDER_VOLTAGE,
89 NULL);
90
91 return IRQ_HANDLED;
92}
93
94/*
95 * General purpose LDOs
96 */
97
98#define WM831X_GP_LDO_SELECTOR_LOW 0xe
99#define WM831X_GP_LDO_MAX_SELECTOR 0x1f
100
101static int wm831x_gp_ldo_list_voltage(struct regulator_dev *rdev,
102 unsigned int selector)
103{
104 /* 0.9-1.6V in 50mV steps */
105 if (selector <= WM831X_GP_LDO_SELECTOR_LOW)
106 return 900000 + (selector * 50000);
107 /* 1.7-3.3V in 50mV steps */
108 if (selector <= WM831X_GP_LDO_MAX_SELECTOR)
109 return 1600000 + ((selector - WM831X_GP_LDO_SELECTOR_LOW)
110 * 100000);
111 return -EINVAL;
112}
113
114static int wm831x_gp_ldo_set_voltage_int(struct regulator_dev *rdev, int reg,
115 int min_uV, int max_uV)
116{
117 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
118 struct wm831x *wm831x = ldo->wm831x;
119 int vsel, ret;
120
121 if (min_uV < 900000)
122 vsel = 0;
123 else if (min_uV < 1700000)
124 vsel = ((min_uV - 900000) / 50000);
125 else
126 vsel = ((min_uV - 1700000) / 100000)
127 + WM831X_GP_LDO_SELECTOR_LOW + 1;
128
129 ret = wm831x_gp_ldo_list_voltage(rdev, vsel);
130 if (ret < 0)
131 return ret;
132 if (ret < min_uV || ret > max_uV)
133 return -EINVAL;
134
135 return wm831x_set_bits(wm831x, reg, WM831X_LDO1_ON_VSEL_MASK, vsel);
136}
137
138static int wm831x_gp_ldo_set_voltage(struct regulator_dev *rdev,
139 int min_uV, int max_uV)
140{
141 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
142 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
143
144 return wm831x_gp_ldo_set_voltage_int(rdev, reg, min_uV, max_uV);
145}
146
147static int wm831x_gp_ldo_set_suspend_voltage(struct regulator_dev *rdev,
148 int uV)
149{
150 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
151 int reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
152
153 return wm831x_gp_ldo_set_voltage_int(rdev, reg, uV, uV);
154}
155
156static int wm831x_gp_ldo_get_voltage(struct regulator_dev *rdev)
157{
158 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
159 struct wm831x *wm831x = ldo->wm831x;
160 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
161 int ret;
162
163 ret = wm831x_reg_read(wm831x, reg);
164 if (ret < 0)
165 return ret;
166
167 ret &= WM831X_LDO1_ON_VSEL_MASK;
168
169 return wm831x_gp_ldo_list_voltage(rdev, ret);
170}
171
172static unsigned int wm831x_gp_ldo_get_mode(struct regulator_dev *rdev)
173{
174 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
175 struct wm831x *wm831x = ldo->wm831x;
176 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
177 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
178 unsigned int ret;
179
180 ret = wm831x_reg_read(wm831x, on_reg);
181 if (ret < 0)
182 return 0;
183
184 if (!(ret & WM831X_LDO1_ON_MODE))
185 return REGULATOR_MODE_NORMAL;
186
187 ret = wm831x_reg_read(wm831x, ctrl_reg);
188 if (ret < 0)
189 return 0;
190
191 if (ret & WM831X_LDO1_LP_MODE)
192 return REGULATOR_MODE_STANDBY;
193 else
194 return REGULATOR_MODE_IDLE;
195}
196
197static int wm831x_gp_ldo_set_mode(struct regulator_dev *rdev,
198 unsigned int mode)
199{
200 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
201 struct wm831x *wm831x = ldo->wm831x;
202 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
203 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
204 int ret;
205
206
207 switch (mode) {
208 case REGULATOR_MODE_NORMAL:
209 ret = wm831x_set_bits(wm831x, on_reg,
210 WM831X_LDO1_ON_MODE, 0);
211 if (ret < 0)
212 return ret;
213 break;
214
215 case REGULATOR_MODE_IDLE:
216 ret = wm831x_set_bits(wm831x, ctrl_reg,
217 WM831X_LDO1_LP_MODE,
218 WM831X_LDO1_LP_MODE);
219 if (ret < 0)
220 return ret;
221
222 ret = wm831x_set_bits(wm831x, on_reg,
223 WM831X_LDO1_ON_MODE,
224 WM831X_LDO1_ON_MODE);
225 if (ret < 0)
226 return ret;
227
228 case REGULATOR_MODE_STANDBY:
229 ret = wm831x_set_bits(wm831x, ctrl_reg,
230 WM831X_LDO1_LP_MODE, 0);
231 if (ret < 0)
232 return ret;
233
234 ret = wm831x_set_bits(wm831x, on_reg,
235 WM831X_LDO1_ON_MODE,
236 WM831X_LDO1_ON_MODE);
237 if (ret < 0)
238 return ret;
239 break;
240
241 default:
242 return -EINVAL;
243 }
244
245 return 0;
246}
247
248static int wm831x_gp_ldo_get_status(struct regulator_dev *rdev)
249{
250 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
251 struct wm831x *wm831x = ldo->wm831x;
252 int mask = 1 << rdev_get_id(rdev);
253 int ret;
254
255 /* Is the regulator on? */
256 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
257 if (ret < 0)
258 return ret;
259 if (!(ret & mask))
260 return REGULATOR_STATUS_OFF;
261
262 /* Is it reporting under voltage? */
263 ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
264 if (ret & mask)
265 return REGULATOR_STATUS_ERROR;
266
267 ret = wm831x_gp_ldo_get_mode(rdev);
268 if (ret < 0)
269 return ret;
270 else
271 return regulator_mode_to_status(ret);
272}
273
274static unsigned int wm831x_gp_ldo_get_optimum_mode(struct regulator_dev *rdev,
275 int input_uV,
276 int output_uV, int load_uA)
277{
278 if (load_uA < 20000)
279 return REGULATOR_MODE_STANDBY;
280 if (load_uA < 50000)
281 return REGULATOR_MODE_IDLE;
282 return REGULATOR_MODE_NORMAL;
283}
284
285
286static struct regulator_ops wm831x_gp_ldo_ops = {
287 .list_voltage = wm831x_gp_ldo_list_voltage,
288 .get_voltage = wm831x_gp_ldo_get_voltage,
289 .set_voltage = wm831x_gp_ldo_set_voltage,
290 .set_suspend_voltage = wm831x_gp_ldo_set_suspend_voltage,
291 .get_mode = wm831x_gp_ldo_get_mode,
292 .set_mode = wm831x_gp_ldo_set_mode,
293 .get_status = wm831x_gp_ldo_get_status,
294 .get_optimum_mode = wm831x_gp_ldo_get_optimum_mode,
295
296 .is_enabled = wm831x_ldo_is_enabled,
297 .enable = wm831x_ldo_enable,
298 .disable = wm831x_ldo_disable,
299};
300
301static __devinit int wm831x_gp_ldo_probe(struct platform_device *pdev)
302{
303 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
304 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
305 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
306 struct wm831x_ldo *ldo;
307 struct resource *res;
308 int ret, irq;
309
310 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
311
312 if (pdata == NULL || pdata->ldo[id] == NULL)
313 return -ENODEV;
314
315 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
316 if (ldo == NULL) {
317 dev_err(&pdev->dev, "Unable to allocate private data\n");
318 return -ENOMEM;
319 }
320
321 ldo->wm831x = wm831x;
322
323 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
324 if (res == NULL) {
325 dev_err(&pdev->dev, "No I/O resource\n");
326 ret = -EINVAL;
327 goto err;
328 }
329 ldo->base = res->start;
330
331 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
332 ldo->desc.name = ldo->name;
333 ldo->desc.id = id;
334 ldo->desc.type = REGULATOR_VOLTAGE;
335 ldo->desc.n_voltages = WM831X_GP_LDO_MAX_SELECTOR + 1;
336 ldo->desc.ops = &wm831x_gp_ldo_ops;
337 ldo->desc.owner = THIS_MODULE;
338
339 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
340 pdata->ldo[id], ldo);
341 if (IS_ERR(ldo->regulator)) {
342 ret = PTR_ERR(ldo->regulator);
343 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
344 id + 1, ret);
345 goto err;
346 }
347
348 irq = platform_get_irq_byname(pdev, "UV");
349 ret = wm831x_request_irq(wm831x, irq, wm831x_ldo_uv_irq,
350 IRQF_TRIGGER_RISING, ldo->name,
351 ldo);
352 if (ret != 0) {
353 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
354 irq, ret);
355 goto err_regulator;
356 }
357
358 platform_set_drvdata(pdev, ldo);
359
360 return 0;
361
362err_regulator:
363 regulator_unregister(ldo->regulator);
364err:
365 kfree(ldo);
366 return ret;
367}
368
369static __devexit int wm831x_gp_ldo_remove(struct platform_device *pdev)
370{
371 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
372 struct wm831x *wm831x = ldo->wm831x;
373
374 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), ldo);
375 regulator_unregister(ldo->regulator);
376 kfree(ldo);
377
378 return 0;
379}
380
381static struct platform_driver wm831x_gp_ldo_driver = {
382 .probe = wm831x_gp_ldo_probe,
383 .remove = __devexit_p(wm831x_gp_ldo_remove),
384 .driver = {
385 .name = "wm831x-ldo",
386 },
387};
388
389/*
390 * Analogue LDOs
391 */
392
393
394#define WM831X_ALDO_SELECTOR_LOW 0xc
395#define WM831X_ALDO_MAX_SELECTOR 0x1f
396
397static int wm831x_aldo_list_voltage(struct regulator_dev *rdev,
398 unsigned int selector)
399{
400 /* 1-1.6V in 50mV steps */
401 if (selector <= WM831X_ALDO_SELECTOR_LOW)
402 return 1000000 + (selector * 50000);
403 /* 1.7-3.5V in 50mV steps */
404 if (selector <= WM831X_ALDO_MAX_SELECTOR)
405 return 1600000 + ((selector - WM831X_ALDO_SELECTOR_LOW)
406 * 100000);
407 return -EINVAL;
408}
409
410static int wm831x_aldo_set_voltage_int(struct regulator_dev *rdev, int reg,
411 int min_uV, int max_uV)
412{
413 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
414 struct wm831x *wm831x = ldo->wm831x;
415 int vsel, ret;
416
417 if (min_uV < 1000000)
418 vsel = 0;
419 else if (min_uV < 1700000)
420 vsel = ((min_uV - 1000000) / 50000);
421 else
422 vsel = ((min_uV - 1700000) / 100000)
423 + WM831X_ALDO_SELECTOR_LOW + 1;
424
425 ret = wm831x_aldo_list_voltage(rdev, vsel);
426 if (ret < 0)
427 return ret;
428 if (ret < min_uV || ret > max_uV)
429 return -EINVAL;
430
431 return wm831x_set_bits(wm831x, reg, WM831X_LDO7_ON_VSEL_MASK, vsel);
432}
433
434static int wm831x_aldo_set_voltage(struct regulator_dev *rdev,
435 int min_uV, int max_uV)
436{
437 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
438 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
439
440 return wm831x_aldo_set_voltage_int(rdev, reg, min_uV, max_uV);
441}
442
443static int wm831x_aldo_set_suspend_voltage(struct regulator_dev *rdev,
444 int uV)
445{
446 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
447 int reg = ldo->base + WM831X_LDO_SLEEP_CONTROL;
448
449 return wm831x_aldo_set_voltage_int(rdev, reg, uV, uV);
450}
451
452static int wm831x_aldo_get_voltage(struct regulator_dev *rdev)
453{
454 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
455 struct wm831x *wm831x = ldo->wm831x;
456 int reg = ldo->base + WM831X_LDO_ON_CONTROL;
457 int ret;
458
459 ret = wm831x_reg_read(wm831x, reg);
460 if (ret < 0)
461 return ret;
462
463 ret &= WM831X_LDO7_ON_VSEL_MASK;
464
465 return wm831x_aldo_list_voltage(rdev, ret);
466}
467
468static unsigned int wm831x_aldo_get_mode(struct regulator_dev *rdev)
469{
470 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
471 struct wm831x *wm831x = ldo->wm831x;
472 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
473 unsigned int ret;
474
475 ret = wm831x_reg_read(wm831x, on_reg);
476 if (ret < 0)
477 return 0;
478
479 if (ret & WM831X_LDO7_ON_MODE)
480 return REGULATOR_MODE_IDLE;
481 else
482 return REGULATOR_MODE_NORMAL;
483}
484
485static int wm831x_aldo_set_mode(struct regulator_dev *rdev,
486 unsigned int mode)
487{
488 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
489 struct wm831x *wm831x = ldo->wm831x;
490 int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
491 int on_reg = ldo->base + WM831X_LDO_ON_CONTROL;
492 int ret;
493
494
495 switch (mode) {
496 case REGULATOR_MODE_NORMAL:
497 ret = wm831x_set_bits(wm831x, on_reg,
498 WM831X_LDO7_ON_MODE, 0);
499 if (ret < 0)
500 return ret;
501 break;
502
503 case REGULATOR_MODE_IDLE:
504 ret = wm831x_set_bits(wm831x, ctrl_reg,
505 WM831X_LDO7_ON_MODE,
506 WM831X_LDO7_ON_MODE);
507 if (ret < 0)
508 return ret;
509 break;
510
511 default:
512 return -EINVAL;
513 }
514
515 return 0;
516}
517
518static int wm831x_aldo_get_status(struct regulator_dev *rdev)
519{
520 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
521 struct wm831x *wm831x = ldo->wm831x;
522 int mask = 1 << rdev_get_id(rdev);
523 int ret;
524
525 /* Is the regulator on? */
526 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
527 if (ret < 0)
528 return ret;
529 if (!(ret & mask))
530 return REGULATOR_STATUS_OFF;
531
532 /* Is it reporting under voltage? */
533 ret = wm831x_reg_read(wm831x, WM831X_LDO_UV_STATUS);
534 if (ret & mask)
535 return REGULATOR_STATUS_ERROR;
536
537 ret = wm831x_aldo_get_mode(rdev);
538 if (ret < 0)
539 return ret;
540 else
541 return regulator_mode_to_status(ret);
542}
543
544static struct regulator_ops wm831x_aldo_ops = {
545 .list_voltage = wm831x_aldo_list_voltage,
546 .get_voltage = wm831x_aldo_get_voltage,
547 .set_voltage = wm831x_aldo_set_voltage,
548 .set_suspend_voltage = wm831x_aldo_set_suspend_voltage,
549 .get_mode = wm831x_aldo_get_mode,
550 .set_mode = wm831x_aldo_set_mode,
551 .get_status = wm831x_aldo_get_status,
552
553 .is_enabled = wm831x_ldo_is_enabled,
554 .enable = wm831x_ldo_enable,
555 .disable = wm831x_ldo_disable,
556};
557
558static __devinit int wm831x_aldo_probe(struct platform_device *pdev)
559{
560 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
561 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
562 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
563 struct wm831x_ldo *ldo;
564 struct resource *res;
565 int ret, irq;
566
567 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
568
569 if (pdata == NULL || pdata->ldo[id] == NULL)
570 return -ENODEV;
571
572 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
573 if (ldo == NULL) {
574 dev_err(&pdev->dev, "Unable to allocate private data\n");
575 return -ENOMEM;
576 }
577
578 ldo->wm831x = wm831x;
579
580 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
581 if (res == NULL) {
582 dev_err(&pdev->dev, "No I/O resource\n");
583 ret = -EINVAL;
584 goto err;
585 }
586 ldo->base = res->start;
587
588 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
589 ldo->desc.name = ldo->name;
590 ldo->desc.id = id;
591 ldo->desc.type = REGULATOR_VOLTAGE;
592 ldo->desc.n_voltages = WM831X_ALDO_MAX_SELECTOR + 1;
593 ldo->desc.ops = &wm831x_aldo_ops;
594 ldo->desc.owner = THIS_MODULE;
595
596 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
597 pdata->ldo[id], ldo);
598 if (IS_ERR(ldo->regulator)) {
599 ret = PTR_ERR(ldo->regulator);
600 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
601 id + 1, ret);
602 goto err;
603 }
604
605 irq = platform_get_irq_byname(pdev, "UV");
606 ret = wm831x_request_irq(wm831x, irq, wm831x_ldo_uv_irq,
607 IRQF_TRIGGER_RISING, ldo->name,
608 ldo);
609 if (ret != 0) {
610 dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
611 irq, ret);
612 goto err_regulator;
613 }
614
615 platform_set_drvdata(pdev, ldo);
616
617 return 0;
618
619err_regulator:
620 regulator_unregister(ldo->regulator);
621err:
622 kfree(ldo);
623 return ret;
624}
625
626static __devexit int wm831x_aldo_remove(struct platform_device *pdev)
627{
628 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
629 struct wm831x *wm831x = ldo->wm831x;
630
631 wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), ldo);
632 regulator_unregister(ldo->regulator);
633 kfree(ldo);
634
635 return 0;
636}
637
638static struct platform_driver wm831x_aldo_driver = {
639 .probe = wm831x_aldo_probe,
640 .remove = __devexit_p(wm831x_aldo_remove),
641 .driver = {
642 .name = "wm831x-aldo",
643 },
644};
645
646/*
647 * Alive LDO
648 */
649
650#define WM831X_ALIVE_LDO_MAX_SELECTOR 0xf
651
652static int wm831x_alive_ldo_list_voltage(struct regulator_dev *rdev,
653 unsigned int selector)
654{
655 /* 0.8-1.55V in 50mV steps */
656 if (selector <= WM831X_ALIVE_LDO_MAX_SELECTOR)
657 return 800000 + (selector * 50000);
658 return -EINVAL;
659}
660
661static int wm831x_alive_ldo_set_voltage_int(struct regulator_dev *rdev,
662 int reg,
663 int min_uV, int max_uV)
664{
665 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
666 struct wm831x *wm831x = ldo->wm831x;
667 int vsel, ret;
668
669 vsel = (min_uV - 800000) / 50000;
670
671 ret = wm831x_alive_ldo_list_voltage(rdev, vsel);
672 if (ret < 0)
673 return ret;
674 if (ret < min_uV || ret > max_uV)
675 return -EINVAL;
676
677 return wm831x_set_bits(wm831x, reg, WM831X_LDO11_ON_VSEL_MASK, vsel);
678}
679
680static int wm831x_alive_ldo_set_voltage(struct regulator_dev *rdev,
681 int min_uV, int max_uV)
682{
683 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
684 int reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL;
685
686 return wm831x_alive_ldo_set_voltage_int(rdev, reg, min_uV, max_uV);
687}
688
689static int wm831x_alive_ldo_set_suspend_voltage(struct regulator_dev *rdev,
690 int uV)
691{
692 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
693 int reg = ldo->base + WM831X_ALIVE_LDO_SLEEP_CONTROL;
694
695 return wm831x_alive_ldo_set_voltage_int(rdev, reg, uV, uV);
696}
697
698static int wm831x_alive_ldo_get_voltage(struct regulator_dev *rdev)
699{
700 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
701 struct wm831x *wm831x = ldo->wm831x;
702 int reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL;
703 int ret;
704
705 ret = wm831x_reg_read(wm831x, reg);
706 if (ret < 0)
707 return ret;
708
709 ret &= WM831X_LDO11_ON_VSEL_MASK;
710
711 return wm831x_alive_ldo_list_voltage(rdev, ret);
712}
713
714static int wm831x_alive_ldo_get_status(struct regulator_dev *rdev)
715{
716 struct wm831x_ldo *ldo = rdev_get_drvdata(rdev);
717 struct wm831x *wm831x = ldo->wm831x;
718 int mask = 1 << rdev_get_id(rdev);
719 int ret;
720
721 /* Is the regulator on? */
722 ret = wm831x_reg_read(wm831x, WM831X_LDO_STATUS);
723 if (ret < 0)
724 return ret;
725 if (ret & mask)
726 return REGULATOR_STATUS_ON;
727 else
728 return REGULATOR_STATUS_OFF;
729}
730
731static struct regulator_ops wm831x_alive_ldo_ops = {
732 .list_voltage = wm831x_alive_ldo_list_voltage,
733 .get_voltage = wm831x_alive_ldo_get_voltage,
734 .set_voltage = wm831x_alive_ldo_set_voltage,
735 .set_suspend_voltage = wm831x_alive_ldo_set_suspend_voltage,
736 .get_status = wm831x_alive_ldo_get_status,
737
738 .is_enabled = wm831x_ldo_is_enabled,
739 .enable = wm831x_ldo_enable,
740 .disable = wm831x_ldo_disable,
741};
742
743static __devinit int wm831x_alive_ldo_probe(struct platform_device *pdev)
744{
745 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
746 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
747 int id = pdev->id % ARRAY_SIZE(pdata->ldo);
748 struct wm831x_ldo *ldo;
749 struct resource *res;
750 int ret;
751
752 dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
753
754 if (pdata == NULL || pdata->ldo[id] == NULL)
755 return -ENODEV;
756
757 ldo = kzalloc(sizeof(struct wm831x_ldo), GFP_KERNEL);
758 if (ldo == NULL) {
759 dev_err(&pdev->dev, "Unable to allocate private data\n");
760 return -ENOMEM;
761 }
762
763 ldo->wm831x = wm831x;
764
765 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
766 if (res == NULL) {
767 dev_err(&pdev->dev, "No I/O resource\n");
768 ret = -EINVAL;
769 goto err;
770 }
771 ldo->base = res->start;
772
773 snprintf(ldo->name, sizeof(ldo->name), "LDO%d", id + 1);
774 ldo->desc.name = ldo->name;
775 ldo->desc.id = id;
776 ldo->desc.type = REGULATOR_VOLTAGE;
777 ldo->desc.n_voltages = WM831X_ALIVE_LDO_MAX_SELECTOR + 1;
778 ldo->desc.ops = &wm831x_alive_ldo_ops;
779 ldo->desc.owner = THIS_MODULE;
780
781 ldo->regulator = regulator_register(&ldo->desc, &pdev->dev,
782 pdata->ldo[id], ldo);
783 if (IS_ERR(ldo->regulator)) {
784 ret = PTR_ERR(ldo->regulator);
785 dev_err(wm831x->dev, "Failed to register LDO%d: %d\n",
786 id + 1, ret);
787 goto err;
788 }
789
790 platform_set_drvdata(pdev, ldo);
791
792 return 0;
793
794err:
795 kfree(ldo);
796 return ret;
797}
798
799static __devexit int wm831x_alive_ldo_remove(struct platform_device *pdev)
800{
801 struct wm831x_ldo *ldo = platform_get_drvdata(pdev);
802
803 regulator_unregister(ldo->regulator);
804 kfree(ldo);
805
806 return 0;
807}
808
809static struct platform_driver wm831x_alive_ldo_driver = {
810 .probe = wm831x_alive_ldo_probe,
811 .remove = __devexit_p(wm831x_alive_ldo_remove),
812 .driver = {
813 .name = "wm831x-alive-ldo",
814 },
815};
816
817static int __init wm831x_ldo_init(void)
818{
819 int ret;
820
821 ret = platform_driver_register(&wm831x_gp_ldo_driver);
822 if (ret != 0)
823 pr_err("Failed to register WM831x GP LDO driver: %d\n", ret);
824
825 ret = platform_driver_register(&wm831x_aldo_driver);
826 if (ret != 0)
827 pr_err("Failed to register WM831x ALDO driver: %d\n", ret);
828
829 ret = platform_driver_register(&wm831x_alive_ldo_driver);
830 if (ret != 0)
831 pr_err("Failed to register WM831x alive LDO driver: %d\n",
832 ret);
833
834 return 0;
835}
836subsys_initcall(wm831x_ldo_init);
837
838static void __exit wm831x_ldo_exit(void)
839{
840 platform_driver_unregister(&wm831x_alive_ldo_driver);
841 platform_driver_unregister(&wm831x_aldo_driver);
842 platform_driver_unregister(&wm831x_gp_ldo_driver);
843}
844module_exit(wm831x_ldo_exit);
845
846/* Module information */
847MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
848MODULE_DESCRIPTION("WM831x LDO driver");
849MODULE_LICENSE("GPL");
850MODULE_ALIAS("platform:wm831x-ldo");
851MODULE_ALIAS("platform:wm831x-aldo");
852MODULE_ALIAS("platform:wm831x-aliveldo");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 81adbdbd5042..73771b09fbd3 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -518,6 +518,16 @@ config RTC_DRV_V3020
518 This driver can also be built as a module. If so, the module 518 This driver can also be built as a module. If so, the module
519 will be called rtc-v3020. 519 will be called rtc-v3020.
520 520
521config RTC_DRV_WM831X
522 tristate "Wolfson Microelectronics WM831x RTC"
523 depends on MFD_WM831X
524 help
525 If you say yes here you will get support for the RTC subsystem
526 of the Wolfson Microelectronics WM831X series PMICs.
527
528 This driver can also be built as a module. If so, the module
529 will be called "rtc-wm831x".
530
521config RTC_DRV_WM8350 531config RTC_DRV_WM8350
522 tristate "Wolfson Microelectronics WM8350 RTC" 532 tristate "Wolfson Microelectronics WM8350 RTC"
523 depends on MFD_WM8350 533 depends on MFD_WM8350
@@ -535,6 +545,15 @@ config RTC_DRV_PCF50633
535 If you say yes here you get support for the RTC subsystem of the 545 If you say yes here you get support for the RTC subsystem of the
536 NXP PCF50633 used in embedded systems. 546 NXP PCF50633 used in embedded systems.
537 547
548config RTC_DRV_AB3100
549 tristate "ST-Ericsson AB3100 RTC"
550 depends on AB3100_CORE
551 default y if AB3100_CORE
552 help
553 Select this to enable the ST-Ericsson AB3100 Mixed Signal IC RTC
554 support. This chip contains a battery- and capacitor-backed RTC.
555
556
538comment "on-CPU RTC drivers" 557comment "on-CPU RTC drivers"
539 558
540config RTC_DRV_OMAP 559config RTC_DRV_OMAP
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3c0f2b2ac927..5e152ffe5058 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -17,6 +17,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
17 17
18# Keep the list ordered. 18# Keep the list ordered.
19 19
20obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
20obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o 21obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
21obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o 22obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
22obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o 23obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
@@ -74,6 +75,7 @@ obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl4030.o
74obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o 75obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o
75obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o 76obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
76obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o 77obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o
78obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o
77obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o 79obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
78obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o 80obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
79obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o 81obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
diff --git a/drivers/rtc/rtc-ab3100.c b/drivers/rtc/rtc-ab3100.c
new file mode 100644
index 000000000000..4704aac2b5af
--- /dev/null
+++ b/drivers/rtc/rtc-ab3100.c
@@ -0,0 +1,281 @@
1/*
2 * Copyright (C) 2007-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * RTC clock driver for the AB3100 Analog Baseband Chip
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 */
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/rtc.h>
12#include <linux/mfd/ab3100.h>
13
14/* Clock rate in Hz */
15#define AB3100_RTC_CLOCK_RATE 32768
16
17/*
18 * The AB3100 RTC registers. These are the same for
19 * AB3000 and AB3100.
20 * Control register:
21 * Bit 0: RTC Monitor cleared=0, active=1, if you set it
22 * to 1 it remains active until RTC power is lost.
23 * Bit 1: 32 kHz Oscillator, 0 = on, 1 = bypass
24 * Bit 2: Alarm on, 0 = off, 1 = on
25 * Bit 3: 32 kHz buffer disabling, 0 = enabled, 1 = disabled
26 */
27#define AB3100_RTC 0x53
28/* default setting, buffer disabled, alarm on */
29#define RTC_SETTING 0x30
30/* Alarm when AL0-AL3 == TI0-TI3 */
31#define AB3100_AL0 0x56
32#define AB3100_AL1 0x57
33#define AB3100_AL2 0x58
34#define AB3100_AL3 0x59
35/* This 48-bit register that counts up at 32768 Hz */
36#define AB3100_TI0 0x5a
37#define AB3100_TI1 0x5b
38#define AB3100_TI2 0x5c
39#define AB3100_TI3 0x5d
40#define AB3100_TI4 0x5e
41#define AB3100_TI5 0x5f
42
43/*
44 * RTC clock functions and device struct declaration
45 */
46static int ab3100_rtc_set_mmss(struct device *dev, unsigned long secs)
47{
48 struct ab3100 *ab3100_data = dev_get_drvdata(dev);
49 u8 regs[] = {AB3100_TI0, AB3100_TI1, AB3100_TI2,
50 AB3100_TI3, AB3100_TI4, AB3100_TI5};
51 unsigned char buf[6];
52 u64 fat_time = (u64) secs * AB3100_RTC_CLOCK_RATE * 2;
53 int err = 0;
54 int i;
55
56 buf[0] = (fat_time) & 0xFF;
57 buf[1] = (fat_time >> 8) & 0xFF;
58 buf[2] = (fat_time >> 16) & 0xFF;
59 buf[3] = (fat_time >> 24) & 0xFF;
60 buf[4] = (fat_time >> 32) & 0xFF;
61 buf[5] = (fat_time >> 40) & 0xFF;
62
63 for (i = 0; i < 6; i++) {
64 err = ab3100_set_register_interruptible(ab3100_data,
65 regs[i], buf[i]);
66 if (err)
67 return err;
68 }
69
70 /* Set the flag to mark that the clock is now set */
71 return ab3100_mask_and_set_register_interruptible(ab3100_data,
72 AB3100_RTC,
73 0xFE, 0x01);
74
75}
76
77static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm)
78{
79 struct ab3100 *ab3100_data = dev_get_drvdata(dev);
80 unsigned long time;
81 u8 rtcval;
82 int err;
83
84 err = ab3100_get_register_interruptible(ab3100_data,
85 AB3100_RTC, &rtcval);
86 if (err)
87 return err;
88
89 if (!(rtcval & 0x01)) {
90 dev_info(dev, "clock not set (lost power)");
91 return -EINVAL;
92 } else {
93 u64 fat_time;
94 u8 buf[6];
95
96 /* Read out time registers */
97 err = ab3100_get_register_page_interruptible(ab3100_data,
98 AB3100_TI0,
99 buf, 6);
100 if (err != 0)
101 return err;
102
103 fat_time = ((u64) buf[5] << 40) | ((u64) buf[4] << 32) |
104 ((u64) buf[3] << 24) | ((u64) buf[2] << 16) |
105 ((u64) buf[1] << 8) | (u64) buf[0];
106 time = (unsigned long) (fat_time /
107 (u64) (AB3100_RTC_CLOCK_RATE * 2));
108 }
109
110 rtc_time_to_tm(time, tm);
111
112 return rtc_valid_tm(tm);
113}
114
115static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
116{
117 struct ab3100 *ab3100_data = dev_get_drvdata(dev);
118 unsigned long time;
119 u64 fat_time;
120 u8 buf[6];
121 u8 rtcval;
122 int err;
123
124 /* Figure out if alarm is enabled or not */
125 err = ab3100_get_register_interruptible(ab3100_data,
126 AB3100_RTC, &rtcval);
127 if (err)
128 return err;
129 if (rtcval & 0x04)
130 alarm->enabled = 1;
131 else
132 alarm->enabled = 0;
133 /* No idea how this could be represented */
134 alarm->pending = 0;
135 /* Read out alarm registers, only 4 bytes */
136 err = ab3100_get_register_page_interruptible(ab3100_data,
137 AB3100_AL0, buf, 4);
138 if (err)
139 return err;
140 fat_time = ((u64) buf[3] << 40) | ((u64) buf[2] << 32) |
141 ((u64) buf[1] << 24) | ((u64) buf[0] << 16);
142 time = (unsigned long) (fat_time / (u64) (AB3100_RTC_CLOCK_RATE * 2));
143
144 rtc_time_to_tm(time, &alarm->time);
145
146 return rtc_valid_tm(&alarm->time);
147}
148
149static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
150{
151 struct ab3100 *ab3100_data = dev_get_drvdata(dev);
152 u8 regs[] = {AB3100_AL0, AB3100_AL1, AB3100_AL2, AB3100_AL3};
153 unsigned char buf[4];
154 unsigned long secs;
155 u64 fat_time;
156 int err;
157 int i;
158
159 rtc_tm_to_time(&alarm->time, &secs);
160 fat_time = (u64) secs * AB3100_RTC_CLOCK_RATE * 2;
161 buf[0] = (fat_time >> 16) & 0xFF;
162 buf[1] = (fat_time >> 24) & 0xFF;
163 buf[2] = (fat_time >> 32) & 0xFF;
164 buf[3] = (fat_time >> 40) & 0xFF;
165
166 /* Set the alarm */
167 for (i = 0; i < 4; i++) {
168 err = ab3100_set_register_interruptible(ab3100_data,
169 regs[i], buf[i]);
170 if (err)
171 return err;
172 }
173 /* Then enable the alarm */
174 return ab3100_mask_and_set_register_interruptible(ab3100_data,
175 AB3100_RTC, ~(1 << 2),
176 alarm->enabled << 2);
177}
178
179static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled)
180{
181 struct ab3100 *ab3100_data = dev_get_drvdata(dev);
182
183 /*
184 * It's not possible to enable/disable the alarm IRQ for this RTC.
185 * It does not actually trigger any IRQ: instead its only function is
186 * to power up the system, if it wasn't on. This will manifest as
187 * a "power up cause" in the AB3100 power driver (battery charging etc)
188 * and need to be handled there instead.
189 */
190 if (enabled)
191 return ab3100_mask_and_set_register_interruptible(ab3100_data,
192 AB3100_RTC, ~(1 << 2),
193 1 << 2);
194 else
195 return ab3100_mask_and_set_register_interruptible(ab3100_data,
196 AB3100_RTC, ~(1 << 2),
197 0);
198}
199
200static const struct rtc_class_ops ab3100_rtc_ops = {
201 .read_time = ab3100_rtc_read_time,
202 .set_mmss = ab3100_rtc_set_mmss,
203 .read_alarm = ab3100_rtc_read_alarm,
204 .set_alarm = ab3100_rtc_set_alarm,
205 .alarm_irq_enable = ab3100_rtc_irq_enable,
206};
207
208static int __init ab3100_rtc_probe(struct platform_device *pdev)
209{
210 int err;
211 u8 regval;
212 struct rtc_device *rtc;
213 struct ab3100 *ab3100_data = platform_get_drvdata(pdev);
214
215 /* The first RTC register needs special treatment */
216 err = ab3100_get_register_interruptible(ab3100_data,
217 AB3100_RTC, &regval);
218 if (err) {
219 dev_err(&pdev->dev, "unable to read RTC register\n");
220 return -ENODEV;
221 }
222
223 if ((regval & 0xFE) != RTC_SETTING) {
224 dev_warn(&pdev->dev, "not default value in RTC reg 0x%x\n",
225 regval);
226 }
227
228 if ((regval & 1) == 0) {
229 /*
230 * Set bit to detect power loss.
231 * This bit remains until RTC power is lost.
232 */
233 regval = 1 | RTC_SETTING;
234 err = ab3100_set_register_interruptible(ab3100_data,
235 AB3100_RTC, regval);
236 /* Ignore any error on this write */
237 }
238
239 rtc = rtc_device_register("ab3100-rtc", &pdev->dev, &ab3100_rtc_ops,
240 THIS_MODULE);
241 if (IS_ERR(rtc)) {
242 err = PTR_ERR(rtc);
243 return err;
244 }
245
246 return 0;
247}
248
249static int __exit ab3100_rtc_remove(struct platform_device *pdev)
250{
251 struct rtc_device *rtc = platform_get_drvdata(pdev);
252
253 rtc_device_unregister(rtc);
254 return 0;
255}
256
257static struct platform_driver ab3100_rtc_driver = {
258 .driver = {
259 .name = "ab3100-rtc",
260 .owner = THIS_MODULE,
261 },
262 .remove = __exit_p(ab3100_rtc_remove),
263};
264
265static int __init ab3100_rtc_init(void)
266{
267 return platform_driver_probe(&ab3100_rtc_driver,
268 ab3100_rtc_probe);
269}
270
271static void __exit ab3100_rtc_exit(void)
272{
273 platform_driver_unregister(&ab3100_rtc_driver);
274}
275
276module_init(ab3100_rtc_init);
277module_exit(ab3100_rtc_exit);
278
279MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
280MODULE_DESCRIPTION("AB3100 RTC Driver");
281MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-wm831x.c b/drivers/rtc/rtc-wm831x.c
new file mode 100644
index 000000000000..79795cdf6ed8
--- /dev/null
+++ b/drivers/rtc/rtc-wm831x.c
@@ -0,0 +1,523 @@
1/*
2 * Real Time Clock driver for Wolfson Microelectronics WM831x
3 *
4 * Copyright (C) 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/time.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20#include <linux/interrupt.h>
21#include <linux/ioctl.h>
22#include <linux/completion.h>
23#include <linux/mfd/wm831x/core.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26
27
28/*
29 * R16416 (0x4020) - RTC Write Counter
30 */
31#define WM831X_RTC_WR_CNT_MASK 0xFFFF /* RTC_WR_CNT - [15:0] */
32#define WM831X_RTC_WR_CNT_SHIFT 0 /* RTC_WR_CNT - [15:0] */
33#define WM831X_RTC_WR_CNT_WIDTH 16 /* RTC_WR_CNT - [15:0] */
34
35/*
36 * R16417 (0x4021) - RTC Time 1
37 */
38#define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
39#define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
40#define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
41
42/*
43 * R16418 (0x4022) - RTC Time 2
44 */
45#define WM831X_RTC_TIME_MASK 0xFFFF /* RTC_TIME - [15:0] */
46#define WM831X_RTC_TIME_SHIFT 0 /* RTC_TIME - [15:0] */
47#define WM831X_RTC_TIME_WIDTH 16 /* RTC_TIME - [15:0] */
48
49/*
50 * R16419 (0x4023) - RTC Alarm 1
51 */
52#define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
53#define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
54#define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
55
56/*
57 * R16420 (0x4024) - RTC Alarm 2
58 */
59#define WM831X_RTC_ALM_MASK 0xFFFF /* RTC_ALM - [15:0] */
60#define WM831X_RTC_ALM_SHIFT 0 /* RTC_ALM - [15:0] */
61#define WM831X_RTC_ALM_WIDTH 16 /* RTC_ALM - [15:0] */
62
63/*
64 * R16421 (0x4025) - RTC Control
65 */
66#define WM831X_RTC_VALID 0x8000 /* RTC_VALID */
67#define WM831X_RTC_VALID_MASK 0x8000 /* RTC_VALID */
68#define WM831X_RTC_VALID_SHIFT 15 /* RTC_VALID */
69#define WM831X_RTC_VALID_WIDTH 1 /* RTC_VALID */
70#define WM831X_RTC_SYNC_BUSY 0x4000 /* RTC_SYNC_BUSY */
71#define WM831X_RTC_SYNC_BUSY_MASK 0x4000 /* RTC_SYNC_BUSY */
72#define WM831X_RTC_SYNC_BUSY_SHIFT 14 /* RTC_SYNC_BUSY */
73#define WM831X_RTC_SYNC_BUSY_WIDTH 1 /* RTC_SYNC_BUSY */
74#define WM831X_RTC_ALM_ENA 0x0400 /* RTC_ALM_ENA */
75#define WM831X_RTC_ALM_ENA_MASK 0x0400 /* RTC_ALM_ENA */
76#define WM831X_RTC_ALM_ENA_SHIFT 10 /* RTC_ALM_ENA */
77#define WM831X_RTC_ALM_ENA_WIDTH 1 /* RTC_ALM_ENA */
78#define WM831X_RTC_PINT_FREQ_MASK 0x0070 /* RTC_PINT_FREQ - [6:4] */
79#define WM831X_RTC_PINT_FREQ_SHIFT 4 /* RTC_PINT_FREQ - [6:4] */
80#define WM831X_RTC_PINT_FREQ_WIDTH 3 /* RTC_PINT_FREQ - [6:4] */
81
82/*
83 * R16422 (0x4026) - RTC Trim
84 */
85#define WM831X_RTC_TRIM_MASK 0x03FF /* RTC_TRIM - [9:0] */
86#define WM831X_RTC_TRIM_SHIFT 0 /* RTC_TRIM - [9:0] */
87#define WM831X_RTC_TRIM_WIDTH 10 /* RTC_TRIM - [9:0] */
88
89#define WM831X_SET_TIME_RETRIES 5
90#define WM831X_GET_TIME_RETRIES 5
91
92struct wm831x_rtc {
93 struct wm831x *wm831x;
94 struct rtc_device *rtc;
95 unsigned int alarm_enabled:1;
96};
97
98/*
99 * Read current time and date in RTC
100 */
101static int wm831x_rtc_readtime(struct device *dev, struct rtc_time *tm)
102{
103 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
104 struct wm831x *wm831x = wm831x_rtc->wm831x;
105 u16 time1[2], time2[2];
106 int ret;
107 int count = 0;
108
109 /* Has the RTC been programmed? */
110 ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
111 if (ret < 0) {
112 dev_err(dev, "Failed to read RTC control: %d\n", ret);
113 return ret;
114 }
115 if (!(ret & WM831X_RTC_VALID)) {
116 dev_dbg(dev, "RTC not yet configured\n");
117 return -EINVAL;
118 }
119
120 /* Read twice to make sure we don't read a corrupt, partially
121 * incremented, value.
122 */
123 do {
124 ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
125 2, time1);
126 if (ret != 0)
127 continue;
128
129 ret = wm831x_bulk_read(wm831x, WM831X_RTC_TIME_1,
130 2, time2);
131 if (ret != 0)
132 continue;
133
134 if (memcmp(time1, time2, sizeof(time1)) == 0) {
135 u32 time = (time1[0] << 16) | time1[1];
136
137 rtc_time_to_tm(time, tm);
138 return rtc_valid_tm(tm);
139 }
140
141 } while (++count < WM831X_GET_TIME_RETRIES);
142
143 dev_err(dev, "Timed out reading current time\n");
144
145 return -EIO;
146}
147
148/*
149 * Set current time and date in RTC
150 */
151static int wm831x_rtc_set_mmss(struct device *dev, unsigned long time)
152{
153 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
154 struct wm831x *wm831x = wm831x_rtc->wm831x;
155 struct rtc_time new_tm;
156 unsigned long new_time;
157 int ret;
158 int count = 0;
159
160 ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_1,
161 (time >> 16) & 0xffff);
162 if (ret < 0) {
163 dev_err(dev, "Failed to write TIME_1: %d\n", ret);
164 return ret;
165 }
166
167 ret = wm831x_reg_write(wm831x, WM831X_RTC_TIME_2, time & 0xffff);
168 if (ret < 0) {
169 dev_err(dev, "Failed to write TIME_2: %d\n", ret);
170 return ret;
171 }
172
173 /* Wait for the update to complete - should happen first time
174 * round but be conservative.
175 */
176 do {
177 msleep(1);
178
179 ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
180 if (ret < 0)
181 ret = WM831X_RTC_SYNC_BUSY;
182 } while (!(ret & WM831X_RTC_SYNC_BUSY) &&
183 ++count < WM831X_SET_TIME_RETRIES);
184
185 if (ret & WM831X_RTC_SYNC_BUSY) {
186 dev_err(dev, "Timed out writing RTC update\n");
187 return -EIO;
188 }
189
190 /* Check that the update was accepted; security features may
191 * have caused the update to be ignored.
192 */
193 ret = wm831x_rtc_readtime(dev, &new_tm);
194 if (ret < 0)
195 return ret;
196
197 ret = rtc_tm_to_time(&new_tm, &new_time);
198 if (ret < 0) {
199 dev_err(dev, "Failed to convert time: %d\n", ret);
200 return ret;
201 }
202
203 /* Allow a second of change in case of tick */
204 if (new_time - time > 1) {
205 dev_err(dev, "RTC update not permitted by hardware\n");
206 return -EPERM;
207 }
208
209 return 0;
210}
211
212/*
213 * Read alarm time and date in RTC
214 */
215static int wm831x_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
216{
217 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
218 int ret;
219 u16 data[2];
220 u32 time;
221
222 ret = wm831x_bulk_read(wm831x_rtc->wm831x, WM831X_RTC_ALARM_1,
223 2, data);
224 if (ret != 0) {
225 dev_err(dev, "Failed to read alarm time: %d\n", ret);
226 return ret;
227 }
228
229 time = (data[0] << 16) | data[1];
230
231 rtc_time_to_tm(time, &alrm->time);
232
233 ret = wm831x_reg_read(wm831x_rtc->wm831x, WM831X_RTC_CONTROL);
234 if (ret < 0) {
235 dev_err(dev, "Failed to read RTC control: %d\n", ret);
236 return ret;
237 }
238
239 if (ret & WM831X_RTC_ALM_ENA)
240 alrm->enabled = 1;
241 else
242 alrm->enabled = 0;
243
244 return 0;
245}
246
247static int wm831x_rtc_stop_alarm(struct wm831x_rtc *wm831x_rtc)
248{
249 wm831x_rtc->alarm_enabled = 0;
250
251 return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
252 WM831X_RTC_ALM_ENA, 0);
253}
254
255static int wm831x_rtc_start_alarm(struct wm831x_rtc *wm831x_rtc)
256{
257 wm831x_rtc->alarm_enabled = 1;
258
259 return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
260 WM831X_RTC_ALM_ENA, WM831X_RTC_ALM_ENA);
261}
262
263static int wm831x_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
264{
265 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
266 struct wm831x *wm831x = wm831x_rtc->wm831x;
267 int ret;
268 unsigned long time;
269
270 ret = rtc_tm_to_time(&alrm->time, &time);
271 if (ret < 0) {
272 dev_err(dev, "Failed to convert time: %d\n", ret);
273 return ret;
274 }
275
276 ret = wm831x_rtc_stop_alarm(wm831x_rtc);
277 if (ret < 0) {
278 dev_err(dev, "Failed to stop alarm: %d\n", ret);
279 return ret;
280 }
281
282 ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_1,
283 (time >> 16) & 0xffff);
284 if (ret < 0) {
285 dev_err(dev, "Failed to write ALARM_1: %d\n", ret);
286 return ret;
287 }
288
289 ret = wm831x_reg_write(wm831x, WM831X_RTC_ALARM_2, time & 0xffff);
290 if (ret < 0) {
291 dev_err(dev, "Failed to write ALARM_2: %d\n", ret);
292 return ret;
293 }
294
295 if (alrm->enabled) {
296 ret = wm831x_rtc_start_alarm(wm831x_rtc);
297 if (ret < 0) {
298 dev_err(dev, "Failed to start alarm: %d\n", ret);
299 return ret;
300 }
301 }
302
303 return 0;
304}
305
306static int wm831x_rtc_alarm_irq_enable(struct device *dev,
307 unsigned int enabled)
308{
309 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
310
311 if (enabled)
312 return wm831x_rtc_start_alarm(wm831x_rtc);
313 else
314 return wm831x_rtc_stop_alarm(wm831x_rtc);
315}
316
317static int wm831x_rtc_update_irq_enable(struct device *dev,
318 unsigned int enabled)
319{
320 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(dev);
321 int val;
322
323 if (enabled)
324 val = 1 << WM831X_RTC_PINT_FREQ_SHIFT;
325 else
326 val = 0;
327
328 return wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
329 WM831X_RTC_PINT_FREQ_MASK, val);
330}
331
332static irqreturn_t wm831x_alm_irq(int irq, void *data)
333{
334 struct wm831x_rtc *wm831x_rtc = data;
335
336 rtc_update_irq(wm831x_rtc->rtc, 1, RTC_IRQF | RTC_AF);
337
338 return IRQ_HANDLED;
339}
340
341static irqreturn_t wm831x_per_irq(int irq, void *data)
342{
343 struct wm831x_rtc *wm831x_rtc = data;
344
345 rtc_update_irq(wm831x_rtc->rtc, 1, RTC_IRQF | RTC_UF);
346
347 return IRQ_HANDLED;
348}
349
350static const struct rtc_class_ops wm831x_rtc_ops = {
351 .read_time = wm831x_rtc_readtime,
352 .set_mmss = wm831x_rtc_set_mmss,
353 .read_alarm = wm831x_rtc_readalarm,
354 .set_alarm = wm831x_rtc_setalarm,
355 .alarm_irq_enable = wm831x_rtc_alarm_irq_enable,
356 .update_irq_enable = wm831x_rtc_update_irq_enable,
357};
358
359#ifdef CONFIG_PM
360/* Turn off the alarm if it should not be a wake source. */
361static int wm831x_rtc_suspend(struct device *dev)
362{
363 struct platform_device *pdev = to_platform_device(dev);
364 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(&pdev->dev);
365 int ret, enable;
366
367 if (wm831x_rtc->alarm_enabled && device_may_wakeup(&pdev->dev))
368 enable = WM831X_RTC_ALM_ENA;
369 else
370 enable = 0;
371
372 ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
373 WM831X_RTC_ALM_ENA, enable);
374 if (ret != 0)
375 dev_err(&pdev->dev, "Failed to update RTC alarm: %d\n", ret);
376
377 return 0;
378}
379
380/* Enable the alarm if it should be enabled (in case it was disabled to
381 * prevent use as a wake source).
382 */
383static int wm831x_rtc_resume(struct device *dev)
384{
385 struct platform_device *pdev = to_platform_device(dev);
386 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(&pdev->dev);
387 int ret;
388
389 if (wm831x_rtc->alarm_enabled) {
390 ret = wm831x_rtc_start_alarm(wm831x_rtc);
391 if (ret != 0)
392 dev_err(&pdev->dev,
393 "Failed to restart RTC alarm: %d\n", ret);
394 }
395
396 return 0;
397}
398
399/* Unconditionally disable the alarm */
400static int wm831x_rtc_freeze(struct device *dev)
401{
402 struct platform_device *pdev = to_platform_device(dev);
403 struct wm831x_rtc *wm831x_rtc = dev_get_drvdata(&pdev->dev);
404 int ret;
405
406 ret = wm831x_set_bits(wm831x_rtc->wm831x, WM831X_RTC_CONTROL,
407 WM831X_RTC_ALM_ENA, 0);
408 if (ret != 0)
409 dev_err(&pdev->dev, "Failed to stop RTC alarm: %d\n", ret);
410
411 return 0;
412}
413#else
414#define wm831x_rtc_suspend NULL
415#define wm831x_rtc_resume NULL
416#define wm831x_rtc_freeze NULL
417#endif
418
419static int wm831x_rtc_probe(struct platform_device *pdev)
420{
421 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
422 struct wm831x_rtc *wm831x_rtc;
423 int per_irq = platform_get_irq_byname(pdev, "PER");
424 int alm_irq = platform_get_irq_byname(pdev, "ALM");
425 int ret = 0;
426
427 wm831x_rtc = kzalloc(sizeof(*wm831x_rtc), GFP_KERNEL);
428 if (wm831x_rtc == NULL)
429 return -ENOMEM;
430
431 platform_set_drvdata(pdev, wm831x_rtc);
432 wm831x_rtc->wm831x = wm831x;
433
434 ret = wm831x_reg_read(wm831x, WM831X_RTC_CONTROL);
435 if (ret < 0) {
436 dev_err(&pdev->dev, "Failed to read RTC control: %d\n", ret);
437 goto err;
438 }
439 if (ret & WM831X_RTC_ALM_ENA)
440 wm831x_rtc->alarm_enabled = 1;
441
442 device_init_wakeup(&pdev->dev, 1);
443
444 wm831x_rtc->rtc = rtc_device_register("wm831x", &pdev->dev,
445 &wm831x_rtc_ops, THIS_MODULE);
446 if (IS_ERR(wm831x_rtc->rtc)) {
447 ret = PTR_ERR(wm831x_rtc->rtc);
448 goto err;
449 }
450
451 ret = wm831x_request_irq(wm831x, per_irq, wm831x_per_irq,
452 IRQF_TRIGGER_RISING, "wm831x_rtc_per",
453 wm831x_rtc);
454 if (ret != 0) {
455 dev_err(&pdev->dev, "Failed to request periodic IRQ %d: %d\n",
456 per_irq, ret);
457 }
458
459 ret = wm831x_request_irq(wm831x, alm_irq, wm831x_alm_irq,
460 IRQF_TRIGGER_RISING, "wm831x_rtc_alm",
461 wm831x_rtc);
462 if (ret != 0) {
463 dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
464 alm_irq, ret);
465 }
466
467 return 0;
468
469err:
470 kfree(wm831x_rtc);
471 return ret;
472}
473
474static int __devexit wm831x_rtc_remove(struct platform_device *pdev)
475{
476 struct wm831x_rtc *wm831x_rtc = platform_get_drvdata(pdev);
477 int per_irq = platform_get_irq_byname(pdev, "PER");
478 int alm_irq = platform_get_irq_byname(pdev, "ALM");
479
480 wm831x_free_irq(wm831x_rtc->wm831x, alm_irq, wm831x_rtc);
481 wm831x_free_irq(wm831x_rtc->wm831x, per_irq, wm831x_rtc);
482 rtc_device_unregister(wm831x_rtc->rtc);
483 kfree(wm831x_rtc);
484
485 return 0;
486}
487
488static struct dev_pm_ops wm831x_rtc_pm_ops = {
489 .suspend = wm831x_rtc_suspend,
490 .resume = wm831x_rtc_resume,
491
492 .freeze = wm831x_rtc_freeze,
493 .thaw = wm831x_rtc_resume,
494 .restore = wm831x_rtc_resume,
495
496 .poweroff = wm831x_rtc_suspend,
497};
498
499static struct platform_driver wm831x_rtc_driver = {
500 .probe = wm831x_rtc_probe,
501 .remove = __devexit_p(wm831x_rtc_remove),
502 .driver = {
503 .name = "wm831x-rtc",
504 .pm = &wm831x_rtc_pm_ops,
505 },
506};
507
508static int __init wm831x_rtc_init(void)
509{
510 return platform_driver_register(&wm831x_rtc_driver);
511}
512module_init(wm831x_rtc_init);
513
514static void __exit wm831x_rtc_exit(void)
515{
516 platform_driver_unregister(&wm831x_rtc_driver);
517}
518module_exit(wm831x_rtc_exit);
519
520MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
521MODULE_DESCRIPTION("RTC driver for the WM831x series PMICs");
522MODULE_LICENSE("GPL");
523MODULE_ALIAS("platform:wm831x-rtc");
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h
index 3fd21d7cb6bf..2d02dfd7076c 100644
--- a/include/linux/i2c/twl4030.h
+++ b/include/linux/i2c/twl4030.h
@@ -223,19 +223,28 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
223 223
224/* Power bus message definitions */ 224/* Power bus message definitions */
225 225
226#define DEV_GRP_NULL 0x0 226/* The TWL4030/5030 splits its power-management resources (the various
227#define DEV_GRP_P1 0x1 227 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
228#define DEV_GRP_P2 0x2 228 * P3. These groups can then be configured to transition between sleep, wait-on
229#define DEV_GRP_P3 0x4 229 * and active states by sending messages to the power bus. See Section 5.4.2
230 * Power Resources of TWL4030 TRM
231 */
230 232
231#define RES_GRP_RES 0x0 233/* Processor groups */
232#define RES_GRP_PP 0x1 234#define DEV_GRP_NULL 0x0
233#define RES_GRP_RC 0x2 235#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
236#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
237#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
238
239/* Resource groups */
240#define RES_GRP_RES 0x0 /* Reserved */
241#define RES_GRP_PP 0x1 /* Power providers */
242#define RES_GRP_RC 0x2 /* Reset and control */
234#define RES_GRP_PP_RC 0x3 243#define RES_GRP_PP_RC 0x3
235#define RES_GRP_PR 0x4 244#define RES_GRP_PR 0x4 /* Power references */
236#define RES_GRP_PP_PR 0x5 245#define RES_GRP_PP_PR 0x5
237#define RES_GRP_RC_PR 0x6 246#define RES_GRP_RC_PR 0x6
238#define RES_GRP_ALL 0x7 247#define RES_GRP_ALL 0x7 /* All resource groups */
239 248
240#define RES_TYPE2_R0 0x0 249#define RES_TYPE2_R0 0x0
241 250
@@ -246,6 +255,41 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
246#define RES_STATE_SLEEP 0x8 255#define RES_STATE_SLEEP 0x8
247#define RES_STATE_OFF 0x0 256#define RES_STATE_OFF 0x0
248 257
258/* Power resources */
259
260/* Power providers */
261#define RES_VAUX1 1
262#define RES_VAUX2 2
263#define RES_VAUX3 3
264#define RES_VAUX4 4
265#define RES_VMMC1 5
266#define RES_VMMC2 6
267#define RES_VPLL1 7
268#define RES_VPLL2 8
269#define RES_VSIM 9
270#define RES_VDAC 10
271#define RES_VINTANA1 11
272#define RES_VINTANA2 12
273#define RES_VINTDIG 13
274#define RES_VIO 14
275#define RES_VDD1 15
276#define RES_VDD2 16
277#define RES_VUSB_1V5 17
278#define RES_VUSB_1V8 18
279#define RES_VUSB_3V1 19
280#define RES_VUSBCP 20
281#define RES_REGEN 21
282/* Reset and control */
283#define RES_NRES_PWRON 22
284#define RES_CLKEN 23
285#define RES_SYSEN 24
286#define RES_HFCLKOUT 25
287#define RES_32KCLKOUT 26
288#define RES_RESET 27
289/* Power Reference */
290#define RES_Main_Ref 28
291
292#define TOTAL_RESOURCES 28
249/* 293/*
250 * Power Bus Message Format ... these can be sent individually by Linux, 294 * Power Bus Message Format ... these can be sent individually by Linux,
251 * but are usually part of downloaded scripts that are run when various 295 * but are usually part of downloaded scripts that are run when various
@@ -327,6 +371,36 @@ struct twl4030_usb_data {
327 enum twl4030_usb_mode usb_mode; 371 enum twl4030_usb_mode usb_mode;
328}; 372};
329 373
374struct twl4030_ins {
375 u16 pmb_message;
376 u8 delay;
377};
378
379struct twl4030_script {
380 struct twl4030_ins *script;
381 unsigned size;
382 u8 flags;
383#define TWL4030_WRST_SCRIPT (1<<0)
384#define TWL4030_WAKEUP12_SCRIPT (1<<1)
385#define TWL4030_WAKEUP3_SCRIPT (1<<2)
386#define TWL4030_SLEEP_SCRIPT (1<<3)
387};
388
389struct twl4030_resconfig {
390 u8 resource;
391 u8 devgroup; /* Processor group that Power resource belongs to */
392 u8 type; /* Power resource addressed, 6 / broadcast message */
393 u8 type2; /* Power resource addressed, 3 / broadcast message */
394};
395
396struct twl4030_power_data {
397 struct twl4030_script **scripts;
398 unsigned num;
399 struct twl4030_resconfig *resource_config;
400};
401
402extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
403
330struct twl4030_platform_data { 404struct twl4030_platform_data {
331 unsigned irq_base, irq_end; 405 unsigned irq_base, irq_end;
332 struct twl4030_bci_platform_data *bci; 406 struct twl4030_bci_platform_data *bci;
@@ -334,6 +408,7 @@ struct twl4030_platform_data {
334 struct twl4030_madc_platform_data *madc; 408 struct twl4030_madc_platform_data *madc;
335 struct twl4030_keypad_data *keypad; 409 struct twl4030_keypad_data *keypad;
336 struct twl4030_usb_data *usb; 410 struct twl4030_usb_data *usb;
411 struct twl4030_power_data *power;
337 412
338 /* LDO regulators */ 413 /* LDO regulators */
339 struct regulator_init_data *vdac; 414 struct regulator_init_data *vdac;
@@ -364,7 +439,6 @@ int twl4030_sih_setup(int module);
364#define TWL4030_VAUX3_DEV_GRP 0x1F 439#define TWL4030_VAUX3_DEV_GRP 0x1F
365#define TWL4030_VAUX3_DEDICATED 0x22 440#define TWL4030_VAUX3_DEDICATED 0x22
366 441
367
368#if defined(CONFIG_TWL4030_BCI_BATTERY) || \ 442#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
369 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE) 443 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
370 extern int twl4030charger_usb_en(int enable); 444 extern int twl4030charger_usb_en(int enable);
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
index 7a3f316e3848..e9aa4c9d749d 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/ab3100.h
@@ -6,6 +6,8 @@
6 */ 6 */
7 7
8#include <linux/device.h> 8#include <linux/device.h>
9#include <linux/workqueue.h>
10#include <linux/regulator/machine.h>
9 11
10#ifndef MFD_AB3100_H 12#ifndef MFD_AB3100_H
11#define MFD_AB3100_H 13#define MFD_AB3100_H
@@ -56,6 +58,14 @@
56#define AB3100_STR_BATT_REMOVAL (0x40) 58#define AB3100_STR_BATT_REMOVAL (0x40)
57#define AB3100_STR_VBUS (0x80) 59#define AB3100_STR_VBUS (0x80)
58 60
61/*
62 * AB3100 contains 8 regulators, one external regulator controller
63 * and a buck converter, further the LDO E and buck converter can
64 * have separate settings if they are in sleep mode, this is
65 * modeled as a separate regulator.
66 */
67#define AB3100_NUM_REGULATORS 10
68
59/** 69/**
60 * struct ab3100 70 * struct ab3100
61 * @access_mutex: lock out concurrent accesses to the AB3100 registers 71 * @access_mutex: lock out concurrent accesses to the AB3100 registers
@@ -86,11 +96,30 @@ struct ab3100 {
86 bool startup_events_read; 96 bool startup_events_read;
87}; 97};
88 98
89int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval); 99/**
90int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval); 100 * struct ab3100_platform_data
91int ab3100_get_register_page(struct ab3100 *ab3100, 101 * Data supplied to initialize board connections to the AB3100
102 * @reg_constraints: regulator constraints for target board
103 * the order of these constraints are: LDO A, C, D, E,
104 * F, G, H, K, EXT and BUCK.
105 * @reg_initvals: initial values for the regulator registers
106 * plus two sleep settings for LDO E and the BUCK converter.
107 * exactly AB3100_NUM_REGULATORS+2 values must be sent in.
108 * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
109 * BUCK sleep, LDO D. (LDO D need to be initialized last.)
110 * @external_voltage: voltage level of the external regulator.
111 */
112struct ab3100_platform_data {
113 struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
114 u8 reg_initvals[AB3100_NUM_REGULATORS+2];
115 int external_voltage;
116};
117
118int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
119int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
120int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
92 u8 first_reg, u8 *regvals, u8 numregs); 121 u8 first_reg, u8 *regvals, u8 numregs);
93int ab3100_mask_and_set_register(struct ab3100 *ab3100, 122int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
94 u8 reg, u8 andmask, u8 ormask); 123 u8 reg, u8 andmask, u8 ormask);
95u8 ab3100_get_chip_type(struct ab3100 *ab3100); 124u8 ab3100_get_chip_type(struct ab3100 *ab3100);
96int ab3100_event_register(struct ab3100 *ab3100, 125int ab3100_event_register(struct ab3100 *ab3100,
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index 49ef857cdb2d..11d740b8831d 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -23,6 +23,7 @@
23 */ 23 */
24struct mfd_cell { 24struct mfd_cell {
25 const char *name; 25 const char *name;
26 int id;
26 27
27 int (*enable)(struct platform_device *dev); 28 int (*enable)(struct platform_device *dev);
28 int (*disable)(struct platform_device *dev); 29 int (*disable)(struct platform_device *dev);
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index c12c3c0932bf..e5124ceea769 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -25,9 +25,12 @@ struct pcap_chip;
25 25
26int ezx_pcap_write(struct pcap_chip *, u8, u32); 26int ezx_pcap_write(struct pcap_chip *, u8, u32);
27int ezx_pcap_read(struct pcap_chip *, u8, u32 *); 27int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
28int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
28int pcap_to_irq(struct pcap_chip *, int); 29int pcap_to_irq(struct pcap_chip *, int);
30int irq_to_pcap(struct pcap_chip *, int);
29int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *); 31int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
30int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]); 32int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
33void pcap_set_ts_bits(struct pcap_chip *, u32);
31 34
32#define PCAP_SECOND_PORT 1 35#define PCAP_SECOND_PORT 1
33#define PCAP_CS_AH 2 36#define PCAP_CS_AH 2
@@ -224,7 +227,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
224#define PCAP_LED1 1 227#define PCAP_LED1 1
225#define PCAP_BL0 2 228#define PCAP_BL0 2
226#define PCAP_BL1 3 229#define PCAP_BL1 3
227#define PCAP_VIB 4
228#define PCAP_LED_3MA 0 230#define PCAP_LED_3MA 0
229#define PCAP_LED_4MA 1 231#define PCAP_LED_4MA 1
230#define PCAP_LED_5MA 2 232#define PCAP_LED_5MA 2
@@ -243,9 +245,6 @@ int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
243#define PCAP_LED0_C_SHIFT 15 245#define PCAP_LED0_C_SHIFT 15
244#define PCAP_LED1_C_SHIFT 17 246#define PCAP_LED1_C_SHIFT 17
245#define PCAP_BL1_SHIFT 20 247#define PCAP_BL1_SHIFT 20
246#define PCAP_VIB_MASK 0x3
247#define PCAP_VIB_SHIFT 20
248#define PCAP_VIB_EN (1 << 19)
249 248
250/* RTC */ 249/* RTC */
251#define PCAP_RTC_DAY_MASK 0x3fff 250#define PCAP_RTC_DAY_MASK 0x3fff
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
new file mode 100644
index 000000000000..47e698cb0f16
--- /dev/null
+++ b/include/linux/mfd/mc13783-private.h
@@ -0,0 +1,396 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __LINUX_MFD_MC13783_PRIV_H
23#define __LINUX_MFD_MC13783_PRIV_H
24
25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/workqueue.h>
28#include <linux/mutex.h>
29
30struct mc13783_irq {
31 void (*handler)(int, void *);
32 void *data;
33};
34
35#define MC13783_NUM_IRQ 2
36#define MC13783_IRQ_TS 0
37#define MC13783_IRQ_REGULATOR 1
38
39#define MC13783_ADC_MODE_TS 1
40#define MC13783_ADC_MODE_SINGLE_CHAN 2
41#define MC13783_ADC_MODE_MULT_CHAN 3
42
43struct mc13783 {
44 int revision;
45 struct device *dev;
46 struct spi_device *spi_device;
47
48 int (*read_dev)(void *data, char reg, int count, u32 *dst);
49 int (*write_dev)(void *data, char reg, int count, const u32 *src);
50
51 struct mutex io_lock;
52 void *io_data;
53 int irq;
54 unsigned int flags;
55
56 struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
57 struct work_struct work;
58 struct completion adc_done;
59 unsigned int ts_active;
60 struct mutex adc_conv_lock;
61
62 struct mc13783_regulator_init_data *regulators;
63 int num_regulators;
64};
65
66int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
67int mc13783_reg_write(struct mc13783 *, int, u32);
68int mc13783_set_bits(struct mc13783 *, int, u32, u32);
69int mc13783_free_irq(struct mc13783 *mc13783, int irq);
70int mc13783_register_irq(struct mc13783 *mc13783, int irq,
71 void (*handler) (int, void *), void *data);
72
73#define MC13783_REG_INTERRUPT_STATUS_0 0
74#define MC13783_REG_INTERRUPT_MASK_0 1
75#define MC13783_REG_INTERRUPT_SENSE_0 2
76#define MC13783_REG_INTERRUPT_STATUS_1 3
77#define MC13783_REG_INTERRUPT_MASK_1 4
78#define MC13783_REG_INTERRUPT_SENSE_1 5
79#define MC13783_REG_POWER_UP_MODE_SENSE 6
80#define MC13783_REG_REVISION 7
81#define MC13783_REG_SEMAPHORE 8
82#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
83#define MC13783_REG_ARBITRATION_SWITCHERS 10
84#define MC13783_REG_ARBITRATION_REGULATORS_0 11
85#define MC13783_REG_ARBITRATION_REGULATORS_1 12
86#define MC13783_REG_POWER_CONTROL_0 13
87#define MC13783_REG_POWER_CONTROL_1 14
88#define MC13783_REG_POWER_CONTROL_2 15
89#define MC13783_REG_REGEN_ASSIGNMENT 16
90#define MC13783_REG_CONTROL_SPARE 17
91#define MC13783_REG_MEMORY_A 18
92#define MC13783_REG_MEMORY_B 19
93#define MC13783_REG_RTC_TIME 20
94#define MC13783_REG_RTC_ALARM 21
95#define MC13783_REG_RTC_DAY 22
96#define MC13783_REG_RTC_DAY_ALARM 23
97#define MC13783_REG_SWITCHERS_0 24
98#define MC13783_REG_SWITCHERS_1 25
99#define MC13783_REG_SWITCHERS_2 26
100#define MC13783_REG_SWITCHERS_3 27
101#define MC13783_REG_SWITCHERS_4 28
102#define MC13783_REG_SWITCHERS_5 29
103#define MC13783_REG_REGULATOR_SETTING_0 30
104#define MC13783_REG_REGULATOR_SETTING_1 31
105#define MC13783_REG_REGULATOR_MODE_0 32
106#define MC13783_REG_REGULATOR_MODE_1 33
107#define MC13783_REG_POWER_MISCELLANEOUS 34
108#define MC13783_REG_POWER_SPARE 35
109#define MC13783_REG_AUDIO_RX_0 36
110#define MC13783_REG_AUDIO_RX_1 37
111#define MC13783_REG_AUDIO_TX 38
112#define MC13783_REG_AUDIO_SSI_NETWORK 39
113#define MC13783_REG_AUDIO_CODEC 40
114#define MC13783_REG_AUDIO_STEREO_DAC 41
115#define MC13783_REG_AUDIO_SPARE 42
116#define MC13783_REG_ADC_0 43
117#define MC13783_REG_ADC_1 44
118#define MC13783_REG_ADC_2 45
119#define MC13783_REG_ADC_3 46
120#define MC13783_REG_ADC_4 47
121#define MC13783_REG_CHARGER 48
122#define MC13783_REG_USB 49
123#define MC13783_REG_CHARGE_USB_SPARE 50
124#define MC13783_REG_LED_CONTROL_0 51
125#define MC13783_REG_LED_CONTROL_1 52
126#define MC13783_REG_LED_CONTROL_2 53
127#define MC13783_REG_LED_CONTROL_3 54
128#define MC13783_REG_LED_CONTROL_4 55
129#define MC13783_REG_LED_CONTROL_5 56
130#define MC13783_REG_SPARE 57
131#define MC13783_REG_TRIM_0 58
132#define MC13783_REG_TRIM_1 59
133#define MC13783_REG_TEST_0 60
134#define MC13783_REG_TEST_1 61
135#define MC13783_REG_TEST_2 62
136#define MC13783_REG_TEST_3 63
137#define MC13783_REG_NB 64
138
139
140/*
141 * Interrupt Status
142 */
143#define MC13783_INT_STAT_ADCDONEI (1 << 0)
144#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
145#define MC13783_INT_STAT_TSI (1 << 2)
146#define MC13783_INT_STAT_WHIGHI (1 << 3)
147#define MC13783_INT_STAT_WLOWI (1 << 4)
148#define MC13783_INT_STAT_CHGDETI (1 << 6)
149#define MC13783_INT_STAT_CHGOVI (1 << 7)
150#define MC13783_INT_STAT_CHGREVI (1 << 8)
151#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
152#define MC13783_INT_STAT_CCCVI (1 << 10)
153#define MC13783_INT_STAT_CHGCURRI (1 << 11)
154#define MC13783_INT_STAT_BPONI (1 << 12)
155#define MC13783_INT_STAT_LOBATLI (1 << 13)
156#define MC13783_INT_STAT_LOBATHI (1 << 14)
157#define MC13783_INT_STAT_UDPI (1 << 15)
158#define MC13783_INT_STAT_USBI (1 << 16)
159#define MC13783_INT_STAT_IDI (1 << 19)
160#define MC13783_INT_STAT_Unused (1 << 20)
161#define MC13783_INT_STAT_SE1I (1 << 21)
162#define MC13783_INT_STAT_CKDETI (1 << 22)
163#define MC13783_INT_STAT_UDMI (1 << 23)
164
165/*
166 * Interrupt Mask
167 */
168#define MC13783_INT_MASK_ADCDONEM (1 << 0)
169#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
170#define MC13783_INT_MASK_TSM (1 << 2)
171#define MC13783_INT_MASK_WHIGHM (1 << 3)
172#define MC13783_INT_MASK_WLOWM (1 << 4)
173#define MC13783_INT_MASK_CHGDETM (1 << 6)
174#define MC13783_INT_MASK_CHGOVM (1 << 7)
175#define MC13783_INT_MASK_CHGREVM (1 << 8)
176#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
177#define MC13783_INT_MASK_CCCVM (1 << 10)
178#define MC13783_INT_MASK_CHGCURRM (1 << 11)
179#define MC13783_INT_MASK_BPONM (1 << 12)
180#define MC13783_INT_MASK_LOBATLM (1 << 13)
181#define MC13783_INT_MASK_LOBATHM (1 << 14)
182#define MC13783_INT_MASK_UDPM (1 << 15)
183#define MC13783_INT_MASK_USBM (1 << 16)
184#define MC13783_INT_MASK_IDM (1 << 19)
185#define MC13783_INT_MASK_SE1M (1 << 21)
186#define MC13783_INT_MASK_CKDETM (1 << 22)
187
188/*
189 * Reg Regulator Mode 0
190 */
191#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
192#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
193#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
194#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
195#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
196#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
197#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
198#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
199#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
200#define MC13783_REGCTRL_VDIG_EN (1 << 9)
201#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
202#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
203#define MC13783_REGCTRL_VGEN_EN (1 << 12)
204#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
205#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
206#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
207#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
208#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
209#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
210#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
211#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
212#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
213#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
214#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
215
216/*
217 * Reg Regulator Mode 1
218 */
219#define MC13783_REGCTRL_VSIM_EN (1 << 0)
220#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
221#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
222#define MC13783_REGCTRL_VESIM_EN (1 << 3)
223#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
224#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
225#define MC13783_REGCTRL_VCAM_EN (1 << 6)
226#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
227#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
228#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
229#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
230#define MC13783_REGCTRL_VVIB_EN (1 << 11)
231#define MC13783_REGCTRL_VRF1_EN (1 << 12)
232#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
233#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
234#define MC13783_REGCTRL_VRF2_EN (1 << 15)
235#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
236#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
237#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
238#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
239#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
240#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
241#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
242#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
243
244/*
245 * Reg Regulator Misc.
246 */
247#define MC13783_REGCTRL_GPO1_EN (1 << 6)
248#define MC13783_REGCTRL_GPO2_EN (1 << 8)
249#define MC13783_REGCTRL_GPO3_EN (1 << 10)
250#define MC13783_REGCTRL_GPO4_EN (1 << 12)
251#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
252
253/*
254 * Reg Switcher 4
255 */
256#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
257#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
258#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
259#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
260#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
261#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
262#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
263#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
264#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
265#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
266#define MC13783_SWCTRL_PLL_EN (1 << 18)
267#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
268
269/*
270 * Reg Switcher 5
271 */
272#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
273#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
274#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
275#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
276#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
277#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
278#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
279#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
280#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
281#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
282#define MC13783_SWSET_SW3 (1 << 18)
283#define MC13783_SWCTRL_SW3_EN (1 << 20)
284#define MC13783_SWCTRL_SW3_STBY (1 << 21)
285#define MC13783_SWCTRL_SW3_MODE (1 << 22)
286
287/*
288 * ADC/Touch
289 */
290#define MC13783_ADC0_LICELLCON (1 << 0)
291#define MC13783_ADC0_CHRGICON (1 << 1)
292#define MC13783_ADC0_BATICON (1 << 2)
293#define MC13783_ADC0_RTHEN (1 << 3)
294#define MC13783_ADC0_DTHEN (1 << 4)
295#define MC13783_ADC0_UIDEN (1 << 5)
296#define MC13783_ADC0_ADOUTEN (1 << 6)
297#define MC13783_ADC0_ADOUTPER (1 << 7)
298#define MC13783_ADC0_ADREFEN (1 << 10)
299#define MC13783_ADC0_ADREFMODE (1 << 11)
300#define MC13783_ADC0_TSMOD0 (1 << 12)
301#define MC13783_ADC0_TSMOD1 (1 << 13)
302#define MC13783_ADC0_TSMOD2 (1 << 14)
303#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
304#define MC13783_ADC0_ADINC1 (1 << 16)
305#define MC13783_ADC0_ADINC2 (1 << 17)
306#define MC13783_ADC0_WCOMP (1 << 18)
307#define MC13783_ADC0_ADCBIS0 (1 << 23)
308
309#define MC13783_ADC1_ADEN (1 << 0)
310#define MC13783_ADC1_RAND (1 << 1)
311#define MC13783_ADC1_ADSEL (1 << 3)
312#define MC13783_ADC1_TRIGMASK (1 << 4)
313#define MC13783_ADC1_ADA10 (1 << 5)
314#define MC13783_ADC1_ADA11 (1 << 6)
315#define MC13783_ADC1_ADA12 (1 << 7)
316#define MC13783_ADC1_ADA20 (1 << 8)
317#define MC13783_ADC1_ADA21 (1 << 9)
318#define MC13783_ADC1_ADA22 (1 << 10)
319#define MC13783_ADC1_ATO0 (1 << 11)
320#define MC13783_ADC1_ATO1 (1 << 12)
321#define MC13783_ADC1_ATO2 (1 << 13)
322#define MC13783_ADC1_ATO3 (1 << 14)
323#define MC13783_ADC1_ATO4 (1 << 15)
324#define MC13783_ADC1_ATO5 (1 << 16)
325#define MC13783_ADC1_ATO6 (1 << 17)
326#define MC13783_ADC1_ATO7 (1 << 18)
327#define MC13783_ADC1_ATOX (1 << 19)
328#define MC13783_ADC1_ASC (1 << 20)
329#define MC13783_ADC1_ADTRIGIGN (1 << 21)
330#define MC13783_ADC1_ADONESHOT (1 << 22)
331#define MC13783_ADC1_ADCBIS1 (1 << 23)
332
333#define MC13783_ADC1_CHAN0_SHIFT 5
334#define MC13783_ADC1_CHAN1_SHIFT 8
335
336#define MC13783_ADC2_ADD10 (1 << 2)
337#define MC13783_ADC2_ADD11 (1 << 3)
338#define MC13783_ADC2_ADD12 (1 << 4)
339#define MC13783_ADC2_ADD13 (1 << 5)
340#define MC13783_ADC2_ADD14 (1 << 6)
341#define MC13783_ADC2_ADD15 (1 << 7)
342#define MC13783_ADC2_ADD16 (1 << 8)
343#define MC13783_ADC2_ADD17 (1 << 9)
344#define MC13783_ADC2_ADD18 (1 << 10)
345#define MC13783_ADC2_ADD19 (1 << 11)
346#define MC13783_ADC2_ADD20 (1 << 14)
347#define MC13783_ADC2_ADD21 (1 << 15)
348#define MC13783_ADC2_ADD22 (1 << 16)
349#define MC13783_ADC2_ADD23 (1 << 17)
350#define MC13783_ADC2_ADD24 (1 << 18)
351#define MC13783_ADC2_ADD25 (1 << 19)
352#define MC13783_ADC2_ADD26 (1 << 20)
353#define MC13783_ADC2_ADD27 (1 << 21)
354#define MC13783_ADC2_ADD28 (1 << 22)
355#define MC13783_ADC2_ADD29 (1 << 23)
356
357#define MC13783_ADC3_WHIGH0 (1 << 0)
358#define MC13783_ADC3_WHIGH1 (1 << 1)
359#define MC13783_ADC3_WHIGH2 (1 << 2)
360#define MC13783_ADC3_WHIGH3 (1 << 3)
361#define MC13783_ADC3_WHIGH4 (1 << 4)
362#define MC13783_ADC3_WHIGH5 (1 << 5)
363#define MC13783_ADC3_ICID0 (1 << 6)
364#define MC13783_ADC3_ICID1 (1 << 7)
365#define MC13783_ADC3_ICID2 (1 << 8)
366#define MC13783_ADC3_WLOW0 (1 << 9)
367#define MC13783_ADC3_WLOW1 (1 << 10)
368#define MC13783_ADC3_WLOW2 (1 << 11)
369#define MC13783_ADC3_WLOW3 (1 << 12)
370#define MC13783_ADC3_WLOW4 (1 << 13)
371#define MC13783_ADC3_WLOW5 (1 << 14)
372#define MC13783_ADC3_ADCBIS2 (1 << 23)
373
374#define MC13783_ADC4_ADDBIS10 (1 << 2)
375#define MC13783_ADC4_ADDBIS11 (1 << 3)
376#define MC13783_ADC4_ADDBIS12 (1 << 4)
377#define MC13783_ADC4_ADDBIS13 (1 << 5)
378#define MC13783_ADC4_ADDBIS14 (1 << 6)
379#define MC13783_ADC4_ADDBIS15 (1 << 7)
380#define MC13783_ADC4_ADDBIS16 (1 << 8)
381#define MC13783_ADC4_ADDBIS17 (1 << 9)
382#define MC13783_ADC4_ADDBIS18 (1 << 10)
383#define MC13783_ADC4_ADDBIS19 (1 << 11)
384#define MC13783_ADC4_ADDBIS20 (1 << 14)
385#define MC13783_ADC4_ADDBIS21 (1 << 15)
386#define MC13783_ADC4_ADDBIS22 (1 << 16)
387#define MC13783_ADC4_ADDBIS23 (1 << 17)
388#define MC13783_ADC4_ADDBIS24 (1 << 18)
389#define MC13783_ADC4_ADDBIS25 (1 << 19)
390#define MC13783_ADC4_ADDBIS26 (1 << 20)
391#define MC13783_ADC4_ADDBIS27 (1 << 21)
392#define MC13783_ADC4_ADDBIS28 (1 << 22)
393#define MC13783_ADC4_ADDBIS29 (1 << 23)
394
395#endif /* __LINUX_MFD_MC13783_PRIV_H */
396
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
new file mode 100644
index 000000000000..b3a2a7243573
--- /dev/null
+++ b/include/linux/mfd/mc13783.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __INCLUDE_LINUX_MFD_MC13783_H
23#define __INCLUDE_LINUX_MFD_MC13783_H
24
25struct mc13783;
26struct regulator_init_data;
27
28struct mc13783_regulator_init_data {
29 int id;
30 struct regulator_init_data *init_data;
31};
32
33struct mc13783_platform_data {
34 struct mc13783_regulator_init_data *regulators;
35 int num_regulators;
36 unsigned int flags;
37};
38
39/* mc13783_platform_data flags */
40#define MC13783_USE_TOUCHSCREEN (1 << 0)
41#define MC13783_USE_CODEC (1 << 1)
42#define MC13783_USE_ADC (1 << 2)
43#define MC13783_USE_RTC (1 << 3)
44#define MC13783_USE_REGULATOR (1 << 4)
45
46int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
47 unsigned int channel, unsigned int *sample);
48
49void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
50
51#define MC13783_SW_SW1A 0
52#define MC13783_SW_SW1B 1
53#define MC13783_SW_SW2A 2
54#define MC13783_SW_SW2B 3
55#define MC13783_SW_SW3 4
56#define MC13783_SW_PLL 5
57#define MC13783_REGU_VAUDIO 6
58#define MC13783_REGU_VIOHI 7
59#define MC13783_REGU_VIOLO 8
60#define MC13783_REGU_VDIG 9
61#define MC13783_REGU_VGEN 10
62#define MC13783_REGU_VRFDIG 11
63#define MC13783_REGU_VRFREF 12
64#define MC13783_REGU_VRFCP 13
65#define MC13783_REGU_VSIM 14
66#define MC13783_REGU_VESIM 15
67#define MC13783_REGU_VCAM 16
68#define MC13783_REGU_VRFBG 17
69#define MC13783_REGU_VVIB 18
70#define MC13783_REGU_VRF1 19
71#define MC13783_REGU_VRF2 20
72#define MC13783_REGU_VMMC1 21
73#define MC13783_REGU_VMMC2 22
74#define MC13783_REGU_GPO1 23
75#define MC13783_REGU_GPO2 24
76#define MC13783_REGU_GPO3 25
77#define MC13783_REGU_GPO4 26
78#define MC13783_REGU_V1 27
79#define MC13783_REGU_V2 28
80#define MC13783_REGU_V3 29
81#define MC13783_REGU_V4 30
82
83#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
84
diff --git a/include/linux/mfd/pcf50633/adc.h b/include/linux/mfd/pcf50633/adc.h
index 56669b4183ad..b35e62801ffa 100644
--- a/include/linux/mfd/pcf50633/adc.h
+++ b/include/linux/mfd/pcf50633/adc.h
@@ -25,7 +25,8 @@
25#define PCF50633_REG_ADCS3 0x57 25#define PCF50633_REG_ADCS3 0x57
26 26
27#define PCF50633_ADCC1_ADCSTART 0x01 27#define PCF50633_ADCC1_ADCSTART 0x01
28#define PCF50633_ADCC1_RES_10BIT 0x02 28#define PCF50633_ADCC1_RES_8BIT 0x02
29#define PCF50633_ADCC1_RES_10BIT 0x00
29#define PCF50633_ADCC1_AVERAGE_NO 0x00 30#define PCF50633_ADCC1_AVERAGE_NO 0x00
30#define PCF50633_ADCC1_AVERAGE_4 0x04 31#define PCF50633_ADCC1_AVERAGE_4 0x04
31#define PCF50633_ADCC1_AVERAGE_8 0x08 32#define PCF50633_ADCC1_AVERAGE_8 0x08
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index c8f51c3c0a72..9aba7b779fbc 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -136,6 +136,7 @@ struct pcf50633 {
136 int irq; 136 int irq;
137 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 137 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
138 struct work_struct irq_work; 138 struct work_struct irq_work;
139 struct workqueue_struct *work_queue;
139 struct mutex lock; 140 struct mutex lock;
140 141
141 u8 mask_regs[5]; 142 u8 mask_regs[5];
diff --git a/include/linux/mfd/wm831x/auxadc.h b/include/linux/mfd/wm831x/auxadc.h
new file mode 100644
index 000000000000..b132067e9e99
--- /dev/null
+++ b/include/linux/mfd/wm831x/auxadc.h
@@ -0,0 +1,216 @@
1/*
2 * include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_AUXADC_H__
16#define __MFD_WM831X_AUXADC_H__
17
18/*
19 * R16429 (0x402D) - AuxADC Data
20 */
21#define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
22#define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
23#define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
24#define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
25#define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
26#define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
27
28/*
29 * R16430 (0x402E) - AuxADC Control
30 */
31#define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
32#define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
33#define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */
34#define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */
35#define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
36#define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
37#define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */
38#define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */
39#define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */
40#define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */
41#define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */
42#define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */
43#define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */
44#define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */
45#define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */
46#define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */
47#define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */
48#define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */
49#define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */
50
51/*
52 * R16431 (0x402F) - AuxADC Source
53 */
54#define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */
55#define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */
56#define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */
57#define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */
58#define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */
59#define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */
60#define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */
61#define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */
62#define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */
63#define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */
64#define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */
65#define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */
66#define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */
67#define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */
68#define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */
69#define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */
70#define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */
71#define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */
72#define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */
73#define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */
74#define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */
75#define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */
76#define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */
77#define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */
78#define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */
79#define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */
80#define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */
81#define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */
82#define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */
83#define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */
84#define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */
85#define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */
86#define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */
87#define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */
88#define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */
89#define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */
90#define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */
91#define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */
92#define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */
93#define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */
94#define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */
95#define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */
96#define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */
97#define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */
98#define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */
99#define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */
100#define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */
101#define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */
102
103/*
104 * R16432 (0x4030) - Comparator Control
105 */
106#define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */
107#define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */
108#define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */
109#define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */
110#define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */
111#define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */
112#define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */
113#define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */
114#define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */
115#define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */
116#define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */
117#define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */
118#define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */
119#define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */
120#define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */
121#define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */
122#define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */
123#define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */
124#define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */
125#define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */
126#define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */
127#define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */
128#define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */
129#define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */
130#define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */
131#define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */
132#define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */
133#define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */
134#define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */
135#define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */
136#define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */
137#define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */
138
139/*
140 * R16433 (0x4031) - Comparator 1
141 */
142#define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */
143#define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */
144#define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */
145#define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */
146#define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */
147#define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */
148#define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */
149#define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */
150#define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */
151#define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */
152
153/*
154 * R16434 (0x4032) - Comparator 2
155 */
156#define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */
157#define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */
158#define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */
159#define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */
160#define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */
161#define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */
162#define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */
163#define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */
164#define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */
165#define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */
166
167/*
168 * R16435 (0x4033) - Comparator 3
169 */
170#define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */
171#define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */
172#define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */
173#define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */
174#define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */
175#define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */
176#define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */
177#define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */
178#define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */
179#define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */
180
181/*
182 * R16436 (0x4034) - Comparator 4
183 */
184#define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */
185#define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */
186#define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */
187#define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */
188#define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */
189#define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */
190#define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */
191#define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */
192#define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */
193#define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */
194
195#define WM831X_AUX_CAL_FACTOR 0xfff
196#define WM831X_AUX_CAL_NOMINAL 0x222
197
198enum wm831x_auxadc {
199 WM831X_AUX_CAL = 15,
200 WM831X_AUX_BKUP_BATT = 10,
201 WM831X_AUX_WALL = 9,
202 WM831X_AUX_BATT = 8,
203 WM831X_AUX_USB = 7,
204 WM831X_AUX_SYSVDD = 6,
205 WM831X_AUX_BATT_TEMP = 5,
206 WM831X_AUX_CHIP_TEMP = 4,
207 WM831X_AUX_AUX4 = 3,
208 WM831X_AUX_AUX3 = 2,
209 WM831X_AUX_AUX2 = 1,
210 WM831X_AUX_AUX1 = 0,
211};
212
213int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input);
214int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input);
215
216#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
new file mode 100644
index 000000000000..91eb493bf14c
--- /dev/null
+++ b/include/linux/mfd/wm831x/core.h
@@ -0,0 +1,289 @@
1/*
2 * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_CORE_H__
16#define __MFD_WM831X_CORE_H__
17
18#include <linux/interrupt.h>
19#include <linux/workqueue.h>
20
21/*
22 * Register values.
23 */
24#define WM831X_RESET_ID 0x00
25#define WM831X_REVISION 0x01
26#define WM831X_PARENT_ID 0x4000
27#define WM831X_SYSVDD_CONTROL 0x4001
28#define WM831X_THERMAL_MONITORING 0x4002
29#define WM831X_POWER_STATE 0x4003
30#define WM831X_WATCHDOG 0x4004
31#define WM831X_ON_PIN_CONTROL 0x4005
32#define WM831X_RESET_CONTROL 0x4006
33#define WM831X_CONTROL_INTERFACE 0x4007
34#define WM831X_SECURITY_KEY 0x4008
35#define WM831X_SOFTWARE_SCRATCH 0x4009
36#define WM831X_OTP_CONTROL 0x400A
37#define WM831X_GPIO_LEVEL 0x400C
38#define WM831X_SYSTEM_STATUS 0x400D
39#define WM831X_ON_SOURCE 0x400E
40#define WM831X_OFF_SOURCE 0x400F
41#define WM831X_SYSTEM_INTERRUPTS 0x4010
42#define WM831X_INTERRUPT_STATUS_1 0x4011
43#define WM831X_INTERRUPT_STATUS_2 0x4012
44#define WM831X_INTERRUPT_STATUS_3 0x4013
45#define WM831X_INTERRUPT_STATUS_4 0x4014
46#define WM831X_INTERRUPT_STATUS_5 0x4015
47#define WM831X_IRQ_CONFIG 0x4017
48#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
49#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
50#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
51#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
52#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
53#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
54#define WM831X_RTC_WRITE_COUNTER 0x4020
55#define WM831X_RTC_TIME_1 0x4021
56#define WM831X_RTC_TIME_2 0x4022
57#define WM831X_RTC_ALARM_1 0x4023
58#define WM831X_RTC_ALARM_2 0x4024
59#define WM831X_RTC_CONTROL 0x4025
60#define WM831X_RTC_TRIM 0x4026
61#define WM831X_TOUCH_CONTROL_1 0x4028
62#define WM831X_TOUCH_CONTROL_2 0x4029
63#define WM831X_TOUCH_DATA_X 0x402A
64#define WM831X_TOUCH_DATA_Y 0x402B
65#define WM831X_TOUCH_DATA_Z 0x402C
66#define WM831X_AUXADC_DATA 0x402D
67#define WM831X_AUXADC_CONTROL 0x402E
68#define WM831X_AUXADC_SOURCE 0x402F
69#define WM831X_COMPARATOR_CONTROL 0x4030
70#define WM831X_COMPARATOR_1 0x4031
71#define WM831X_COMPARATOR_2 0x4032
72#define WM831X_COMPARATOR_3 0x4033
73#define WM831X_COMPARATOR_4 0x4034
74#define WM831X_GPIO1_CONTROL 0x4038
75#define WM831X_GPIO2_CONTROL 0x4039
76#define WM831X_GPIO3_CONTROL 0x403A
77#define WM831X_GPIO4_CONTROL 0x403B
78#define WM831X_GPIO5_CONTROL 0x403C
79#define WM831X_GPIO6_CONTROL 0x403D
80#define WM831X_GPIO7_CONTROL 0x403E
81#define WM831X_GPIO8_CONTROL 0x403F
82#define WM831X_GPIO9_CONTROL 0x4040
83#define WM831X_GPIO10_CONTROL 0x4041
84#define WM831X_GPIO11_CONTROL 0x4042
85#define WM831X_GPIO12_CONTROL 0x4043
86#define WM831X_GPIO13_CONTROL 0x4044
87#define WM831X_GPIO14_CONTROL 0x4045
88#define WM831X_GPIO15_CONTROL 0x4046
89#define WM831X_GPIO16_CONTROL 0x4047
90#define WM831X_CHARGER_CONTROL_1 0x4048
91#define WM831X_CHARGER_CONTROL_2 0x4049
92#define WM831X_CHARGER_STATUS 0x404A
93#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
94#define WM831X_STATUS_LED_1 0x404C
95#define WM831X_STATUS_LED_2 0x404D
96#define WM831X_CURRENT_SINK_1 0x404E
97#define WM831X_CURRENT_SINK_2 0x404F
98#define WM831X_DCDC_ENABLE 0x4050
99#define WM831X_LDO_ENABLE 0x4051
100#define WM831X_DCDC_STATUS 0x4052
101#define WM831X_LDO_STATUS 0x4053
102#define WM831X_DCDC_UV_STATUS 0x4054
103#define WM831X_LDO_UV_STATUS 0x4055
104#define WM831X_DC1_CONTROL_1 0x4056
105#define WM831X_DC1_CONTROL_2 0x4057
106#define WM831X_DC1_ON_CONFIG 0x4058
107#define WM831X_DC1_SLEEP_CONTROL 0x4059
108#define WM831X_DC1_DVS_CONTROL 0x405A
109#define WM831X_DC2_CONTROL_1 0x405B
110#define WM831X_DC2_CONTROL_2 0x405C
111#define WM831X_DC2_ON_CONFIG 0x405D
112#define WM831X_DC2_SLEEP_CONTROL 0x405E
113#define WM831X_DC2_DVS_CONTROL 0x405F
114#define WM831X_DC3_CONTROL_1 0x4060
115#define WM831X_DC3_CONTROL_2 0x4061
116#define WM831X_DC3_ON_CONFIG 0x4062
117#define WM831X_DC3_SLEEP_CONTROL 0x4063
118#define WM831X_DC4_CONTROL 0x4064
119#define WM831X_DC4_SLEEP_CONTROL 0x4065
120#define WM831X_EPE1_CONTROL 0x4066
121#define WM831X_EPE2_CONTROL 0x4067
122#define WM831X_LDO1_CONTROL 0x4068
123#define WM831X_LDO1_ON_CONTROL 0x4069
124#define WM831X_LDO1_SLEEP_CONTROL 0x406A
125#define WM831X_LDO2_CONTROL 0x406B
126#define WM831X_LDO2_ON_CONTROL 0x406C
127#define WM831X_LDO2_SLEEP_CONTROL 0x406D
128#define WM831X_LDO3_CONTROL 0x406E
129#define WM831X_LDO3_ON_CONTROL 0x406F
130#define WM831X_LDO3_SLEEP_CONTROL 0x4070
131#define WM831X_LDO4_CONTROL 0x4071
132#define WM831X_LDO4_ON_CONTROL 0x4072
133#define WM831X_LDO4_SLEEP_CONTROL 0x4073
134#define WM831X_LDO5_CONTROL 0x4074
135#define WM831X_LDO5_ON_CONTROL 0x4075
136#define WM831X_LDO5_SLEEP_CONTROL 0x4076
137#define WM831X_LDO6_CONTROL 0x4077
138#define WM831X_LDO6_ON_CONTROL 0x4078
139#define WM831X_LDO6_SLEEP_CONTROL 0x4079
140#define WM831X_LDO7_CONTROL 0x407A
141#define WM831X_LDO7_ON_CONTROL 0x407B
142#define WM831X_LDO7_SLEEP_CONTROL 0x407C
143#define WM831X_LDO8_CONTROL 0x407D
144#define WM831X_LDO8_ON_CONTROL 0x407E
145#define WM831X_LDO8_SLEEP_CONTROL 0x407F
146#define WM831X_LDO9_CONTROL 0x4080
147#define WM831X_LDO9_ON_CONTROL 0x4081
148#define WM831X_LDO9_SLEEP_CONTROL 0x4082
149#define WM831X_LDO10_CONTROL 0x4083
150#define WM831X_LDO10_ON_CONTROL 0x4084
151#define WM831X_LDO10_SLEEP_CONTROL 0x4085
152#define WM831X_LDO11_ON_CONTROL 0x4087
153#define WM831X_LDO11_SLEEP_CONTROL 0x4088
154#define WM831X_POWER_GOOD_SOURCE_1 0x408E
155#define WM831X_POWER_GOOD_SOURCE_2 0x408F
156#define WM831X_CLOCK_CONTROL_1 0x4090
157#define WM831X_CLOCK_CONTROL_2 0x4091
158#define WM831X_FLL_CONTROL_1 0x4092
159#define WM831X_FLL_CONTROL_2 0x4093
160#define WM831X_FLL_CONTROL_3 0x4094
161#define WM831X_FLL_CONTROL_4 0x4095
162#define WM831X_FLL_CONTROL_5 0x4096
163#define WM831X_UNIQUE_ID_1 0x7800
164#define WM831X_UNIQUE_ID_2 0x7801
165#define WM831X_UNIQUE_ID_3 0x7802
166#define WM831X_UNIQUE_ID_4 0x7803
167#define WM831X_UNIQUE_ID_5 0x7804
168#define WM831X_UNIQUE_ID_6 0x7805
169#define WM831X_UNIQUE_ID_7 0x7806
170#define WM831X_UNIQUE_ID_8 0x7807
171#define WM831X_FACTORY_OTP_ID 0x7808
172#define WM831X_FACTORY_OTP_1 0x7809
173#define WM831X_FACTORY_OTP_2 0x780A
174#define WM831X_FACTORY_OTP_3 0x780B
175#define WM831X_FACTORY_OTP_4 0x780C
176#define WM831X_FACTORY_OTP_5 0x780D
177#define WM831X_CUSTOMER_OTP_ID 0x7810
178#define WM831X_DC1_OTP_CONTROL 0x7811
179#define WM831X_DC2_OTP_CONTROL 0x7812
180#define WM831X_DC3_OTP_CONTROL 0x7813
181#define WM831X_LDO1_2_OTP_CONTROL 0x7814
182#define WM831X_LDO3_4_OTP_CONTROL 0x7815
183#define WM831X_LDO5_6_OTP_CONTROL 0x7816
184#define WM831X_LDO7_8_OTP_CONTROL 0x7817
185#define WM831X_LDO9_10_OTP_CONTROL 0x7818
186#define WM831X_LDO11_EPE_CONTROL 0x7819
187#define WM831X_GPIO1_OTP_CONTROL 0x781A
188#define WM831X_GPIO2_OTP_CONTROL 0x781B
189#define WM831X_GPIO3_OTP_CONTROL 0x781C
190#define WM831X_GPIO4_OTP_CONTROL 0x781D
191#define WM831X_GPIO5_OTP_CONTROL 0x781E
192#define WM831X_GPIO6_OTP_CONTROL 0x781F
193#define WM831X_DBE_CHECK_DATA 0x7827
194
195/*
196 * R0 (0x00) - Reset ID
197 */
198#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
199#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
200#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
201
202/*
203 * R1 (0x01) - Revision
204 */
205#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
206#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
207#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
208#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
209#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
210#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
211
212/*
213 * R16384 (0x4000) - Parent ID
214 */
215#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
216#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
217#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
218
219/*
220 * R16389 (0x4005) - ON Pin Control
221 */
222#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
223#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
224#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
225#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
226#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
227#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
228#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
229#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
230#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
231#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
232#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
233#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
234#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
235
236struct regulator_dev;
237
238struct wm831x {
239 struct mutex io_lock;
240
241 struct device *dev;
242 int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
243 int bytes, void *dest);
244 int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
245 int bytes, void *src);
246
247 void *control_data;
248
249 int irq; /* Our chip IRQ */
250 struct mutex irq_lock;
251 struct workqueue_struct *irq_wq;
252 struct work_struct irq_work;
253 unsigned int irq_base;
254 int irq_masks[5];
255
256 struct mutex auxadc_lock;
257
258 /* The WM831x has a security key blocking access to certain
259 * registers. The mutex is taken by the accessors for locking
260 * and unlocking the security key, locked is used to fail
261 * writes if the lock is held.
262 */
263 struct mutex key_lock;
264 unsigned int locked:1;
265};
266
267/* Device I/O API */
268int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
269int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
270 unsigned short val);
271void wm831x_reg_lock(struct wm831x *wm831x);
272int wm831x_reg_unlock(struct wm831x *wm831x);
273int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
274 unsigned short mask, unsigned short val);
275int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
276 int count, u16 *buf);
277
278int wm831x_irq_init(struct wm831x *wm831x, int irq);
279void wm831x_irq_exit(struct wm831x *wm831x);
280
281int __must_check wm831x_request_irq(struct wm831x *wm831x,
282 unsigned int irq, irq_handler_t handler,
283 unsigned long flags, const char *name,
284 void *dev);
285void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
286void wm831x_disable_irq(struct wm831x *wm831x, int irq);
287void wm831x_enable_irq(struct wm831x *wm831x, int irq);
288
289#endif
diff --git a/include/linux/mfd/wm831x/gpio.h b/include/linux/mfd/wm831x/gpio.h
new file mode 100644
index 000000000000..2835614af0e3
--- /dev/null
+++ b/include/linux/mfd/wm831x/gpio.h
@@ -0,0 +1,55 @@
1/*
2 * include/linux/mfd/wm831x/gpio.h -- GPIO for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_GPIO_H__
16#define __MFD_WM831X_GPIO_H__
17
18/*
19 * R16440-16455 (0x4038-0x4047) - GPIOx Control
20 */
21#define WM831X_GPN_DIR 0x8000 /* GPN_DIR */
22#define WM831X_GPN_DIR_MASK 0x8000 /* GPN_DIR */
23#define WM831X_GPN_DIR_SHIFT 15 /* GPN_DIR */
24#define WM831X_GPN_DIR_WIDTH 1 /* GPN_DIR */
25#define WM831X_GPN_PULL_MASK 0x6000 /* GPN_PULL - [14:13] */
26#define WM831X_GPN_PULL_SHIFT 13 /* GPN_PULL - [14:13] */
27#define WM831X_GPN_PULL_WIDTH 2 /* GPN_PULL - [14:13] */
28#define WM831X_GPN_INT_MODE 0x1000 /* GPN_INT_MODE */
29#define WM831X_GPN_INT_MODE_MASK 0x1000 /* GPN_INT_MODE */
30#define WM831X_GPN_INT_MODE_SHIFT 12 /* GPN_INT_MODE */
31#define WM831X_GPN_INT_MODE_WIDTH 1 /* GPN_INT_MODE */
32#define WM831X_GPN_PWR_DOM 0x0800 /* GPN_PWR_DOM */
33#define WM831X_GPN_PWR_DOM_MASK 0x0800 /* GPN_PWR_DOM */
34#define WM831X_GPN_PWR_DOM_SHIFT 11 /* GPN_PWR_DOM */
35#define WM831X_GPN_PWR_DOM_WIDTH 1 /* GPN_PWR_DOM */
36#define WM831X_GPN_POL 0x0400 /* GPN_POL */
37#define WM831X_GPN_POL_MASK 0x0400 /* GPN_POL */
38#define WM831X_GPN_POL_SHIFT 10 /* GPN_POL */
39#define WM831X_GPN_POL_WIDTH 1 /* GPN_POL */
40#define WM831X_GPN_OD 0x0200 /* GPN_OD */
41#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
42#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
43#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
44#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
45#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
46#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
47#define WM831X_GPN_TRI_WIDTH 1 /* GPN_TRI */
48#define WM831X_GPN_FN_MASK 0x000F /* GPN_FN - [3:0] */
49#define WM831X_GPN_FN_SHIFT 0 /* GPN_FN - [3:0] */
50#define WM831X_GPN_FN_WIDTH 4 /* GPN_FN - [3:0] */
51
52#define WM831X_GPIO_PULL_NONE (0 << WM831X_GPN_PULL_SHIFT)
53#define WM831X_GPIO_PULL_DOWN (1 << WM831X_GPN_PULL_SHIFT)
54#define WM831X_GPIO_PULL_UP (2 << WM831X_GPN_PULL_SHIFT)
55#endif
diff --git a/include/linux/mfd/wm831x/irq.h b/include/linux/mfd/wm831x/irq.h
new file mode 100644
index 000000000000..3a8c97656fda
--- /dev/null
+++ b/include/linux/mfd/wm831x/irq.h
@@ -0,0 +1,764 @@
1/*
2 * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_IRQ_H__
16#define __MFD_WM831X_IRQ_H__
17
18/* Interrupt number assignments within Linux */
19#define WM831X_IRQ_TEMP_THW 0
20#define WM831X_IRQ_GPIO_1 1
21#define WM831X_IRQ_GPIO_2 2
22#define WM831X_IRQ_GPIO_3 3
23#define WM831X_IRQ_GPIO_4 4
24#define WM831X_IRQ_GPIO_5 5
25#define WM831X_IRQ_GPIO_6 6
26#define WM831X_IRQ_GPIO_7 7
27#define WM831X_IRQ_GPIO_8 8
28#define WM831X_IRQ_GPIO_9 9
29#define WM831X_IRQ_GPIO_10 10
30#define WM831X_IRQ_GPIO_11 11
31#define WM831X_IRQ_GPIO_12 12
32#define WM831X_IRQ_GPIO_13 13
33#define WM831X_IRQ_GPIO_14 14
34#define WM831X_IRQ_GPIO_15 15
35#define WM831X_IRQ_GPIO_16 16
36#define WM831X_IRQ_ON 17
37#define WM831X_IRQ_PPM_SYSLO 18
38#define WM831X_IRQ_PPM_PWR_SRC 19
39#define WM831X_IRQ_PPM_USB_CURR 20
40#define WM831X_IRQ_WDOG_TO 21
41#define WM831X_IRQ_RTC_PER 22
42#define WM831X_IRQ_RTC_ALM 23
43#define WM831X_IRQ_CHG_BATT_HOT 24
44#define WM831X_IRQ_CHG_BATT_COLD 25
45#define WM831X_IRQ_CHG_BATT_FAIL 26
46#define WM831X_IRQ_CHG_OV 27
47#define WM831X_IRQ_CHG_END 29
48#define WM831X_IRQ_CHG_TO 30
49#define WM831X_IRQ_CHG_MODE 31
50#define WM831X_IRQ_CHG_START 32
51#define WM831X_IRQ_TCHDATA 33
52#define WM831X_IRQ_TCHPD 34
53#define WM831X_IRQ_AUXADC_DATA 35
54#define WM831X_IRQ_AUXADC_DCOMP1 36
55#define WM831X_IRQ_AUXADC_DCOMP2 37
56#define WM831X_IRQ_AUXADC_DCOMP3 38
57#define WM831X_IRQ_AUXADC_DCOMP4 39
58#define WM831X_IRQ_CS1 40
59#define WM831X_IRQ_CS2 41
60#define WM831X_IRQ_HC_DC1 42
61#define WM831X_IRQ_HC_DC2 43
62#define WM831X_IRQ_UV_LDO1 44
63#define WM831X_IRQ_UV_LDO2 45
64#define WM831X_IRQ_UV_LDO3 46
65#define WM831X_IRQ_UV_LDO4 47
66#define WM831X_IRQ_UV_LDO5 48
67#define WM831X_IRQ_UV_LDO6 49
68#define WM831X_IRQ_UV_LDO7 50
69#define WM831X_IRQ_UV_LDO8 51
70#define WM831X_IRQ_UV_LDO9 52
71#define WM831X_IRQ_UV_LDO10 53
72#define WM831X_IRQ_UV_DC1 54
73#define WM831X_IRQ_UV_DC2 55
74#define WM831X_IRQ_UV_DC3 56
75#define WM831X_IRQ_UV_DC4 57
76
77#define WM831X_NUM_IRQS 58
78
79/*
80 * R16400 (0x4010) - System Interrupts
81 */
82#define WM831X_PS_INT 0x8000 /* PS_INT */
83#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
84#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
85#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
86#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
87#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
88#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
89#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
90#define WM831X_GP_INT 0x2000 /* GP_INT */
91#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
92#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
93#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
94#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
95#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
96#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
97#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
98#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
99#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
100#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
101#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
102#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
103#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
104#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
105#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
106#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
107#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
108#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
109#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
110#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
111#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
112#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
113#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
114#define WM831X_PPM_INT 0x0080 /* PPM_INT */
115#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
116#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
117#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
118#define WM831X_CS_INT 0x0040 /* CS_INT */
119#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
120#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
121#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
122#define WM831X_RTC_INT 0x0020 /* RTC_INT */
123#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
124#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
125#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
126#define WM831X_OTP_INT 0x0010 /* OTP_INT */
127#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
128#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
129#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
130#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
131#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
132#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
133#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
134#define WM831X_CHG_INT 0x0004 /* CHG_INT */
135#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
136#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
137#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
138#define WM831X_HC_INT 0x0002 /* HC_INT */
139#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
140#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
141#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
142#define WM831X_UV_INT 0x0001 /* UV_INT */
143#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
144#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
145#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
146
147/*
148 * R16401 (0x4011) - Interrupt Status 1
149 */
150#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
151#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
152#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
153#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
154#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
155#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
156#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
157#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
158#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
159#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
160#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
161#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
162#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
163#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
164#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
165#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
166#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
167#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
168#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
169#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
170#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
171#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
172#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
173#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
174#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
175#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
176#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
177#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
178#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
179#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
180#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
181#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
182#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
183#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
184#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
185#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
186#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
187#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
188#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
189#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
190#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
191#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
192#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
193#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
194#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
195#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
196#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
197#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
198#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
199#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
200#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
201#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
202#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
203#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
204#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
205#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
206#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
207#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
208#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
209#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
210
211/*
212 * R16402 (0x4012) - Interrupt Status 2
213 */
214#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
215#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
216#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
217#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
218#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
219#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
220#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
221#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
222#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
223#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
224#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
225#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
226#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
227#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
228#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
229#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
230#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
231#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
232#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
233#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
234#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
235#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
236#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
237#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
238#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
239#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
240#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
241#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
242#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
243#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
244#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
245#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
246#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
247#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
248#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
249#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
250#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
251#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
252#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
253#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
254#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
255#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
256#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
257#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
258#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
259#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
260#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
261#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
262#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
263#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
264#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
265#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
266#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
267#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
268#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
269#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
270#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
271#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
272#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
273#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
274
275/*
276 * R16403 (0x4013) - Interrupt Status 3
277 */
278#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
279#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
280#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
281#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
282#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
283#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
284#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
285#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
286#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
287#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
288#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
289#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
290#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
291#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
292#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
293#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
294#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
295#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
296#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
297#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
298#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
299#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
300#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
301#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
302#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
303#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
304#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
305#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
306#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
307#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
308#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
309#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
310#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
311#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
312#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
313#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
314#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
315#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
316#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
317#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
318
319/*
320 * R16404 (0x4014) - Interrupt Status 4
321 */
322#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
323#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
324#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
325#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
326#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
327#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
328#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
329#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
330#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
331#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
332#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
333#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
334#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
335#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
336#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
337#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
338#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
339#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
340#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
341#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
342#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
343#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
344#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
345#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
346
347/*
348 * R16405 (0x4015) - Interrupt Status 5
349 */
350#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
351#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
352#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
353#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
354#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
355#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
356#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
357#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
358#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
359#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
360#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
361#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
362#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
363#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
364#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
365#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
366#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
367#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
368#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
369#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
370#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
371#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
372#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
373#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
374#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
375#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
376#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
377#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
378#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
379#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
380#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
381#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
382#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
383#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
384#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
385#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
386#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
387#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
388#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
389#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
390#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
391#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
392#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
393#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
394#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
395#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
396#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
397#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
398#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
399#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
400#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
401#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
402#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
403#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
404#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
405#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
406#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
407#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
408#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
409#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
410#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
411#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
412#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
413#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
414
415/*
416 * R16407 (0x4017) - IRQ Config
417 */
418#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
419#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
420#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
421#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
422#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
423#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
424#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
425#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
426
427/*
428 * R16408 (0x4018) - System Interrupts Mask
429 */
430#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
431#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
432#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
433#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
434#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
435#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
436#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
437#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
438#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
439#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
440#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
441#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
442#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
443#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
444#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
445#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
446#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
447#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
448#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
449#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
450#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
451#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
452#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
453#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
454#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
455#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
456#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
457#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
458#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
459#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
460#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
461#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
462#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
463#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
464#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
465#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
466#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
467#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
468#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
469#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
470#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
471#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
472#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
473#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
474#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
475#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
476#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
477#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
478#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
479#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
480#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
481#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
482#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
483#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
484#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
485#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
486#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
487#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
488#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
489#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
490#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
491#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
492#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
493#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
494
495/*
496 * R16409 (0x4019) - Interrupt Status 1 Mask
497 */
498#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
499#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
500#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
501#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
502#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
503#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
504#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
505#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
506#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
507#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
508#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
509#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
510#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
511#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
512#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
513#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
514#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
515#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
516#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
517#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
518#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
519#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
520#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
521#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
522#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
523#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
524#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
525#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
526#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
527#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
528#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
529#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
530#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
531#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
532#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
533#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
534#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
535#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
536#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
537#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
538#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
539#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
540#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
541#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
542#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
543#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
544#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
545#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
546#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
547#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
548#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
549#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
550#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
551#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
552#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
553#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
554#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
555#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
556#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
557#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
558
559/*
560 * R16410 (0x401A) - Interrupt Status 2 Mask
561 */
562#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
563#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
564#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
565#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
566#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
567#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
568#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
569#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
570#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
571#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
572#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
573#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
574#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
575#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
576#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
577#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
578#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
579#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
580#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
581#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
582#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
583#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
584#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
585#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
586#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
587#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
588#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
589#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
590#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
591#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
592#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
593#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
594#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
595#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
596#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
597#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
598#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
599#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
600#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
601#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
602#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
603#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
604#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
605#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
606#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
607#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
608#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
609#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
610#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
611#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
612#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
613#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
614#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
615#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
616#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
617#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
618#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
619#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
620#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
621#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
622
623/*
624 * R16411 (0x401B) - Interrupt Status 3 Mask
625 */
626#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
627#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
628#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
629#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
630#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
631#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
632#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
633#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
634#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
635#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
636#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
637#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
638#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
639#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
640#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
641#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
642#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
643#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
644#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
645#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
646#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
647#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
648#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
649#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
650#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
651#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
652#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
653#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
654#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
655#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
656#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
657#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
658#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
659#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
660#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
661#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
662#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
663#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
664#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
665#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
666
667/*
668 * R16412 (0x401C) - Interrupt Status 4 Mask
669 */
670#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
671#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
672#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
673#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
674#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
675#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
676#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
677#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
678#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
679#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
680#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
681#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
682#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
683#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
684#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
685#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
686#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
687#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
688#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
689#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
690#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
691#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
692#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
693#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
694
695/*
696 * R16413 (0x401D) - Interrupt Status 5 Mask
697 */
698#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
699#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
700#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
701#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
702#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
703#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
704#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
705#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
706#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
707#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
708#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
709#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
710#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
711#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
712#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
713#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
714#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
715#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
716#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
717#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
718#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
719#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
720#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
721#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
722#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
723#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
724#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
725#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
726#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
727#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
728#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
729#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
730#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
731#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
732#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
733#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
734#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
735#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
736#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
737#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
738#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
739#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
740#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
741#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
742#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
743#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
744#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
745#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
746#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
747#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
748#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
749#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
750#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
751#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
752#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
753#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
754#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
755#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
756#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
757#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
758#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
759#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
760#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
761#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
762
763
764#endif
diff --git a/include/linux/mfd/wm831x/otp.h b/include/linux/mfd/wm831x/otp.h
new file mode 100644
index 000000000000..ce1f81a39bfc
--- /dev/null
+++ b/include/linux/mfd/wm831x/otp.h
@@ -0,0 +1,162 @@
1/*
2 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_OTP_H__
16#define __MFD_WM831X_OTP_H__
17
18int wm831x_otp_init(struct wm831x *wm831x);
19void wm831x_otp_exit(struct wm831x *wm831x);
20
21/*
22 * R30720 (0x7800) - Unique ID 1
23 */
24#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
25#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
26#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
27
28/*
29 * R30721 (0x7801) - Unique ID 2
30 */
31#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
32#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
33#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
34
35/*
36 * R30722 (0x7802) - Unique ID 3
37 */
38#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
39#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
40#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
41
42/*
43 * R30723 (0x7803) - Unique ID 4
44 */
45#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
46#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
47#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
48
49/*
50 * R30724 (0x7804) - Unique ID 5
51 */
52#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
53#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
54#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
55
56/*
57 * R30725 (0x7805) - Unique ID 6
58 */
59#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
60#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
61#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
62
63/*
64 * R30726 (0x7806) - Unique ID 7
65 */
66#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
67#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
68#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
69
70/*
71 * R30727 (0x7807) - Unique ID 8
72 */
73#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
74#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
75#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
76
77/*
78 * R30728 (0x7808) - Factory OTP ID
79 */
80#define WM831X_OTP_FACT_ID_MASK 0xFFFE /* OTP_FACT_ID - [15:1] */
81#define WM831X_OTP_FACT_ID_SHIFT 1 /* OTP_FACT_ID - [15:1] */
82#define WM831X_OTP_FACT_ID_WIDTH 15 /* OTP_FACT_ID - [15:1] */
83#define WM831X_OTP_FACT_FINAL 0x0001 /* OTP_FACT_FINAL */
84#define WM831X_OTP_FACT_FINAL_MASK 0x0001 /* OTP_FACT_FINAL */
85#define WM831X_OTP_FACT_FINAL_SHIFT 0 /* OTP_FACT_FINAL */
86#define WM831X_OTP_FACT_FINAL_WIDTH 1 /* OTP_FACT_FINAL */
87
88/*
89 * R30729 (0x7809) - Factory OTP 1
90 */
91#define WM831X_DC3_TRIM_MASK 0xF000 /* DC3_TRIM - [15:12] */
92#define WM831X_DC3_TRIM_SHIFT 12 /* DC3_TRIM - [15:12] */
93#define WM831X_DC3_TRIM_WIDTH 4 /* DC3_TRIM - [15:12] */
94#define WM831X_DC2_TRIM_MASK 0x0FC0 /* DC2_TRIM - [11:6] */
95#define WM831X_DC2_TRIM_SHIFT 6 /* DC2_TRIM - [11:6] */
96#define WM831X_DC2_TRIM_WIDTH 6 /* DC2_TRIM - [11:6] */
97#define WM831X_DC1_TRIM_MASK 0x003F /* DC1_TRIM - [5:0] */
98#define WM831X_DC1_TRIM_SHIFT 0 /* DC1_TRIM - [5:0] */
99#define WM831X_DC1_TRIM_WIDTH 6 /* DC1_TRIM - [5:0] */
100
101/*
102 * R30730 (0x780A) - Factory OTP 2
103 */
104#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
105#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
106#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
107
108/*
109 * R30731 (0x780B) - Factory OTP 3
110 */
111#define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
112#define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
113#define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
114#define WM831X_BG_TRIM_MASK 0x0078 /* BG_TRIM - [6:3] */
115#define WM831X_BG_TRIM_SHIFT 3 /* BG_TRIM - [6:3] */
116#define WM831X_BG_TRIM_WIDTH 4 /* BG_TRIM - [6:3] */
117#define WM831X_LPBG_TRIM_MASK 0x0007 /* LPBG_TRIM - [2:0] */
118#define WM831X_LPBG_TRIM_SHIFT 0 /* LPBG_TRIM - [2:0] */
119#define WM831X_LPBG_TRIM_WIDTH 3 /* LPBG_TRIM - [2:0] */
120
121/*
122 * R30732 (0x780C) - Factory OTP 4
123 */
124#define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
125#define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
126#define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
127#define WM831X_CH_AW 0x0001 /* CH_AW */
128#define WM831X_CH_AW_MASK 0x0001 /* CH_AW */
129#define WM831X_CH_AW_SHIFT 0 /* CH_AW */
130#define WM831X_CH_AW_WIDTH 1 /* CH_AW */
131
132/*
133 * R30733 (0x780D) - Factory OTP 5
134 */
135#define WM831X_CHARGE_TRIM_MASK 0x003F /* CHARGE_TRIM - [5:0] */
136#define WM831X_CHARGE_TRIM_SHIFT 0 /* CHARGE_TRIM - [5:0] */
137#define WM831X_CHARGE_TRIM_WIDTH 6 /* CHARGE_TRIM - [5:0] */
138
139/*
140 * R30736 (0x7810) - Customer OTP ID
141 */
142#define WM831X_OTP_AUTO_PROG 0x8000 /* OTP_AUTO_PROG */
143#define WM831X_OTP_AUTO_PROG_MASK 0x8000 /* OTP_AUTO_PROG */
144#define WM831X_OTP_AUTO_PROG_SHIFT 15 /* OTP_AUTO_PROG */
145#define WM831X_OTP_AUTO_PROG_WIDTH 1 /* OTP_AUTO_PROG */
146#define WM831X_OTP_CUST_ID_MASK 0x7FFE /* OTP_CUST_ID - [14:1] */
147#define WM831X_OTP_CUST_ID_SHIFT 1 /* OTP_CUST_ID - [14:1] */
148#define WM831X_OTP_CUST_ID_WIDTH 14 /* OTP_CUST_ID - [14:1] */
149#define WM831X_OTP_CUST_FINAL 0x0001 /* OTP_CUST_FINAL */
150#define WM831X_OTP_CUST_FINAL_MASK 0x0001 /* OTP_CUST_FINAL */
151#define WM831X_OTP_CUST_FINAL_SHIFT 0 /* OTP_CUST_FINAL */
152#define WM831X_OTP_CUST_FINAL_WIDTH 1 /* OTP_CUST_FINAL */
153
154/*
155 * R30759 (0x7827) - DBE CHECK DATA
156 */
157#define WM831X_DBE_VALID_DATA_MASK 0xFFFF /* DBE_VALID_DATA - [15:0] */
158#define WM831X_DBE_VALID_DATA_SHIFT 0 /* DBE_VALID_DATA - [15:0] */
159#define WM831X_DBE_VALID_DATA_WIDTH 16 /* DBE_VALID_DATA - [15:0] */
160
161
162#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
new file mode 100644
index 000000000000..90d820260aad
--- /dev/null
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -0,0 +1,113 @@
1/*
2 * include/linux/mfd/wm831x/pdata.h -- Platform data for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_PDATA_H__
16#define __MFD_WM831X_PDATA_H__
17
18struct wm831x;
19struct regulator_init_data;
20
21struct wm831x_backlight_pdata {
22 int isink; /** ISINK to use, 1 or 2 */
23 int max_uA; /** Maximum current to allow */
24};
25
26struct wm831x_backup_pdata {
27 int charger_enable;
28 int no_constant_voltage; /** Disable constant voltage charging */
29 int vlim; /** Voltage limit in milivolts */
30 int ilim; /** Current limit in microamps */
31};
32
33struct wm831x_battery_pdata {
34 int enable; /** Enable charging */
35 int fast_enable; /** Enable fast charging */
36 int off_mask; /** Mask OFF while charging */
37 int trickle_ilim; /** Trickle charge current limit, in mA */
38 int vsel; /** Target voltage, in mV */
39 int eoc_iterm; /** End of trickle charge current, in mA */
40 int fast_ilim; /** Fast charge current limit, in mA */
41 int timeout; /** Charge cycle timeout, in minutes */
42};
43
44/* Sources for status LED configuration. Values are register values
45 * plus 1 to allow for a zero default for preserve.
46 */
47enum wm831x_status_src {
48 WM831X_STATUS_PRESERVE = 0, /* Keep the current hardware setting */
49 WM831X_STATUS_OTP = 1,
50 WM831X_STATUS_POWER = 2,
51 WM831X_STATUS_CHARGER = 3,
52 WM831X_STATUS_MANUAL = 4,
53};
54
55struct wm831x_status_pdata {
56 enum wm831x_status_src default_src;
57 const char *name;
58 const char *default_trigger;
59};
60
61struct wm831x_touch_pdata {
62 int fivewire; /** 1 for five wire mode, 0 for 4 wire */
63 int isel; /** Current for pen down (uA) */
64 int rpu; /** Pen down sensitivity resistor divider */
65 int pressure; /** Report pressure (boolean) */
66 int data_irq; /** Touch data ready IRQ */
67};
68
69enum wm831x_watchdog_action {
70 WM831X_WDOG_NONE = 0,
71 WM831X_WDOG_INTERRUPT = 1,
72 WM831X_WDOG_RESET = 2,
73 WM831X_WDOG_WAKE = 3,
74};
75
76struct wm831x_watchdog_pdata {
77 enum wm831x_watchdog_action primary, secondary;
78 int update_gpio;
79 unsigned int software:1;
80};
81
82#define WM831X_MAX_STATUS 2
83#define WM831X_MAX_DCDC 4
84#define WM831X_MAX_EPE 2
85#define WM831X_MAX_LDO 11
86#define WM831X_MAX_ISINK 2
87
88struct wm831x_pdata {
89 /** Called before subdevices are set up */
90 int (*pre_init)(struct wm831x *wm831x);
91 /** Called after subdevices are set up */
92 int (*post_init)(struct wm831x *wm831x);
93
94 int gpio_base;
95 struct wm831x_backlight_pdata *backlight;
96 struct wm831x_backup_pdata *backup;
97 struct wm831x_battery_pdata *battery;
98 struct wm831x_touch_pdata *touch;
99 struct wm831x_watchdog_pdata *watchdog;
100
101 /** LED1 = 0 and so on */
102 struct wm831x_status_pdata *status[WM831X_MAX_STATUS];
103 /** DCDC1 = 0 and so on */
104 struct regulator_init_data *dcdc[WM831X_MAX_DCDC];
105 /** EPE1 = 0 and so on */
106 struct regulator_init_data *epe[WM831X_MAX_EPE];
107 /** LDO1 = 0 and so on */
108 struct regulator_init_data *ldo[WM831X_MAX_LDO];
109 /** ISINK1 = 0 and so on*/
110 struct regulator_init_data *isink[WM831X_MAX_ISINK];
111};
112
113#endif
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
new file mode 100644
index 000000000000..f95466343fb2
--- /dev/null
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -0,0 +1,1218 @@
1/*
2 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_REGULATOR_H__
16#define __MFD_WM831X_REGULATOR_H__
17
18/*
19 * R16462 (0x404E) - Current Sink 1
20 */
21#define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
22#define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
23#define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
24#define WM831X_CS1_ENA_WIDTH 1 /* CS1_ENA */
25#define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
26#define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
27#define WM831X_CS1_DRIVE_SHIFT 14 /* CS1_DRIVE */
28#define WM831X_CS1_DRIVE_WIDTH 1 /* CS1_DRIVE */
29#define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
30#define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
31#define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
32#define WM831X_CS1_SLPENA_WIDTH 1 /* CS1_SLPENA */
33#define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
34#define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
35#define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
36#define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
37#define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
38#define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
39#define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
40#define WM831X_CS1_ISEL_SHIFT 0 /* CS1_ISEL - [5:0] */
41#define WM831X_CS1_ISEL_WIDTH 6 /* CS1_ISEL - [5:0] */
42
43/*
44 * R16463 (0x404F) - Current Sink 2
45 */
46#define WM831X_CS2_ENA 0x8000 /* CS2_ENA */
47#define WM831X_CS2_ENA_MASK 0x8000 /* CS2_ENA */
48#define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */
49#define WM831X_CS2_ENA_WIDTH 1 /* CS2_ENA */
50#define WM831X_CS2_DRIVE 0x4000 /* CS2_DRIVE */
51#define WM831X_CS2_DRIVE_MASK 0x4000 /* CS2_DRIVE */
52#define WM831X_CS2_DRIVE_SHIFT 14 /* CS2_DRIVE */
53#define WM831X_CS2_DRIVE_WIDTH 1 /* CS2_DRIVE */
54#define WM831X_CS2_SLPENA 0x1000 /* CS2_SLPENA */
55#define WM831X_CS2_SLPENA_MASK 0x1000 /* CS2_SLPENA */
56#define WM831X_CS2_SLPENA_SHIFT 12 /* CS2_SLPENA */
57#define WM831X_CS2_SLPENA_WIDTH 1 /* CS2_SLPENA */
58#define WM831X_CS2_OFF_RAMP_MASK 0x0C00 /* CS2_OFF_RAMP - [11:10] */
59#define WM831X_CS2_OFF_RAMP_SHIFT 10 /* CS2_OFF_RAMP - [11:10] */
60#define WM831X_CS2_OFF_RAMP_WIDTH 2 /* CS2_OFF_RAMP - [11:10] */
61#define WM831X_CS2_ON_RAMP_MASK 0x0300 /* CS2_ON_RAMP - [9:8] */
62#define WM831X_CS2_ON_RAMP_SHIFT 8 /* CS2_ON_RAMP - [9:8] */
63#define WM831X_CS2_ON_RAMP_WIDTH 2 /* CS2_ON_RAMP - [9:8] */
64#define WM831X_CS2_ISEL_MASK 0x003F /* CS2_ISEL - [5:0] */
65#define WM831X_CS2_ISEL_SHIFT 0 /* CS2_ISEL - [5:0] */
66#define WM831X_CS2_ISEL_WIDTH 6 /* CS2_ISEL - [5:0] */
67
68/*
69 * R16464 (0x4050) - DCDC Enable
70 */
71#define WM831X_EPE2_ENA 0x0080 /* EPE2_ENA */
72#define WM831X_EPE2_ENA_MASK 0x0080 /* EPE2_ENA */
73#define WM831X_EPE2_ENA_SHIFT 7 /* EPE2_ENA */
74#define WM831X_EPE2_ENA_WIDTH 1 /* EPE2_ENA */
75#define WM831X_EPE1_ENA 0x0040 /* EPE1_ENA */
76#define WM831X_EPE1_ENA_MASK 0x0040 /* EPE1_ENA */
77#define WM831X_EPE1_ENA_SHIFT 6 /* EPE1_ENA */
78#define WM831X_EPE1_ENA_WIDTH 1 /* EPE1_ENA */
79#define WM831X_DC4_ENA 0x0008 /* DC4_ENA */
80#define WM831X_DC4_ENA_MASK 0x0008 /* DC4_ENA */
81#define WM831X_DC4_ENA_SHIFT 3 /* DC4_ENA */
82#define WM831X_DC4_ENA_WIDTH 1 /* DC4_ENA */
83#define WM831X_DC3_ENA 0x0004 /* DC3_ENA */
84#define WM831X_DC3_ENA_MASK 0x0004 /* DC3_ENA */
85#define WM831X_DC3_ENA_SHIFT 2 /* DC3_ENA */
86#define WM831X_DC3_ENA_WIDTH 1 /* DC3_ENA */
87#define WM831X_DC2_ENA 0x0002 /* DC2_ENA */
88#define WM831X_DC2_ENA_MASK 0x0002 /* DC2_ENA */
89#define WM831X_DC2_ENA_SHIFT 1 /* DC2_ENA */
90#define WM831X_DC2_ENA_WIDTH 1 /* DC2_ENA */
91#define WM831X_DC1_ENA 0x0001 /* DC1_ENA */
92#define WM831X_DC1_ENA_MASK 0x0001 /* DC1_ENA */
93#define WM831X_DC1_ENA_SHIFT 0 /* DC1_ENA */
94#define WM831X_DC1_ENA_WIDTH 1 /* DC1_ENA */
95
96/*
97 * R16465 (0x4051) - LDO Enable
98 */
99#define WM831X_LDO11_ENA 0x0400 /* LDO11_ENA */
100#define WM831X_LDO11_ENA_MASK 0x0400 /* LDO11_ENA */
101#define WM831X_LDO11_ENA_SHIFT 10 /* LDO11_ENA */
102#define WM831X_LDO11_ENA_WIDTH 1 /* LDO11_ENA */
103#define WM831X_LDO10_ENA 0x0200 /* LDO10_ENA */
104#define WM831X_LDO10_ENA_MASK 0x0200 /* LDO10_ENA */
105#define WM831X_LDO10_ENA_SHIFT 9 /* LDO10_ENA */
106#define WM831X_LDO10_ENA_WIDTH 1 /* LDO10_ENA */
107#define WM831X_LDO9_ENA 0x0100 /* LDO9_ENA */
108#define WM831X_LDO9_ENA_MASK 0x0100 /* LDO9_ENA */
109#define WM831X_LDO9_ENA_SHIFT 8 /* LDO9_ENA */
110#define WM831X_LDO9_ENA_WIDTH 1 /* LDO9_ENA */
111#define WM831X_LDO8_ENA 0x0080 /* LDO8_ENA */
112#define WM831X_LDO8_ENA_MASK 0x0080 /* LDO8_ENA */
113#define WM831X_LDO8_ENA_SHIFT 7 /* LDO8_ENA */
114#define WM831X_LDO8_ENA_WIDTH 1 /* LDO8_ENA */
115#define WM831X_LDO7_ENA 0x0040 /* LDO7_ENA */
116#define WM831X_LDO7_ENA_MASK 0x0040 /* LDO7_ENA */
117#define WM831X_LDO7_ENA_SHIFT 6 /* LDO7_ENA */
118#define WM831X_LDO7_ENA_WIDTH 1 /* LDO7_ENA */
119#define WM831X_LDO6_ENA 0x0020 /* LDO6_ENA */
120#define WM831X_LDO6_ENA_MASK 0x0020 /* LDO6_ENA */
121#define WM831X_LDO6_ENA_SHIFT 5 /* LDO6_ENA */
122#define WM831X_LDO6_ENA_WIDTH 1 /* LDO6_ENA */
123#define WM831X_LDO5_ENA 0x0010 /* LDO5_ENA */
124#define WM831X_LDO5_ENA_MASK 0x0010 /* LDO5_ENA */
125#define WM831X_LDO5_ENA_SHIFT 4 /* LDO5_ENA */
126#define WM831X_LDO5_ENA_WIDTH 1 /* LDO5_ENA */
127#define WM831X_LDO4_ENA 0x0008 /* LDO4_ENA */
128#define WM831X_LDO4_ENA_MASK 0x0008 /* LDO4_ENA */
129#define WM831X_LDO4_ENA_SHIFT 3 /* LDO4_ENA */
130#define WM831X_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
131#define WM831X_LDO3_ENA 0x0004 /* LDO3_ENA */
132#define WM831X_LDO3_ENA_MASK 0x0004 /* LDO3_ENA */
133#define WM831X_LDO3_ENA_SHIFT 2 /* LDO3_ENA */
134#define WM831X_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
135#define WM831X_LDO2_ENA 0x0002 /* LDO2_ENA */
136#define WM831X_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
137#define WM831X_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
138#define WM831X_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
139#define WM831X_LDO1_ENA 0x0001 /* LDO1_ENA */
140#define WM831X_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
141#define WM831X_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
142#define WM831X_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
143
144/*
145 * R16466 (0x4052) - DCDC Status
146 */
147#define WM831X_EPE2_STS 0x0080 /* EPE2_STS */
148#define WM831X_EPE2_STS_MASK 0x0080 /* EPE2_STS */
149#define WM831X_EPE2_STS_SHIFT 7 /* EPE2_STS */
150#define WM831X_EPE2_STS_WIDTH 1 /* EPE2_STS */
151#define WM831X_EPE1_STS 0x0040 /* EPE1_STS */
152#define WM831X_EPE1_STS_MASK 0x0040 /* EPE1_STS */
153#define WM831X_EPE1_STS_SHIFT 6 /* EPE1_STS */
154#define WM831X_EPE1_STS_WIDTH 1 /* EPE1_STS */
155#define WM831X_DC4_STS 0x0008 /* DC4_STS */
156#define WM831X_DC4_STS_MASK 0x0008 /* DC4_STS */
157#define WM831X_DC4_STS_SHIFT 3 /* DC4_STS */
158#define WM831X_DC4_STS_WIDTH 1 /* DC4_STS */
159#define WM831X_DC3_STS 0x0004 /* DC3_STS */
160#define WM831X_DC3_STS_MASK 0x0004 /* DC3_STS */
161#define WM831X_DC3_STS_SHIFT 2 /* DC3_STS */
162#define WM831X_DC3_STS_WIDTH 1 /* DC3_STS */
163#define WM831X_DC2_STS 0x0002 /* DC2_STS */
164#define WM831X_DC2_STS_MASK 0x0002 /* DC2_STS */
165#define WM831X_DC2_STS_SHIFT 1 /* DC2_STS */
166#define WM831X_DC2_STS_WIDTH 1 /* DC2_STS */
167#define WM831X_DC1_STS 0x0001 /* DC1_STS */
168#define WM831X_DC1_STS_MASK 0x0001 /* DC1_STS */
169#define WM831X_DC1_STS_SHIFT 0 /* DC1_STS */
170#define WM831X_DC1_STS_WIDTH 1 /* DC1_STS */
171
172/*
173 * R16467 (0x4053) - LDO Status
174 */
175#define WM831X_LDO11_STS 0x0400 /* LDO11_STS */
176#define WM831X_LDO11_STS_MASK 0x0400 /* LDO11_STS */
177#define WM831X_LDO11_STS_SHIFT 10 /* LDO11_STS */
178#define WM831X_LDO11_STS_WIDTH 1 /* LDO11_STS */
179#define WM831X_LDO10_STS 0x0200 /* LDO10_STS */
180#define WM831X_LDO10_STS_MASK 0x0200 /* LDO10_STS */
181#define WM831X_LDO10_STS_SHIFT 9 /* LDO10_STS */
182#define WM831X_LDO10_STS_WIDTH 1 /* LDO10_STS */
183#define WM831X_LDO9_STS 0x0100 /* LDO9_STS */
184#define WM831X_LDO9_STS_MASK 0x0100 /* LDO9_STS */
185#define WM831X_LDO9_STS_SHIFT 8 /* LDO9_STS */
186#define WM831X_LDO9_STS_WIDTH 1 /* LDO9_STS */
187#define WM831X_LDO8_STS 0x0080 /* LDO8_STS */
188#define WM831X_LDO8_STS_MASK 0x0080 /* LDO8_STS */
189#define WM831X_LDO8_STS_SHIFT 7 /* LDO8_STS */
190#define WM831X_LDO8_STS_WIDTH 1 /* LDO8_STS */
191#define WM831X_LDO7_STS 0x0040 /* LDO7_STS */
192#define WM831X_LDO7_STS_MASK 0x0040 /* LDO7_STS */
193#define WM831X_LDO7_STS_SHIFT 6 /* LDO7_STS */
194#define WM831X_LDO7_STS_WIDTH 1 /* LDO7_STS */
195#define WM831X_LDO6_STS 0x0020 /* LDO6_STS */
196#define WM831X_LDO6_STS_MASK 0x0020 /* LDO6_STS */
197#define WM831X_LDO6_STS_SHIFT 5 /* LDO6_STS */
198#define WM831X_LDO6_STS_WIDTH 1 /* LDO6_STS */
199#define WM831X_LDO5_STS 0x0010 /* LDO5_STS */
200#define WM831X_LDO5_STS_MASK 0x0010 /* LDO5_STS */
201#define WM831X_LDO5_STS_SHIFT 4 /* LDO5_STS */
202#define WM831X_LDO5_STS_WIDTH 1 /* LDO5_STS */
203#define WM831X_LDO4_STS 0x0008 /* LDO4_STS */
204#define WM831X_LDO4_STS_MASK 0x0008 /* LDO4_STS */
205#define WM831X_LDO4_STS_SHIFT 3 /* LDO4_STS */
206#define WM831X_LDO4_STS_WIDTH 1 /* LDO4_STS */
207#define WM831X_LDO3_STS 0x0004 /* LDO3_STS */
208#define WM831X_LDO3_STS_MASK 0x0004 /* LDO3_STS */
209#define WM831X_LDO3_STS_SHIFT 2 /* LDO3_STS */
210#define WM831X_LDO3_STS_WIDTH 1 /* LDO3_STS */
211#define WM831X_LDO2_STS 0x0002 /* LDO2_STS */
212#define WM831X_LDO2_STS_MASK 0x0002 /* LDO2_STS */
213#define WM831X_LDO2_STS_SHIFT 1 /* LDO2_STS */
214#define WM831X_LDO2_STS_WIDTH 1 /* LDO2_STS */
215#define WM831X_LDO1_STS 0x0001 /* LDO1_STS */
216#define WM831X_LDO1_STS_MASK 0x0001 /* LDO1_STS */
217#define WM831X_LDO1_STS_SHIFT 0 /* LDO1_STS */
218#define WM831X_LDO1_STS_WIDTH 1 /* LDO1_STS */
219
220/*
221 * R16468 (0x4054) - DCDC UV Status
222 */
223#define WM831X_DC2_OV_STS 0x2000 /* DC2_OV_STS */
224#define WM831X_DC2_OV_STS_MASK 0x2000 /* DC2_OV_STS */
225#define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */
226#define WM831X_DC2_OV_STS_WIDTH 1 /* DC2_OV_STS */
227#define WM831X_DC1_OV_STS 0x1000 /* DC1_OV_STS */
228#define WM831X_DC1_OV_STS_MASK 0x1000 /* DC1_OV_STS */
229#define WM831X_DC1_OV_STS_SHIFT 12 /* DC1_OV_STS */
230#define WM831X_DC1_OV_STS_WIDTH 1 /* DC1_OV_STS */
231#define WM831X_DC2_HC_STS 0x0200 /* DC2_HC_STS */
232#define WM831X_DC2_HC_STS_MASK 0x0200 /* DC2_HC_STS */
233#define WM831X_DC2_HC_STS_SHIFT 9 /* DC2_HC_STS */
234#define WM831X_DC2_HC_STS_WIDTH 1 /* DC2_HC_STS */
235#define WM831X_DC1_HC_STS 0x0100 /* DC1_HC_STS */
236#define WM831X_DC1_HC_STS_MASK 0x0100 /* DC1_HC_STS */
237#define WM831X_DC1_HC_STS_SHIFT 8 /* DC1_HC_STS */
238#define WM831X_DC1_HC_STS_WIDTH 1 /* DC1_HC_STS */
239#define WM831X_DC4_UV_STS 0x0008 /* DC4_UV_STS */
240#define WM831X_DC4_UV_STS_MASK 0x0008 /* DC4_UV_STS */
241#define WM831X_DC4_UV_STS_SHIFT 3 /* DC4_UV_STS */
242#define WM831X_DC4_UV_STS_WIDTH 1 /* DC4_UV_STS */
243#define WM831X_DC3_UV_STS 0x0004 /* DC3_UV_STS */
244#define WM831X_DC3_UV_STS_MASK 0x0004 /* DC3_UV_STS */
245#define WM831X_DC3_UV_STS_SHIFT 2 /* DC3_UV_STS */
246#define WM831X_DC3_UV_STS_WIDTH 1 /* DC3_UV_STS */
247#define WM831X_DC2_UV_STS 0x0002 /* DC2_UV_STS */
248#define WM831X_DC2_UV_STS_MASK 0x0002 /* DC2_UV_STS */
249#define WM831X_DC2_UV_STS_SHIFT 1 /* DC2_UV_STS */
250#define WM831X_DC2_UV_STS_WIDTH 1 /* DC2_UV_STS */
251#define WM831X_DC1_UV_STS 0x0001 /* DC1_UV_STS */
252#define WM831X_DC1_UV_STS_MASK 0x0001 /* DC1_UV_STS */
253#define WM831X_DC1_UV_STS_SHIFT 0 /* DC1_UV_STS */
254#define WM831X_DC1_UV_STS_WIDTH 1 /* DC1_UV_STS */
255
256/*
257 * R16469 (0x4055) - LDO UV Status
258 */
259#define WM831X_INTLDO_UV_STS 0x8000 /* INTLDO_UV_STS */
260#define WM831X_INTLDO_UV_STS_MASK 0x8000 /* INTLDO_UV_STS */
261#define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */
262#define WM831X_INTLDO_UV_STS_WIDTH 1 /* INTLDO_UV_STS */
263#define WM831X_LDO10_UV_STS 0x0200 /* LDO10_UV_STS */
264#define WM831X_LDO10_UV_STS_MASK 0x0200 /* LDO10_UV_STS */
265#define WM831X_LDO10_UV_STS_SHIFT 9 /* LDO10_UV_STS */
266#define WM831X_LDO10_UV_STS_WIDTH 1 /* LDO10_UV_STS */
267#define WM831X_LDO9_UV_STS 0x0100 /* LDO9_UV_STS */
268#define WM831X_LDO9_UV_STS_MASK 0x0100 /* LDO9_UV_STS */
269#define WM831X_LDO9_UV_STS_SHIFT 8 /* LDO9_UV_STS */
270#define WM831X_LDO9_UV_STS_WIDTH 1 /* LDO9_UV_STS */
271#define WM831X_LDO8_UV_STS 0x0080 /* LDO8_UV_STS */
272#define WM831X_LDO8_UV_STS_MASK 0x0080 /* LDO8_UV_STS */
273#define WM831X_LDO8_UV_STS_SHIFT 7 /* LDO8_UV_STS */
274#define WM831X_LDO8_UV_STS_WIDTH 1 /* LDO8_UV_STS */
275#define WM831X_LDO7_UV_STS 0x0040 /* LDO7_UV_STS */
276#define WM831X_LDO7_UV_STS_MASK 0x0040 /* LDO7_UV_STS */
277#define WM831X_LDO7_UV_STS_SHIFT 6 /* LDO7_UV_STS */
278#define WM831X_LDO7_UV_STS_WIDTH 1 /* LDO7_UV_STS */
279#define WM831X_LDO6_UV_STS 0x0020 /* LDO6_UV_STS */
280#define WM831X_LDO6_UV_STS_MASK 0x0020 /* LDO6_UV_STS */
281#define WM831X_LDO6_UV_STS_SHIFT 5 /* LDO6_UV_STS */
282#define WM831X_LDO6_UV_STS_WIDTH 1 /* LDO6_UV_STS */
283#define WM831X_LDO5_UV_STS 0x0010 /* LDO5_UV_STS */
284#define WM831X_LDO5_UV_STS_MASK 0x0010 /* LDO5_UV_STS */
285#define WM831X_LDO5_UV_STS_SHIFT 4 /* LDO5_UV_STS */
286#define WM831X_LDO5_UV_STS_WIDTH 1 /* LDO5_UV_STS */
287#define WM831X_LDO4_UV_STS 0x0008 /* LDO4_UV_STS */
288#define WM831X_LDO4_UV_STS_MASK 0x0008 /* LDO4_UV_STS */
289#define WM831X_LDO4_UV_STS_SHIFT 3 /* LDO4_UV_STS */
290#define WM831X_LDO4_UV_STS_WIDTH 1 /* LDO4_UV_STS */
291#define WM831X_LDO3_UV_STS 0x0004 /* LDO3_UV_STS */
292#define WM831X_LDO3_UV_STS_MASK 0x0004 /* LDO3_UV_STS */
293#define WM831X_LDO3_UV_STS_SHIFT 2 /* LDO3_UV_STS */
294#define WM831X_LDO3_UV_STS_WIDTH 1 /* LDO3_UV_STS */
295#define WM831X_LDO2_UV_STS 0x0002 /* LDO2_UV_STS */
296#define WM831X_LDO2_UV_STS_MASK 0x0002 /* LDO2_UV_STS */
297#define WM831X_LDO2_UV_STS_SHIFT 1 /* LDO2_UV_STS */
298#define WM831X_LDO2_UV_STS_WIDTH 1 /* LDO2_UV_STS */
299#define WM831X_LDO1_UV_STS 0x0001 /* LDO1_UV_STS */
300#define WM831X_LDO1_UV_STS_MASK 0x0001 /* LDO1_UV_STS */
301#define WM831X_LDO1_UV_STS_SHIFT 0 /* LDO1_UV_STS */
302#define WM831X_LDO1_UV_STS_WIDTH 1 /* LDO1_UV_STS */
303
304/*
305 * R16470 (0x4056) - DC1 Control 1
306 */
307#define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */
308#define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */
309#define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */
310#define WM831X_DC1_PHASE 0x1000 /* DC1_PHASE */
311#define WM831X_DC1_PHASE_MASK 0x1000 /* DC1_PHASE */
312#define WM831X_DC1_PHASE_SHIFT 12 /* DC1_PHASE */
313#define WM831X_DC1_PHASE_WIDTH 1 /* DC1_PHASE */
314#define WM831X_DC1_FREQ_MASK 0x0300 /* DC1_FREQ - [9:8] */
315#define WM831X_DC1_FREQ_SHIFT 8 /* DC1_FREQ - [9:8] */
316#define WM831X_DC1_FREQ_WIDTH 2 /* DC1_FREQ - [9:8] */
317#define WM831X_DC1_FLT 0x0080 /* DC1_FLT */
318#define WM831X_DC1_FLT_MASK 0x0080 /* DC1_FLT */
319#define WM831X_DC1_FLT_SHIFT 7 /* DC1_FLT */
320#define WM831X_DC1_FLT_WIDTH 1 /* DC1_FLT */
321#define WM831X_DC1_SOFT_START_MASK 0x0030 /* DC1_SOFT_START - [5:4] */
322#define WM831X_DC1_SOFT_START_SHIFT 4 /* DC1_SOFT_START - [5:4] */
323#define WM831X_DC1_SOFT_START_WIDTH 2 /* DC1_SOFT_START - [5:4] */
324#define WM831X_DC1_CAP_MASK 0x0003 /* DC1_CAP - [1:0] */
325#define WM831X_DC1_CAP_SHIFT 0 /* DC1_CAP - [1:0] */
326#define WM831X_DC1_CAP_WIDTH 2 /* DC1_CAP - [1:0] */
327
328/*
329 * R16471 (0x4057) - DC1 Control 2
330 */
331#define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */
332#define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */
333#define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */
334#define WM831X_DC1_HWC_SRC_MASK 0x1800 /* DC1_HWC_SRC - [12:11] */
335#define WM831X_DC1_HWC_SRC_SHIFT 11 /* DC1_HWC_SRC - [12:11] */
336#define WM831X_DC1_HWC_SRC_WIDTH 2 /* DC1_HWC_SRC - [12:11] */
337#define WM831X_DC1_HWC_VSEL 0x0400 /* DC1_HWC_VSEL */
338#define WM831X_DC1_HWC_VSEL_MASK 0x0400 /* DC1_HWC_VSEL */
339#define WM831X_DC1_HWC_VSEL_SHIFT 10 /* DC1_HWC_VSEL */
340#define WM831X_DC1_HWC_VSEL_WIDTH 1 /* DC1_HWC_VSEL */
341#define WM831X_DC1_HWC_MODE_MASK 0x0300 /* DC1_HWC_MODE - [9:8] */
342#define WM831X_DC1_HWC_MODE_SHIFT 8 /* DC1_HWC_MODE - [9:8] */
343#define WM831X_DC1_HWC_MODE_WIDTH 2 /* DC1_HWC_MODE - [9:8] */
344#define WM831X_DC1_HC_THR_MASK 0x0070 /* DC1_HC_THR - [6:4] */
345#define WM831X_DC1_HC_THR_SHIFT 4 /* DC1_HC_THR - [6:4] */
346#define WM831X_DC1_HC_THR_WIDTH 3 /* DC1_HC_THR - [6:4] */
347#define WM831X_DC1_HC_IND_ENA 0x0001 /* DC1_HC_IND_ENA */
348#define WM831X_DC1_HC_IND_ENA_MASK 0x0001 /* DC1_HC_IND_ENA */
349#define WM831X_DC1_HC_IND_ENA_SHIFT 0 /* DC1_HC_IND_ENA */
350#define WM831X_DC1_HC_IND_ENA_WIDTH 1 /* DC1_HC_IND_ENA */
351
352/*
353 * R16472 (0x4058) - DC1 ON Config
354 */
355#define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
356#define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */
357#define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */
358#define WM831X_DC1_ON_MODE_MASK 0x0300 /* DC1_ON_MODE - [9:8] */
359#define WM831X_DC1_ON_MODE_SHIFT 8 /* DC1_ON_MODE - [9:8] */
360#define WM831X_DC1_ON_MODE_WIDTH 2 /* DC1_ON_MODE - [9:8] */
361#define WM831X_DC1_ON_VSEL_MASK 0x007F /* DC1_ON_VSEL - [6:0] */
362#define WM831X_DC1_ON_VSEL_SHIFT 0 /* DC1_ON_VSEL - [6:0] */
363#define WM831X_DC1_ON_VSEL_WIDTH 7 /* DC1_ON_VSEL - [6:0] */
364
365/*
366 * R16473 (0x4059) - DC1 SLEEP Control
367 */
368#define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */
369#define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */
370#define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */
371#define WM831X_DC1_SLP_MODE_MASK 0x0300 /* DC1_SLP_MODE - [9:8] */
372#define WM831X_DC1_SLP_MODE_SHIFT 8 /* DC1_SLP_MODE - [9:8] */
373#define WM831X_DC1_SLP_MODE_WIDTH 2 /* DC1_SLP_MODE - [9:8] */
374#define WM831X_DC1_SLP_VSEL_MASK 0x007F /* DC1_SLP_VSEL - [6:0] */
375#define WM831X_DC1_SLP_VSEL_SHIFT 0 /* DC1_SLP_VSEL - [6:0] */
376#define WM831X_DC1_SLP_VSEL_WIDTH 7 /* DC1_SLP_VSEL - [6:0] */
377
378/*
379 * R16474 (0x405A) - DC1 DVS Control
380 */
381#define WM831X_DC1_DVS_SRC_MASK 0x1800 /* DC1_DVS_SRC - [12:11] */
382#define WM831X_DC1_DVS_SRC_SHIFT 11 /* DC1_DVS_SRC - [12:11] */
383#define WM831X_DC1_DVS_SRC_WIDTH 2 /* DC1_DVS_SRC - [12:11] */
384#define WM831X_DC1_DVS_VSEL_MASK 0x007F /* DC1_DVS_VSEL - [6:0] */
385#define WM831X_DC1_DVS_VSEL_SHIFT 0 /* DC1_DVS_VSEL - [6:0] */
386#define WM831X_DC1_DVS_VSEL_WIDTH 7 /* DC1_DVS_VSEL - [6:0] */
387
388/*
389 * R16475 (0x405B) - DC2 Control 1
390 */
391#define WM831X_DC2_RATE_MASK 0xC000 /* DC2_RATE - [15:14] */
392#define WM831X_DC2_RATE_SHIFT 14 /* DC2_RATE - [15:14] */
393#define WM831X_DC2_RATE_WIDTH 2 /* DC2_RATE - [15:14] */
394#define WM831X_DC2_PHASE 0x1000 /* DC2_PHASE */
395#define WM831X_DC2_PHASE_MASK 0x1000 /* DC2_PHASE */
396#define WM831X_DC2_PHASE_SHIFT 12 /* DC2_PHASE */
397#define WM831X_DC2_PHASE_WIDTH 1 /* DC2_PHASE */
398#define WM831X_DC2_FREQ_MASK 0x0300 /* DC2_FREQ - [9:8] */
399#define WM831X_DC2_FREQ_SHIFT 8 /* DC2_FREQ - [9:8] */
400#define WM831X_DC2_FREQ_WIDTH 2 /* DC2_FREQ - [9:8] */
401#define WM831X_DC2_FLT 0x0080 /* DC2_FLT */
402#define WM831X_DC2_FLT_MASK 0x0080 /* DC2_FLT */
403#define WM831X_DC2_FLT_SHIFT 7 /* DC2_FLT */
404#define WM831X_DC2_FLT_WIDTH 1 /* DC2_FLT */
405#define WM831X_DC2_SOFT_START_MASK 0x0030 /* DC2_SOFT_START - [5:4] */
406#define WM831X_DC2_SOFT_START_SHIFT 4 /* DC2_SOFT_START - [5:4] */
407#define WM831X_DC2_SOFT_START_WIDTH 2 /* DC2_SOFT_START - [5:4] */
408#define WM831X_DC2_CAP_MASK 0x0003 /* DC2_CAP - [1:0] */
409#define WM831X_DC2_CAP_SHIFT 0 /* DC2_CAP - [1:0] */
410#define WM831X_DC2_CAP_WIDTH 2 /* DC2_CAP - [1:0] */
411
412/*
413 * R16476 (0x405C) - DC2 Control 2
414 */
415#define WM831X_DC2_ERR_ACT_MASK 0xC000 /* DC2_ERR_ACT - [15:14] */
416#define WM831X_DC2_ERR_ACT_SHIFT 14 /* DC2_ERR_ACT - [15:14] */
417#define WM831X_DC2_ERR_ACT_WIDTH 2 /* DC2_ERR_ACT - [15:14] */
418#define WM831X_DC2_HWC_SRC_MASK 0x1800 /* DC2_HWC_SRC - [12:11] */
419#define WM831X_DC2_HWC_SRC_SHIFT 11 /* DC2_HWC_SRC - [12:11] */
420#define WM831X_DC2_HWC_SRC_WIDTH 2 /* DC2_HWC_SRC - [12:11] */
421#define WM831X_DC2_HWC_VSEL 0x0400 /* DC2_HWC_VSEL */
422#define WM831X_DC2_HWC_VSEL_MASK 0x0400 /* DC2_HWC_VSEL */
423#define WM831X_DC2_HWC_VSEL_SHIFT 10 /* DC2_HWC_VSEL */
424#define WM831X_DC2_HWC_VSEL_WIDTH 1 /* DC2_HWC_VSEL */
425#define WM831X_DC2_HWC_MODE_MASK 0x0300 /* DC2_HWC_MODE - [9:8] */
426#define WM831X_DC2_HWC_MODE_SHIFT 8 /* DC2_HWC_MODE - [9:8] */
427#define WM831X_DC2_HWC_MODE_WIDTH 2 /* DC2_HWC_MODE - [9:8] */
428#define WM831X_DC2_HC_THR_MASK 0x0070 /* DC2_HC_THR - [6:4] */
429#define WM831X_DC2_HC_THR_SHIFT 4 /* DC2_HC_THR - [6:4] */
430#define WM831X_DC2_HC_THR_WIDTH 3 /* DC2_HC_THR - [6:4] */
431#define WM831X_DC2_HC_IND_ENA 0x0001 /* DC2_HC_IND_ENA */
432#define WM831X_DC2_HC_IND_ENA_MASK 0x0001 /* DC2_HC_IND_ENA */
433#define WM831X_DC2_HC_IND_ENA_SHIFT 0 /* DC2_HC_IND_ENA */
434#define WM831X_DC2_HC_IND_ENA_WIDTH 1 /* DC2_HC_IND_ENA */
435
436/*
437 * R16477 (0x405D) - DC2 ON Config
438 */
439#define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */
440#define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */
441#define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */
442#define WM831X_DC2_ON_MODE_MASK 0x0300 /* DC2_ON_MODE - [9:8] */
443#define WM831X_DC2_ON_MODE_SHIFT 8 /* DC2_ON_MODE - [9:8] */
444#define WM831X_DC2_ON_MODE_WIDTH 2 /* DC2_ON_MODE - [9:8] */
445#define WM831X_DC2_ON_VSEL_MASK 0x007F /* DC2_ON_VSEL - [6:0] */
446#define WM831X_DC2_ON_VSEL_SHIFT 0 /* DC2_ON_VSEL - [6:0] */
447#define WM831X_DC2_ON_VSEL_WIDTH 7 /* DC2_ON_VSEL - [6:0] */
448
449/*
450 * R16478 (0x405E) - DC2 SLEEP Control
451 */
452#define WM831X_DC2_SLP_SLOT_MASK 0xE000 /* DC2_SLP_SLOT - [15:13] */
453#define WM831X_DC2_SLP_SLOT_SHIFT 13 /* DC2_SLP_SLOT - [15:13] */
454#define WM831X_DC2_SLP_SLOT_WIDTH 3 /* DC2_SLP_SLOT - [15:13] */
455#define WM831X_DC2_SLP_MODE_MASK 0x0300 /* DC2_SLP_MODE - [9:8] */
456#define WM831X_DC2_SLP_MODE_SHIFT 8 /* DC2_SLP_MODE - [9:8] */
457#define WM831X_DC2_SLP_MODE_WIDTH 2 /* DC2_SLP_MODE - [9:8] */
458#define WM831X_DC2_SLP_VSEL_MASK 0x007F /* DC2_SLP_VSEL - [6:0] */
459#define WM831X_DC2_SLP_VSEL_SHIFT 0 /* DC2_SLP_VSEL - [6:0] */
460#define WM831X_DC2_SLP_VSEL_WIDTH 7 /* DC2_SLP_VSEL - [6:0] */
461
462/*
463 * R16479 (0x405F) - DC2 DVS Control
464 */
465#define WM831X_DC2_DVS_SRC_MASK 0x1800 /* DC2_DVS_SRC - [12:11] */
466#define WM831X_DC2_DVS_SRC_SHIFT 11 /* DC2_DVS_SRC - [12:11] */
467#define WM831X_DC2_DVS_SRC_WIDTH 2 /* DC2_DVS_SRC - [12:11] */
468#define WM831X_DC2_DVS_VSEL_MASK 0x007F /* DC2_DVS_VSEL - [6:0] */
469#define WM831X_DC2_DVS_VSEL_SHIFT 0 /* DC2_DVS_VSEL - [6:0] */
470#define WM831X_DC2_DVS_VSEL_WIDTH 7 /* DC2_DVS_VSEL - [6:0] */
471
472/*
473 * R16480 (0x4060) - DC3 Control 1
474 */
475#define WM831X_DC3_PHASE 0x1000 /* DC3_PHASE */
476#define WM831X_DC3_PHASE_MASK 0x1000 /* DC3_PHASE */
477#define WM831X_DC3_PHASE_SHIFT 12 /* DC3_PHASE */
478#define WM831X_DC3_PHASE_WIDTH 1 /* DC3_PHASE */
479#define WM831X_DC3_FLT 0x0080 /* DC3_FLT */
480#define WM831X_DC3_FLT_MASK 0x0080 /* DC3_FLT */
481#define WM831X_DC3_FLT_SHIFT 7 /* DC3_FLT */
482#define WM831X_DC3_FLT_WIDTH 1 /* DC3_FLT */
483#define WM831X_DC3_SOFT_START_MASK 0x0030 /* DC3_SOFT_START - [5:4] */
484#define WM831X_DC3_SOFT_START_SHIFT 4 /* DC3_SOFT_START - [5:4] */
485#define WM831X_DC3_SOFT_START_WIDTH 2 /* DC3_SOFT_START - [5:4] */
486#define WM831X_DC3_STNBY_LIM_MASK 0x000C /* DC3_STNBY_LIM - [3:2] */
487#define WM831X_DC3_STNBY_LIM_SHIFT 2 /* DC3_STNBY_LIM - [3:2] */
488#define WM831X_DC3_STNBY_LIM_WIDTH 2 /* DC3_STNBY_LIM - [3:2] */
489#define WM831X_DC3_CAP_MASK 0x0003 /* DC3_CAP - [1:0] */
490#define WM831X_DC3_CAP_SHIFT 0 /* DC3_CAP - [1:0] */
491#define WM831X_DC3_CAP_WIDTH 2 /* DC3_CAP - [1:0] */
492
493/*
494 * R16481 (0x4061) - DC3 Control 2
495 */
496#define WM831X_DC3_ERR_ACT_MASK 0xC000 /* DC3_ERR_ACT - [15:14] */
497#define WM831X_DC3_ERR_ACT_SHIFT 14 /* DC3_ERR_ACT - [15:14] */
498#define WM831X_DC3_ERR_ACT_WIDTH 2 /* DC3_ERR_ACT - [15:14] */
499#define WM831X_DC3_HWC_SRC_MASK 0x1800 /* DC3_HWC_SRC - [12:11] */
500#define WM831X_DC3_HWC_SRC_SHIFT 11 /* DC3_HWC_SRC - [12:11] */
501#define WM831X_DC3_HWC_SRC_WIDTH 2 /* DC3_HWC_SRC - [12:11] */
502#define WM831X_DC3_HWC_VSEL 0x0400 /* DC3_HWC_VSEL */
503#define WM831X_DC3_HWC_VSEL_MASK 0x0400 /* DC3_HWC_VSEL */
504#define WM831X_DC3_HWC_VSEL_SHIFT 10 /* DC3_HWC_VSEL */
505#define WM831X_DC3_HWC_VSEL_WIDTH 1 /* DC3_HWC_VSEL */
506#define WM831X_DC3_HWC_MODE_MASK 0x0300 /* DC3_HWC_MODE - [9:8] */
507#define WM831X_DC3_HWC_MODE_SHIFT 8 /* DC3_HWC_MODE - [9:8] */
508#define WM831X_DC3_HWC_MODE_WIDTH 2 /* DC3_HWC_MODE - [9:8] */
509#define WM831X_DC3_OVP 0x0080 /* DC3_OVP */
510#define WM831X_DC3_OVP_MASK 0x0080 /* DC3_OVP */
511#define WM831X_DC3_OVP_SHIFT 7 /* DC3_OVP */
512#define WM831X_DC3_OVP_WIDTH 1 /* DC3_OVP */
513
514/*
515 * R16482 (0x4062) - DC3 ON Config
516 */
517#define WM831X_DC3_ON_SLOT_MASK 0xE000 /* DC3_ON_SLOT - [15:13] */
518#define WM831X_DC3_ON_SLOT_SHIFT 13 /* DC3_ON_SLOT - [15:13] */
519#define WM831X_DC3_ON_SLOT_WIDTH 3 /* DC3_ON_SLOT - [15:13] */
520#define WM831X_DC3_ON_MODE_MASK 0x0300 /* DC3_ON_MODE - [9:8] */
521#define WM831X_DC3_ON_MODE_SHIFT 8 /* DC3_ON_MODE - [9:8] */
522#define WM831X_DC3_ON_MODE_WIDTH 2 /* DC3_ON_MODE - [9:8] */
523#define WM831X_DC3_ON_VSEL_MASK 0x007F /* DC3_ON_VSEL - [6:0] */
524#define WM831X_DC3_ON_VSEL_SHIFT 0 /* DC3_ON_VSEL - [6:0] */
525#define WM831X_DC3_ON_VSEL_WIDTH 7 /* DC3_ON_VSEL - [6:0] */
526
527/*
528 * R16483 (0x4063) - DC3 SLEEP Control
529 */
530#define WM831X_DC3_SLP_SLOT_MASK 0xE000 /* DC3_SLP_SLOT - [15:13] */
531#define WM831X_DC3_SLP_SLOT_SHIFT 13 /* DC3_SLP_SLOT - [15:13] */
532#define WM831X_DC3_SLP_SLOT_WIDTH 3 /* DC3_SLP_SLOT - [15:13] */
533#define WM831X_DC3_SLP_MODE_MASK 0x0300 /* DC3_SLP_MODE - [9:8] */
534#define WM831X_DC3_SLP_MODE_SHIFT 8 /* DC3_SLP_MODE - [9:8] */
535#define WM831X_DC3_SLP_MODE_WIDTH 2 /* DC3_SLP_MODE - [9:8] */
536#define WM831X_DC3_SLP_VSEL_MASK 0x007F /* DC3_SLP_VSEL - [6:0] */
537#define WM831X_DC3_SLP_VSEL_SHIFT 0 /* DC3_SLP_VSEL - [6:0] */
538#define WM831X_DC3_SLP_VSEL_WIDTH 7 /* DC3_SLP_VSEL - [6:0] */
539
540/*
541 * R16484 (0x4064) - DC4 Control
542 */
543#define WM831X_DC4_ERR_ACT_MASK 0xC000 /* DC4_ERR_ACT - [15:14] */
544#define WM831X_DC4_ERR_ACT_SHIFT 14 /* DC4_ERR_ACT - [15:14] */
545#define WM831X_DC4_ERR_ACT_WIDTH 2 /* DC4_ERR_ACT - [15:14] */
546#define WM831X_DC4_HWC_SRC_MASK 0x1800 /* DC4_HWC_SRC - [12:11] */
547#define WM831X_DC4_HWC_SRC_SHIFT 11 /* DC4_HWC_SRC - [12:11] */
548#define WM831X_DC4_HWC_SRC_WIDTH 2 /* DC4_HWC_SRC - [12:11] */
549#define WM831X_DC4_HWC_MODE 0x0100 /* DC4_HWC_MODE */
550#define WM831X_DC4_HWC_MODE_MASK 0x0100 /* DC4_HWC_MODE */
551#define WM831X_DC4_HWC_MODE_SHIFT 8 /* DC4_HWC_MODE */
552#define WM831X_DC4_HWC_MODE_WIDTH 1 /* DC4_HWC_MODE */
553#define WM831X_DC4_RANGE_MASK 0x000C /* DC4_RANGE - [3:2] */
554#define WM831X_DC4_RANGE_SHIFT 2 /* DC4_RANGE - [3:2] */
555#define WM831X_DC4_RANGE_WIDTH 2 /* DC4_RANGE - [3:2] */
556#define WM831X_DC4_FBSRC 0x0001 /* DC4_FBSRC */
557#define WM831X_DC4_FBSRC_MASK 0x0001 /* DC4_FBSRC */
558#define WM831X_DC4_FBSRC_SHIFT 0 /* DC4_FBSRC */
559#define WM831X_DC4_FBSRC_WIDTH 1 /* DC4_FBSRC */
560
561/*
562 * R16485 (0x4065) - DC4 SLEEP Control
563 */
564#define WM831X_DC4_SLPENA 0x0100 /* DC4_SLPENA */
565#define WM831X_DC4_SLPENA_MASK 0x0100 /* DC4_SLPENA */
566#define WM831X_DC4_SLPENA_SHIFT 8 /* DC4_SLPENA */
567#define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */
568
569/*
570 * R16488 (0x4068) - LDO1 Control
571 */
572#define WM831X_LDO1_ERR_ACT_MASK 0xC000 /* LDO1_ERR_ACT - [15:14] */
573#define WM831X_LDO1_ERR_ACT_SHIFT 14 /* LDO1_ERR_ACT - [15:14] */
574#define WM831X_LDO1_ERR_ACT_WIDTH 2 /* LDO1_ERR_ACT - [15:14] */
575#define WM831X_LDO1_HWC_SRC_MASK 0x1800 /* LDO1_HWC_SRC - [12:11] */
576#define WM831X_LDO1_HWC_SRC_SHIFT 11 /* LDO1_HWC_SRC - [12:11] */
577#define WM831X_LDO1_HWC_SRC_WIDTH 2 /* LDO1_HWC_SRC - [12:11] */
578#define WM831X_LDO1_HWC_VSEL 0x0400 /* LDO1_HWC_VSEL */
579#define WM831X_LDO1_HWC_VSEL_MASK 0x0400 /* LDO1_HWC_VSEL */
580#define WM831X_LDO1_HWC_VSEL_SHIFT 10 /* LDO1_HWC_VSEL */
581#define WM831X_LDO1_HWC_VSEL_WIDTH 1 /* LDO1_HWC_VSEL */
582#define WM831X_LDO1_HWC_MODE_MASK 0x0300 /* LDO1_HWC_MODE - [9:8] */
583#define WM831X_LDO1_HWC_MODE_SHIFT 8 /* LDO1_HWC_MODE - [9:8] */
584#define WM831X_LDO1_HWC_MODE_WIDTH 2 /* LDO1_HWC_MODE - [9:8] */
585#define WM831X_LDO1_FLT 0x0080 /* LDO1_FLT */
586#define WM831X_LDO1_FLT_MASK 0x0080 /* LDO1_FLT */
587#define WM831X_LDO1_FLT_SHIFT 7 /* LDO1_FLT */
588#define WM831X_LDO1_FLT_WIDTH 1 /* LDO1_FLT */
589#define WM831X_LDO1_SWI 0x0040 /* LDO1_SWI */
590#define WM831X_LDO1_SWI_MASK 0x0040 /* LDO1_SWI */
591#define WM831X_LDO1_SWI_SHIFT 6 /* LDO1_SWI */
592#define WM831X_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
593#define WM831X_LDO1_LP_MODE 0x0001 /* LDO1_LP_MODE */
594#define WM831X_LDO1_LP_MODE_MASK 0x0001 /* LDO1_LP_MODE */
595#define WM831X_LDO1_LP_MODE_SHIFT 0 /* LDO1_LP_MODE */
596#define WM831X_LDO1_LP_MODE_WIDTH 1 /* LDO1_LP_MODE */
597
598/*
599 * R16489 (0x4069) - LDO1 ON Control
600 */
601#define WM831X_LDO1_ON_SLOT_MASK 0xE000 /* LDO1_ON_SLOT - [15:13] */
602#define WM831X_LDO1_ON_SLOT_SHIFT 13 /* LDO1_ON_SLOT - [15:13] */
603#define WM831X_LDO1_ON_SLOT_WIDTH 3 /* LDO1_ON_SLOT - [15:13] */
604#define WM831X_LDO1_ON_MODE 0x0100 /* LDO1_ON_MODE */
605#define WM831X_LDO1_ON_MODE_MASK 0x0100 /* LDO1_ON_MODE */
606#define WM831X_LDO1_ON_MODE_SHIFT 8 /* LDO1_ON_MODE */
607#define WM831X_LDO1_ON_MODE_WIDTH 1 /* LDO1_ON_MODE */
608#define WM831X_LDO1_ON_VSEL_MASK 0x001F /* LDO1_ON_VSEL - [4:0] */
609#define WM831X_LDO1_ON_VSEL_SHIFT 0 /* LDO1_ON_VSEL - [4:0] */
610#define WM831X_LDO1_ON_VSEL_WIDTH 5 /* LDO1_ON_VSEL - [4:0] */
611
612/*
613 * R16490 (0x406A) - LDO1 SLEEP Control
614 */
615#define WM831X_LDO1_SLP_SLOT_MASK 0xE000 /* LDO1_SLP_SLOT - [15:13] */
616#define WM831X_LDO1_SLP_SLOT_SHIFT 13 /* LDO1_SLP_SLOT - [15:13] */
617#define WM831X_LDO1_SLP_SLOT_WIDTH 3 /* LDO1_SLP_SLOT - [15:13] */
618#define WM831X_LDO1_SLP_MODE 0x0100 /* LDO1_SLP_MODE */
619#define WM831X_LDO1_SLP_MODE_MASK 0x0100 /* LDO1_SLP_MODE */
620#define WM831X_LDO1_SLP_MODE_SHIFT 8 /* LDO1_SLP_MODE */
621#define WM831X_LDO1_SLP_MODE_WIDTH 1 /* LDO1_SLP_MODE */
622#define WM831X_LDO1_SLP_VSEL_MASK 0x001F /* LDO1_SLP_VSEL - [4:0] */
623#define WM831X_LDO1_SLP_VSEL_SHIFT 0 /* LDO1_SLP_VSEL - [4:0] */
624#define WM831X_LDO1_SLP_VSEL_WIDTH 5 /* LDO1_SLP_VSEL - [4:0] */
625
626/*
627 * R16491 (0x406B) - LDO2 Control
628 */
629#define WM831X_LDO2_ERR_ACT_MASK 0xC000 /* LDO2_ERR_ACT - [15:14] */
630#define WM831X_LDO2_ERR_ACT_SHIFT 14 /* LDO2_ERR_ACT - [15:14] */
631#define WM831X_LDO2_ERR_ACT_WIDTH 2 /* LDO2_ERR_ACT - [15:14] */
632#define WM831X_LDO2_HWC_SRC_MASK 0x1800 /* LDO2_HWC_SRC - [12:11] */
633#define WM831X_LDO2_HWC_SRC_SHIFT 11 /* LDO2_HWC_SRC - [12:11] */
634#define WM831X_LDO2_HWC_SRC_WIDTH 2 /* LDO2_HWC_SRC - [12:11] */
635#define WM831X_LDO2_HWC_VSEL 0x0400 /* LDO2_HWC_VSEL */
636#define WM831X_LDO2_HWC_VSEL_MASK 0x0400 /* LDO2_HWC_VSEL */
637#define WM831X_LDO2_HWC_VSEL_SHIFT 10 /* LDO2_HWC_VSEL */
638#define WM831X_LDO2_HWC_VSEL_WIDTH 1 /* LDO2_HWC_VSEL */
639#define WM831X_LDO2_HWC_MODE_MASK 0x0300 /* LDO2_HWC_MODE - [9:8] */
640#define WM831X_LDO2_HWC_MODE_SHIFT 8 /* LDO2_HWC_MODE - [9:8] */
641#define WM831X_LDO2_HWC_MODE_WIDTH 2 /* LDO2_HWC_MODE - [9:8] */
642#define WM831X_LDO2_FLT 0x0080 /* LDO2_FLT */
643#define WM831X_LDO2_FLT_MASK 0x0080 /* LDO2_FLT */
644#define WM831X_LDO2_FLT_SHIFT 7 /* LDO2_FLT */
645#define WM831X_LDO2_FLT_WIDTH 1 /* LDO2_FLT */
646#define WM831X_LDO2_SWI 0x0040 /* LDO2_SWI */
647#define WM831X_LDO2_SWI_MASK 0x0040 /* LDO2_SWI */
648#define WM831X_LDO2_SWI_SHIFT 6 /* LDO2_SWI */
649#define WM831X_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
650#define WM831X_LDO2_LP_MODE 0x0001 /* LDO2_LP_MODE */
651#define WM831X_LDO2_LP_MODE_MASK 0x0001 /* LDO2_LP_MODE */
652#define WM831X_LDO2_LP_MODE_SHIFT 0 /* LDO2_LP_MODE */
653#define WM831X_LDO2_LP_MODE_WIDTH 1 /* LDO2_LP_MODE */
654
655/*
656 * R16492 (0x406C) - LDO2 ON Control
657 */
658#define WM831X_LDO2_ON_SLOT_MASK 0xE000 /* LDO2_ON_SLOT - [15:13] */
659#define WM831X_LDO2_ON_SLOT_SHIFT 13 /* LDO2_ON_SLOT - [15:13] */
660#define WM831X_LDO2_ON_SLOT_WIDTH 3 /* LDO2_ON_SLOT - [15:13] */
661#define WM831X_LDO2_ON_MODE 0x0100 /* LDO2_ON_MODE */
662#define WM831X_LDO2_ON_MODE_MASK 0x0100 /* LDO2_ON_MODE */
663#define WM831X_LDO2_ON_MODE_SHIFT 8 /* LDO2_ON_MODE */
664#define WM831X_LDO2_ON_MODE_WIDTH 1 /* LDO2_ON_MODE */
665#define WM831X_LDO2_ON_VSEL_MASK 0x001F /* LDO2_ON_VSEL - [4:0] */
666#define WM831X_LDO2_ON_VSEL_SHIFT 0 /* LDO2_ON_VSEL - [4:0] */
667#define WM831X_LDO2_ON_VSEL_WIDTH 5 /* LDO2_ON_VSEL - [4:0] */
668
669/*
670 * R16493 (0x406D) - LDO2 SLEEP Control
671 */
672#define WM831X_LDO2_SLP_SLOT_MASK 0xE000 /* LDO2_SLP_SLOT - [15:13] */
673#define WM831X_LDO2_SLP_SLOT_SHIFT 13 /* LDO2_SLP_SLOT - [15:13] */
674#define WM831X_LDO2_SLP_SLOT_WIDTH 3 /* LDO2_SLP_SLOT - [15:13] */
675#define WM831X_LDO2_SLP_MODE 0x0100 /* LDO2_SLP_MODE */
676#define WM831X_LDO2_SLP_MODE_MASK 0x0100 /* LDO2_SLP_MODE */
677#define WM831X_LDO2_SLP_MODE_SHIFT 8 /* LDO2_SLP_MODE */
678#define WM831X_LDO2_SLP_MODE_WIDTH 1 /* LDO2_SLP_MODE */
679#define WM831X_LDO2_SLP_VSEL_MASK 0x001F /* LDO2_SLP_VSEL - [4:0] */
680#define WM831X_LDO2_SLP_VSEL_SHIFT 0 /* LDO2_SLP_VSEL - [4:0] */
681#define WM831X_LDO2_SLP_VSEL_WIDTH 5 /* LDO2_SLP_VSEL - [4:0] */
682
683/*
684 * R16494 (0x406E) - LDO3 Control
685 */
686#define WM831X_LDO3_ERR_ACT_MASK 0xC000 /* LDO3_ERR_ACT - [15:14] */
687#define WM831X_LDO3_ERR_ACT_SHIFT 14 /* LDO3_ERR_ACT - [15:14] */
688#define WM831X_LDO3_ERR_ACT_WIDTH 2 /* LDO3_ERR_ACT - [15:14] */
689#define WM831X_LDO3_HWC_SRC_MASK 0x1800 /* LDO3_HWC_SRC - [12:11] */
690#define WM831X_LDO3_HWC_SRC_SHIFT 11 /* LDO3_HWC_SRC - [12:11] */
691#define WM831X_LDO3_HWC_SRC_WIDTH 2 /* LDO3_HWC_SRC - [12:11] */
692#define WM831X_LDO3_HWC_VSEL 0x0400 /* LDO3_HWC_VSEL */
693#define WM831X_LDO3_HWC_VSEL_MASK 0x0400 /* LDO3_HWC_VSEL */
694#define WM831X_LDO3_HWC_VSEL_SHIFT 10 /* LDO3_HWC_VSEL */
695#define WM831X_LDO3_HWC_VSEL_WIDTH 1 /* LDO3_HWC_VSEL */
696#define WM831X_LDO3_HWC_MODE_MASK 0x0300 /* LDO3_HWC_MODE - [9:8] */
697#define WM831X_LDO3_HWC_MODE_SHIFT 8 /* LDO3_HWC_MODE - [9:8] */
698#define WM831X_LDO3_HWC_MODE_WIDTH 2 /* LDO3_HWC_MODE - [9:8] */
699#define WM831X_LDO3_FLT 0x0080 /* LDO3_FLT */
700#define WM831X_LDO3_FLT_MASK 0x0080 /* LDO3_FLT */
701#define WM831X_LDO3_FLT_SHIFT 7 /* LDO3_FLT */
702#define WM831X_LDO3_FLT_WIDTH 1 /* LDO3_FLT */
703#define WM831X_LDO3_SWI 0x0040 /* LDO3_SWI */
704#define WM831X_LDO3_SWI_MASK 0x0040 /* LDO3_SWI */
705#define WM831X_LDO3_SWI_SHIFT 6 /* LDO3_SWI */
706#define WM831X_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
707#define WM831X_LDO3_LP_MODE 0x0001 /* LDO3_LP_MODE */
708#define WM831X_LDO3_LP_MODE_MASK 0x0001 /* LDO3_LP_MODE */
709#define WM831X_LDO3_LP_MODE_SHIFT 0 /* LDO3_LP_MODE */
710#define WM831X_LDO3_LP_MODE_WIDTH 1 /* LDO3_LP_MODE */
711
712/*
713 * R16495 (0x406F) - LDO3 ON Control
714 */
715#define WM831X_LDO3_ON_SLOT_MASK 0xE000 /* LDO3_ON_SLOT - [15:13] */
716#define WM831X_LDO3_ON_SLOT_SHIFT 13 /* LDO3_ON_SLOT - [15:13] */
717#define WM831X_LDO3_ON_SLOT_WIDTH 3 /* LDO3_ON_SLOT - [15:13] */
718#define WM831X_LDO3_ON_MODE 0x0100 /* LDO3_ON_MODE */
719#define WM831X_LDO3_ON_MODE_MASK 0x0100 /* LDO3_ON_MODE */
720#define WM831X_LDO3_ON_MODE_SHIFT 8 /* LDO3_ON_MODE */
721#define WM831X_LDO3_ON_MODE_WIDTH 1 /* LDO3_ON_MODE */
722#define WM831X_LDO3_ON_VSEL_MASK 0x001F /* LDO3_ON_VSEL - [4:0] */
723#define WM831X_LDO3_ON_VSEL_SHIFT 0 /* LDO3_ON_VSEL - [4:0] */
724#define WM831X_LDO3_ON_VSEL_WIDTH 5 /* LDO3_ON_VSEL - [4:0] */
725
726/*
727 * R16496 (0x4070) - LDO3 SLEEP Control
728 */
729#define WM831X_LDO3_SLP_SLOT_MASK 0xE000 /* LDO3_SLP_SLOT - [15:13] */
730#define WM831X_LDO3_SLP_SLOT_SHIFT 13 /* LDO3_SLP_SLOT - [15:13] */
731#define WM831X_LDO3_SLP_SLOT_WIDTH 3 /* LDO3_SLP_SLOT - [15:13] */
732#define WM831X_LDO3_SLP_MODE 0x0100 /* LDO3_SLP_MODE */
733#define WM831X_LDO3_SLP_MODE_MASK 0x0100 /* LDO3_SLP_MODE */
734#define WM831X_LDO3_SLP_MODE_SHIFT 8 /* LDO3_SLP_MODE */
735#define WM831X_LDO3_SLP_MODE_WIDTH 1 /* LDO3_SLP_MODE */
736#define WM831X_LDO3_SLP_VSEL_MASK 0x001F /* LDO3_SLP_VSEL - [4:0] */
737#define WM831X_LDO3_SLP_VSEL_SHIFT 0 /* LDO3_SLP_VSEL - [4:0] */
738#define WM831X_LDO3_SLP_VSEL_WIDTH 5 /* LDO3_SLP_VSEL - [4:0] */
739
740/*
741 * R16497 (0x4071) - LDO4 Control
742 */
743#define WM831X_LDO4_ERR_ACT_MASK 0xC000 /* LDO4_ERR_ACT - [15:14] */
744#define WM831X_LDO4_ERR_ACT_SHIFT 14 /* LDO4_ERR_ACT - [15:14] */
745#define WM831X_LDO4_ERR_ACT_WIDTH 2 /* LDO4_ERR_ACT - [15:14] */
746#define WM831X_LDO4_HWC_SRC_MASK 0x1800 /* LDO4_HWC_SRC - [12:11] */
747#define WM831X_LDO4_HWC_SRC_SHIFT 11 /* LDO4_HWC_SRC - [12:11] */
748#define WM831X_LDO4_HWC_SRC_WIDTH 2 /* LDO4_HWC_SRC - [12:11] */
749#define WM831X_LDO4_HWC_VSEL 0x0400 /* LDO4_HWC_VSEL */
750#define WM831X_LDO4_HWC_VSEL_MASK 0x0400 /* LDO4_HWC_VSEL */
751#define WM831X_LDO4_HWC_VSEL_SHIFT 10 /* LDO4_HWC_VSEL */
752#define WM831X_LDO4_HWC_VSEL_WIDTH 1 /* LDO4_HWC_VSEL */
753#define WM831X_LDO4_HWC_MODE_MASK 0x0300 /* LDO4_HWC_MODE - [9:8] */
754#define WM831X_LDO4_HWC_MODE_SHIFT 8 /* LDO4_HWC_MODE - [9:8] */
755#define WM831X_LDO4_HWC_MODE_WIDTH 2 /* LDO4_HWC_MODE - [9:8] */
756#define WM831X_LDO4_FLT 0x0080 /* LDO4_FLT */
757#define WM831X_LDO4_FLT_MASK 0x0080 /* LDO4_FLT */
758#define WM831X_LDO4_FLT_SHIFT 7 /* LDO4_FLT */
759#define WM831X_LDO4_FLT_WIDTH 1 /* LDO4_FLT */
760#define WM831X_LDO4_SWI 0x0040 /* LDO4_SWI */
761#define WM831X_LDO4_SWI_MASK 0x0040 /* LDO4_SWI */
762#define WM831X_LDO4_SWI_SHIFT 6 /* LDO4_SWI */
763#define WM831X_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
764#define WM831X_LDO4_LP_MODE 0x0001 /* LDO4_LP_MODE */
765#define WM831X_LDO4_LP_MODE_MASK 0x0001 /* LDO4_LP_MODE */
766#define WM831X_LDO4_LP_MODE_SHIFT 0 /* LDO4_LP_MODE */
767#define WM831X_LDO4_LP_MODE_WIDTH 1 /* LDO4_LP_MODE */
768
769/*
770 * R16498 (0x4072) - LDO4 ON Control
771 */
772#define WM831X_LDO4_ON_SLOT_MASK 0xE000 /* LDO4_ON_SLOT - [15:13] */
773#define WM831X_LDO4_ON_SLOT_SHIFT 13 /* LDO4_ON_SLOT - [15:13] */
774#define WM831X_LDO4_ON_SLOT_WIDTH 3 /* LDO4_ON_SLOT - [15:13] */
775#define WM831X_LDO4_ON_MODE 0x0100 /* LDO4_ON_MODE */
776#define WM831X_LDO4_ON_MODE_MASK 0x0100 /* LDO4_ON_MODE */
777#define WM831X_LDO4_ON_MODE_SHIFT 8 /* LDO4_ON_MODE */
778#define WM831X_LDO4_ON_MODE_WIDTH 1 /* LDO4_ON_MODE */
779#define WM831X_LDO4_ON_VSEL_MASK 0x001F /* LDO4_ON_VSEL - [4:0] */
780#define WM831X_LDO4_ON_VSEL_SHIFT 0 /* LDO4_ON_VSEL - [4:0] */
781#define WM831X_LDO4_ON_VSEL_WIDTH 5 /* LDO4_ON_VSEL - [4:0] */
782
783/*
784 * R16499 (0x4073) - LDO4 SLEEP Control
785 */
786#define WM831X_LDO4_SLP_SLOT_MASK 0xE000 /* LDO4_SLP_SLOT - [15:13] */
787#define WM831X_LDO4_SLP_SLOT_SHIFT 13 /* LDO4_SLP_SLOT - [15:13] */
788#define WM831X_LDO4_SLP_SLOT_WIDTH 3 /* LDO4_SLP_SLOT - [15:13] */
789#define WM831X_LDO4_SLP_MODE 0x0100 /* LDO4_SLP_MODE */
790#define WM831X_LDO4_SLP_MODE_MASK 0x0100 /* LDO4_SLP_MODE */
791#define WM831X_LDO4_SLP_MODE_SHIFT 8 /* LDO4_SLP_MODE */
792#define WM831X_LDO4_SLP_MODE_WIDTH 1 /* LDO4_SLP_MODE */
793#define WM831X_LDO4_SLP_VSEL_MASK 0x001F /* LDO4_SLP_VSEL - [4:0] */
794#define WM831X_LDO4_SLP_VSEL_SHIFT 0 /* LDO4_SLP_VSEL - [4:0] */
795#define WM831X_LDO4_SLP_VSEL_WIDTH 5 /* LDO4_SLP_VSEL - [4:0] */
796
797/*
798 * R16500 (0x4074) - LDO5 Control
799 */
800#define WM831X_LDO5_ERR_ACT_MASK 0xC000 /* LDO5_ERR_ACT - [15:14] */
801#define WM831X_LDO5_ERR_ACT_SHIFT 14 /* LDO5_ERR_ACT - [15:14] */
802#define WM831X_LDO5_ERR_ACT_WIDTH 2 /* LDO5_ERR_ACT - [15:14] */
803#define WM831X_LDO5_HWC_SRC_MASK 0x1800 /* LDO5_HWC_SRC - [12:11] */
804#define WM831X_LDO5_HWC_SRC_SHIFT 11 /* LDO5_HWC_SRC - [12:11] */
805#define WM831X_LDO5_HWC_SRC_WIDTH 2 /* LDO5_HWC_SRC - [12:11] */
806#define WM831X_LDO5_HWC_VSEL 0x0400 /* LDO5_HWC_VSEL */
807#define WM831X_LDO5_HWC_VSEL_MASK 0x0400 /* LDO5_HWC_VSEL */
808#define WM831X_LDO5_HWC_VSEL_SHIFT 10 /* LDO5_HWC_VSEL */
809#define WM831X_LDO5_HWC_VSEL_WIDTH 1 /* LDO5_HWC_VSEL */
810#define WM831X_LDO5_HWC_MODE_MASK 0x0300 /* LDO5_HWC_MODE - [9:8] */
811#define WM831X_LDO5_HWC_MODE_SHIFT 8 /* LDO5_HWC_MODE - [9:8] */
812#define WM831X_LDO5_HWC_MODE_WIDTH 2 /* LDO5_HWC_MODE - [9:8] */
813#define WM831X_LDO5_FLT 0x0080 /* LDO5_FLT */
814#define WM831X_LDO5_FLT_MASK 0x0080 /* LDO5_FLT */
815#define WM831X_LDO5_FLT_SHIFT 7 /* LDO5_FLT */
816#define WM831X_LDO5_FLT_WIDTH 1 /* LDO5_FLT */
817#define WM831X_LDO5_SWI 0x0040 /* LDO5_SWI */
818#define WM831X_LDO5_SWI_MASK 0x0040 /* LDO5_SWI */
819#define WM831X_LDO5_SWI_SHIFT 6 /* LDO5_SWI */
820#define WM831X_LDO5_SWI_WIDTH 1 /* LDO5_SWI */
821#define WM831X_LDO5_LP_MODE 0x0001 /* LDO5_LP_MODE */
822#define WM831X_LDO5_LP_MODE_MASK 0x0001 /* LDO5_LP_MODE */
823#define WM831X_LDO5_LP_MODE_SHIFT 0 /* LDO5_LP_MODE */
824#define WM831X_LDO5_LP_MODE_WIDTH 1 /* LDO5_LP_MODE */
825
826/*
827 * R16501 (0x4075) - LDO5 ON Control
828 */
829#define WM831X_LDO5_ON_SLOT_MASK 0xE000 /* LDO5_ON_SLOT - [15:13] */
830#define WM831X_LDO5_ON_SLOT_SHIFT 13 /* LDO5_ON_SLOT - [15:13] */
831#define WM831X_LDO5_ON_SLOT_WIDTH 3 /* LDO5_ON_SLOT - [15:13] */
832#define WM831X_LDO5_ON_MODE 0x0100 /* LDO5_ON_MODE */
833#define WM831X_LDO5_ON_MODE_MASK 0x0100 /* LDO5_ON_MODE */
834#define WM831X_LDO5_ON_MODE_SHIFT 8 /* LDO5_ON_MODE */
835#define WM831X_LDO5_ON_MODE_WIDTH 1 /* LDO5_ON_MODE */
836#define WM831X_LDO5_ON_VSEL_MASK 0x001F /* LDO5_ON_VSEL - [4:0] */
837#define WM831X_LDO5_ON_VSEL_SHIFT 0 /* LDO5_ON_VSEL - [4:0] */
838#define WM831X_LDO5_ON_VSEL_WIDTH 5 /* LDO5_ON_VSEL - [4:0] */
839
840/*
841 * R16502 (0x4076) - LDO5 SLEEP Control
842 */
843#define WM831X_LDO5_SLP_SLOT_MASK 0xE000 /* LDO5_SLP_SLOT - [15:13] */
844#define WM831X_LDO5_SLP_SLOT_SHIFT 13 /* LDO5_SLP_SLOT - [15:13] */
845#define WM831X_LDO5_SLP_SLOT_WIDTH 3 /* LDO5_SLP_SLOT - [15:13] */
846#define WM831X_LDO5_SLP_MODE 0x0100 /* LDO5_SLP_MODE */
847#define WM831X_LDO5_SLP_MODE_MASK 0x0100 /* LDO5_SLP_MODE */
848#define WM831X_LDO5_SLP_MODE_SHIFT 8 /* LDO5_SLP_MODE */
849#define WM831X_LDO5_SLP_MODE_WIDTH 1 /* LDO5_SLP_MODE */
850#define WM831X_LDO5_SLP_VSEL_MASK 0x001F /* LDO5_SLP_VSEL - [4:0] */
851#define WM831X_LDO5_SLP_VSEL_SHIFT 0 /* LDO5_SLP_VSEL - [4:0] */
852#define WM831X_LDO5_SLP_VSEL_WIDTH 5 /* LDO5_SLP_VSEL - [4:0] */
853
854/*
855 * R16503 (0x4077) - LDO6 Control
856 */
857#define WM831X_LDO6_ERR_ACT_MASK 0xC000 /* LDO6_ERR_ACT - [15:14] */
858#define WM831X_LDO6_ERR_ACT_SHIFT 14 /* LDO6_ERR_ACT - [15:14] */
859#define WM831X_LDO6_ERR_ACT_WIDTH 2 /* LDO6_ERR_ACT - [15:14] */
860#define WM831X_LDO6_HWC_SRC_MASK 0x1800 /* LDO6_HWC_SRC - [12:11] */
861#define WM831X_LDO6_HWC_SRC_SHIFT 11 /* LDO6_HWC_SRC - [12:11] */
862#define WM831X_LDO6_HWC_SRC_WIDTH 2 /* LDO6_HWC_SRC - [12:11] */
863#define WM831X_LDO6_HWC_VSEL 0x0400 /* LDO6_HWC_VSEL */
864#define WM831X_LDO6_HWC_VSEL_MASK 0x0400 /* LDO6_HWC_VSEL */
865#define WM831X_LDO6_HWC_VSEL_SHIFT 10 /* LDO6_HWC_VSEL */
866#define WM831X_LDO6_HWC_VSEL_WIDTH 1 /* LDO6_HWC_VSEL */
867#define WM831X_LDO6_HWC_MODE_MASK 0x0300 /* LDO6_HWC_MODE - [9:8] */
868#define WM831X_LDO6_HWC_MODE_SHIFT 8 /* LDO6_HWC_MODE - [9:8] */
869#define WM831X_LDO6_HWC_MODE_WIDTH 2 /* LDO6_HWC_MODE - [9:8] */
870#define WM831X_LDO6_FLT 0x0080 /* LDO6_FLT */
871#define WM831X_LDO6_FLT_MASK 0x0080 /* LDO6_FLT */
872#define WM831X_LDO6_FLT_SHIFT 7 /* LDO6_FLT */
873#define WM831X_LDO6_FLT_WIDTH 1 /* LDO6_FLT */
874#define WM831X_LDO6_SWI 0x0040 /* LDO6_SWI */
875#define WM831X_LDO6_SWI_MASK 0x0040 /* LDO6_SWI */
876#define WM831X_LDO6_SWI_SHIFT 6 /* LDO6_SWI */
877#define WM831X_LDO6_SWI_WIDTH 1 /* LDO6_SWI */
878#define WM831X_LDO6_LP_MODE 0x0001 /* LDO6_LP_MODE */
879#define WM831X_LDO6_LP_MODE_MASK 0x0001 /* LDO6_LP_MODE */
880#define WM831X_LDO6_LP_MODE_SHIFT 0 /* LDO6_LP_MODE */
881#define WM831X_LDO6_LP_MODE_WIDTH 1 /* LDO6_LP_MODE */
882
883/*
884 * R16504 (0x4078) - LDO6 ON Control
885 */
886#define WM831X_LDO6_ON_SLOT_MASK 0xE000 /* LDO6_ON_SLOT - [15:13] */
887#define WM831X_LDO6_ON_SLOT_SHIFT 13 /* LDO6_ON_SLOT - [15:13] */
888#define WM831X_LDO6_ON_SLOT_WIDTH 3 /* LDO6_ON_SLOT - [15:13] */
889#define WM831X_LDO6_ON_MODE 0x0100 /* LDO6_ON_MODE */
890#define WM831X_LDO6_ON_MODE_MASK 0x0100 /* LDO6_ON_MODE */
891#define WM831X_LDO6_ON_MODE_SHIFT 8 /* LDO6_ON_MODE */
892#define WM831X_LDO6_ON_MODE_WIDTH 1 /* LDO6_ON_MODE */
893#define WM831X_LDO6_ON_VSEL_MASK 0x001F /* LDO6_ON_VSEL - [4:0] */
894#define WM831X_LDO6_ON_VSEL_SHIFT 0 /* LDO6_ON_VSEL - [4:0] */
895#define WM831X_LDO6_ON_VSEL_WIDTH 5 /* LDO6_ON_VSEL - [4:0] */
896
897/*
898 * R16505 (0x4079) - LDO6 SLEEP Control
899 */
900#define WM831X_LDO6_SLP_SLOT_MASK 0xE000 /* LDO6_SLP_SLOT - [15:13] */
901#define WM831X_LDO6_SLP_SLOT_SHIFT 13 /* LDO6_SLP_SLOT - [15:13] */
902#define WM831X_LDO6_SLP_SLOT_WIDTH 3 /* LDO6_SLP_SLOT - [15:13] */
903#define WM831X_LDO6_SLP_MODE 0x0100 /* LDO6_SLP_MODE */
904#define WM831X_LDO6_SLP_MODE_MASK 0x0100 /* LDO6_SLP_MODE */
905#define WM831X_LDO6_SLP_MODE_SHIFT 8 /* LDO6_SLP_MODE */
906#define WM831X_LDO6_SLP_MODE_WIDTH 1 /* LDO6_SLP_MODE */
907#define WM831X_LDO6_SLP_VSEL_MASK 0x001F /* LDO6_SLP_VSEL - [4:0] */
908#define WM831X_LDO6_SLP_VSEL_SHIFT 0 /* LDO6_SLP_VSEL - [4:0] */
909#define WM831X_LDO6_SLP_VSEL_WIDTH 5 /* LDO6_SLP_VSEL - [4:0] */
910
911/*
912 * R16506 (0x407A) - LDO7 Control
913 */
914#define WM831X_LDO7_ERR_ACT_MASK 0xC000 /* LDO7_ERR_ACT - [15:14] */
915#define WM831X_LDO7_ERR_ACT_SHIFT 14 /* LDO7_ERR_ACT - [15:14] */
916#define WM831X_LDO7_ERR_ACT_WIDTH 2 /* LDO7_ERR_ACT - [15:14] */
917#define WM831X_LDO7_HWC_SRC_MASK 0x1800 /* LDO7_HWC_SRC - [12:11] */
918#define WM831X_LDO7_HWC_SRC_SHIFT 11 /* LDO7_HWC_SRC - [12:11] */
919#define WM831X_LDO7_HWC_SRC_WIDTH 2 /* LDO7_HWC_SRC - [12:11] */
920#define WM831X_LDO7_HWC_VSEL 0x0400 /* LDO7_HWC_VSEL */
921#define WM831X_LDO7_HWC_VSEL_MASK 0x0400 /* LDO7_HWC_VSEL */
922#define WM831X_LDO7_HWC_VSEL_SHIFT 10 /* LDO7_HWC_VSEL */
923#define WM831X_LDO7_HWC_VSEL_WIDTH 1 /* LDO7_HWC_VSEL */
924#define WM831X_LDO7_HWC_MODE_MASK 0x0300 /* LDO7_HWC_MODE - [9:8] */
925#define WM831X_LDO7_HWC_MODE_SHIFT 8 /* LDO7_HWC_MODE - [9:8] */
926#define WM831X_LDO7_HWC_MODE_WIDTH 2 /* LDO7_HWC_MODE - [9:8] */
927#define WM831X_LDO7_FLT 0x0080 /* LDO7_FLT */
928#define WM831X_LDO7_FLT_MASK 0x0080 /* LDO7_FLT */
929#define WM831X_LDO7_FLT_SHIFT 7 /* LDO7_FLT */
930#define WM831X_LDO7_FLT_WIDTH 1 /* LDO7_FLT */
931#define WM831X_LDO7_SWI 0x0040 /* LDO7_SWI */
932#define WM831X_LDO7_SWI_MASK 0x0040 /* LDO7_SWI */
933#define WM831X_LDO7_SWI_SHIFT 6 /* LDO7_SWI */
934#define WM831X_LDO7_SWI_WIDTH 1 /* LDO7_SWI */
935
936/*
937 * R16507 (0x407B) - LDO7 ON Control
938 */
939#define WM831X_LDO7_ON_SLOT_MASK 0xE000 /* LDO7_ON_SLOT - [15:13] */
940#define WM831X_LDO7_ON_SLOT_SHIFT 13 /* LDO7_ON_SLOT - [15:13] */
941#define WM831X_LDO7_ON_SLOT_WIDTH 3 /* LDO7_ON_SLOT - [15:13] */
942#define WM831X_LDO7_ON_MODE 0x0100 /* LDO7_ON_MODE */
943#define WM831X_LDO7_ON_MODE_MASK 0x0100 /* LDO7_ON_MODE */
944#define WM831X_LDO7_ON_MODE_SHIFT 8 /* LDO7_ON_MODE */
945#define WM831X_LDO7_ON_MODE_WIDTH 1 /* LDO7_ON_MODE */
946#define WM831X_LDO7_ON_VSEL_MASK 0x001F /* LDO7_ON_VSEL - [4:0] */
947#define WM831X_LDO7_ON_VSEL_SHIFT 0 /* LDO7_ON_VSEL - [4:0] */
948#define WM831X_LDO7_ON_VSEL_WIDTH 5 /* LDO7_ON_VSEL - [4:0] */
949
950/*
951 * R16508 (0x407C) - LDO7 SLEEP Control
952 */
953#define WM831X_LDO7_SLP_SLOT_MASK 0xE000 /* LDO7_SLP_SLOT - [15:13] */
954#define WM831X_LDO7_SLP_SLOT_SHIFT 13 /* LDO7_SLP_SLOT - [15:13] */
955#define WM831X_LDO7_SLP_SLOT_WIDTH 3 /* LDO7_SLP_SLOT - [15:13] */
956#define WM831X_LDO7_SLP_MODE 0x0100 /* LDO7_SLP_MODE */
957#define WM831X_LDO7_SLP_MODE_MASK 0x0100 /* LDO7_SLP_MODE */
958#define WM831X_LDO7_SLP_MODE_SHIFT 8 /* LDO7_SLP_MODE */
959#define WM831X_LDO7_SLP_MODE_WIDTH 1 /* LDO7_SLP_MODE */
960#define WM831X_LDO7_SLP_VSEL_MASK 0x001F /* LDO7_SLP_VSEL - [4:0] */
961#define WM831X_LDO7_SLP_VSEL_SHIFT 0 /* LDO7_SLP_VSEL - [4:0] */
962#define WM831X_LDO7_SLP_VSEL_WIDTH 5 /* LDO7_SLP_VSEL - [4:0] */
963
964/*
965 * R16509 (0x407D) - LDO8 Control
966 */
967#define WM831X_LDO8_ERR_ACT_MASK 0xC000 /* LDO8_ERR_ACT - [15:14] */
968#define WM831X_LDO8_ERR_ACT_SHIFT 14 /* LDO8_ERR_ACT - [15:14] */
969#define WM831X_LDO8_ERR_ACT_WIDTH 2 /* LDO8_ERR_ACT - [15:14] */
970#define WM831X_LDO8_HWC_SRC_MASK 0x1800 /* LDO8_HWC_SRC - [12:11] */
971#define WM831X_LDO8_HWC_SRC_SHIFT 11 /* LDO8_HWC_SRC - [12:11] */
972#define WM831X_LDO8_HWC_SRC_WIDTH 2 /* LDO8_HWC_SRC - [12:11] */
973#define WM831X_LDO8_HWC_VSEL 0x0400 /* LDO8_HWC_VSEL */
974#define WM831X_LDO8_HWC_VSEL_MASK 0x0400 /* LDO8_HWC_VSEL */
975#define WM831X_LDO8_HWC_VSEL_SHIFT 10 /* LDO8_HWC_VSEL */
976#define WM831X_LDO8_HWC_VSEL_WIDTH 1 /* LDO8_HWC_VSEL */
977#define WM831X_LDO8_HWC_MODE_MASK 0x0300 /* LDO8_HWC_MODE - [9:8] */
978#define WM831X_LDO8_HWC_MODE_SHIFT 8 /* LDO8_HWC_MODE - [9:8] */
979#define WM831X_LDO8_HWC_MODE_WIDTH 2 /* LDO8_HWC_MODE - [9:8] */
980#define WM831X_LDO8_FLT 0x0080 /* LDO8_FLT */
981#define WM831X_LDO8_FLT_MASK 0x0080 /* LDO8_FLT */
982#define WM831X_LDO8_FLT_SHIFT 7 /* LDO8_FLT */
983#define WM831X_LDO8_FLT_WIDTH 1 /* LDO8_FLT */
984#define WM831X_LDO8_SWI 0x0040 /* LDO8_SWI */
985#define WM831X_LDO8_SWI_MASK 0x0040 /* LDO8_SWI */
986#define WM831X_LDO8_SWI_SHIFT 6 /* LDO8_SWI */
987#define WM831X_LDO8_SWI_WIDTH 1 /* LDO8_SWI */
988
989/*
990 * R16510 (0x407E) - LDO8 ON Control
991 */
992#define WM831X_LDO8_ON_SLOT_MASK 0xE000 /* LDO8_ON_SLOT - [15:13] */
993#define WM831X_LDO8_ON_SLOT_SHIFT 13 /* LDO8_ON_SLOT - [15:13] */
994#define WM831X_LDO8_ON_SLOT_WIDTH 3 /* LDO8_ON_SLOT - [15:13] */
995#define WM831X_LDO8_ON_MODE 0x0100 /* LDO8_ON_MODE */
996#define WM831X_LDO8_ON_MODE_MASK 0x0100 /* LDO8_ON_MODE */
997#define WM831X_LDO8_ON_MODE_SHIFT 8 /* LDO8_ON_MODE */
998#define WM831X_LDO8_ON_MODE_WIDTH 1 /* LDO8_ON_MODE */
999#define WM831X_LDO8_ON_VSEL_MASK 0x001F /* LDO8_ON_VSEL - [4:0] */
1000#define WM831X_LDO8_ON_VSEL_SHIFT 0 /* LDO8_ON_VSEL - [4:0] */
1001#define WM831X_LDO8_ON_VSEL_WIDTH 5 /* LDO8_ON_VSEL - [4:0] */
1002
1003/*
1004 * R16511 (0x407F) - LDO8 SLEEP Control
1005 */
1006#define WM831X_LDO8_SLP_SLOT_MASK 0xE000 /* LDO8_SLP_SLOT - [15:13] */
1007#define WM831X_LDO8_SLP_SLOT_SHIFT 13 /* LDO8_SLP_SLOT - [15:13] */
1008#define WM831X_LDO8_SLP_SLOT_WIDTH 3 /* LDO8_SLP_SLOT - [15:13] */
1009#define WM831X_LDO8_SLP_MODE 0x0100 /* LDO8_SLP_MODE */
1010#define WM831X_LDO8_SLP_MODE_MASK 0x0100 /* LDO8_SLP_MODE */
1011#define WM831X_LDO8_SLP_MODE_SHIFT 8 /* LDO8_SLP_MODE */
1012#define WM831X_LDO8_SLP_MODE_WIDTH 1 /* LDO8_SLP_MODE */
1013#define WM831X_LDO8_SLP_VSEL_MASK 0x001F /* LDO8_SLP_VSEL - [4:0] */
1014#define WM831X_LDO8_SLP_VSEL_SHIFT 0 /* LDO8_SLP_VSEL - [4:0] */
1015#define WM831X_LDO8_SLP_VSEL_WIDTH 5 /* LDO8_SLP_VSEL - [4:0] */
1016
1017/*
1018 * R16512 (0x4080) - LDO9 Control
1019 */
1020#define WM831X_LDO9_ERR_ACT_MASK 0xC000 /* LDO9_ERR_ACT - [15:14] */
1021#define WM831X_LDO9_ERR_ACT_SHIFT 14 /* LDO9_ERR_ACT - [15:14] */
1022#define WM831X_LDO9_ERR_ACT_WIDTH 2 /* LDO9_ERR_ACT - [15:14] */
1023#define WM831X_LDO9_HWC_SRC_MASK 0x1800 /* LDO9_HWC_SRC - [12:11] */
1024#define WM831X_LDO9_HWC_SRC_SHIFT 11 /* LDO9_HWC_SRC - [12:11] */
1025#define WM831X_LDO9_HWC_SRC_WIDTH 2 /* LDO9_HWC_SRC - [12:11] */
1026#define WM831X_LDO9_HWC_VSEL 0x0400 /* LDO9_HWC_VSEL */
1027#define WM831X_LDO9_HWC_VSEL_MASK 0x0400 /* LDO9_HWC_VSEL */
1028#define WM831X_LDO9_HWC_VSEL_SHIFT 10 /* LDO9_HWC_VSEL */
1029#define WM831X_LDO9_HWC_VSEL_WIDTH 1 /* LDO9_HWC_VSEL */
1030#define WM831X_LDO9_HWC_MODE_MASK 0x0300 /* LDO9_HWC_MODE - [9:8] */
1031#define WM831X_LDO9_HWC_MODE_SHIFT 8 /* LDO9_HWC_MODE - [9:8] */
1032#define WM831X_LDO9_HWC_MODE_WIDTH 2 /* LDO9_HWC_MODE - [9:8] */
1033#define WM831X_LDO9_FLT 0x0080 /* LDO9_FLT */
1034#define WM831X_LDO9_FLT_MASK 0x0080 /* LDO9_FLT */
1035#define WM831X_LDO9_FLT_SHIFT 7 /* LDO9_FLT */
1036#define WM831X_LDO9_FLT_WIDTH 1 /* LDO9_FLT */
1037#define WM831X_LDO9_SWI 0x0040 /* LDO9_SWI */
1038#define WM831X_LDO9_SWI_MASK 0x0040 /* LDO9_SWI */
1039#define WM831X_LDO9_SWI_SHIFT 6 /* LDO9_SWI */
1040#define WM831X_LDO9_SWI_WIDTH 1 /* LDO9_SWI */
1041
1042/*
1043 * R16513 (0x4081) - LDO9 ON Control
1044 */
1045#define WM831X_LDO9_ON_SLOT_MASK 0xE000 /* LDO9_ON_SLOT - [15:13] */
1046#define WM831X_LDO9_ON_SLOT_SHIFT 13 /* LDO9_ON_SLOT - [15:13] */
1047#define WM831X_LDO9_ON_SLOT_WIDTH 3 /* LDO9_ON_SLOT - [15:13] */
1048#define WM831X_LDO9_ON_MODE 0x0100 /* LDO9_ON_MODE */
1049#define WM831X_LDO9_ON_MODE_MASK 0x0100 /* LDO9_ON_MODE */
1050#define WM831X_LDO9_ON_MODE_SHIFT 8 /* LDO9_ON_MODE */
1051#define WM831X_LDO9_ON_MODE_WIDTH 1 /* LDO9_ON_MODE */
1052#define WM831X_LDO9_ON_VSEL_MASK 0x001F /* LDO9_ON_VSEL - [4:0] */
1053#define WM831X_LDO9_ON_VSEL_SHIFT 0 /* LDO9_ON_VSEL - [4:0] */
1054#define WM831X_LDO9_ON_VSEL_WIDTH 5 /* LDO9_ON_VSEL - [4:0] */
1055
1056/*
1057 * R16514 (0x4082) - LDO9 SLEEP Control
1058 */
1059#define WM831X_LDO9_SLP_SLOT_MASK 0xE000 /* LDO9_SLP_SLOT - [15:13] */
1060#define WM831X_LDO9_SLP_SLOT_SHIFT 13 /* LDO9_SLP_SLOT - [15:13] */
1061#define WM831X_LDO9_SLP_SLOT_WIDTH 3 /* LDO9_SLP_SLOT - [15:13] */
1062#define WM831X_LDO9_SLP_MODE 0x0100 /* LDO9_SLP_MODE */
1063#define WM831X_LDO9_SLP_MODE_MASK 0x0100 /* LDO9_SLP_MODE */
1064#define WM831X_LDO9_SLP_MODE_SHIFT 8 /* LDO9_SLP_MODE */
1065#define WM831X_LDO9_SLP_MODE_WIDTH 1 /* LDO9_SLP_MODE */
1066#define WM831X_LDO9_SLP_VSEL_MASK 0x001F /* LDO9_SLP_VSEL - [4:0] */
1067#define WM831X_LDO9_SLP_VSEL_SHIFT 0 /* LDO9_SLP_VSEL - [4:0] */
1068#define WM831X_LDO9_SLP_VSEL_WIDTH 5 /* LDO9_SLP_VSEL - [4:0] */
1069
1070/*
1071 * R16515 (0x4083) - LDO10 Control
1072 */
1073#define WM831X_LDO10_ERR_ACT_MASK 0xC000 /* LDO10_ERR_ACT - [15:14] */
1074#define WM831X_LDO10_ERR_ACT_SHIFT 14 /* LDO10_ERR_ACT - [15:14] */
1075#define WM831X_LDO10_ERR_ACT_WIDTH 2 /* LDO10_ERR_ACT - [15:14] */
1076#define WM831X_LDO10_HWC_SRC_MASK 0x1800 /* LDO10_HWC_SRC - [12:11] */
1077#define WM831X_LDO10_HWC_SRC_SHIFT 11 /* LDO10_HWC_SRC - [12:11] */
1078#define WM831X_LDO10_HWC_SRC_WIDTH 2 /* LDO10_HWC_SRC - [12:11] */
1079#define WM831X_LDO10_HWC_VSEL 0x0400 /* LDO10_HWC_VSEL */
1080#define WM831X_LDO10_HWC_VSEL_MASK 0x0400 /* LDO10_HWC_VSEL */
1081#define WM831X_LDO10_HWC_VSEL_SHIFT 10 /* LDO10_HWC_VSEL */
1082#define WM831X_LDO10_HWC_VSEL_WIDTH 1 /* LDO10_HWC_VSEL */
1083#define WM831X_LDO10_HWC_MODE_MASK 0x0300 /* LDO10_HWC_MODE - [9:8] */
1084#define WM831X_LDO10_HWC_MODE_SHIFT 8 /* LDO10_HWC_MODE - [9:8] */
1085#define WM831X_LDO10_HWC_MODE_WIDTH 2 /* LDO10_HWC_MODE - [9:8] */
1086#define WM831X_LDO10_FLT 0x0080 /* LDO10_FLT */
1087#define WM831X_LDO10_FLT_MASK 0x0080 /* LDO10_FLT */
1088#define WM831X_LDO10_FLT_SHIFT 7 /* LDO10_FLT */
1089#define WM831X_LDO10_FLT_WIDTH 1 /* LDO10_FLT */
1090#define WM831X_LDO10_SWI 0x0040 /* LDO10_SWI */
1091#define WM831X_LDO10_SWI_MASK 0x0040 /* LDO10_SWI */
1092#define WM831X_LDO10_SWI_SHIFT 6 /* LDO10_SWI */
1093#define WM831X_LDO10_SWI_WIDTH 1 /* LDO10_SWI */
1094
1095/*
1096 * R16516 (0x4084) - LDO10 ON Control
1097 */
1098#define WM831X_LDO10_ON_SLOT_MASK 0xE000 /* LDO10_ON_SLOT - [15:13] */
1099#define WM831X_LDO10_ON_SLOT_SHIFT 13 /* LDO10_ON_SLOT - [15:13] */
1100#define WM831X_LDO10_ON_SLOT_WIDTH 3 /* LDO10_ON_SLOT - [15:13] */
1101#define WM831X_LDO10_ON_MODE 0x0100 /* LDO10_ON_MODE */
1102#define WM831X_LDO10_ON_MODE_MASK 0x0100 /* LDO10_ON_MODE */
1103#define WM831X_LDO10_ON_MODE_SHIFT 8 /* LDO10_ON_MODE */
1104#define WM831X_LDO10_ON_MODE_WIDTH 1 /* LDO10_ON_MODE */
1105#define WM831X_LDO10_ON_VSEL_MASK 0x001F /* LDO10_ON_VSEL - [4:0] */
1106#define WM831X_LDO10_ON_VSEL_SHIFT 0 /* LDO10_ON_VSEL - [4:0] */
1107#define WM831X_LDO10_ON_VSEL_WIDTH 5 /* LDO10_ON_VSEL - [4:0] */
1108
1109/*
1110 * R16517 (0x4085) - LDO10 SLEEP Control
1111 */
1112#define WM831X_LDO10_SLP_SLOT_MASK 0xE000 /* LDO10_SLP_SLOT - [15:13] */
1113#define WM831X_LDO10_SLP_SLOT_SHIFT 13 /* LDO10_SLP_SLOT - [15:13] */
1114#define WM831X_LDO10_SLP_SLOT_WIDTH 3 /* LDO10_SLP_SLOT - [15:13] */
1115#define WM831X_LDO10_SLP_MODE 0x0100 /* LDO10_SLP_MODE */
1116#define WM831X_LDO10_SLP_MODE_MASK 0x0100 /* LDO10_SLP_MODE */
1117#define WM831X_LDO10_SLP_MODE_SHIFT 8 /* LDO10_SLP_MODE */
1118#define WM831X_LDO10_SLP_MODE_WIDTH 1 /* LDO10_SLP_MODE */
1119#define WM831X_LDO10_SLP_VSEL_MASK 0x001F /* LDO10_SLP_VSEL - [4:0] */
1120#define WM831X_LDO10_SLP_VSEL_SHIFT 0 /* LDO10_SLP_VSEL - [4:0] */
1121#define WM831X_LDO10_SLP_VSEL_WIDTH 5 /* LDO10_SLP_VSEL - [4:0] */
1122
1123/*
1124 * R16519 (0x4087) - LDO11 ON Control
1125 */
1126#define WM831X_LDO11_ON_SLOT_MASK 0xE000 /* LDO11_ON_SLOT - [15:13] */
1127#define WM831X_LDO11_ON_SLOT_SHIFT 13 /* LDO11_ON_SLOT - [15:13] */
1128#define WM831X_LDO11_ON_SLOT_WIDTH 3 /* LDO11_ON_SLOT - [15:13] */
1129#define WM831X_LDO11_OFFENA 0x1000 /* LDO11_OFFENA */
1130#define WM831X_LDO11_OFFENA_MASK 0x1000 /* LDO11_OFFENA */
1131#define WM831X_LDO11_OFFENA_SHIFT 12 /* LDO11_OFFENA */
1132#define WM831X_LDO11_OFFENA_WIDTH 1 /* LDO11_OFFENA */
1133#define WM831X_LDO11_VSEL_SRC 0x0080 /* LDO11_VSEL_SRC */
1134#define WM831X_LDO11_VSEL_SRC_MASK 0x0080 /* LDO11_VSEL_SRC */
1135#define WM831X_LDO11_VSEL_SRC_SHIFT 7 /* LDO11_VSEL_SRC */
1136#define WM831X_LDO11_VSEL_SRC_WIDTH 1 /* LDO11_VSEL_SRC */
1137#define WM831X_LDO11_ON_VSEL_MASK 0x000F /* LDO11_ON_VSEL - [3:0] */
1138#define WM831X_LDO11_ON_VSEL_SHIFT 0 /* LDO11_ON_VSEL - [3:0] */
1139#define WM831X_LDO11_ON_VSEL_WIDTH 4 /* LDO11_ON_VSEL - [3:0] */
1140
1141/*
1142 * R16520 (0x4088) - LDO11 SLEEP Control
1143 */
1144#define WM831X_LDO11_SLP_SLOT_MASK 0xE000 /* LDO11_SLP_SLOT - [15:13] */
1145#define WM831X_LDO11_SLP_SLOT_SHIFT 13 /* LDO11_SLP_SLOT - [15:13] */
1146#define WM831X_LDO11_SLP_SLOT_WIDTH 3 /* LDO11_SLP_SLOT - [15:13] */
1147#define WM831X_LDO11_SLP_VSEL_MASK 0x000F /* LDO11_SLP_VSEL - [3:0] */
1148#define WM831X_LDO11_SLP_VSEL_SHIFT 0 /* LDO11_SLP_VSEL - [3:0] */
1149#define WM831X_LDO11_SLP_VSEL_WIDTH 4 /* LDO11_SLP_VSEL - [3:0] */
1150
1151/*
1152 * R16526 (0x408E) - Power Good Source 1
1153 */
1154#define WM831X_DC4_OK 0x0008 /* DC4_OK */
1155#define WM831X_DC4_OK_MASK 0x0008 /* DC4_OK */
1156#define WM831X_DC4_OK_SHIFT 3 /* DC4_OK */
1157#define WM831X_DC4_OK_WIDTH 1 /* DC4_OK */
1158#define WM831X_DC3_OK 0x0004 /* DC3_OK */
1159#define WM831X_DC3_OK_MASK 0x0004 /* DC3_OK */
1160#define WM831X_DC3_OK_SHIFT 2 /* DC3_OK */
1161#define WM831X_DC3_OK_WIDTH 1 /* DC3_OK */
1162#define WM831X_DC2_OK 0x0002 /* DC2_OK */
1163#define WM831X_DC2_OK_MASK 0x0002 /* DC2_OK */
1164#define WM831X_DC2_OK_SHIFT 1 /* DC2_OK */
1165#define WM831X_DC2_OK_WIDTH 1 /* DC2_OK */
1166#define WM831X_DC1_OK 0x0001 /* DC1_OK */
1167#define WM831X_DC1_OK_MASK 0x0001 /* DC1_OK */
1168#define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */
1169#define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */
1170
1171/*
1172 * R16527 (0x408F) - Power Good Source 2
1173 */
1174#define WM831X_LDO10_OK 0x0200 /* LDO10_OK */
1175#define WM831X_LDO10_OK_MASK 0x0200 /* LDO10_OK */
1176#define WM831X_LDO10_OK_SHIFT 9 /* LDO10_OK */
1177#define WM831X_LDO10_OK_WIDTH 1 /* LDO10_OK */
1178#define WM831X_LDO9_OK 0x0100 /* LDO9_OK */
1179#define WM831X_LDO9_OK_MASK 0x0100 /* LDO9_OK */
1180#define WM831X_LDO9_OK_SHIFT 8 /* LDO9_OK */
1181#define WM831X_LDO9_OK_WIDTH 1 /* LDO9_OK */
1182#define WM831X_LDO8_OK 0x0080 /* LDO8_OK */
1183#define WM831X_LDO8_OK_MASK 0x0080 /* LDO8_OK */
1184#define WM831X_LDO8_OK_SHIFT 7 /* LDO8_OK */
1185#define WM831X_LDO8_OK_WIDTH 1 /* LDO8_OK */
1186#define WM831X_LDO7_OK 0x0040 /* LDO7_OK */
1187#define WM831X_LDO7_OK_MASK 0x0040 /* LDO7_OK */
1188#define WM831X_LDO7_OK_SHIFT 6 /* LDO7_OK */
1189#define WM831X_LDO7_OK_WIDTH 1 /* LDO7_OK */
1190#define WM831X_LDO6_OK 0x0020 /* LDO6_OK */
1191#define WM831X_LDO6_OK_MASK 0x0020 /* LDO6_OK */
1192#define WM831X_LDO6_OK_SHIFT 5 /* LDO6_OK */
1193#define WM831X_LDO6_OK_WIDTH 1 /* LDO6_OK */
1194#define WM831X_LDO5_OK 0x0010 /* LDO5_OK */
1195#define WM831X_LDO5_OK_MASK 0x0010 /* LDO5_OK */
1196#define WM831X_LDO5_OK_SHIFT 4 /* LDO5_OK */
1197#define WM831X_LDO5_OK_WIDTH 1 /* LDO5_OK */
1198#define WM831X_LDO4_OK 0x0008 /* LDO4_OK */
1199#define WM831X_LDO4_OK_MASK 0x0008 /* LDO4_OK */
1200#define WM831X_LDO4_OK_SHIFT 3 /* LDO4_OK */
1201#define WM831X_LDO4_OK_WIDTH 1 /* LDO4_OK */
1202#define WM831X_LDO3_OK 0x0004 /* LDO3_OK */
1203#define WM831X_LDO3_OK_MASK 0x0004 /* LDO3_OK */
1204#define WM831X_LDO3_OK_SHIFT 2 /* LDO3_OK */
1205#define WM831X_LDO3_OK_WIDTH 1 /* LDO3_OK */
1206#define WM831X_LDO2_OK 0x0002 /* LDO2_OK */
1207#define WM831X_LDO2_OK_MASK 0x0002 /* LDO2_OK */
1208#define WM831X_LDO2_OK_SHIFT 1 /* LDO2_OK */
1209#define WM831X_LDO2_OK_WIDTH 1 /* LDO2_OK */
1210#define WM831X_LDO1_OK 0x0001 /* LDO1_OK */
1211#define WM831X_LDO1_OK_MASK 0x0001 /* LDO1_OK */
1212#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */
1213#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */
1214
1215#define WM831X_ISINK_MAX_ISEL 56
1216extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
1217
1218#endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 42cca672f340..1d595de6a055 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -605,6 +605,11 @@ struct wm8350_irq {
605 void *data; 605 void *data;
606}; 606};
607 607
608struct wm8350_hwmon {
609 struct platform_device *pdev;
610 struct device *classdev;
611};
612
608struct wm8350 { 613struct wm8350 {
609 struct device *dev; 614 struct device *dev;
610 615
@@ -621,7 +626,6 @@ struct wm8350 {
621 struct mutex auxadc_mutex; 626 struct mutex auxadc_mutex;
622 627
623 /* Interrupt handling */ 628 /* Interrupt handling */
624 struct work_struct irq_work;
625 struct mutex irq_mutex; /* IRQ table mutex */ 629 struct mutex irq_mutex; /* IRQ table mutex */
626 struct wm8350_irq irq[WM8350_NUM_IRQ]; 630 struct wm8350_irq irq[WM8350_NUM_IRQ];
627 int chip_irq; 631 int chip_irq;
@@ -629,6 +633,7 @@ struct wm8350 {
629 /* Client devices */ 633 /* Client devices */
630 struct wm8350_codec codec; 634 struct wm8350_codec codec;
631 struct wm8350_gpio gpio; 635 struct wm8350_gpio gpio;
636 struct wm8350_hwmon hwmon;
632 struct wm8350_pmic pmic; 637 struct wm8350_pmic pmic;
633 struct wm8350_power power; 638 struct wm8350_power power;
634 struct wm8350_rtc rtc; 639 struct wm8350_rtc rtc;
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 225f733e7533..ce1be708ca16 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -193,6 +193,8 @@ void *rdev_get_drvdata(struct regulator_dev *rdev);
193struct device *rdev_get_dev(struct regulator_dev *rdev); 193struct device *rdev_get_dev(struct regulator_dev *rdev);
194int rdev_get_id(struct regulator_dev *rdev); 194int rdev_get_id(struct regulator_dev *rdev);
195 195
196int regulator_mode_to_status(unsigned int);
197
196void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); 198void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
197 199
198#endif 200#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 19:50:22 -0500