41 files changed, 2099 insertions, 1456 deletions

diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index e0aec1007a0d..6bbb1b8b8294 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -578,7 +578,7 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 
-void __init omap1_clk_disable_unused(struct clk *clk)
+void omap1_clk_disable_unused(struct clk *clk)
 {
         __u32 regval32;
 
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index a4190afb8614..75d0d7d90bff 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -39,7 +39,7 @@ extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
 extern unsigned long omap1_watchdog_recalc(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
-extern void __init omap1_clk_disable_unused(struct clk *clk);
+extern void omap1_clk_disable_unused(struct clk *clk);
 #else
 #define omap1_clk_disable_unused        NULL
 #endif
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 43d7246ce335..66e01acfd585 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -70,12 +70,12 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
 
 static int omap2_clk_apll96_enable(struct clk *clk)
 {
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
 }
 
 static int omap2_clk_apll54_enable(struct clk *clk)
 {
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
 }
 
 /* Stop APLL */
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index e60ca4e47bbd..aef62918aaf0 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,16 +68,13 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         const struct prcm_config *ptr;
         long highest_rate;
-        long sys_ck_rate;
-
-        sys_ck_rate = clk_get_rate(sclk);
 
         highest_rate = -EINVAL;
 
         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                 if (!(ptr->flags & cpu_mask))
                         continue;
-                if (ptr->xtal_speed != sys_ck_rate)
+                if (ptr->xtal_speed != sclk->rate)
                         continue;
 
                 highest_rate = ptr->mpu_speed;
@@ -96,15 +93,12 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
         const struct prcm_config *prcm;
         unsigned long found_speed = 0;
         unsigned long flags;
-        long sys_ck_rate;
-
-        sys_ck_rate = clk_get_rate(sclk);
 
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
 
-                if (prcm->xtal_speed != sys_ck_rate)
+                if (prcm->xtal_speed != sclk->rate)
                         continue;
 
                 if (prcm->mpu_speed <= rate) {
@@ -181,19 +175,16 @@ static struct cpufreq_frequency_table *freq_table;
 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
         const struct prcm_config *prcm;
-        long sys_ck_rate;
         int i = 0;
         int tbl_sz = 0;
 
         if (!cpu_is_omap24xx())
                 return;
 
-        sys_ck_rate = clk_get_rate(sclk);
-
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
-                if (prcm->xtal_speed != sys_ck_rate)
+                if (prcm->xtal_speed != sclk->rate)
                         continue;
 
                 /* don't put bypass rates in table */
@@ -226,7 +217,7 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
-                if (prcm->xtal_speed != sys_ck_rate)
+                if (prcm->xtal_speed != sclk->rate)
                         continue;
 
                 /* don't put bypass rates in table */
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e50812dd03fd..a781cd6795a4 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -12,8 +12,26 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * XXX At some point these clksel clocks should be split into
- * "divider" clocks and "mux" clocks to better match the hardware.
+ *
+ * clksel clocks are clocks that do not have a fixed parent, or that
+ * can divide their parent's rate, or possibly both at the same time, based
+ * on the contents of a hardware register bitfield.
+ *
+ * All of the various mux and divider settings can be encoded into
+ * struct clksel* data structures, and then these can be autogenerated
+ * from some hardware database for each new chip generation.  This
+ * should avoid the need to write, review, and validate a lot of new
+ * clock code for each new chip, since it can be exported from the SoC
+ * design flow.  This is now done on OMAP4.
+ *
+ * The fusion of mux and divider clocks is a software creation.  In
+ * hardware reality, the multiplexer (parent selection) and the
+ * divider exist separately.  XXX At some point these clksel clocks
+ * should be split into "divider" clocks and "mux" clocks to better
+ * match the hardware.
+ *
+ * (The name "clksel" comes from the name of the corresponding
+ * register field in the OMAP2/3 family of SoCs.)
  *
  * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
  * many of the OMAP1 clocks should be convertible to use this
@@ -29,14 +47,11 @@
 #include <plat/clock.h>
 
 #include "clock.h"
-#include "cm.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
 
 /* Private functions */
 
 /**
- * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * _get_clksel_by_parent() - return clksel struct for a given clk & parent
  * @clk: OMAP struct clk ptr to inspect
  * @src_clk: OMAP struct clk ptr of the parent clk to search for
  *
@@ -44,141 +59,217 @@
  * the element associated with the supplied parent clock address.
  * Returns a pointer to the struct clksel on success or NULL on error.
  */
-static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
-                                                        struct clk *src_clk)
+static const struct clksel *_get_clksel_by_parent(struct clk *clk,
+                                                  struct clk *src_clk)
 {
         const struct clksel *clks;
 
-        if (!clk->clksel)
-                return NULL;
-
-        for (clks = clk->clksel; clks->parent; clks++) {
+        for (clks = clk->clksel; clks->parent; clks++)
                 if (clks->parent == src_clk)
                         break; /* Found the requested parent */
-        }
 
         if (!clks->parent) {
-                printk(KERN_ERR "clock: Could not find parent clock %s in "
-                       "clksel array of clock %s\n", src_clk->name,
-                       clk->name);
+                /* This indicates a data problem */
+                WARN(1, "clock: Could not find parent clock %s in clksel array "
+                     "of clock %s\n", src_clk->name, clk->name);
                 return NULL;
         }
 
         return clks;
 }
 
-/*
- * Converts encoded control register address into a full address
- * On error, the return value (parent_div) will be 0.
+/**
+ * _get_div_and_fieldval() - find the new clksel divisor and field value to use
+ * @src_clk: planned new parent struct clk *
+ * @clk: struct clk * that is being reparented
+ * @field_val: pointer to a u32 to contain the register data for the divisor
+ *
+ * Given an intended new parent struct clk * @src_clk, and the struct
+ * clk * @clk to the clock that is being reparented, find the
+ * appropriate rate divisor for the new clock (returned as the return
+ * value), and the corresponding register bitfield data to program to
+ * reach that divisor (returned in the u32 pointed to by @field_val).
+ * Returns 0 on error, or returns the newly-selected divisor upon
+ * success (in this latter case, the corresponding register bitfield
+ * value is passed back in the variable pointed to by @field_val)
  */
-static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
-                                       u32 *field_val)
+static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
+                                u32 *field_val)
 {
         const struct clksel *clks;
-        const struct clksel_rate *clkr;
+        const struct clksel_rate *clkr, *max_clkr;
+        u8 max_div = 0;
 
-        clks = _omap2_get_clksel_by_parent(clk, src_clk);
+        clks = _get_clksel_by_parent(clk, src_clk);
         if (!clks)
                 return 0;
 
+        /*
+         * Find the highest divisor (e.g., the one resulting in the
+         * lowest rate) to use as the default.  This should avoid
+         * clock rates that are too high for the device.  XXX A better
+         * solution here would be to try to determine if there is a
+         * divisor matching the original clock rate before the parent
+         * switch, and if it cannot be found, to fall back to the
+         * highest divisor.
+         */
         for (clkr = clks->rates; clkr->div; clkr++) {
-                if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
-                        break; /* Found the default rate for this platform */
+                if (!(clkr->flags & cpu_mask))
+                        continue;
+
+                if (clkr->div > max_div) {
+                        max_div = clkr->div;
+                        max_clkr = clkr;
+                }
         }
 
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find default rate for "
-                       "clock %s parent %s\n", clk->name,
-                       src_clk->parent->name);
+        if (max_div == 0) {
+                /* This indicates an error in the clksel data */
+                WARN(1, "clock: Could not find divisor for clock %s parent %s"
+                     "\n", clk->name, src_clk->parent->name);
                 return 0;
         }
 
-        /* Should never happen.  Add a clksel mask to the struct clk. */
-        WARN_ON(clk->clksel_mask == 0);
+        *field_val = max_clkr->val;
 
-        *field_val = clkr->val;
-
-        return clkr->div;
+        return max_div;
 }
 
+/**
+ * _write_clksel_reg() - program a clock's clksel register in hardware
+ * @clk: struct clk * to program
+ * @v: clksel bitfield value to program (with LSB at bit 0)
+ *
+ * Shift the clksel register bitfield value @v to its appropriate
+ * location in the clksel register and write it in.  This function
+ * will ensure that the write to the clksel_reg reaches its
+ * destination before returning -- important since PRM and CM register
+ * accesses can be quite slow compared to ARM cycles -- but does not
+ * take into account any time the hardware might take to switch the
+ * clock source.
+ */
+static void _write_clksel_reg(struct clk *clk, u32 field_val)
+{
+        u32 v;
 
-/* Public functions */
+        v = __raw_readl(clk->clksel_reg);
+        v &= ~clk->clksel_mask;
+        v |= field_val << __ffs(clk->clksel_mask);
+        __raw_writel(v, clk->clksel_reg);
+
+        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+}
 
 /**
- * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
- * @clk: OMAP clock struct ptr to use
+ * _clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
  *
- * Given a pointer to a source-selectable struct clk, read the hardware
- * register and determine what its parent is currently set to.  Update the
- * clk->parent field with the appropriate clk ptr.
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor.  The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling.  Returns 0 on error or returns the actual integer divisor
+ * upon success.
  */
-void omap2_init_clksel_parent(struct clk *clk)
+static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
-        u32 r, found = 0;
 
-        if (!clk->clksel)
-                return;
+        clks = _get_clksel_by_parent(clk, clk->parent);
+        if (!clks)
+                return 0;
 
-        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        r >>= __ffs(clk->clksel_mask);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                        continue;
 
-        for (clks = clk->clksel; clks->parent && !found; clks++) {
-                for (clkr = clks->rates; clkr->div && !found; clkr++) {
-                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
-                                if (clk->parent != clks->parent) {
-                                        pr_debug("clock: inited %s parent "
-                                                 "to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
-                                        clk_reparent(clk, clks->parent);
-                                };
-                                found = 1;
-                        }
-                }
+                if (clkr->val == field_val)
+                        break;
         }
 
-        if (!found)
-                printk(KERN_ERR "clock: init parent: could not find "
-                       "regval %0x for clock %s\n", r,  clk->name);
+        if (!clkr->div) {
+                /* This indicates a data error */
+                WARN(1, "clock: Could not find fieldval %d for clock %s parent "
+                     "%s\n", field_val, clk->name, clk->parent->name);
+                return 0;
+        }
 
-        return;
+        return clkr->div;
 }
 
-/*
- * Used for clocks that are part of CLKSEL_xyz governed clocks.
- * REVISIT: Maybe change to use clk->enable() functions like on omap1?
+/**
+ * _divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock
+ * divisor, find the corresponding register field value.  Returns the
+ * register field value _before_ left-shifting (i.e., LSB is at bit
+ * 0); or returns 0xFFFFFFFF (~0) upon error.
  */
-unsigned long omap2_clksel_recalc(struct clk *clk)
+static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
-        unsigned long rate;
-        u32 div = 0;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
+        /* should never happen */
+        WARN_ON(div == 0);
 
-        div = omap2_clksel_get_divisor(clk);
-        if (div == 0)
-                return clk->rate;
+        clks = _get_clksel_by_parent(clk, clk->parent);
+        if (!clks)
+                return ~0;
 
-        rate = clk->parent->rate / div;
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                        continue;
 
-        pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
+                if (clkr->div == div)
+                        break;
+        }
 
-        return rate;
+        if (!clkr->div) {
+                pr_err("clock: Could not find divisor %d for clock %s parent "
+                       "%s\n", div, clk->name, clk->parent->name);
+                return ~0;
+        }
+
+        return clkr->val;
+}
+
+/**
+ * _read_divisor() - get current divisor applied to parent clock (from hdwr)
+ * @clk: OMAP struct clk to use.
+ *
+ * Read the current divisor register value for @clk that is programmed
+ * into the hardware, convert it into the actual divisor value, and
+ * return it; or return 0 on error.
+ */
+static u32 _read_divisor(struct clk *clk)
+{
+        u32 v;
+
+        if (!clk->clksel || !clk->clksel_mask)
+                return 0;
+
+        v = __raw_readl(clk->clksel_reg);
+        v &= clk->clksel_mask;
+        v >>= __ffs(clk->clksel_mask);
+
+        return _clksel_to_divisor(clk, v);
 }
 
+/* Public functions */
+
 /**
- * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
  * @clk: OMAP struct clk to use
  * @target_rate: desired clock rate
  * @new_div: ptr to where we should store the divisor
  *
  * Finds 'best' divider value in an array based on the source and target
  * rates.  The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
+ * This function is also used by the DPLL3 M2 divider code.
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
@@ -190,12 +281,15 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         const struct clksel_rate *clkr;
         u32 last_div = 0;
 
+        if (!clk->clksel || !clk->clksel_mask)
+                return ~0;
+
         pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
                  clk->name, target_rate);
 
         *new_div = 1;
 
-        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+        clks = _get_clksel_by_parent(clk, clk->parent);
         if (!clks)
                 return ~0;
 
@@ -231,168 +325,174 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         return clk->parent->rate / clkr->div;
 }
 
-/**
- * omap2_clksel_round_rate - find rounded rate for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- *
- * Compatibility wrapper for OMAP clock framework
- * Finds best target rate based on the source clock and possible dividers.
- * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
+/*
+ * Clocktype interface functions to the OMAP clock code
+ * (i.e., those used in struct clk field function pointers, etc.)
  */
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
-        u32 new_div;
-
-        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
-}
-
-
-/* Given a clock and a rate apply a clock specific rounding function */
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk->round_rate)
-                return clk->round_rate(clk, rate);
-
-        return clk->rate;
-}
 
 /**
- * omap2_clksel_to_divisor() - turn clksel field value into integer divider
- * @clk: OMAP struct clk to use
- * @field_val: register field value to find
+ * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
+ * @clk: OMAP clock struct ptr to use
  *
- * Given a struct clk of a rate-selectable clksel clock, and a register field
- * value to search for, find the corresponding clock divisor.  The register
- * field value should be pre-masked and shifted down so the LSB is at bit 0
- * before calling.  Returns 0 on error
+ * Given a pointer @clk to a source-selectable struct clk, read the
+ * hardware register and determine what its parent is currently set
+ * to.  Update @clk's .parent field with the appropriate clk ptr.  No
+ * return value.
  */
-u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
+void omap2_init_clksel_parent(struct clk *clk)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        u32 r, found = 0;
 
-        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return 0;
+        if (!clk->clksel || !clk->clksel_mask)
+                return;
 
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
-                        break;
-        }
+        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r >>= __ffs(clk->clksel_mask);
 
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find fieldval %d for "
-                       "clock %s parent %s\n", field_val, clk->name,
-                       clk->parent->name);
-                return 0;
+        for (clks = clk->clksel; clks->parent && !found; clks++) {
+                for (clkr = clks->rates; clkr->div && !found; clkr++) {
+                        if (!(clkr->flags & cpu_mask))
+                                continue;
+
+                        if (clkr->val == r) {
+                                if (clk->parent != clks->parent) {
+                                        pr_debug("clock: inited %s parent "
+                                                 "to %s (was %s)\n",
+                                                 clk->name, clks->parent->name,
+                                                 ((clk->parent) ?
+                                                  clk->parent->name : "NULL"));
+                                        clk_reparent(clk, clks->parent);
+                                };
+                                found = 1;
+                        }
+                }
         }
 
-        return clkr->div;
+        /* This indicates a data error */
+        WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
+             clk->name, r);
+
+        return;
 }
 
 /**
- * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
- * @clk: OMAP struct clk to use
- * @div: integer divisor to search for
+ * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
+ * @clk: struct clk *
  *
- * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
- * find the corresponding register field value.  The return register value is
- * the value before left-shifting.  Returns ~0 on error
+ * This function is intended to be called only by the clock framework.
+ * Each clksel clock should have its struct clk .recalc field set to this
+ * function.  Returns the clock's current rate, based on its parent's rate
+ * and its current divisor setting in the hardware.
  */
-u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
+unsigned long omap2_clksel_recalc(struct clk *clk)
 {
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        /* should never happen */
-        WARN_ON(div == 0);
+        unsigned long rate;
+        u32 div = 0;
 
-        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return ~0;
+        div = _read_divisor(clk);
+        if (div == 0)
+                return clk->rate;
 
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->div == div))
-                        break;
-        }
+        rate = clk->parent->rate / div;
 
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find divisor %d for "
-                       "clock %s parent %s\n", div, clk->name,
-                       clk->parent->name);
-                return ~0;
-        }
+        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
+                 rate, div);
 
-        return clkr->val;
+        return rate;
 }
 
 /**
- * omap2_clksel_get_divisor - get current divider applied to parent clock.
- * @clk: OMAP struct clk to use.
+ * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * This function is intended to be called only by the clock framework.
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
  *
- * Returns the integer divisor upon success or 0 on error.
+ * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-u32 omap2_clksel_get_divisor(struct clk *clk)
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        u32 v;
-
-        if (!clk->clksel_mask)
-                return 0;
-
-        v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        v >>= __ffs(clk->clksel_mask);
+        u32 new_div;
 
-        return omap2_clksel_to_divisor(clk, v);
+        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
 }
 
+/**
+ * omap2_clksel_set_rate() - program clock rate in hardware
+ * @clk: struct clk * to program rate
+ * @rate: target rate to program
+ *
+ * This function is intended to be called only by the clock framework.
+ * Program @clk's rate to @rate in the hardware.  The clock can be
+ * either enabled or disabled when this happens, although if the clock
+ * is enabled, some downstream devices may glitch or behave
+ * unpredictably when the clock rate is changed - this depends on the
+ * hardware. This function does not currently check the usecount of
+ * the clock, so if multiple drivers are using the clock, and the rate
+ * is changed, they will all be affected without any notification.
+ * Returns -EINVAL upon error, or 0 upon success.
+ */
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 v, field_val, validrate, new_div = 0;
+        u32 field_val, validrate, new_div = 0;
 
-        if (!clk->clksel_mask)
+        if (!clk->clksel || !clk->clksel_mask)
                 return -EINVAL;
 
         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
         if (validrate != rate)
                 return -EINVAL;
 
-        field_val = omap2_divisor_to_clksel(clk, new_div);
+        field_val = _divisor_to_clksel(clk, new_div);
         if (field_val == ~0)
                 return -EINVAL;
 
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+        _write_clksel_reg(clk, field_val);
 
         clk->rate = clk->parent->rate / new_div;
 
+        pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+
         return 0;
 }
 
+/*
+ * Clksel parent setting function - not passed in struct clk function
+ * pointer - instead, the OMAP clock code currently assumes that any
+ * parent-setting clock is a clksel clock, and calls
+ * omap2_clksel_set_parent() by default
+ */
+
+/**
+ * omap2_clksel_set_parent() - change a clock's parent clock
+ * @clk: struct clk * of the child clock
+ * @new_parent: struct clk * of the new parent clock
+ *
+ * This function is intended to be called only by the clock framework.
+ * Change the parent clock of clock @clk to @new_parent.  This is
+ * intended to be used while @clk is disabled.  This function does not
+ * currently check the usecount of the clock, so if multiple drivers
+ * are using the clock, and the parent is changed, they will all be
+ * affected without any notification.  Returns -EINVAL upon error, or
+ * 0 upon success.
+ */
 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 field_val, v, parent_div;
+        u32 field_val = 0;
+        u32 parent_div;
 
-        if (!clk->clksel)
+        if (!clk->clksel || !clk->clksel_mask)
                 return -EINVAL;
 
-        parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+        parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
         if (!parent_div)
                 return -EINVAL;
 
-        /* Set new source value (previous dividers if any in effect) */
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg);    /* OCP barrier */
+        _write_clksel_reg(clk, field_val);
 
         clk_reparent(clk, new_parent);
 
@@ -402,7 +502,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
         if (parent_div > 0)
                 clk->rate /= parent_div;
 
-        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+        pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
                  clk->name, clk->parent->name, clk->rate);
 
         return 0;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index a6d0b34b7990..605f531783a8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -334,6 +334,15 @@ oce_err1:
         return ret;
 }
 
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->round_rate)
+                return clk->round_rate(clk, rate);
+
+        return clk->rate;
+}
+
 /* Set the clock rate for a clock source */
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ad8a1f7c1afc..a535c7a2a62a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -73,19 +73,20 @@ void omap2_clk_disable_unused(struct clk *clk);
 #define omap2_clk_disable_unused        NULL
 #endif
 
-unsigned long omap2_clksel_recalc(struct clk *clk);
 void omap2_init_clk_clkdm(struct clk *clk);
-void omap2_init_clksel_parent(struct clk *clk);
-u32 omap2_clksel_get_divisor(struct clk *clk);
+
+/* clkt_clksel.c public functions */
 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                                 u32 *new_div);
-u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
-u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
+void omap2_init_clksel_parent(struct clk *clk);
+unsigned long omap2_clksel_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
+
 u32 omap2_get_dpll_rate(struct clk *clk);
 void omap2_init_dpll_parent(struct clk *clk);
+
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 
 
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index d932b142d0b6..23bc981574f6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
 /* func_54m_ck */
 
 static const struct clksel_rate func_54m_apll54_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate func_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_54M_SOURCE,
+        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
         .clksel         = func_54m_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
@@ -201,12 +201,12 @@ static struct clk func_96m_ck = {
 /* func_48m_ck */
 
 static const struct clksel_rate func_48m_apll96_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate func_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
@@ -223,7 +223,7 @@ static struct clk func_48m_ck = {
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_48M_SOURCE,
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
         .clksel         = func_48m_clksel,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
@@ -256,22 +256,22 @@ static struct clk wdt1_osc_ck = {
  * flags fields, which mark them as 2420-only.
  */
 static const struct clksel_rate common_clkout_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -300,7 +300,7 @@ static struct clk sys_clkout_src = {
 };
 
 static const struct clksel_rate common_clkout_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -384,7 +384,7 @@ static struct clk emul_ck = {
  *
  */
 static const struct clksel_rate mpu_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_242X },
         { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -420,7 +420,7 @@ static struct clk mpu_ck = {	/* Control cpu */
  * routed into a synchronizer and out of clocks abc.
  */
 static const struct clksel_rate dsp_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -450,7 +450,7 @@ static struct clk dsp_fck = {
 
 /* DSP interface clock */
 static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
@@ -532,7 +532,7 @@ static struct clk iva1_mpu_int_ifck = {
 static const struct clksel_rate core_l3_core_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_242X },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
         { .div = 8, .val = 8, .flags = RATE_IN_242X },
         { .div = 12, .val = 12, .flags = RATE_IN_242X },
@@ -559,7 +559,7 @@ static struct clk core_l3_ck = {	/* Used for ick and fck, interconnect */
 /* usb_l4_ick */
 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
@@ -591,7 +591,7 @@ static struct clk usb_l4_ick = {	/* FS-USB interface clock */
  * this domain.
  */
 static const struct clksel_rate l4_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
@@ -622,7 +622,7 @@ static struct clk l4_ck = {		/* used both as an ick and fck */
  */
 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 6, .val = 6, .flags = RATE_IN_242X },
@@ -730,7 +730,7 @@ static struct clk gfx_ick = {
 /* XXX Add RATE_NOT_VALIDATED */
 
 static const struct clksel_rate dss1_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -744,7 +744,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -779,12 +779,12 @@ static struct clk dss1_fck = {
 };
 
 static const struct clksel_rate dss2_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate dss2_fck_48m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -825,7 +825,7 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
  * functional clock parents.
  */
 static const struct clksel_rate gpt_alt_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -1588,7 +1588,7 @@ static struct clk vlynq_ick = {
 };
 
 static const struct clksel_rate vlynq_fck_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_242X },
         { .div = 0 }
 };
 
@@ -1601,7 +1601,7 @@ static const struct clksel_rate vlynq_fck_core_rates[] = {
         { .div = 8, .val = 8, .flags = RATE_IN_242X },
         { .div = 9, .val = 9, .flags = RATE_IN_242X },
         { .div = 12, .val = 12, .flags = RATE_IN_242X },
-        { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
         { .div = 18, .val = 18, .flags = RATE_IN_242X },
         { .div = 0 }
 };
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0438b6e4f51a..2df50d97deb2 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -155,12 +155,12 @@ static struct clk apll54_ck = {
 /* func_54m_ck */
 
 static const struct clksel_rate func_54m_apll54_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate func_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_54M_SOURCE,
+        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
         .clksel         = func_54m_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
@@ -192,12 +192,12 @@ static struct clk core_ck = {
 
 /* func_96m_ck */
 static const struct clksel_rate func_96m_apll96_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate func_96m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
         { .div = 0 },
 };
 
@@ -214,7 +214,7 @@ static struct clk func_96m_ck = {
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP2430_96M_SOURCE,
+        .clksel_mask    = OMAP2430_96M_SOURCE_MASK,
         .clksel         = func_96m_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
@@ -222,12 +222,12 @@ static struct clk func_96m_ck = {
 /* func_48m_ck */
 
 static const struct clksel_rate func_48m_apll96_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate func_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
 
@@ -244,7 +244,7 @@ static struct clk func_48m_ck = {
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_48M_SOURCE,
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
         .clksel         = func_48m_clksel,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
@@ -277,22 +277,22 @@ static struct clk wdt1_osc_ck = {
  * flags fields, which mark them as 2420-only.
  */
 static const struct clksel_rate common_clkout_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_clkout_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -321,7 +321,7 @@ static struct clk sys_clkout_src = {
 };
 
 static const struct clksel_rate common_clkout_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
@@ -369,7 +369,7 @@ static struct clk emul_ck = {
  *
  */
 static const struct clksel_rate mpu_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 },
 };
@@ -402,7 +402,7 @@ static struct clk mpu_ck = {	/* Control cpu */
  * routed into a synchronizer and out of clocks abc.
  */
 static const struct clksel_rate dsp_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
@@ -429,7 +429,7 @@ static struct clk dsp_fck = {
 
 /* DSP interface clock */
 static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 3, .val = 3, .flags = RATE_IN_243X },
         { .div = 0 },
@@ -481,7 +481,7 @@ static struct clk iva2_1_ick = {
  */
 static const struct clksel_rate core_l3_core_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
@@ -505,7 +505,7 @@ static struct clk core_l3_ck = {	/* Used for ick and fck, interconnect */
 /* usb_l4_ick */
 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
@@ -537,7 +537,7 @@ static struct clk usb_l4_ick = {	/* FS-USB interface clock */
  * this domain.
  */
 static const struct clksel_rate l4_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
@@ -568,7 +568,7 @@ static struct clk l4_ck = {		/* used both as an ick and fck */
  */
 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
         { .div = 5, .val = 5, .flags = RATE_IN_243X },
@@ -673,7 +673,7 @@ static struct clk gfx_ick = {
  */
 static const struct clksel_rate mdm_ick_core_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_243X },
-        { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X },
         { .div = 6, .val = 6, .flags = RATE_IN_243X },
         { .div = 9, .val = 9, .flags = RATE_IN_243X },
         { .div = 0 }
@@ -718,7 +718,7 @@ static struct clk mdm_osc_ck = {
 /* XXX Add RATE_NOT_VALIDATED */
 
 static const struct clksel_rate dss1_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -732,7 +732,7 @@ static const struct clksel_rate dss1_fck_core_rates[] = {
         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -767,12 +767,12 @@ static struct clk dss1_fck = {
 };
 
 static const struct clksel_rate dss2_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
 static const struct clksel_rate dss2_fck_48m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
@@ -813,7 +813,7 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
  * functional clock parents.
  */
 static const struct clksel_rate gpt_alt_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
         { .div = 0 }
 };
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 6905eb7aa67c..833be485c89e 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -110,32 +110,32 @@ static struct clk virt_38_4m_ck = {
 };
 
 static const struct clksel_rate osc_sys_12m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_13m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
         { .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_19_2m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_26m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate osc_sys_38_4m_rates[] = {
-        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -163,8 +163,8 @@ static struct clk osc_sys_ck = {
 };
 
 static const struct clksel_rate div2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -213,42 +213,42 @@ static struct clk sys_clkout1 = {
 /* CM CLOCKS */
 
 static const struct clksel_rate div16_dpll_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 5, .val = 5, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 7, .val = 7, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
-        { .div = 9, .val = 9, .flags = RATE_IN_343X },
-        { .div = 10, .val = 10, .flags = RATE_IN_343X },
-        { .div = 11, .val = 11, .flags = RATE_IN_343X },
-        { .div = 12, .val = 12, .flags = RATE_IN_343X },
-        { .div = 13, .val = 13, .flags = RATE_IN_343X },
-        { .div = 14, .val = 14, .flags = RATE_IN_343X },
-        { .div = 15, .val = 15, .flags = RATE_IN_343X },
-        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
-static const struct clksel_rate div32_dpll4_rates_3630[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_36XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_36XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_36XX },
-        { .div = 5, .val = 5, .flags = RATE_IN_36XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_36XX },
-        { .div = 7, .val = 7, .flags = RATE_IN_36XX },
-        { .div = 8, .val = 8, .flags = RATE_IN_36XX },
-        { .div = 9, .val = 9, .flags = RATE_IN_36XX },
-        { .div = 10, .val = 10, .flags = RATE_IN_36XX },
-        { .div = 11, .val = 11, .flags = RATE_IN_36XX },
-        { .div = 12, .val = 12, .flags = RATE_IN_36XX },
-        { .div = 13, .val = 13, .flags = RATE_IN_36XX },
-        { .div = 14, .val = 14, .flags = RATE_IN_36XX },
-        { .div = 15, .val = 15, .flags = RATE_IN_36XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_36XX },
+static const struct clksel_rate dpll4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
@@ -450,37 +450,37 @@ static struct clk dpll3_x2_ck = {
 };
 
 static const struct clksel_rate div31_dpll3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
         { .div = 0 },
 };
 
@@ -562,6 +562,7 @@ static struct clk emu_core_alwon_ck = {
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
 static struct dpll_data dpll4_dd;
+
 static struct dpll_data dpll4_dd_34xx __initdata = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
@@ -632,39 +633,20 @@ static struct clk dpll4_x2_ck = {
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
-static const struct clksel div16_dpll4_clksel[] = {
-        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-static const struct clksel div32_dpll4_clksel[] = {
-        { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
+static const struct clksel dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = dpll4_rates },
         { .parent = NULL }
 };
 
 /* This virtual clock is the source for dpll4_m2x2_ck */
-static struct clk dpll4_m2_ck;
-
-static struct clk dpll4_m2_ck_34xx __initdata = {
-        .name           = "dpll4_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
-        .clksel_mask    = OMAP3430_DIV_96M_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dpll4_m2_ck_3630 __initdata  = {
+static struct clk dpll4_m2_ck = {
         .name           = "dpll4_m2_ck",
         .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
         .clksel_mask    = OMAP3630_DIV_96M_MASK,
-        .clksel         = div32_dpll4_clksel,
+        .clksel         = dpll4_clksel,
         .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -698,7 +680,7 @@ static struct clk omap_192m_alwon_fck = {
 
 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_36XX },
         { .div = 0 }
 };
 
@@ -708,12 +690,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
 };
 
 static const struct clksel_rate omap_96m_dpll_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate omap_96m_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -760,28 +742,14 @@ static struct clk omap_96m_fck = {
 };
 
 /* This virtual clock is the source for dpll4_m3x2_ck */
-static struct clk dpll4_m3_ck;
-
-static struct clk dpll4_m3_ck_34xx __initdata = {
+static struct clk dpll4_m3_ck = {
         .name           = "dpll4_m3_ck",
         .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dpll4_m3_ck_3630 __initdata = {
-        .name           = "dpll4_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
-        .clksel         = div32_dpll4_clksel,
+        .clksel         = dpll4_clksel,
         .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -799,12 +767,12 @@ static struct clk dpll4_m3x2_ck = {
 };
 
 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate omap_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -825,12 +793,12 @@ static struct clk omap_54m_fck = {
 };
 
 static const struct clksel_rate omap_48m_cm96m_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate omap_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -858,31 +826,15 @@ static struct clk omap_12m_fck = {
         .recalc         = &omap_fixed_divisor_recalc,
 };
 
-/* This virstual clock is the source for dpll4_m4x2_ck */
-static struct clk dpll4_m4_ck;
-
-static struct clk dpll4_m4_ck_34xx __initdata = {
+/* This virtual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
         .name           = "dpll4_m4_ck",
         .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-
-static struct clk dpll4_m4_ck_3630 __initdata = {
-        .name           = "dpll4_m4_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
-        .clksel         = div32_dpll4_clksel,
+        .clksel         = dpll4_clksel,
         .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
         .set_rate       = &omap2_clksel_set_rate,
@@ -902,30 +854,14 @@ static struct clk dpll4_m4x2_ck = {
 };
 
 /* This virtual clock is the source for dpll4_m5x2_ck */
-static struct clk dpll4_m5_ck;
-
-static struct clk dpll4_m5_ck_34xx __initdata = {
+static struct clk dpll4_m5_ck = {
         .name           = "dpll4_m5_ck",
         .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dpll4_m5_ck_3630 __initdata = {
-        .name           = "dpll4_m5_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
-        .clksel         = div32_dpll4_clksel,
+        .clksel         = dpll4_clksel,
         .clkdm_name     = "dpll4_clkdm",
         .set_rate       = &omap2_clksel_set_rate,
         .round_rate     = &omap2_clksel_round_rate,
@@ -945,28 +881,14 @@ static struct clk dpll4_m5x2_ck = {
 };
 
 /* This virtual clock is the source for dpll4_m6x2_ck */
-static struct clk dpll4_m6_ck;
-
-static struct clk dpll4_m6_ck_34xx __initdata = {
+static struct clk dpll4_m6_ck = {
         .name           = "dpll4_m6_ck",
         .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dpll4_m6_ck_3630 __initdata = {
-        .name           = "dpll4_m6_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
-        .clksel         = div32_dpll4_clksel,
+        .clksel         = dpll4_clksel,
         .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -1049,22 +971,22 @@ static struct clk dpll5_m2_ck = {
 /* CM EXTERNAL CLOCK OUTPUTS */
 
 static const struct clksel_rate clkout2_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate clkout2_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -1090,11 +1012,11 @@ static struct clk clkout2_src_ck = {
 };
 
 static const struct clksel_rate sys_clkout2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
-        { .div = 4, .val = 2, .flags = RATE_IN_343X },
-        { .div = 8, .val = 3, .flags = RATE_IN_343X },
-        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -1111,6 +1033,8 @@ static struct clk sys_clkout2 = {
         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
         .clksel         = sys_clkout2_clksel,
         .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
 };
 
 /* CM OUTPUT CLOCKS */
@@ -1125,9 +1049,9 @@ static struct clk corex2_fck = {
 /* DPLL power domain clock controls */
 
 static const struct clksel_rate div4_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -1161,8 +1085,8 @@ static struct clk mpu_ck = {
 
 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 static const struct clksel_rate arm_fck_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -1333,25 +1257,25 @@ static struct clk gfx_cg2_ck = {
 
 static const struct clksel_rate sgx_core_rates[] = {
         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
-        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4, .val = 1, .flags = RATE_IN_343X },
-        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
 static const struct clksel_rate sgx_192m_rates[] = {
-        { .div = 1,  .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate sgx_corex2_rates[] = {
-        { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
+        { .div = 3, .val = 6, .flags = RATE_IN_36XX },
         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
         { .div = 0 },
 };
 
 static const struct clksel_rate sgx_96m_rates[] = {
-        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -1576,12 +1500,12 @@ static struct clk i2c1_fck = {
  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  */
 static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -1714,12 +1638,12 @@ static struct clk hdq_fck = {
 /* DPLL3-derived clock */
 
 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
         { .div = 0 }
 };
 
@@ -2353,18 +2277,18 @@ static struct clk usbhost_ick = {
 /* WKUP */
 
 static const struct clksel_rate usim_96m_rates[] = {
-        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
-        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
-        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
 static const struct clksel_rate usim_120m_rates[] = {
-        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
-        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
-        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
+        { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -2951,22 +2875,22 @@ static struct clk mcbsp4_fck = {
 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
 
 static const struct clksel_rate emu_src_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
 static const struct clksel_rate emu_src_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
 static const struct clksel_rate emu_src_per_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
 static const struct clksel_rate emu_src_mpu_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -2995,10 +2919,10 @@ static struct clk emu_src_ck = {
 };
 
 static const struct clksel_rate pclk_emu_rates[] = {
-        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -3019,9 +2943,9 @@ static struct clk pclk_fck = {
 };
 
 static const struct clksel_rate pclkx2_emu_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -3069,9 +2993,9 @@ static struct clk traceclk_src_fck = {
 };
 
 static const struct clksel_rate traceclk_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
         { .div = 0 },
 };
 
@@ -3488,14 +3412,8 @@ int __init omap3xxx_clk_init(void)
         struct omap_clk *c;
         u32 cpu_clkflg = CK_3XXX;
 
-        if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
-                cpu_clkflg |= CK_3517;
-        } else if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
-                cpu_clkflg |= CK_3505;
-        } else if (cpu_is_omap34xx()) {
-                cpu_mask = RATE_IN_343X;
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_3XXX;
                 cpu_clkflg |= CK_343X;
 
                 /*
@@ -3506,10 +3424,17 @@ int __init omap3xxx_clk_init(void)
                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
                         cpu_clkflg |= CK_3430ES1;
                 } else {
-                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_mask |= RATE_IN_3430ES2PLUS;
                         cpu_clkflg |= CK_3430ES2;
                 }
+        } else if (cpu_is_omap3517()) {
+                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+                cpu_clkflg |= CK_3517;
+        } else if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+                cpu_clkflg |= CK_3505;
         }
+
         if (omap3_has_192mhz_clk())
                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
 
@@ -3520,14 +3445,7 @@ int __init omap3xxx_clk_init(void)
                 /*
                  * XXX This type of dynamic rewriting of the clock tree is
                  * deprecated and should be revised soon.
-                 */
-                dpll4_m2_ck = dpll4_m2_ck_3630;
-                dpll4_m3_ck = dpll4_m3_ck_3630;
-                dpll4_m4_ck = dpll4_m4_ck_3630;
-                dpll4_m5_ck = dpll4_m5_ck_3630;
-                dpll4_m6_ck = dpll4_m6_ck_3630;
-
-                /*
+                 *
                  * For 3630: override clkops_omap2_dflt_wait for the
                  * clocks affected from PWRDN reset Limitation
                  */
@@ -3543,18 +3461,12 @@ int __init omap3xxx_clk_init(void)
                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
                 dpll4_m6x2_ck.ops =
                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-        } else {
-                /*
-                 * XXX This type of dynamic rewriting of the clock tree is
-                 * deprecated and should be revised soon.
-                 */
-                dpll4_m2_ck = dpll4_m2_ck_34xx;
-                dpll4_m3_ck = dpll4_m3_ck_34xx;
-                dpll4_m4_ck = dpll4_m4_ck_34xx;
-                dpll4_m5_ck = dpll4_m5_ck_34xx;
-                dpll4_m6_ck = dpll4_m6_ck_34xx;
         }
 
+        /*
+         * XXX This type of dynamic rewriting of the clock tree is
+         * deprecated and should be revised soon.
+         */
         if (cpu_is_omap3630())
                 dpll4_dd = dpll4_dd_3630;
         else
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index f69096b88cdb..1cf8131205fa 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -20,20 +20,20 @@
 
 /* clksel_rate data common to 24xx/343x */
 const struct clksel_rate gpt_32k_rates[] = {
-         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
          { .div = 0 }
 };
 
 const struct clksel_rate gpt_sys_rates[] = {
-         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
          { .div = 0 }
 };
 
 const struct clksel_rate gfx_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
         { .div = 0 }
 };
 
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6e568ec995ee..5d80cb897489 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -809,7 +809,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
 
         if (cpu_is_omap24xx()) {
 
-                cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
+                cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
                             clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
         } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -853,7 +853,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
 
         if (cpu_is_omap24xx()) {
 
-                cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
+                cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
                               clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
         } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
index 438aaee2e392..7e5ba0f67925 100644
--- a/arch/arm/mach-omap2/clockdomains44xx.h
+++ b/arch/arm/mach-omap2/clockdomains44xx.h
@@ -131,7 +131,7 @@ static struct clockdomain mpuss_44xx_clkdm = {
 static struct clockdomain mpu0_44xx_clkdm = {
         .name             = "mpu0_clkdm",
         .pwrdm            = { .name = "cpu0_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
+        .clkstctrl_reg    = OMAP4430_CM_CPU0_CLKSTCTRL,
         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -140,7 +140,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
 static struct clockdomain mpu1_44xx_clkdm = {
         .name             = "mpu1_clkdm",
         .pwrdm            = { .name = "cpu1_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
+        .clkstctrl_reg    = OMAP4430_CM_CPU1_CLKSTCTRL,
         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 297a2fe634ea..da51cc3ed7eb 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -20,43 +20,43 @@
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
 #define OMAP24XX_EN_CAM_SHIFT                           31
-#define OMAP24XX_EN_CAM                                 (1 << 31)
+#define OMAP24XX_EN_CAM_MASK                            (1 << 31)
 #define OMAP24XX_EN_WDT4_SHIFT                          29
-#define OMAP24XX_EN_WDT4                                (1 << 29)
+#define OMAP24XX_EN_WDT4_MASK                           (1 << 29)
 #define OMAP2420_EN_WDT3_SHIFT                          28
-#define OMAP2420_EN_WDT3                                (1 << 28)
+#define OMAP2420_EN_WDT3_MASK                           (1 << 28)
 #define OMAP24XX_EN_MSPRO_SHIFT                         27
-#define OMAP24XX_EN_MSPRO                               (1 << 27)
+#define OMAP24XX_EN_MSPRO_MASK                          (1 << 27)
 #define OMAP24XX_EN_FAC_SHIFT                           25
-#define OMAP24XX_EN_FAC                                 (1 << 25)
+#define OMAP24XX_EN_FAC_MASK                            (1 << 25)
 #define OMAP2420_EN_EAC_SHIFT                           24
-#define OMAP2420_EN_EAC                                 (1 << 24)
+#define OMAP2420_EN_EAC_MASK                            (1 << 24)
 #define OMAP24XX_EN_HDQ_SHIFT                           23
-#define OMAP24XX_EN_HDQ                                 (1 << 23)
+#define OMAP24XX_EN_HDQ_MASK                            (1 << 23)
 #define OMAP2420_EN_I2C2_SHIFT                          20
-#define OMAP2420_EN_I2C2                                (1 << 20)
+#define OMAP2420_EN_I2C2_MASK                           (1 << 20)
 #define OMAP2420_EN_I2C1_SHIFT                          19
-#define OMAP2420_EN_I2C1                                (1 << 19)
+#define OMAP2420_EN_I2C1_MASK                           (1 << 19)
 
 /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
 #define OMAP2430_EN_MCBSP5_SHIFT                        5
-#define OMAP2430_EN_MCBSP5                              (1 << 5)
+#define OMAP2430_EN_MCBSP5_MASK                         (1 << 5)
 #define OMAP2430_EN_MCBSP4_SHIFT                        4
-#define OMAP2430_EN_MCBSP4                              (1 << 4)
+#define OMAP2430_EN_MCBSP4_MASK                         (1 << 4)
 #define OMAP2430_EN_MCBSP3_SHIFT                        3
-#define OMAP2430_EN_MCBSP3                              (1 << 3)
+#define OMAP2430_EN_MCBSP3_MASK                         (1 << 3)
 #define OMAP24XX_EN_SSI_SHIFT                           1
-#define OMAP24XX_EN_SSI                                 (1 << 1)
+#define OMAP24XX_EN_SSI_MASK                            (1 << 1)
 
 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
 #define OMAP24XX_EN_MPU_WDT_SHIFT                       3
-#define OMAP24XX_EN_MPU_WDT                             (1 << 3)
+#define OMAP24XX_EN_MPU_WDT_MASK                        (1 << 3)
 
 /* Bits specific to each register */
 
 /* CM_IDLEST_MPU */
 /* 2430 only */
-#define OMAP2430_ST_MPU                                 (1 << 0)
+#define OMAP2430_ST_MPU_MASK                            (1 << 0)
 
 /* CM_CLKSEL_MPU */
 #define OMAP24XX_CLKSEL_MPU_SHIFT                       0
@@ -68,46 +68,46 @@
 
 /* CM_FCLKEN1_CORE specific bits*/
 #define OMAP24XX_EN_TV_SHIFT                            2
-#define OMAP24XX_EN_TV                                  (1 << 2)
+#define OMAP24XX_EN_TV_MASK                             (1 << 2)
 #define OMAP24XX_EN_DSS2_SHIFT                          1
-#define OMAP24XX_EN_DSS2                                (1 << 1)
+#define OMAP24XX_EN_DSS2_MASK                           (1 << 1)
 #define OMAP24XX_EN_DSS1_SHIFT                          0
-#define OMAP24XX_EN_DSS1                                (1 << 0)
+#define OMAP24XX_EN_DSS1_MASK                           (1 << 0)
 
 /* CM_FCLKEN2_CORE specific bits */
 #define OMAP2430_EN_I2CHS2_SHIFT                        20
-#define OMAP2430_EN_I2CHS2                              (1 << 20)
+#define OMAP2430_EN_I2CHS2_MASK                         (1 << 20)
 #define OMAP2430_EN_I2CHS1_SHIFT                        19
-#define OMAP2430_EN_I2CHS1                              (1 << 19)
+#define OMAP2430_EN_I2CHS1_MASK                         (1 << 19)
 #define OMAP2430_EN_MMCHSDB2_SHIFT                      17
-#define OMAP2430_EN_MMCHSDB2                            (1 << 17)
+#define OMAP2430_EN_MMCHSDB2_MASK                       (1 << 17)
 #define OMAP2430_EN_MMCHSDB1_SHIFT                      16
-#define OMAP2430_EN_MMCHSDB1                            (1 << 16)
+#define OMAP2430_EN_MMCHSDB1_MASK                       (1 << 16)
 
 /* CM_ICLKEN1_CORE specific bits */
 #define OMAP24XX_EN_MAILBOXES_SHIFT                     30
-#define OMAP24XX_EN_MAILBOXES                           (1 << 30)
+#define OMAP24XX_EN_MAILBOXES_MASK                      (1 << 30)
 #define OMAP24XX_EN_DSS_SHIFT                           0
-#define OMAP24XX_EN_DSS                                 (1 << 0)
+#define OMAP24XX_EN_DSS_MASK                            (1 << 0)
 
 /* CM_ICLKEN2_CORE specific bits */
 
 /* CM_ICLKEN3_CORE */
 /* 2430 only */
 #define OMAP2430_EN_SDRC_SHIFT                          2
-#define OMAP2430_EN_SDRC                                (1 << 2)
+#define OMAP2430_EN_SDRC_MASK                           (1 << 2)
 
 /* CM_ICLKEN4_CORE */
 #define OMAP24XX_EN_PKA_SHIFT                           4
-#define OMAP24XX_EN_PKA                                 (1 << 4)
+#define OMAP24XX_EN_PKA_MASK                            (1 << 4)
 #define OMAP24XX_EN_AES_SHIFT                           3
-#define OMAP24XX_EN_AES                                 (1 << 3)
+#define OMAP24XX_EN_AES_MASK                            (1 << 3)
 #define OMAP24XX_EN_RNG_SHIFT                           2
-#define OMAP24XX_EN_RNG                                 (1 << 2)
+#define OMAP24XX_EN_RNG_MASK                            (1 << 2)
 #define OMAP24XX_EN_SHA_SHIFT                           1
-#define OMAP24XX_EN_SHA                                 (1 << 1)
+#define OMAP24XX_EN_SHA_MASK                            (1 << 1)
 #define OMAP24XX_EN_DES_SHIFT                           0
-#define OMAP24XX_EN_DES                                 (1 << 0)
+#define OMAP24XX_EN_DES_MASK                            (1 << 0)
 
 /* CM_IDLEST1_CORE specific bits */
 #define OMAP24XX_ST_MAILBOXES_SHIFT                     30
@@ -138,9 +138,9 @@
 /* CM_IDLEST2_CORE */
 #define OMAP2430_ST_MCBSP5_SHIFT                        5
 #define OMAP2430_ST_MCBSP5_MASK                         (1 << 5)
-#define OMAP2430_ST_MCBSP4_SHIFT                                4
+#define OMAP2430_ST_MCBSP4_SHIFT                        4
 #define OMAP2430_ST_MCBSP4_MASK                         (1 << 4)
-#define OMAP2430_ST_MCBSP3_SHIFT                                3
+#define OMAP2430_ST_MCBSP3_SHIFT                        3
 #define OMAP2430_ST_MCBSP3_MASK                         (1 << 3)
 #define OMAP24XX_ST_SSI_SHIFT                           1
 #define OMAP24XX_ST_SSI_MASK                            (1 << 1)
@@ -162,62 +162,62 @@
 #define OMAP24XX_ST_DES_MASK                            (1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
-#define OMAP24XX_AUTO_CAM                               (1 << 31)
-#define OMAP24XX_AUTO_MAILBOXES                         (1 << 30)
-#define OMAP24XX_AUTO_WDT4                              (1 << 29)
-#define OMAP2420_AUTO_WDT3                              (1 << 28)
-#define OMAP24XX_AUTO_MSPRO                             (1 << 27)
-#define OMAP2420_AUTO_MMC                               (1 << 26)
-#define OMAP24XX_AUTO_FAC                               (1 << 25)
-#define OMAP2420_AUTO_EAC                               (1 << 24)
-#define OMAP24XX_AUTO_HDQ                               (1 << 23)
-#define OMAP24XX_AUTO_UART2                             (1 << 22)
-#define OMAP24XX_AUTO_UART1                             (1 << 21)
-#define OMAP24XX_AUTO_I2C2                              (1 << 20)
-#define OMAP24XX_AUTO_I2C1                              (1 << 19)
-#define OMAP24XX_AUTO_MCSPI2                            (1 << 18)
-#define OMAP24XX_AUTO_MCSPI1                            (1 << 17)
-#define OMAP24XX_AUTO_MCBSP2                            (1 << 16)
-#define OMAP24XX_AUTO_MCBSP1                            (1 << 15)
-#define OMAP24XX_AUTO_GPT12                             (1 << 14)
-#define OMAP24XX_AUTO_GPT11                             (1 << 13)
-#define OMAP24XX_AUTO_GPT10                             (1 << 12)
-#define OMAP24XX_AUTO_GPT9                              (1 << 11)
-#define OMAP24XX_AUTO_GPT8                              (1 << 10)
-#define OMAP24XX_AUTO_GPT7                              (1 << 9)
-#define OMAP24XX_AUTO_GPT6                              (1 << 8)
-#define OMAP24XX_AUTO_GPT5                              (1 << 7)
-#define OMAP24XX_AUTO_GPT4                              (1 << 6)
-#define OMAP24XX_AUTO_GPT3                              (1 << 5)
-#define OMAP24XX_AUTO_GPT2                              (1 << 4)
-#define OMAP2420_AUTO_VLYNQ                             (1 << 3)
-#define OMAP24XX_AUTO_DSS                               (1 << 0)
+#define OMAP24XX_AUTO_CAM_MASK                          (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES_MASK                    (1 << 30)
+#define OMAP24XX_AUTO_WDT4_MASK                         (1 << 29)
+#define OMAP2420_AUTO_WDT3_MASK                         (1 << 28)
+#define OMAP24XX_AUTO_MSPRO_MASK                        (1 << 27)
+#define OMAP2420_AUTO_MMC_MASK                          (1 << 26)
+#define OMAP24XX_AUTO_FAC_MASK                          (1 << 25)
+#define OMAP2420_AUTO_EAC_MASK                          (1 << 24)
+#define OMAP24XX_AUTO_HDQ_MASK                          (1 << 23)
+#define OMAP24XX_AUTO_UART2_MASK                        (1 << 22)
+#define OMAP24XX_AUTO_UART1_MASK                        (1 << 21)
+#define OMAP24XX_AUTO_I2C2_MASK                         (1 << 20)
+#define OMAP24XX_AUTO_I2C1_MASK                         (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2_MASK                       (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1_MASK                       (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2_MASK                       (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1_MASK                       (1 << 15)
+#define OMAP24XX_AUTO_GPT12_MASK                        (1 << 14)
+#define OMAP24XX_AUTO_GPT11_MASK                        (1 << 13)
+#define OMAP24XX_AUTO_GPT10_MASK                        (1 << 12)
+#define OMAP24XX_AUTO_GPT9_MASK                         (1 << 11)
+#define OMAP24XX_AUTO_GPT8_MASK                         (1 << 10)
+#define OMAP24XX_AUTO_GPT7_MASK                         (1 << 9)
+#define OMAP24XX_AUTO_GPT6_MASK                         (1 << 8)
+#define OMAP24XX_AUTO_GPT5_MASK                         (1 << 7)
+#define OMAP24XX_AUTO_GPT4_MASK                         (1 << 6)
+#define OMAP24XX_AUTO_GPT3_MASK                         (1 << 5)
+#define OMAP24XX_AUTO_GPT2_MASK                         (1 << 4)
+#define OMAP2420_AUTO_VLYNQ_MASK                        (1 << 3)
+#define OMAP24XX_AUTO_DSS_MASK                          (1 << 0)
 
 /* CM_AUTOIDLE2_CORE */
-#define OMAP2430_AUTO_MDM_INTC                          (1 << 11)
-#define OMAP2430_AUTO_GPIO5                             (1 << 10)
-#define OMAP2430_AUTO_MCSPI3                            (1 << 9)
-#define OMAP2430_AUTO_MMCHS2                            (1 << 8)
-#define OMAP2430_AUTO_MMCHS1                            (1 << 7)
-#define OMAP2430_AUTO_USBHS                             (1 << 6)
-#define OMAP2430_AUTO_MCBSP5                            (1 << 5)
-#define OMAP2430_AUTO_MCBSP4                            (1 << 4)
-#define OMAP2430_AUTO_MCBSP3                            (1 << 3)
-#define OMAP24XX_AUTO_UART3                             (1 << 2)
-#define OMAP24XX_AUTO_SSI                               (1 << 1)
-#define OMAP24XX_AUTO_USB                               (1 << 0)
+#define OMAP2430_AUTO_MDM_INTC_MASK                     (1 << 11)
+#define OMAP2430_AUTO_GPIO5_MASK                        (1 << 10)
+#define OMAP2430_AUTO_MCSPI3_MASK                       (1 << 9)
+#define OMAP2430_AUTO_MMCHS2_MASK                       (1 << 8)
+#define OMAP2430_AUTO_MMCHS1_MASK                       (1 << 7)
+#define OMAP2430_AUTO_USBHS_MASK                        (1 << 6)
+#define OMAP2430_AUTO_MCBSP5_MASK                       (1 << 5)
+#define OMAP2430_AUTO_MCBSP4_MASK                       (1 << 4)
+#define OMAP2430_AUTO_MCBSP3_MASK                       (1 << 3)
+#define OMAP24XX_AUTO_UART3_MASK                        (1 << 2)
+#define OMAP24XX_AUTO_SSI_MASK                          (1 << 1)
+#define OMAP24XX_AUTO_USB_MASK                          (1 << 0)
 
 /* CM_AUTOIDLE3_CORE */
-#define OMAP24XX_AUTO_SDRC                              (1 << 2)
-#define OMAP24XX_AUTO_GPMC                              (1 << 1)
-#define OMAP24XX_AUTO_SDMA                              (1 << 0)
+#define OMAP24XX_AUTO_SDRC_MASK                         (1 << 2)
+#define OMAP24XX_AUTO_GPMC_MASK                         (1 << 1)
+#define OMAP24XX_AUTO_SDMA_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE4_CORE */
-#define OMAP24XX_AUTO_PKA                               (1 << 4)
-#define OMAP24XX_AUTO_AES                               (1 << 3)
-#define OMAP24XX_AUTO_RNG                               (1 << 2)
-#define OMAP24XX_AUTO_SHA                               (1 << 1)
-#define OMAP24XX_AUTO_DES                               (1 << 0)
+#define OMAP24XX_AUTO_PKA_MASK                          (1 << 4)
+#define OMAP24XX_AUTO_AES_MASK                          (1 << 3)
+#define OMAP24XX_AUTO_RNG_MASK                          (1 << 2)
+#define OMAP24XX_AUTO_SHA_MASK                          (1 << 1)
+#define OMAP24XX_AUTO_DES_MASK                          (1 << 0)
 
 /* CM_CLKSEL1_CORE */
 #define OMAP24XX_CLKSEL_USB_SHIFT                       25
@@ -269,9 +269,9 @@
 
 /* CM_FCLKEN_GFX */
 #define OMAP24XX_EN_3D_SHIFT                            2
-#define OMAP24XX_EN_3D                                  (1 << 2)
+#define OMAP24XX_EN_3D_MASK                             (1 << 2)
 #define OMAP24XX_EN_2D_SHIFT                            1
-#define OMAP24XX_EN_2D                                  (1 << 1)
+#define OMAP24XX_EN_2D_MASK                             (1 << 1)
 
 /* CM_ICLKEN_GFX specific bits */
 
@@ -287,13 +287,13 @@
 
 /* CM_ICLKEN_WKUP specific bits */
 #define OMAP2430_EN_ICR_SHIFT                           6
-#define OMAP2430_EN_ICR                                 (1 << 6)
+#define OMAP2430_EN_ICR_MASK                            (1 << 6)
 #define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
-#define OMAP24XX_EN_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_EN_OMAPCTRL_MASK                       (1 << 5)
 #define OMAP24XX_EN_WDT1_SHIFT                          4
-#define OMAP24XX_EN_WDT1                                (1 << 4)
+#define OMAP24XX_EN_WDT1_MASK                           (1 << 4)
 #define OMAP24XX_EN_32KSYNC_SHIFT                       1
-#define OMAP24XX_EN_32KSYNC                             (1 << 1)
+#define OMAP24XX_EN_32KSYNC_MASK                        (1 << 1)
 
 /* CM_IDLEST_WKUP specific bits */
 #define OMAP2430_ST_ICR_SHIFT                           6
@@ -308,12 +308,12 @@
 #define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
 
 /* CM_AUTOIDLE_WKUP */
-#define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
-#define OMAP24XX_AUTO_WDT1                              (1 << 4)
-#define OMAP24XX_AUTO_MPU_WDT                           (1 << 3)
-#define OMAP24XX_AUTO_GPIOS                             (1 << 2)
-#define OMAP24XX_AUTO_32KSYNC                           (1 << 1)
-#define OMAP24XX_AUTO_GPT1                              (1 << 0)
+#define OMAP24XX_AUTO_OMAPCTRL_MASK                     (1 << 5)
+#define OMAP24XX_AUTO_WDT1_MASK                         (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT_MASK                      (1 << 3)
+#define OMAP24XX_AUTO_GPIOS_MASK                        (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC_MASK                      (1 << 1)
+#define OMAP24XX_AUTO_GPT1_MASK                         (1 << 0)
 
 /* CM_CLKSEL_WKUP */
 #define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
@@ -328,12 +328,12 @@
 #define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
 
 /* CM_IDLEST_CKGEN */
-#define OMAP24XX_ST_54M_APLL                            (1 << 9)
-#define OMAP24XX_ST_96M_APLL                            (1 << 8)
-#define OMAP24XX_ST_54M_CLK                             (1 << 6)
-#define OMAP24XX_ST_12M_CLK                             (1 << 5)
-#define OMAP24XX_ST_48M_CLK                             (1 << 4)
-#define OMAP24XX_ST_96M_CLK                             (1 << 2)
+#define OMAP24XX_ST_54M_APLL_MASK                       (1 << 9)
+#define OMAP24XX_ST_96M_APLL_MASK                       (1 << 8)
+#define OMAP24XX_ST_54M_CLK_MASK                        (1 << 6)
+#define OMAP24XX_ST_12M_CLK_MASK                        (1 << 5)
+#define OMAP24XX_ST_48M_CLK_MASK                        (1 << 4)
+#define OMAP24XX_ST_96M_CLK_MASK                        (1 << 2)
 #define OMAP24XX_ST_CORE_CLK_SHIFT                      0
 #define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
 
@@ -355,11 +355,11 @@
 #define OMAP24XX_DPLL_DIV_SHIFT                         8
 #define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
 #define OMAP24XX_54M_SOURCE_SHIFT                       5
-#define OMAP24XX_54M_SOURCE                             (1 << 5)
+#define OMAP24XX_54M_SOURCE_MASK                        (1 << 5)
 #define OMAP2430_96M_SOURCE_SHIFT                       4
-#define OMAP2430_96M_SOURCE                             (1 << 4)
+#define OMAP2430_96M_SOURCE_MASK                        (1 << 4)
 #define OMAP24XX_48M_SOURCE_SHIFT                       3
-#define OMAP24XX_48M_SOURCE                             (1 << 3)
+#define OMAP24XX_48M_SOURCE_MASK                        (1 << 3)
 #define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
 #define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
 
@@ -369,29 +369,29 @@
 
 /* CM_FCLKEN_DSP */
 #define OMAP2420_EN_IVA_COP_SHIFT                       10
-#define OMAP2420_EN_IVA_COP                             (1 << 10)
+#define OMAP2420_EN_IVA_COP_MASK                        (1 << 10)
 #define OMAP2420_EN_IVA_MPU_SHIFT                       8
-#define OMAP2420_EN_IVA_MPU                             (1 << 8)
+#define OMAP2420_EN_IVA_MPU_MASK                        (1 << 8)
 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
-#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP                   (1 << 0)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK              (1 << 0)
 
 /* CM_ICLKEN_DSP */
 #define OMAP2420_EN_DSP_IPI_SHIFT                       1
-#define OMAP2420_EN_DSP_IPI                             (1 << 1)
+#define OMAP2420_EN_DSP_IPI_MASK                        (1 << 1)
 
 /* CM_IDLEST_DSP */
-#define OMAP2420_ST_IVA                                 (1 << 8)
-#define OMAP2420_ST_IPI                                 (1 << 1)
-#define OMAP24XX_ST_DSP                                 (1 << 0)
+#define OMAP2420_ST_IVA_MASK                            (1 << 8)
+#define OMAP2420_ST_IPI_MASK                            (1 << 1)
+#define OMAP24XX_ST_DSP_MASK                            (1 << 0)
 
 /* CM_AUTOIDLE_DSP */
-#define OMAP2420_AUTO_DSP_IPI                           (1 << 1)
+#define OMAP2420_AUTO_DSP_IPI_MASK                      (1 << 1)
 
 /* CM_CLKSEL_DSP */
-#define OMAP2420_SYNC_IVA                               (1 << 13)
+#define OMAP2420_SYNC_IVA_MASK                          (1 << 13)
 #define OMAP2420_CLKSEL_IVA_SHIFT                       8
 #define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
-#define OMAP24XX_SYNC_DSP                               (1 << 7)
+#define OMAP24XX_SYNC_DSP_MASK                          (1 << 7)
 #define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
 #define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
 #define OMAP24XX_CLKSEL_DSP_SHIFT                       0
@@ -406,24 +406,24 @@
 /* CM_FCLKEN_MDM */
 /* 2430 only */
 #define OMAP2430_EN_OSC_SHIFT                           1
-#define OMAP2430_EN_OSC                                 (1 << 1)
+#define OMAP2430_EN_OSC_MASK                            (1 << 1)
 
 /* CM_ICLKEN_MDM */
 /* 2430 only */
 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
-#define OMAP2430_CM_ICLKEN_MDM_EN_MDM                   (1 << 0)
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK              (1 << 0)
 
 /* CM_IDLEST_MDM specific bits */
 /* 2430 only */
 
 /* CM_AUTOIDLE_MDM */
 /* 2430 only */
-#define OMAP2430_AUTO_OSC                               (1 << 1)
-#define OMAP2430_AUTO_MDM                               (1 << 0)
+#define OMAP2430_AUTO_OSC_MASK                          (1 << 1)
+#define OMAP2430_AUTO_MDM_MASK                          (1 << 0)
 
 /* CM_CLKSEL_MDM */
 /* 2430 only */
-#define OMAP2430_SYNC_MDM                               (1 << 4)
+#define OMAP2430_SYNC_MDM_MASK                          (1 << 4)
 #define OMAP2430_CLKSEL_MDM_SHIFT                       0
 #define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
 
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index a3a3ca07e383..fe82b79d5f3b 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -21,15 +21,15 @@
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
 #define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
 #define OMAP3430ES2_EN_MMC3_SHIFT                       30
-#define OMAP3430_EN_MSPRO                               (1 << 23)
+#define OMAP3430_EN_MSPRO_MASK                          (1 << 23)
 #define OMAP3430_EN_MSPRO_SHIFT                         23
-#define OMAP3430_EN_HDQ                                 (1 << 22)
+#define OMAP3430_EN_HDQ_MASK                            (1 << 22)
 #define OMAP3430_EN_HDQ_SHIFT                           22
-#define OMAP3430ES1_EN_FSHOSTUSB                        (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_MASK                   (1 << 5)
 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
-#define OMAP3430ES1_EN_D2D                              (1 << 3)
+#define OMAP3430ES1_EN_D2D_MASK                         (1 << 3)
 #define OMAP3430ES1_EN_D2D_SHIFT                        3
-#define OMAP3430_EN_SSI                                 (1 << 0)
+#define OMAP3430_EN_SSI_MASK                            (1 << 0)
 #define OMAP3430_EN_SSI_SHIFT                           0
 
 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
@@ -37,19 +37,19 @@
 #define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
 
 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
-#define OMAP3430_EN_WDT2                                (1 << 5)
+#define OMAP3430_EN_WDT2_MASK                           (1 << 5)
 #define OMAP3430_EN_WDT2_SHIFT                          5
 
 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
-#define OMAP3430_EN_CAM                                 (1 << 0)
+#define OMAP3430_EN_CAM_MASK                            (1 << 0)
 #define OMAP3430_EN_CAM_SHIFT                           0
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
-#define OMAP3430_EN_WDT3                                (1 << 12)
+#define OMAP3430_EN_WDT3_MASK                           (1 << 12)
 #define OMAP3430_EN_WDT3_SHIFT                          12
 
 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
-#define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
+#define OMAP3430_OVERRIDE_ENABLE_MASK                   (1 << 19)
 
 
 /* Bits specific to each register */
@@ -69,7 +69,7 @@
 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
 
 /* CM_IDLEST_IVA2 */
-#define OMAP3430_ST_IVA2                                (1 << 0)
+#define OMAP3430_ST_IVA2_MASK                           (1 << 0)
 
 /* CM_IDLEST_PLL_IVA2 */
 #define OMAP3430_ST_IVA2_CLK_SHIFT                      0
@@ -114,7 +114,7 @@
 #define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
 
 /* CM_IDLEST_MPU */
-#define OMAP3430_ST_MPU                                 (1 << 0)
+#define OMAP3430_ST_MPU_MASK                            (1 << 0)
 
 /* CM_IDLEST_PLL_MPU */
 #define OMAP3430_ST_MPU_CLK_SHIFT                       0
@@ -145,50 +145,50 @@
 #define OMAP3430_CLKACTIVITY_MPU_MASK                   (1 << 0)
 
 /* CM_FCLKEN1_CORE specific bits */
-#define OMAP3430_EN_MODEM                               (1 << 31)
+#define OMAP3430_EN_MODEM_MASK                          (1 << 31)
 #define OMAP3430_EN_MODEM_SHIFT                         31
 
 /* CM_ICLKEN1_CORE specific bits */
-#define OMAP3430_EN_ICR                                 (1 << 29)
+#define OMAP3430_EN_ICR_MASK                            (1 << 29)
 #define OMAP3430_EN_ICR_SHIFT                           29
-#define OMAP3430_EN_AES2                                (1 << 28)
+#define OMAP3430_EN_AES2_MASK                           (1 << 28)
 #define OMAP3430_EN_AES2_SHIFT                          28
-#define OMAP3430_EN_SHA12                               (1 << 27)
+#define OMAP3430_EN_SHA12_MASK                          (1 << 27)
 #define OMAP3430_EN_SHA12_SHIFT                         27
-#define OMAP3430_EN_DES2                                (1 << 26)
+#define OMAP3430_EN_DES2_MASK                           (1 << 26)
 #define OMAP3430_EN_DES2_SHIFT                          26
-#define OMAP3430ES1_EN_FAC                              (1 << 8)
+#define OMAP3430ES1_EN_FAC_MASK                         (1 << 8)
 #define OMAP3430ES1_EN_FAC_SHIFT                        8
-#define OMAP3430_EN_MAILBOXES                           (1 << 7)
+#define OMAP3430_EN_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_EN_MAILBOXES_SHIFT                     7
-#define OMAP3430_EN_OMAPCTRL                            (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_MASK                       (1 << 6)
 #define OMAP3430_EN_OMAPCTRL_SHIFT                      6
-#define OMAP3430_EN_SAD2D                               (1 << 3)
+#define OMAP3430_EN_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_EN_SAD2D_SHIFT                         3
-#define OMAP3430_EN_SDRC                                (1 << 1)
+#define OMAP3430_EN_SDRC_MASK                           (1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT                          1
 
 /* AM35XX specific CM_ICLKEN1_CORE bits */
 #define AM35XX_EN_IPSS_MASK                             (1 << 4)
 #define AM35XX_EN_IPSS_SHIFT                            4
-#define AM35XX_EN_UART4_MASK                    (1 << 23)
+#define AM35XX_EN_UART4_MASK                            (1 << 23)
 #define AM35XX_EN_UART4_SHIFT                           23
 
 /* CM_ICLKEN2_CORE */
-#define OMAP3430_EN_PKA                                 (1 << 4)
+#define OMAP3430_EN_PKA_MASK                            (1 << 4)
 #define OMAP3430_EN_PKA_SHIFT                           4
-#define OMAP3430_EN_AES1                                (1 << 3)
+#define OMAP3430_EN_AES1_MASK                           (1 << 3)
 #define OMAP3430_EN_AES1_SHIFT                          3
-#define OMAP3430_EN_RNG                                 (1 << 2)
+#define OMAP3430_EN_RNG_MASK                            (1 << 2)
 #define OMAP3430_EN_RNG_SHIFT                           2
-#define OMAP3430_EN_SHA11                               (1 << 1)
+#define OMAP3430_EN_SHA11_MASK                          (1 << 1)
 #define OMAP3430_EN_SHA11_SHIFT                         1
-#define OMAP3430_EN_DES1                                (1 << 0)
+#define OMAP3430_EN_DES1_MASK                           (1 << 0)
 #define OMAP3430_EN_DES1_SHIFT                          0
 
 /* CM_ICLKEN3_CORE */
 #define OMAP3430_EN_MAD2D_SHIFT                         3
-#define OMAP3430_EN_MAD2D                               (1 << 3)
+#define OMAP3430_EN_MAD2D_MASK                          (1 << 3)
 
 /* CM_FCLKEN3_CORE specific bits */
 #define OMAP3430ES2_EN_TS_SHIFT                         1
@@ -249,79 +249,79 @@
 #define OMAP3430ES2_ST_CPEFUSE_MASK                     (1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
-#define OMAP3430_AUTO_MODEM                             (1 << 31)
+#define OMAP3430_AUTO_MODEM_MASK                        (1 << 31)
 #define OMAP3430_AUTO_MODEM_SHIFT                       31
-#define OMAP3430ES2_AUTO_MMC3                           (1 << 30)
+#define OMAP3430ES2_AUTO_MMC3_MASK                      (1 << 30)
 #define OMAP3430ES2_AUTO_MMC3_SHIFT                     30
-#define OMAP3430ES2_AUTO_ICR                            (1 << 29)
+#define OMAP3430ES2_AUTO_ICR_MASK                       (1 << 29)
 #define OMAP3430ES2_AUTO_ICR_SHIFT                      29
-#define OMAP3430_AUTO_AES2                              (1 << 28)
+#define OMAP3430_AUTO_AES2_MASK                         (1 << 28)
 #define OMAP3430_AUTO_AES2_SHIFT                        28
-#define OMAP3430_AUTO_SHA12                             (1 << 27)
+#define OMAP3430_AUTO_SHA12_MASK                        (1 << 27)
 #define OMAP3430_AUTO_SHA12_SHIFT                       27
-#define OMAP3430_AUTO_DES2                              (1 << 26)
+#define OMAP3430_AUTO_DES2_MASK                         (1 << 26)
 #define OMAP3430_AUTO_DES2_SHIFT                        26
-#define OMAP3430_AUTO_MMC2                              (1 << 25)
+#define OMAP3430_AUTO_MMC2_MASK                         (1 << 25)
 #define OMAP3430_AUTO_MMC2_SHIFT                        25
-#define OMAP3430_AUTO_MMC1                              (1 << 24)
+#define OMAP3430_AUTO_MMC1_MASK                         (1 << 24)
 #define OMAP3430_AUTO_MMC1_SHIFT                        24
-#define OMAP3430_AUTO_MSPRO                             (1 << 23)
+#define OMAP3430_AUTO_MSPRO_MASK                        (1 << 23)
 #define OMAP3430_AUTO_MSPRO_SHIFT                       23
-#define OMAP3430_AUTO_HDQ                               (1 << 22)
+#define OMAP3430_AUTO_HDQ_MASK                          (1 << 22)
 #define OMAP3430_AUTO_HDQ_SHIFT                         22
-#define OMAP3430_AUTO_MCSPI4                            (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_MASK                       (1 << 21)
 #define OMAP3430_AUTO_MCSPI4_SHIFT                      21
-#define OMAP3430_AUTO_MCSPI3                            (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_MASK                       (1 << 20)
 #define OMAP3430_AUTO_MCSPI3_SHIFT                      20
-#define OMAP3430_AUTO_MCSPI2                            (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_MASK                       (1 << 19)
 #define OMAP3430_AUTO_MCSPI2_SHIFT                      19
-#define OMAP3430_AUTO_MCSPI1                            (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_MASK                       (1 << 18)
 #define OMAP3430_AUTO_MCSPI1_SHIFT                      18
-#define OMAP3430_AUTO_I2C3                              (1 << 17)
+#define OMAP3430_AUTO_I2C3_MASK                         (1 << 17)
 #define OMAP3430_AUTO_I2C3_SHIFT                        17
-#define OMAP3430_AUTO_I2C2                              (1 << 16)
+#define OMAP3430_AUTO_I2C2_MASK                         (1 << 16)
 #define OMAP3430_AUTO_I2C2_SHIFT                        16
-#define OMAP3430_AUTO_I2C1                              (1 << 15)
+#define OMAP3430_AUTO_I2C1_MASK                         (1 << 15)
 #define OMAP3430_AUTO_I2C1_SHIFT                        15
-#define OMAP3430_AUTO_UART2                             (1 << 14)
+#define OMAP3430_AUTO_UART2_MASK                        (1 << 14)
 #define OMAP3430_AUTO_UART2_SHIFT                       14
-#define OMAP3430_AUTO_UART1                             (1 << 13)
+#define OMAP3430_AUTO_UART1_MASK                        (1 << 13)
 #define OMAP3430_AUTO_UART1_SHIFT                       13
-#define OMAP3430_AUTO_GPT11                             (1 << 12)
+#define OMAP3430_AUTO_GPT11_MASK                        (1 << 12)
 #define OMAP3430_AUTO_GPT11_SHIFT                       12
-#define OMAP3430_AUTO_GPT10                             (1 << 11)
+#define OMAP3430_AUTO_GPT10_MASK                        (1 << 11)
 #define OMAP3430_AUTO_GPT10_SHIFT                       11
-#define OMAP3430_AUTO_MCBSP5                            (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_MASK                       (1 << 10)
 #define OMAP3430_AUTO_MCBSP5_SHIFT                      10
-#define OMAP3430_AUTO_MCBSP1                            (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_MASK                       (1 << 9)
 #define OMAP3430_AUTO_MCBSP1_SHIFT                      9
-#define OMAP3430ES1_AUTO_FAC                            (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_MASK                       (1 << 8)
 #define OMAP3430ES1_AUTO_FAC_SHIFT                      8
-#define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_MASK                    (1 << 7)
 #define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
-#define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_MASK                     (1 << 6)
 #define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
-#define OMAP3430ES1_AUTO_FSHOSTUSB                      (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK                 (1 << 5)
 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
-#define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_MASK                     (1 << 4)
 #define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
-#define OMAP3430ES1_AUTO_D2D                            (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_MASK                       (1 << 3)
 #define OMAP3430ES1_AUTO_D2D_SHIFT                      3
-#define OMAP3430_AUTO_SAD2D                             (1 << 3)
+#define OMAP3430_AUTO_SAD2D_MASK                        (1 << 3)
 #define OMAP3430_AUTO_SAD2D_SHIFT                       3
-#define OMAP3430_AUTO_SSI                               (1 << 0)
+#define OMAP3430_AUTO_SSI_MASK                          (1 << 0)
 #define OMAP3430_AUTO_SSI_SHIFT                         0
 
 /* CM_AUTOIDLE2_CORE */
-#define OMAP3430_AUTO_PKA                               (1 << 4)
+#define OMAP3430_AUTO_PKA_MASK                          (1 << 4)
 #define OMAP3430_AUTO_PKA_SHIFT                         4
-#define OMAP3430_AUTO_AES1                              (1 << 3)
+#define OMAP3430_AUTO_AES1_MASK                         (1 << 3)
 #define OMAP3430_AUTO_AES1_SHIFT                        3
-#define OMAP3430_AUTO_RNG                               (1 << 2)
+#define OMAP3430_AUTO_RNG_MASK                          (1 << 2)
 #define OMAP3430_AUTO_RNG_SHIFT                         2
-#define OMAP3430_AUTO_SHA11                             (1 << 1)
+#define OMAP3430_AUTO_SHA11_MASK                        (1 << 1)
 #define OMAP3430_AUTO_SHA11_SHIFT                       1
-#define OMAP3430_AUTO_DES1                              (1 << 0)
+#define OMAP3430_AUTO_DES1_MASK                         (1 << 0)
 #define OMAP3430_AUTO_DES1_SHIFT                        0
 
 /* CM_AUTOIDLE3_CORE */
@@ -331,7 +331,7 @@
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
 #define OMAP3430_AUTO_MAD2D_SHIFT                       3
-#define OMAP3430_AUTO_MAD2D                             (1 << 3)
+#define OMAP3430_AUTO_MAD2D_MASK                        (1 << 3)
 
 /* CM_CLKSEL_CORE */
 #define OMAP3430_CLKSEL_SSI_SHIFT                       8
@@ -366,9 +366,9 @@
 #define OMAP3430_CLKACTIVITY_L3_MASK                    (1 << 0)
 
 /* CM_FCLKEN_GFX */
-#define OMAP3430ES1_EN_3D                               (1 << 2)
+#define OMAP3430ES1_EN_3D_MASK                          (1 << 2)
 #define OMAP3430ES1_EN_3D_SHIFT                         2
-#define OMAP3430ES1_EN_2D                               (1 << 1)
+#define OMAP3430ES1_EN_2D_MASK                          (1 << 1)
 #define OMAP3430ES1_EN_2D_SHIFT                         1
 
 /* CM_ICLKEN_GFX specific bits */
@@ -416,9 +416,9 @@
 #define OMAP3430ES2_EN_USIMOCP_MASK                     (1 << 9)
 
 /* CM_ICLKEN_WKUP specific bits */
-#define OMAP3430_EN_WDT1                                (1 << 4)
+#define OMAP3430_EN_WDT1_MASK                           (1 << 4)
 #define OMAP3430_EN_WDT1_SHIFT                          4
-#define OMAP3430_EN_32KSYNC                             (1 << 2)
+#define OMAP3430_EN_32KSYNC_MASK                        (1 << 2)
 #define OMAP3430_EN_32KSYNC_SHIFT                       2
 
 /* CM_IDLEST_WKUP specific bits */
@@ -432,19 +432,19 @@
 #define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
 
 /* CM_AUTOIDLE_WKUP */
-#define OMAP3430ES2_AUTO_USIMOCP                                (1 << 9)
+#define OMAP3430ES2_AUTO_USIMOCP_MASK                   (1 << 9)
 #define OMAP3430ES2_AUTO_USIMOCP_SHIFT                  9
-#define OMAP3430_AUTO_WDT2                              (1 << 5)
+#define OMAP3430_AUTO_WDT2_MASK                         (1 << 5)
 #define OMAP3430_AUTO_WDT2_SHIFT                        5
-#define OMAP3430_AUTO_WDT1                              (1 << 4)
+#define OMAP3430_AUTO_WDT1_MASK                         (1 << 4)
 #define OMAP3430_AUTO_WDT1_SHIFT                        4
-#define OMAP3430_AUTO_GPIO1                             (1 << 3)
+#define OMAP3430_AUTO_GPIO1_MASK                        (1 << 3)
 #define OMAP3430_AUTO_GPIO1_SHIFT                       3
-#define OMAP3430_AUTO_32KSYNC                           (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_MASK                      (1 << 2)
 #define OMAP3430_AUTO_32KSYNC_SHIFT                     2
-#define OMAP3430_AUTO_GPT12                             (1 << 1)
+#define OMAP3430_AUTO_GPT12_MASK                        (1 << 1)
 #define OMAP3430_AUTO_GPT12_SHIFT                       1
-#define OMAP3430_AUTO_GPT1                              (1 << 0)
+#define OMAP3430_AUTO_GPT1_MASK                         (1 << 0)
 #define OMAP3430_AUTO_GPT1_SHIFT                        0
 
 /* CM_CLKSEL_WKUP */
@@ -479,7 +479,7 @@
 #define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
 
 /* CM_CLKEN2_PLL */
-#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT                10
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT        10
 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT          4
 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
@@ -488,10 +488,10 @@
 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                (0x7 << 0)
 
 /* CM_IDLEST_CKGEN */
-#define OMAP3430_ST_54M_CLK                             (1 << 5)
-#define OMAP3430_ST_12M_CLK                             (1 << 4)
-#define OMAP3430_ST_48M_CLK                             (1 << 3)
-#define OMAP3430_ST_96M_CLK                             (1 << 2)
+#define OMAP3430_ST_54M_CLK_MASK                        (1 << 5)
+#define OMAP3430_ST_12M_CLK_MASK                        (1 << 4)
+#define OMAP3430_ST_48M_CLK_MASK                        (1 << 3)
+#define OMAP3430_ST_96M_CLK_MASK                        (1 << 2)
 #define OMAP3430_ST_PERIPH_CLK_SHIFT                    1
 #define OMAP3430_ST_PERIPH_CLK_MASK                     (1 << 1)
 #define OMAP3430_ST_CORE_CLK_SHIFT                      0
@@ -558,22 +558,22 @@
 
 /* CM_CLKOUT_CTRL */
 #define OMAP3430_CLKOUT2_EN_SHIFT                       7
-#define OMAP3430_CLKOUT2_EN                             (1 << 7)
+#define OMAP3430_CLKOUT2_EN_MASK                        (1 << 7)
 #define OMAP3430_CLKOUT2_DIV_SHIFT                      3
 #define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
 #define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
 #define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
 
 /* CM_FCLKEN_DSS */
-#define OMAP3430_EN_TV                                  (1 << 2)
+#define OMAP3430_EN_TV_MASK                             (1 << 2)
 #define OMAP3430_EN_TV_SHIFT                            2
-#define OMAP3430_EN_DSS2                                (1 << 1)
+#define OMAP3430_EN_DSS2_MASK                           (1 << 1)
 #define OMAP3430_EN_DSS2_SHIFT                          1
-#define OMAP3430_EN_DSS1                                (1 << 0)
+#define OMAP3430_EN_DSS1_MASK                           (1 << 0)
 #define OMAP3430_EN_DSS1_SHIFT                          0
 
 /* CM_ICLKEN_DSS */
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK              (1 << 0)
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
 
 /* CM_IDLEST_DSS */
@@ -585,7 +585,7 @@
 #define OMAP3430ES1_ST_DSS_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_DSS */
-#define OMAP3430_AUTO_DSS                               (1 << 0)
+#define OMAP3430_AUTO_DSS_MASK                          (1 << 0)
 #define OMAP3430_AUTO_DSS_SHIFT                         0
 
 /* CM_CLKSEL_DSS */
@@ -607,16 +607,16 @@
 #define OMAP3430_CLKACTIVITY_DSS_MASK                   (1 << 0)
 
 /* CM_FCLKEN_CAM specific bits */
-#define OMAP3430_EN_CSI2                                (1 << 1)
+#define OMAP3430_EN_CSI2_MASK                           (1 << 1)
 #define OMAP3430_EN_CSI2_SHIFT                          1
 
 /* CM_ICLKEN_CAM specific bits */
 
 /* CM_IDLEST_CAM */
-#define OMAP3430_ST_CAM                                 (1 << 0)
+#define OMAP3430_ST_CAM_MASK                            (1 << 0)
 
 /* CM_AUTOIDLE_CAM */
-#define OMAP3430_AUTO_CAM                               (1 << 0)
+#define OMAP3430_AUTO_CAM_MASK                          (1 << 0)
 #define OMAP3430_AUTO_CAM_SHIFT                         0
 
 /* CM_CLKSEL_CAM */
@@ -649,41 +649,41 @@
 #define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_PER */
-#define OMAP3430_AUTO_GPIO6                             (1 << 17)
+#define OMAP3430_AUTO_GPIO6_MASK                        (1 << 17)
 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
-#define OMAP3430_AUTO_GPIO5                             (1 << 16)
+#define OMAP3430_AUTO_GPIO5_MASK                        (1 << 16)
 #define OMAP3430_AUTO_GPIO5_SHIFT                       16
-#define OMAP3430_AUTO_GPIO4                             (1 << 15)
+#define OMAP3430_AUTO_GPIO4_MASK                        (1 << 15)
 #define OMAP3430_AUTO_GPIO4_SHIFT                       15
-#define OMAP3430_AUTO_GPIO3                             (1 << 14)
+#define OMAP3430_AUTO_GPIO3_MASK                        (1 << 14)
 #define OMAP3430_AUTO_GPIO3_SHIFT                       14
-#define OMAP3430_AUTO_GPIO2                             (1 << 13)
+#define OMAP3430_AUTO_GPIO2_MASK                        (1 << 13)
 #define OMAP3430_AUTO_GPIO2_SHIFT                       13
-#define OMAP3430_AUTO_WDT3                              (1 << 12)
+#define OMAP3430_AUTO_WDT3_MASK                         (1 << 12)
 #define OMAP3430_AUTO_WDT3_SHIFT                        12
-#define OMAP3430_AUTO_UART3                             (1 << 11)
+#define OMAP3430_AUTO_UART3_MASK                        (1 << 11)
 #define OMAP3430_AUTO_UART3_SHIFT                       11
-#define OMAP3430_AUTO_GPT9                              (1 << 10)
+#define OMAP3430_AUTO_GPT9_MASK                         (1 << 10)
 #define OMAP3430_AUTO_GPT9_SHIFT                        10
-#define OMAP3430_AUTO_GPT8                              (1 << 9)
+#define OMAP3430_AUTO_GPT8_MASK                         (1 << 9)
 #define OMAP3430_AUTO_GPT8_SHIFT                        9
-#define OMAP3430_AUTO_GPT7                              (1 << 8)
+#define OMAP3430_AUTO_GPT7_MASK                         (1 << 8)
 #define OMAP3430_AUTO_GPT7_SHIFT                        8
-#define OMAP3430_AUTO_GPT6                              (1 << 7)
+#define OMAP3430_AUTO_GPT6_MASK                         (1 << 7)
 #define OMAP3430_AUTO_GPT6_SHIFT                        7
-#define OMAP3430_AUTO_GPT5                              (1 << 6)
+#define OMAP3430_AUTO_GPT5_MASK                         (1 << 6)
 #define OMAP3430_AUTO_GPT5_SHIFT                        6
-#define OMAP3430_AUTO_GPT4                              (1 << 5)
+#define OMAP3430_AUTO_GPT4_MASK                         (1 << 5)
 #define OMAP3430_AUTO_GPT4_SHIFT                        5
-#define OMAP3430_AUTO_GPT3                              (1 << 4)
+#define OMAP3430_AUTO_GPT3_MASK                         (1 << 4)
 #define OMAP3430_AUTO_GPT3_SHIFT                        4
-#define OMAP3430_AUTO_GPT2                              (1 << 3)
+#define OMAP3430_AUTO_GPT2_MASK                         (1 << 3)
 #define OMAP3430_AUTO_GPT2_SHIFT                        3
-#define OMAP3430_AUTO_MCBSP4                            (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_MASK                       (1 << 2)
 #define OMAP3430_AUTO_MCBSP4_SHIFT                      2
-#define OMAP3430_AUTO_MCBSP3                            (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_MASK                       (1 << 1)
 #define OMAP3430_AUTO_MCBSP3_SHIFT                      1
-#define OMAP3430_AUTO_MCBSP2                            (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_MASK                       (1 << 0)
 #define OMAP3430_AUTO_MCBSP2_SHIFT                      0
 
 /* CM_CLKSEL_PER */
@@ -705,7 +705,7 @@
 #define OMAP3430_CLKSEL_GPT2_SHIFT                      0
 
 /* CM_SLEEPDEP_PER specific bits */
-#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK           (1 << 2)
 
 /* CM_CLKSTCTRL_PER */
 #define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
@@ -755,10 +755,10 @@
 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
 
 /* CM_POLCTRL */
-#define OMAP3430_CLKOUT2_POL                            (1 << 0)
+#define OMAP3430_CLKOUT2_POL_MASK                       (1 << 0)
 
 /* CM_IDLEST_NEON */
-#define OMAP3430_ST_NEON                                (1 << 0)
+#define OMAP3430_ST_NEON_MASK                           (1 << 0)
 
 /* CM_CLKSTCTRL_NEON */
 #define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
index 58e4a1c557d8..2d83565d2be2 100644
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm.c
@@ -27,9 +27,6 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
-#define MAX_MODULE_READY_TIME           20000
-
 static const u8 cm_idlest_offs[] = {
         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
 };
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 94728b1ee3c4..a02ca30423dc 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -112,7 +112,7 @@ extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 
 extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
                                       u8 idlest_shift);
-extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs);
+extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
 
 static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
@@ -134,13 +134,23 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 
 /* CM_ICLKEN_GFX */
 #define OMAP_EN_GFX_SHIFT                               0
-#define OMAP_EN_GFX                                     (1 << 0)
+#define OMAP_EN_GFX_MASK                                (1 << 0)
 
 /* CM_IDLEST_GFX */
-#define OMAP_ST_GFX                                     (1 << 0)
+#define OMAP_ST_GFX_MASK                                (1 << 0)
+
 
 /* CM_IDLEST indicator */
 #define OMAP24XX_CM_IDLEST_VAL          0
 #define OMAP34XX_CM_IDLEST_VAL          1
 
+/*
+ * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
+ * PRCM to request that a module exit the inactive state in the case of
+ * OMAP2 & 3.
+ * In the case of OMAP4 this is the max duration in microseconds for the
+ * module to reach the functionnal state from an inactive state.
+ */
+#define MAX_MODULE_READY_TIME           2000
+
 #endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index c575b9b0c041..336d94889e5b 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx CM1 & CM2 instance offset macros
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -25,334 +25,557 @@
 
 /* CM1 */
 
-
 /* CM1.OCP_SOCKET_CM1 register offsets */
+#define OMAP4_REVISION_CM1_OFFSET                       0x0000
 #define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
 
 /* CM1.CKGEN_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
 #define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
+#define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
 #define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
+#define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
 #define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
 #define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
+#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
 #define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
 #define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
 #define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
 #define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
 #define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
 #define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
 #define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
 #define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
+#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
+#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
 #define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
+#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
 #define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
+#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
+#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
 #define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
+#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
 #define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
+#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
 #define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
+#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
 #define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
+#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
 #define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
+#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
+#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
 #define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
+#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
 #define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
+#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
 #define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
+#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
 #define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
+#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
 #define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
+#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
 #define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
+#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
+#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
 #define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
+#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
 #define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
+#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
 #define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
+#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
+#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
+#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
+#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
 #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
+#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
+#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
+#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
 #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
+#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
+#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
 #define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
+#define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
 #define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
 
 /* CM1.MPU_CM1 register offsets */
+#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
 #define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
+#define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
 #define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
+#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
 #define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
+#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
 #define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
 
 /* CM1.TESLA_CM1 register offsets */
+#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
 #define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
+#define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
 #define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
+#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
 #define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
+#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
 
 /* CM1.ABE_CM1 register offsets */
+#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
 #define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
+#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
+#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
 #define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
+#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
 #define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
+#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
+#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
+#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
+#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
+#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
+#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
+#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
+#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
+#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
+#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
+#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
 
-/* CM1.RESTORE_CM1 register offsets */
-#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
-#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
-#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
-#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
-#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
-#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
-#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
-#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
-#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
-#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
-
 /* CM2 */
 
-
 /* CM2.OCP_SOCKET_CM2 register offsets */
+#define OMAP4_REVISION_CM2_OFFSET                       0x0000
 #define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
 #define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
 
 /* CM2.CKGEN_CM2 register offsets */
+#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
 #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
+#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
 #define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
+#define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
 #define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
+#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
 #define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
+#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
 #define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
+#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
 #define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
+#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
 #define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
+#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
 #define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
+#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
 #define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
+#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
 #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
+#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
 #define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
+#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
 #define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
+#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
 #define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
+#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
 #define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
+#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
 #define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
+#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
 #define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
+#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
 #define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
+#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
 #define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
+#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
 #define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
+#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
 #define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
+#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
 #define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
+#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
 #define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
+#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET           0x0070
 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
+#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
 #define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
+#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
 #define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
+#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
 #define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
+#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
 #define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
+#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
 #define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET         0x00ac
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
+#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
+#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
 #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
+#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
 #define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
+#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
 #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
+#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
 #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
+#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET      0x00ec
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
 
 /* CM2.ALWAYS_ON_CM2 register offsets */
+#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
 #define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
+#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
+#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
 #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
 
 /* CM2.CORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
 #define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
+#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
 #define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
+#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
 #define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
+#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
 #define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
+#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
 #define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
+#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
 #define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
+#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
 #define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
+#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
 #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
+#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
 #define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
+#define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
 #define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
+#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
 #define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
+#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
 #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
+#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
 #define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
+#define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
 #define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
+#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
 #define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
+#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
 #define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
 #define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
+#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
 #define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
+#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
 #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
+#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
 #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
+#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
 #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
+#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
 #define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
+#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
 #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
+#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
 #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
+#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
 #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
+#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
 #define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
+#define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
 #define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
+#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
 #define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
+#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
+#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET           0x0528
 #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
+#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
 #define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
 #define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
+#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
 #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
+#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
 #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
+#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
 #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
+#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
 #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
+#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
 #define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
 #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
 #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
 #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
 
 /* CM2.IVAHD_CM2 register offsets */
+#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
 #define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
+#define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
 #define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
+#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
 #define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
+#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
 #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
+#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
 #define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
 
 /* CM2.CAM_CM2 register offsets */
+#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
 #define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
+#define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
 #define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
+#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
 #define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
+#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
 #define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
+#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
 #define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
 
 /* CM2.DSS_CM2 register offsets */
+#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
 #define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
+#define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
 #define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
+#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
 #define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
+#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
 #define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
+#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
 #define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
 
 /* CM2.GFX_CM2 register offsets */
+#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
 #define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
+#define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
 #define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
+#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
 #define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
+#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
 #define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
 
 /* CM2.L3INIT_CM2 register offsets */
+#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
 #define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
+#define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
 #define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
+#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
 #define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
+#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
 #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
+#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
 #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
+#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
 #define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
+#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
 #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
 #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
+#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
 #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
 #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
+#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
 #define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
+#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
 #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
+#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
 #define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
+#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
 #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
+#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
 #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
+#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
 #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
+#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
 #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
+#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
 #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
+#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
 #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
+#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
 #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
 
 /* CM2.L4PER_CM2 register offsets */
+#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
 #define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
+#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
 #define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
+#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
 #define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
+#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
 #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
+#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
 #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
+#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
 #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
+#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
 #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
+#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
 #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
+#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
 #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
+#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
 #define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
 #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
 #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
 #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
 #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
 #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
+#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
 #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
+#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
 #define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
+#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
 #define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
+#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
 #define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
+#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
 #define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
+#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
 #define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
+#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
 #define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
+#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
 #define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
+#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
 #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
+#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
 #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
+#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
 #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
+#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
 #define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
+#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
 #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
+#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
 #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
+#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
 #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
+#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
 #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
+#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
 #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
+#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
 #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
+#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
 #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
+#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
 #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
+#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
 #define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
+#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
 #define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
+#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
 #define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
+#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
 #define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
+#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
 #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
+#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
 #define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
+#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
 #define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
+#define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
 #define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
+#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
 #define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
+#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
 #define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
+#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
 #define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
+#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
 #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
+#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
 #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
+#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
 #define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
+#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
 #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
+#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
 #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
 
 /* CM2.CEFUSE_CM2 register offsets */
+#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
 #define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
+#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
-
-/* CM2.RESTORE_CM2 register offsets */
-#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
-#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
-#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
-#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
-#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
-#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
-#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
 #endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index 4af76bb1003a..b101091e95d6 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -21,35 +21,41 @@
 
 #include <asm/atomic.h>
 
-#include "cm.h"
-
-/* XXX move this to cm.h */
-/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
-#define MAX_MODULE_READY_TIME                   20000
+#include <plat/common.h>
 
-/*
- * OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the
- * CM_CLKCTRL register.
- */
-#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK       (0x2 << 16)
-
-/*
- * OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and
- * the PRCM module offset address (from the CM module base) in bits 15-0.
- */
-#define OMAP4_PRCM_MOD_CM_ID_SHIFT              16
-#define OMAP4_PRCM_MOD_OFFS_MASK                0xffff
+#include "cm.h"
+#include "cm-regbits-44xx.h"
 
 /**
- * omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby
- * @prcm_mod: PRCM module offset (XXX example)
- * @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example)
+ * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @clkctrl_reg: CLKCTRL module address
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ *
+ * Module idle state:
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
  *
- * XXX document
+ * TODO: Need to handle module accessible in idle state
  */
-int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs)
+int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
 {
-        /* FIXME: Add clock manager related code */
-        return 0;
+        int i = 0;
+
+        if (!clkctrl_reg)
+                return 0;
+
+        omap_test_timeout(((__raw_readl(clkctrl_reg) &
+                            OMAP4430_IDLEST_MASK) == 0),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
 
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 43f8a33655d4..a8d20eef2306 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -194,11 +194,12 @@ void omap3_clear_scratchpad_contents(void)
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
         if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
-                OMAP3430_GLOBAL_COLD_RST) {
+            OMAP3430_GLOBAL_COLD_RST_MASK) {
                 for ( ; offset <= max_offset; offset += 0x4)
                         __raw_writel(0x0, (v_addr + offset));
-                prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
-                        OMAP3_PRM_RSTST_OFFSET);
+                prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
+                                     OMAP3430_GR_MOD,
+                                     OMAP3_PRM_RSTST_OFFSET);
         }
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index e436dcb19795..0a563a671dde 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,12 +2,12 @@
  * omap_hwmod implementation for OMAP2/3/4
  *
  * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- * With fixes and testing from Kevin Hilman
  *
- * Created in collaboration with (alphabetical order): Benoit Cousson,
- * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
- * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
+ * Paul Walmsley, Benoît Cousson, Kevin Hilman
+ *
+ * Created in collaboration with (alphabetical order): Thara Gopinath,
+ * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
+ * Sawant, Santosh Shilimkar, Richard Woodruff
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -58,7 +58,7 @@
 #define MAX_MODULE_RESET_WAIT           10000
 
 /* Name of the OMAP hwmod for the MPU */
-#define MPU_INITIATOR_NAME              "mpu_hwmod"
+#define MPU_INITIATOR_NAME              "mpu"
 
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
@@ -404,21 +404,20 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
  */
 static int _init_main_clk(struct omap_hwmod *oh)
 {
-        struct clk *c;
         int ret = 0;
 
         if (!oh->main_clk)
                 return 0;
 
-        c = omap_clk_get_by_name(oh->main_clk);
-        WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n",
-             oh->name, oh->main_clk);
-        if (IS_ERR(c))
-                ret = -EINVAL;
-        oh->_clk = c;
+        oh->_clk = omap_clk_get_by_name(oh->main_clk);
+        if (!oh->_clk)
+                pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
+                           oh->name, oh->main_clk);
+                return -EINVAL;
 
-        WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
-             oh->main_clk, c->name);
+        if (!oh->_clk->clkdm)
+                pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
+                           oh->main_clk, oh->_clk->name);
 
         return ret;
 }
@@ -432,7 +431,6 @@ static int _init_main_clk(struct omap_hwmod *oh)
  */
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
-        struct omap_hwmod_ocp_if *os;
         struct clk *c;
         int i;
         int ret = 0;
@@ -440,14 +438,16 @@ static int _init_interface_clks(struct omap_hwmod *oh)
         if (oh->slaves_cnt == 0)
                 return 0;
 
-        for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+        for (i = 0; i < oh->slaves_cnt; i++) {
+                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+
                 if (!os->clk)
                         continue;
 
                 c = omap_clk_get_by_name(os->clk);
-                WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get "
-                     "interface_clk %s\n", oh->name, os->clk);
-                if (IS_ERR(c))
+                if (!c)
+                        pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
+                                   oh->name, os->clk);
                         ret = -EINVAL;
                 os->_clk = c;
         }
@@ -471,9 +471,9 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
                 c = omap_clk_get_by_name(oc->clk);
-                WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk "
-                     "%s\n", oh->name, oc->clk);
-                if (IS_ERR(c))
+                if (!c)
+                        pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
+                                   oh->name, oc->clk);
                         ret = -EINVAL;
                 oc->_clk = c;
         }
@@ -490,19 +490,19 @@ static int _init_opt_clks(struct omap_hwmod *oh)
  */
 static int _enable_clocks(struct omap_hwmod *oh)
 {
-        struct omap_hwmod_ocp_if *os;
         int i;
 
         pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
 
-        if (oh->_clk && !IS_ERR(oh->_clk))
+        if (oh->_clk)
                 clk_enable(oh->_clk);
 
         if (oh->slaves_cnt > 0) {
-                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                for (i = 0; i < oh->slaves_cnt; i++) {
+                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
                         struct clk *c = os->_clk;
 
-                        if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE))
+                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
                                 clk_enable(c);
                 }
         }
@@ -520,19 +520,19 @@ static int _enable_clocks(struct omap_hwmod *oh)
  */
 static int _disable_clocks(struct omap_hwmod *oh)
 {
-        struct omap_hwmod_ocp_if *os;
         int i;
 
         pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
 
-        if (oh->_clk && !IS_ERR(oh->_clk))
+        if (oh->_clk)
                 clk_disable(oh->_clk);
 
         if (oh->slaves_cnt > 0) {
-                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                for (i = 0; i < oh->slaves_cnt; i++) {
+                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
                         struct clk *c = os->_clk;
 
-                        if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE))
+                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
                                 clk_disable(c);
                 }
         }
@@ -551,14 +551,15 @@ static int _disable_clocks(struct omap_hwmod *oh)
  */
 static int _find_mpu_port_index(struct omap_hwmod *oh)
 {
-        struct omap_hwmod_ocp_if *os;
         int i;
         int found = 0;
 
         if (!oh || oh->slaves_cnt == 0)
                 return -EINVAL;
 
-        for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+        for (i = 0; i < oh->slaves_cnt; i++) {
+                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+
                 if (os->user & OCP_USER_MPU) {
                         found = 1;
                         break;
@@ -593,7 +594,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
         if (!oh || oh->slaves_cnt == 0)
                 return NULL;
 
-        os = *oh->slaves + index;
+        os = oh->slaves[index];
 
         for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
                 if (mem->flags & ADDR_TYPE_RT) {
@@ -781,9 +782,10 @@ static int _init_clocks(struct omap_hwmod *oh)
         ret |= _init_interface_clks(oh);
         ret |= _init_opt_clks(oh);
 
-        oh->_state = _HWMOD_STATE_CLKS_INITED;
+        if (!ret)
+                oh->_state = _HWMOD_STATE_CLKS_INITED;
 
-        return ret;
+        return 0;
 }
 
 /**
@@ -806,9 +808,9 @@ static int _wait_target_ready(struct omap_hwmod *oh)
         if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
                 return 0;
 
-        os = *oh->slaves + oh->_mpu_port_index;
+        os = oh->slaves[oh->_mpu_port_index];
 
-        if (!(os->flags & OCPIF_HAS_IDLEST))
+        if (oh->flags & HWMOD_NO_IDLEST)
                 return 0;
 
         /* XXX check module SIDLEMODE */
@@ -819,11 +821,8 @@ static int _wait_target_ready(struct omap_hwmod *oh)
                 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
                                                  oh->prcm.omap2.idlest_reg_id,
                                                  oh->prcm.omap2.idlest_idle_bit);
-#if 0
         } else if (cpu_is_omap44xx()) {
-                ret = omap4_cm_wait_module_ready(oh->prcm.omap4.module_offs,
-                                                 oh->prcm.omap4.device_offs);
-#endif
+                ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
         } else {
                 BUG();
         };
@@ -912,16 +911,21 @@ static int _enable(struct omap_hwmod *oh)
         _add_initiator_dep(oh, mpu_oh);
         _enable_clocks(oh);
 
-        if (oh->class->sysc) {
-                if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
-                        _update_sysc_cache(oh);
-                _sysc_enable(oh);
-        }
-
         r = _wait_target_ready(oh);
-        if (!r)
+        if (!r) {
                 oh->_state = _HWMOD_STATE_ENABLED;
 
+                /* Access the sysconfig only if the target is ready */
+                if (oh->class->sysc) {
+                        if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
+                                _update_sysc_cache(oh);
+                        _sysc_enable(oh);
+                }
+        } else {
+                pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
+                         oh->name, r);
+        }
+
         return r;
 }
 
@@ -998,18 +1002,18 @@ static int _shutdown(struct omap_hwmod *oh)
  */
 static int _setup(struct omap_hwmod *oh)
 {
-        struct omap_hwmod_ocp_if *os;
-        int i;
+        int i, r;
 
         if (!oh)
                 return -EINVAL;
 
         /* Set iclk autoidle mode */
         if (oh->slaves_cnt > 0) {
-                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                for (i = 0; i < oh->slaves_cnt; i++) {
+                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
                         struct clk *c = os->_clk;
 
-                        if (!c || IS_ERR(c))
+                        if (!c)
                                 continue;
 
                         if (os->flags & OCPIF_SWSUP_IDLE) {
@@ -1023,7 +1027,12 @@ static int _setup(struct omap_hwmod *oh)
 
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
-        _enable(oh);
+        r = _enable(oh);
+        if (r) {
+                pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
+                           oh->name, oh->_state);
+                return 0;
+        }
 
         if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
                 /*
@@ -1431,7 +1440,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
         ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
 
         for (i = 0; i < oh->slaves_cnt; i++)
-                ret += (*oh->slaves + i)->addr_cnt;
+                ret += oh->slaves[i]->addr_cnt;
 
         return ret;
 }
@@ -1472,7 +1481,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
         for (i = 0; i < oh->slaves_cnt; i++) {
                 struct omap_hwmod_ocp_if *os;
 
-                os = *oh->slaves + i;
+                os = oh->slaves[i];
 
                 for (j = 0; j < os->addr_cnt; j++) {
                         (res + r)->start = (os->addr + j)->pa_start;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index eb7ee2453b24..e5530c51f77d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -125,7 +125,7 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 
 /* MPU */
 static struct omap_hwmod omap2420_mpu_hwmod = {
-        .name           = "mpu_hwmod",
+        .name           = "mpu",
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
         .masters        = omap2420_mpu_masters,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 241bd8230729..0852d954da40 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -127,7 +127,7 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 
 /* MPU */
 static struct omap_hwmod omap2430_mpu_hwmod = {
-        .name           = "mpu_hwmod",
+        .name           = "mpu",
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
         .masters        = omap2430_mpu_masters,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ed6084004260..39b0c0eaa37d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -156,7 +156,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 
 /* MPU */
 static struct omap_hwmod omap3xxx_mpu_hwmod = {
-        .name           = "mpu_hwmod",
+        .name           = "mpu",
         .class          = &mpu_hwmod_class,
         .main_clk       = "arm_fck",
         .masters        = omap3xxx_mpu_masters,
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 7816c4e84a32..e321281ab6e1 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -70,8 +70,8 @@ static int omap2_fclks_active(void)
         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 
         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
-        f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
-        f2 &= ~OMAP24XX_EN_UART3;
+        f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
+        f2 &= ~OMAP24XX_EN_UART3_MASK;
 
         if (f1 | f2)
                 return 1;
@@ -170,7 +170,7 @@ static int omap2_i2c_active(void)
         u32 l;
 
         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
+        return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 }
 
 static int sti_console_enabled;
@@ -181,13 +181,13 @@ static int omap2_allow_mpu_retention(void)
 
         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
-                 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
-                 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
+        if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
+                 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
+                 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
                 return 0;
         /* Check for UART3. */
         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-        if (l & OMAP24XX_EN_UART3)
+        if (l & OMAP24XX_EN_UART3_MASK)
                 return 0;
         if (sti_console_enabled)
                 return 0;
@@ -215,12 +215,12 @@ static void omap2_enter_mpu_retention(void)
 
                 /* Try to enter MPU retention */
                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
-                                  OMAP_LOGICRETSTATE,
+                                  OMAP_LOGICRETSTATE_MASK,
                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
         } else {
                 /* Block MPU retention */
 
-                prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
+                prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                  OMAP2_PM_PWSTCTRL);
                 only_idle = 1;
         }
@@ -288,7 +288,8 @@ static int omap2_pm_suspend(void)
         u32 wken_wkup, mir1;
 
         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-        prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
+        wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
+        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         /* Mask GPT1 */
         mir1 = omap_readl(0x480fe0a4);
@@ -351,7 +352,7 @@ static void __init prcm_setup_regs(void)
         struct powerdomain *pwrdm;
 
         /* Enable autoidle */
-        prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
+        prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
         /*
@@ -390,53 +391,54 @@ static void __init prcm_setup_regs(void)
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
         /* Enable clock autoidle for all domains */
-        cm_write_mod_reg(OMAP24XX_AUTO_CAM |
-                         OMAP24XX_AUTO_MAILBOXES |
-                         OMAP24XX_AUTO_WDT4 |
-                         OMAP2420_AUTO_WDT3 |
-                         OMAP24XX_AUTO_MSPRO |
-                         OMAP2420_AUTO_MMC |
-                         OMAP24XX_AUTO_FAC |
-                         OMAP2420_AUTO_EAC |
-                         OMAP24XX_AUTO_HDQ |
-                         OMAP24XX_AUTO_UART2 |
-                         OMAP24XX_AUTO_UART1 |
-                         OMAP24XX_AUTO_I2C2 |
-                         OMAP24XX_AUTO_I2C1 |
-                         OMAP24XX_AUTO_MCSPI2 |
-                         OMAP24XX_AUTO_MCSPI1 |
-                         OMAP24XX_AUTO_MCBSP2 |
-                         OMAP24XX_AUTO_MCBSP1 |
-                         OMAP24XX_AUTO_GPT12 |
-                         OMAP24XX_AUTO_GPT11 |
-                         OMAP24XX_AUTO_GPT10 |
-                         OMAP24XX_AUTO_GPT9 |
-                         OMAP24XX_AUTO_GPT8 |
-                         OMAP24XX_AUTO_GPT7 |
-                         OMAP24XX_AUTO_GPT6 |
-                         OMAP24XX_AUTO_GPT5 |
-                         OMAP24XX_AUTO_GPT4 |
-                         OMAP24XX_AUTO_GPT3 |
-                         OMAP24XX_AUTO_GPT2 |
-                         OMAP2420_AUTO_VLYNQ |
-                         OMAP24XX_AUTO_DSS,
+        cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
+                         OMAP24XX_AUTO_MAILBOXES_MASK |
+                         OMAP24XX_AUTO_WDT4_MASK |
+                         OMAP2420_AUTO_WDT3_MASK |
+                         OMAP24XX_AUTO_MSPRO_MASK |
+                         OMAP2420_AUTO_MMC_MASK |
+                         OMAP24XX_AUTO_FAC_MASK |
+                         OMAP2420_AUTO_EAC_MASK |
+                         OMAP24XX_AUTO_HDQ_MASK |
+                         OMAP24XX_AUTO_UART2_MASK |
+                         OMAP24XX_AUTO_UART1_MASK |
+                         OMAP24XX_AUTO_I2C2_MASK |
+                         OMAP24XX_AUTO_I2C1_MASK |
+                         OMAP24XX_AUTO_MCSPI2_MASK |
+                         OMAP24XX_AUTO_MCSPI1_MASK |
+                         OMAP24XX_AUTO_MCBSP2_MASK |
+                         OMAP24XX_AUTO_MCBSP1_MASK |
+                         OMAP24XX_AUTO_GPT12_MASK |
+                         OMAP24XX_AUTO_GPT11_MASK |
+                         OMAP24XX_AUTO_GPT10_MASK |
+                         OMAP24XX_AUTO_GPT9_MASK |
+                         OMAP24XX_AUTO_GPT8_MASK |
+                         OMAP24XX_AUTO_GPT7_MASK |
+                         OMAP24XX_AUTO_GPT6_MASK |
+                         OMAP24XX_AUTO_GPT5_MASK |
+                         OMAP24XX_AUTO_GPT4_MASK |
+                         OMAP24XX_AUTO_GPT3_MASK |
+                         OMAP24XX_AUTO_GPT2_MASK |
+                         OMAP2420_AUTO_VLYNQ_MASK |
+                         OMAP24XX_AUTO_DSS_MASK,
                          CORE_MOD, CM_AUTOIDLE1);
-        cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
-                         OMAP24XX_AUTO_SSI |
-                         OMAP24XX_AUTO_USB,
+        cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
+                         OMAP24XX_AUTO_SSI_MASK |
+                         OMAP24XX_AUTO_USB_MASK,
                          CORE_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
-                         OMAP24XX_AUTO_GPMC |
-                         OMAP24XX_AUTO_SDMA,
+        cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
+                         OMAP24XX_AUTO_GPMC_MASK |
+                         OMAP24XX_AUTO_SDMA_MASK,
                          CORE_MOD, CM_AUTOIDLE3);
-        cm_write_mod_reg(OMAP24XX_AUTO_PKA |
-                         OMAP24XX_AUTO_AES |
-                         OMAP24XX_AUTO_RNG |
-                         OMAP24XX_AUTO_SHA |
-                         OMAP24XX_AUTO_DES,
+        cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
+                         OMAP24XX_AUTO_AES_MASK |
+                         OMAP24XX_AUTO_RNG_MASK |
+                         OMAP24XX_AUTO_SHA_MASK |
+                         OMAP24XX_AUTO_DES_MASK,
                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 
-        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
+        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+                         CM_AUTOIDLE);
 
         /* Put DPLL and both APLLs into autoidle mode */
         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
@@ -444,12 +446,12 @@ static void __init prcm_setup_regs(void)
                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
                          PLL_MOD, CM_AUTOIDLE);
 
-        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
-                         OMAP24XX_AUTO_WDT1 |
-                         OMAP24XX_AUTO_MPU_WDT |
-                         OMAP24XX_AUTO_GPIOS |
-                         OMAP24XX_AUTO_32KSYNC |
-                         OMAP24XX_AUTO_GPT1,
+        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+                         OMAP24XX_AUTO_WDT1_MASK |
+                         OMAP24XX_AUTO_MPU_WDT_MASK |
+                         OMAP24XX_AUTO_GPIOS_MASK |
+                         OMAP24XX_AUTO_32KSYNC_MASK |
+                         OMAP24XX_AUTO_GPT1_MASK,
                          WKUP_MOD, CM_AUTOIDLE);
 
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
@@ -460,15 +462,15 @@ static void __init prcm_setup_regs(void)
         /* Configure automatic voltage transition */
         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
                           OMAP2_PRCM_VOLTSETUP_OFFSET);
-        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
+        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
                           (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
-                          OMAP24XX_MEMRETCTRL |
+                          OMAP24XX_MEMRETCTRL_MASK |
                           (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
                           (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
                           OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 
         /* Enable wake-up events */
-        prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
+        prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
                           WKUP_MOD, PM_WKEN);
 }
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 24c1966f935e..2e967716cc3f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,19 +94,20 @@ static void omap3_enable_io_chain(void)
         int timeout = 0;
 
         if (omap_rev() >= OMAP3430_REV_ES3_1) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
+                prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                     PM_WKEN);
                 /* Do a readback to assure write has been done */
                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
-                         OMAP3430_ST_IO_CHAIN)) {
+                         OMAP3430_ST_IO_CHAIN_MASK)) {
                         timeout++;
                         if (timeout > 1000) {
                                 printk(KERN_ERR "Wake up daisy chain "
                                        "activation failed.\n");
                                 return;
                         }
-                        prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
+                        prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
                                              WKUP_MOD, PM_WKST);
                 }
         }
@@ -115,7 +116,8 @@ static void omap3_enable_io_chain(void)
 static void omap3_disable_io_chain(void)
 {
         if (omap_rev() >= OMAP3430_REV_ES3_1)
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
+                prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                       PM_WKEN);
 }
 
 static void omap3_core_save_context(void)
@@ -278,7 +280,8 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         irqstatus_mpu &= irqenable_mpu;
 
         do {
-                if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
+                if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
+                                     OMAP3430_IO_ST_MASK)) {
                         c = _prcm_int_handle_wakeup();
 
                         /*
@@ -384,7 +387,7 @@ void omap_sram_idle(void)
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
         if (per_next_state < PWRDM_POWER_ON ||
                         core_next_state < PWRDM_POWER_ON) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+                prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
 
@@ -458,7 +461,7 @@ void omap_sram_idle(void)
                 omap_uart_resume_idle(0);
                 omap_uart_resume_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF)
-                        prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
+                        prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
         }
@@ -476,9 +479,8 @@ void omap_sram_idle(void)
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
-        if (per_next_state < PWRDM_POWER_ON ||
-                        core_next_state < PWRDM_POWER_ON) {
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
+        if (core_next_state < PWRDM_POWER_ON) {
+                prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_disable_io_chain();
         }
 
@@ -699,9 +701,9 @@ static void __init omap3_iva_idle(void)
                 return;
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2 |
-                          OMAP3430_RST2_IVA2 |
-                          OMAP3430_RST3_IVA2,
+        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+                          OMAP3430_RST2_IVA2_MASK |
+                          OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Enable IVA2 clock */
@@ -719,9 +721,9 @@ static void __init omap3_iva_idle(void)
         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2 |
-                          OMAP3430_RST2_IVA2 |
-                          OMAP3430_RST3_IVA2,
+        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+                          OMAP3430_RST2_IVA2_MASK |
+                          OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 }
 
@@ -743,8 +745,8 @@ static void __init omap3_d2d_idle(void)
         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 
         /* reset modem */
-        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
-                          OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
+        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
+                          OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
                           CORE_MOD, OMAP2_RM_RSTCTRL);
         prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 }
@@ -770,102 +772,102 @@ static void __init prcm_setup_regs(void)
          * Note that in the long run this should be done by clockfw
          */
         cm_write_mod_reg(
-                OMAP3430_AUTO_MODEM |
-                OMAP3430ES2_AUTO_MMC3 |
-                OMAP3430ES2_AUTO_ICR |
-                OMAP3430_AUTO_AES2 |
-                OMAP3430_AUTO_SHA12 |
-                OMAP3430_AUTO_DES2 |
-                OMAP3430_AUTO_MMC2 |
-                OMAP3430_AUTO_MMC1 |
-                OMAP3430_AUTO_MSPRO |
-                OMAP3430_AUTO_HDQ |
-                OMAP3430_AUTO_MCSPI4 |
-                OMAP3430_AUTO_MCSPI3 |
-                OMAP3430_AUTO_MCSPI2 |
-                OMAP3430_AUTO_MCSPI1 |
-                OMAP3430_AUTO_I2C3 |
-                OMAP3430_AUTO_I2C2 |
-                OMAP3430_AUTO_I2C1 |
-                OMAP3430_AUTO_UART2 |
-                OMAP3430_AUTO_UART1 |
-                OMAP3430_AUTO_GPT11 |
-                OMAP3430_AUTO_GPT10 |
-                OMAP3430_AUTO_MCBSP5 |
-                OMAP3430_AUTO_MCBSP1 |
-                OMAP3430ES1_AUTO_FAC | /* This is es1 only */
-                OMAP3430_AUTO_MAILBOXES |
-                OMAP3430_AUTO_OMAPCTRL |
-                OMAP3430ES1_AUTO_FSHOSTUSB |
-                OMAP3430_AUTO_HSOTGUSB |
-                OMAP3430_AUTO_SAD2D |
-                OMAP3430_AUTO_SSI,
+                OMAP3430_AUTO_MODEM_MASK |
+                OMAP3430ES2_AUTO_MMC3_MASK |
+                OMAP3430ES2_AUTO_ICR_MASK |
+                OMAP3430_AUTO_AES2_MASK |
+                OMAP3430_AUTO_SHA12_MASK |
+                OMAP3430_AUTO_DES2_MASK |
+                OMAP3430_AUTO_MMC2_MASK |
+                OMAP3430_AUTO_MMC1_MASK |
+                OMAP3430_AUTO_MSPRO_MASK |
+                OMAP3430_AUTO_HDQ_MASK |
+                OMAP3430_AUTO_MCSPI4_MASK |
+                OMAP3430_AUTO_MCSPI3_MASK |
+                OMAP3430_AUTO_MCSPI2_MASK |
+                OMAP3430_AUTO_MCSPI1_MASK |
+                OMAP3430_AUTO_I2C3_MASK |
+                OMAP3430_AUTO_I2C2_MASK |
+                OMAP3430_AUTO_I2C1_MASK |
+                OMAP3430_AUTO_UART2_MASK |
+                OMAP3430_AUTO_UART1_MASK |
+                OMAP3430_AUTO_GPT11_MASK |
+                OMAP3430_AUTO_GPT10_MASK |
+                OMAP3430_AUTO_MCBSP5_MASK |
+                OMAP3430_AUTO_MCBSP1_MASK |
+                OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
+                OMAP3430_AUTO_MAILBOXES_MASK |
+                OMAP3430_AUTO_OMAPCTRL_MASK |
+                OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
+                OMAP3430_AUTO_HSOTGUSB_MASK |
+                OMAP3430_AUTO_SAD2D_MASK |
+                OMAP3430_AUTO_SSI_MASK,
                 CORE_MOD, CM_AUTOIDLE1);
 
         cm_write_mod_reg(
-                OMAP3430_AUTO_PKA |
-                OMAP3430_AUTO_AES1 |
-                OMAP3430_AUTO_RNG |
-                OMAP3430_AUTO_SHA11 |
-                OMAP3430_AUTO_DES1,
+                OMAP3430_AUTO_PKA_MASK |
+                OMAP3430_AUTO_AES1_MASK |
+                OMAP3430_AUTO_RNG_MASK |
+                OMAP3430_AUTO_SHA11_MASK |
+                OMAP3430_AUTO_DES1_MASK,
                 CORE_MOD, CM_AUTOIDLE2);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
                 cm_write_mod_reg(
-                        OMAP3430_AUTO_MAD2D |
-                        OMAP3430ES2_AUTO_USBTLL,
+                        OMAP3430_AUTO_MAD2D_MASK |
+                        OMAP3430ES2_AUTO_USBTLL_MASK,
                         CORE_MOD, CM_AUTOIDLE3);
         }
 
         cm_write_mod_reg(
-                OMAP3430_AUTO_WDT2 |
-                OMAP3430_AUTO_WDT1 |
-                OMAP3430_AUTO_GPIO1 |
-                OMAP3430_AUTO_32KSYNC |
-                OMAP3430_AUTO_GPT12 |
-                OMAP3430_AUTO_GPT1 ,
+                OMAP3430_AUTO_WDT2_MASK |
+                OMAP3430_AUTO_WDT1_MASK |
+                OMAP3430_AUTO_GPIO1_MASK |
+                OMAP3430_AUTO_32KSYNC_MASK |
+                OMAP3430_AUTO_GPT12_MASK |
+                OMAP3430_AUTO_GPT1_MASK,
                 WKUP_MOD, CM_AUTOIDLE);
 
         cm_write_mod_reg(
-                OMAP3430_AUTO_DSS,
+                OMAP3430_AUTO_DSS_MASK,
                 OMAP3430_DSS_MOD,
                 CM_AUTOIDLE);
 
         cm_write_mod_reg(
-                OMAP3430_AUTO_CAM,
+                OMAP3430_AUTO_CAM_MASK,
                 OMAP3430_CAM_MOD,
                 CM_AUTOIDLE);
 
         cm_write_mod_reg(
-                OMAP3430_AUTO_GPIO6 |
-                OMAP3430_AUTO_GPIO5 |
-                OMAP3430_AUTO_GPIO4 |
-                OMAP3430_AUTO_GPIO3 |
-                OMAP3430_AUTO_GPIO2 |
-                OMAP3430_AUTO_WDT3 |
-                OMAP3430_AUTO_UART3 |
-                OMAP3430_AUTO_GPT9 |
-                OMAP3430_AUTO_GPT8 |
-                OMAP3430_AUTO_GPT7 |
-                OMAP3430_AUTO_GPT6 |
-                OMAP3430_AUTO_GPT5 |
-                OMAP3430_AUTO_GPT4 |
-                OMAP3430_AUTO_GPT3 |
-                OMAP3430_AUTO_GPT2 |
-                OMAP3430_AUTO_MCBSP4 |
-                OMAP3430_AUTO_MCBSP3 |
-                OMAP3430_AUTO_MCBSP2,
+                OMAP3430_AUTO_GPIO6_MASK |
+                OMAP3430_AUTO_GPIO5_MASK |
+                OMAP3430_AUTO_GPIO4_MASK |
+                OMAP3430_AUTO_GPIO3_MASK |
+                OMAP3430_AUTO_GPIO2_MASK |
+                OMAP3430_AUTO_WDT3_MASK |
+                OMAP3430_AUTO_UART3_MASK |
+                OMAP3430_AUTO_GPT9_MASK |
+                OMAP3430_AUTO_GPT8_MASK |
+                OMAP3430_AUTO_GPT7_MASK |
+                OMAP3430_AUTO_GPT6_MASK |
+                OMAP3430_AUTO_GPT5_MASK |
+                OMAP3430_AUTO_GPT4_MASK |
+                OMAP3430_AUTO_GPT3_MASK |
+                OMAP3430_AUTO_GPT2_MASK |
+                OMAP3430_AUTO_MCBSP4_MASK |
+                OMAP3430_AUTO_MCBSP3_MASK |
+                OMAP3430_AUTO_MCBSP2_MASK,
                 OMAP3430_PER_MOD,
                 CM_AUTOIDLE);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
                 cm_write_mod_reg(
-                        OMAP3430ES2_AUTO_USBHOST,
+                        OMAP3430ES2_AUTO_USBHOST_MASK,
                         OMAP3430ES2_USBHOST_MOD,
                         CM_AUTOIDLE);
         }
 
-        omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
+        omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
         /*
          * Set all plls to autoidle. This is needed until autoidle is
@@ -895,35 +897,40 @@ static void __init prcm_setup_regs(void)
                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 
         /* setup wakup source */
-        prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
-                          OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
+        prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
+                          OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
                           WKUP_MOD, PM_WKEN);
         /* No need to write EN_IO, that is always enabled */
-        prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
-                          OMAP3430_EN_GPT12,
+        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
+                          OMAP3430_GRPSEL_GPT1_MASK |
+                          OMAP3430_GRPSEL_GPT12_MASK,
                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
         /* For some reason IO doesn't generate wakeup event even if
          * it is selected to mpu wakeup goup */
-        prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
+        prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
         /* Enable PM_WKEN to support DSS LPR */
-        prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
+        prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
-                          OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
-                          OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
-                          OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
-                          OMAP3430_EN_MCBSP4,
+        prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
+                          OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
+                          OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
+                          OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
+                          OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
-                          OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
-                          OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
-                          OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
-                          OMAP3430_EN_MCBSP4,
+        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
+                          OMAP3430_GRPSEL_GPIO3_MASK |
+                          OMAP3430_GRPSEL_GPIO4_MASK |
+                          OMAP3430_GRPSEL_GPIO5_MASK |
+                          OMAP3430_GRPSEL_GPIO6_MASK |
+                          OMAP3430_GRPSEL_UART3_MASK |
+                          OMAP3430_GRPSEL_MCBSP2_MASK |
+                          OMAP3430_GRPSEL_MCBSP3_MASK |
+                          OMAP3430_GRPSEL_MCBSP4_MASK,
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index ebfce7d1a5d3..a2904aa7065e 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -5,8 +5,8 @@
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
- *
  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+ * State counting code by Tero Kristo <tero.kristo@nokia.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -64,10 +64,10 @@ static u16 pwrstst_reg_offs;
 #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
 
 /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
-#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE
-#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE
-#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE
-#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE
+#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
+#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
+#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
+#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
 #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
 
 /* OMAP3 and OMAP4 Memory Status bits */
@@ -511,6 +511,8 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 {
+        u32 v;
+
         if (!pwrdm)
                 return -EINVAL;
 
@@ -526,9 +528,9 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
          * but the type of value returned is the same for each
          * powerdomain.
          */
-        prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
-                             (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
-                                 pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
+        prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -676,8 +678,8 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                 pwrstst_reg_offs, OMAP3430_LOGICSTATEST);
+        return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs,
+                                       OMAP3430_LOGICSTATEST_MASK);
 }
 
 /**
@@ -700,7 +702,7 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
          * powerdomain.
          */
         return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
-                                        OMAP3430_LASTLOGICSTATEENTERED);
+                                        OMAP3430_LASTLOGICSTATEENTERED_MASK);
 }
 
 /**
@@ -723,7 +725,7 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
          * powerdomain.
          */
         return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs,
-                                        OMAP3430_LOGICSTATEST);
+                                       OMAP3430_LOGICSTATEST_MASK);
 }
 
 /**
@@ -978,6 +980,34 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_set_lowpwrstchange - Request a low power state change
+ * @pwrdm: struct powerdomain *
+ *
+ * Allows a powerdomain to transtion to a lower power sleep state
+ * from an existing sleep state without waking up the powerdomain.
+ * Returns -EINVAL if the powerdomain pointer is null or if the
+ * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
+ * upon success.
+ */
+int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        if (!pwrdm)
+                return -EINVAL;
+
+        if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
+                return -EINVAL;
+
+        pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
+                 pwrdm->name);
+
+        prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                             (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+
+        return 0;
+}
+
+/**
  * pwrdm_wait_transition - wait for powerdomain power transition to finish
  * @pwrdm: struct powerdomain * to wait for
  *
@@ -1002,7 +1032,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
 
         /* XXX Is this udelay() value meaningful? */
         while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
-                OMAP_INTRANSITION) &&
+                OMAP_INTRANSITION_MASK) &&
                (c++ < PWRDM_TRANSITION_BAILOUT))
                         udelay(1);
 
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c1015147d579..c7219513472a 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -1,12 +1,12 @@
 /*
  * OMAP4 Power domains framework
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
  * Benoit Cousson (b-cousson@ti.com)
- * Paul Walmsley
+ * Paul Walmsley (paul@pwsan.com)
  *
  * This file is automatically generated from the OMAP hardware databases.
  * We respectfully ask that any modifications to this file be coordinated
@@ -54,6 +54,7 @@ static struct powerdomain core_44xx_pwrdm = {
                 [3] = PWRDM_POWER_ON,   /* ducati_l2ram */
                 [4] = PWRDM_POWER_ON,   /* ducati_unicache */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -69,6 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRDM_POWER_ON,   /* gfx_mem */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* abe_44xx_pwrdm: Audio back end power domain */
@@ -87,6 +89,7 @@ static struct powerdomain abe_44xx_pwrdm = {
                 [0] = PWRDM_POWER_ON,   /* aessmem */
                 [1] = PWRDM_POWER_ON,   /* periphmem */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* dss_44xx_pwrdm: Display subsystem power domain */
@@ -103,6 +106,7 @@ static struct powerdomain dss_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRDM_POWER_ON,   /* dss_mem */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -123,6 +127,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
                 [1] = PWRDM_POWER_ON,   /* tesla_l1 */
                 [2] = PWRDM_POWER_ON,   /* tesla_l2 */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* wkup_44xx_pwrdm: Wake-up power domain */
@@ -130,7 +135,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
         .name             = "wkup_pwrdm",
         .prcm_offs        = OMAP4430_PRM_WKUP_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRDM_POWER_ON,
+        .pwrsts           = PWRSTS_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRDM_POWER_OFF,  /* wkup_bank */
@@ -143,7 +148,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 static struct powerdomain cpu0_44xx_pwrdm = {
         .name             = "cpu0_pwrdm",
-        .prcm_offs        = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -159,7 +164,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 static struct powerdomain cpu1_44xx_pwrdm = {
         .name             = "cpu1_pwrdm",
-        .prcm_offs        = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -227,6 +232,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
                 [2] = PWRDM_POWER_ON,   /* tcm1_mem */
                 [3] = PWRDM_POWER_ON,   /* tcm2_mem */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -242,6 +248,7 @@ static struct powerdomain cam_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRDM_POWER_ON,   /* cam_mem */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
@@ -258,6 +265,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
         .pwrsts_mem_on  = {
                 [0] = PWRDM_POWER_ON,   /* l3init_bank1 */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -276,6 +284,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
                 [0] = PWRDM_POWER_ON,   /* nonretained_bank */
                 [1] = PWRDM_POWER_ON,   /* retained_bank */
         },
+        .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
 
 /*
@@ -286,7 +295,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
         .name             = "always_on_core_pwrdm",
         .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRDM_POWER_ON,
+        .pwrsts           = PWRSTS_ON,
 };
 
 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 90f603d434c6..995b7edbf18d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -112,83 +112,75 @@
 
 #define OMAP4430_SCRM_SCRM_MOD  0x0000
 
-/* CHIRONSS instances */
+/* PRCM_MPU instances */
 
-#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD  0x0000
-#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD       0x0200
-#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD             0x0400
-#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD             0x0800
-
-/* Base Addresses for the OMAP4 */
-
-#define OMAP4430_CM1_BASE               0x4a004000
-#define OMAP4430_CM2_BASE               0x4a008000
-#define OMAP4430_PRM_BASE               0x4a306000
-#define OMAP4430_SCRM_BASE              0x4a30a000
-#define OMAP4430_CHIRONSS_BASE          0x48243000
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD   0x0000
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD        0x0200
+#define OMAP4430_PRCM_MPU_CPU0_MOD              0x0400
+#define OMAP4430_PRCM_MPU_CPU1_MOD              0x0800
 
 
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
 #define OMAP2420_EN_MMC_SHIFT                           26
-#define OMAP2420_EN_MMC                                 (1 << 26)
+#define OMAP2420_EN_MMC_MASK                            (1 << 26)
 #define OMAP24XX_EN_UART2_SHIFT                         22
-#define OMAP24XX_EN_UART2                               (1 << 22)
+#define OMAP24XX_EN_UART2_MASK                          (1 << 22)
 #define OMAP24XX_EN_UART1_SHIFT                         21
-#define OMAP24XX_EN_UART1                               (1 << 21)
+#define OMAP24XX_EN_UART1_MASK                          (1 << 21)
 #define OMAP24XX_EN_MCSPI2_SHIFT                        18
-#define OMAP24XX_EN_MCSPI2                              (1 << 18)
+#define OMAP24XX_EN_MCSPI2_MASK                         (1 << 18)
 #define OMAP24XX_EN_MCSPI1_SHIFT                        17
-#define OMAP24XX_EN_MCSPI1                              (1 << 17)
+#define OMAP24XX_EN_MCSPI1_MASK                         (1 << 17)
 #define OMAP24XX_EN_MCBSP2_SHIFT                        16
-#define OMAP24XX_EN_MCBSP2                              (1 << 16)
+#define OMAP24XX_EN_MCBSP2_MASK                         (1 << 16)
 #define OMAP24XX_EN_MCBSP1_SHIFT                        15
-#define OMAP24XX_EN_MCBSP1                              (1 << 15)
+#define OMAP24XX_EN_MCBSP1_MASK                         (1 << 15)
 #define OMAP24XX_EN_GPT12_SHIFT                         14
-#define OMAP24XX_EN_GPT12                               (1 << 14)
+#define OMAP24XX_EN_GPT12_MASK                          (1 << 14)
 #define OMAP24XX_EN_GPT11_SHIFT                         13
-#define OMAP24XX_EN_GPT11                               (1 << 13)
+#define OMAP24XX_EN_GPT11_MASK                          (1 << 13)
 #define OMAP24XX_EN_GPT10_SHIFT                         12
-#define OMAP24XX_EN_GPT10                               (1 << 12)
+#define OMAP24XX_EN_GPT10_MASK                          (1 << 12)
 #define OMAP24XX_EN_GPT9_SHIFT                          11
-#define OMAP24XX_EN_GPT9                                (1 << 11)
+#define OMAP24XX_EN_GPT9_MASK                           (1 << 11)
 #define OMAP24XX_EN_GPT8_SHIFT                          10
-#define OMAP24XX_EN_GPT8                                (1 << 10)
+#define OMAP24XX_EN_GPT8_MASK                           (1 << 10)
 #define OMAP24XX_EN_GPT7_SHIFT                          9
-#define OMAP24XX_EN_GPT7                                (1 << 9)
+#define OMAP24XX_EN_GPT7_MASK                           (1 << 9)
 #define OMAP24XX_EN_GPT6_SHIFT                          8
-#define OMAP24XX_EN_GPT6                                (1 << 8)
+#define OMAP24XX_EN_GPT6_MASK                           (1 << 8)
 #define OMAP24XX_EN_GPT5_SHIFT                          7
-#define OMAP24XX_EN_GPT5                                (1 << 7)
+#define OMAP24XX_EN_GPT5_MASK                           (1 << 7)
 #define OMAP24XX_EN_GPT4_SHIFT                          6
-#define OMAP24XX_EN_GPT4                                (1 << 6)
+#define OMAP24XX_EN_GPT4_MASK                           (1 << 6)
 #define OMAP24XX_EN_GPT3_SHIFT                          5
-#define OMAP24XX_EN_GPT3                                (1 << 5)
+#define OMAP24XX_EN_GPT3_MASK                           (1 << 5)
 #define OMAP24XX_EN_GPT2_SHIFT                          4
-#define OMAP24XX_EN_GPT2                                (1 << 4)
+#define OMAP24XX_EN_GPT2_MASK                           (1 << 4)
 #define OMAP2420_EN_VLYNQ_SHIFT                         3
-#define OMAP2420_EN_VLYNQ                               (1 << 3)
+#define OMAP2420_EN_VLYNQ_MASK                          (1 << 3)
 
 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
 #define OMAP2430_EN_GPIO5_SHIFT                         10
-#define OMAP2430_EN_GPIO5                               (1 << 10)
+#define OMAP2430_EN_GPIO5_MASK                          (1 << 10)
 #define OMAP2430_EN_MCSPI3_SHIFT                        9
-#define OMAP2430_EN_MCSPI3                              (1 << 9)
+#define OMAP2430_EN_MCSPI3_MASK                         (1 << 9)
 #define OMAP2430_EN_MMCHS2_SHIFT                        8
-#define OMAP2430_EN_MMCHS2                              (1 << 8)
+#define OMAP2430_EN_MMCHS2_MASK                         (1 << 8)
 #define OMAP2430_EN_MMCHS1_SHIFT                        7
-#define OMAP2430_EN_MMCHS1                              (1 << 7)
+#define OMAP2430_EN_MMCHS1_MASK                         (1 << 7)
 #define OMAP24XX_EN_UART3_SHIFT                         2
-#define OMAP24XX_EN_UART3                               (1 << 2)
+#define OMAP24XX_EN_UART3_MASK                          (1 << 2)
 #define OMAP24XX_EN_USB_SHIFT                           0
-#define OMAP24XX_EN_USB                                 (1 << 0)
+#define OMAP24XX_EN_USB_MASK                            (1 << 0)
 
 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
 #define OMAP2430_EN_MDM_INTC_SHIFT                      11
-#define OMAP2430_EN_MDM_INTC                            (1 << 11)
+#define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT                         6
-#define OMAP2430_EN_USBHS                               (1 << 6)
+#define OMAP2430_EN_USBHS_MASK                          (1 << 6)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT                           26
@@ -246,9 +238,9 @@
 
 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 #define OMAP24XX_EN_GPIOS_SHIFT                         2
-#define OMAP24XX_EN_GPIOS                               (1 << 2)
+#define OMAP24XX_EN_GPIOS_MASK                          (1 << 2)
 #define OMAP24XX_EN_GPT1_SHIFT                          0
-#define OMAP24XX_EN_GPT1                                (1 << 0)
+#define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
@@ -267,47 +259,47 @@
 #define OMAP3430_REV_MASK                               (0xff << 0)
 
 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
-#define OMAP3430_AUTOIDLE                               (1 << 0)
+#define OMAP3430_AUTOIDLE_MASK                          (1 << 0)
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_MMC2                                (1 << 25)
+#define OMAP3430_EN_MMC2_MASK                           (1 << 25)
 #define OMAP3430_EN_MMC2_SHIFT                          25
-#define OMAP3430_EN_MMC1                                (1 << 24)
+#define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 #define OMAP3430_EN_MMC1_SHIFT                          24
-#define OMAP3430_EN_MCSPI4                              (1 << 21)
+#define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 #define OMAP3430_EN_MCSPI4_SHIFT                        21
-#define OMAP3430_EN_MCSPI3                              (1 << 20)
+#define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
 #define OMAP3430_EN_MCSPI3_SHIFT                        20
-#define OMAP3430_EN_MCSPI2                              (1 << 19)
+#define OMAP3430_EN_MCSPI2_MASK                         (1 << 19)
 #define OMAP3430_EN_MCSPI2_SHIFT                        19
-#define OMAP3430_EN_MCSPI1                              (1 << 18)
+#define OMAP3430_EN_MCSPI1_MASK                         (1 << 18)
 #define OMAP3430_EN_MCSPI1_SHIFT                        18
-#define OMAP3430_EN_I2C3                                (1 << 17)
+#define OMAP3430_EN_I2C3_MASK                           (1 << 17)
 #define OMAP3430_EN_I2C3_SHIFT                          17
-#define OMAP3430_EN_I2C2                                (1 << 16)
+#define OMAP3430_EN_I2C2_MASK                           (1 << 16)
 #define OMAP3430_EN_I2C2_SHIFT                          16
-#define OMAP3430_EN_I2C1                                (1 << 15)
+#define OMAP3430_EN_I2C1_MASK                           (1 << 15)
 #define OMAP3430_EN_I2C1_SHIFT                          15
-#define OMAP3430_EN_UART2                               (1 << 14)
+#define OMAP3430_EN_UART2_MASK                          (1 << 14)
 #define OMAP3430_EN_UART2_SHIFT                         14
-#define OMAP3430_EN_UART1                               (1 << 13)
+#define OMAP3430_EN_UART1_MASK                          (1 << 13)
 #define OMAP3430_EN_UART1_SHIFT                         13
-#define OMAP3430_EN_GPT11                               (1 << 12)
+#define OMAP3430_EN_GPT11_MASK                          (1 << 12)
 #define OMAP3430_EN_GPT11_SHIFT                         12
-#define OMAP3430_EN_GPT10                               (1 << 11)
+#define OMAP3430_EN_GPT10_MASK                          (1 << 11)
 #define OMAP3430_EN_GPT10_SHIFT                         11
-#define OMAP3430_EN_MCBSP5                              (1 << 10)
+#define OMAP3430_EN_MCBSP5_MASK                         (1 << 10)
 #define OMAP3430_EN_MCBSP5_SHIFT                        10
-#define OMAP3430_EN_MCBSP1                              (1 << 9)
+#define OMAP3430_EN_MCBSP1_MASK                         (1 << 9)
 #define OMAP3430_EN_MCBSP1_SHIFT                        9
-#define OMAP3430_EN_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_MASK                      (1 << 5)
 #define OMAP3430_EN_FSHOSTUSB_SHIFT                     5
-#define OMAP3430_EN_D2D                                 (1 << 3)
+#define OMAP3430_EN_D2D_MASK                            (1 << 3)
 #define OMAP3430_EN_D2D_SHIFT                           3
 
 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_HSOTGUSB                            (1 << 4)
-#define OMAP3430_EN_HSOTGUSB_SHIFT                              4
+#define OMAP3430_EN_HSOTGUSB_MASK                       (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT                      4
 
 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
 #define OMAP3430_ST_MMC2_SHIFT                          25
@@ -352,21 +344,21 @@
 #define OMAP3430_ST_D2D_MASK                            (1 << 3)
 
 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPIO1                               (1 << 3)
+#define OMAP3430_EN_GPIO1_MASK                          (1 << 3)
 #define OMAP3430_EN_GPIO1_SHIFT                         3
-#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_MASK                          (1 << 1)
 #define OMAP3430_EN_GPT12_SHIFT                         1
-#define OMAP3430_EN_GPT1                                (1 << 0)
+#define OMAP3430_EN_GPT1_MASK                           (1 << 0)
 #define OMAP3430_EN_GPT1_SHIFT                          0
 
 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_SR2                                 (1 << 7)
+#define OMAP3430_EN_SR2_MASK                            (1 << 7)
 #define OMAP3430_EN_SR2_SHIFT                           7
-#define OMAP3430_EN_SR1                                 (1 << 6)
+#define OMAP3430_EN_SR1_MASK                            (1 << 6)
 #define OMAP3430_EN_SR1_SHIFT                           6
 
 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_MASK                          (1 << 1)
 #define OMAP3430_EN_GPT12_SHIFT                         1
 
 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
@@ -386,47 +378,47 @@
  * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
  * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
  */
-#define OMAP3430_EN_MPU                                 (1 << 1)
+#define OMAP3430_EN_MPU_MASK                            (1 << 1)
 #define OMAP3430_EN_MPU_SHIFT                           1
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
-#define OMAP3430_EN_GPIO6                               (1 << 17)
+#define OMAP3430_EN_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_EN_GPIO6_SHIFT                         17
-#define OMAP3430_EN_GPIO5                               (1 << 16)
+#define OMAP3430_EN_GPIO5_MASK                          (1 << 16)
 #define OMAP3430_EN_GPIO5_SHIFT                         16
-#define OMAP3430_EN_GPIO4                               (1 << 15)
+#define OMAP3430_EN_GPIO4_MASK                          (1 << 15)
 #define OMAP3430_EN_GPIO4_SHIFT                         15
-#define OMAP3430_EN_GPIO3                               (1 << 14)
+#define OMAP3430_EN_GPIO3_MASK                          (1 << 14)
 #define OMAP3430_EN_GPIO3_SHIFT                         14
-#define OMAP3430_EN_GPIO2                               (1 << 13)
+#define OMAP3430_EN_GPIO2_MASK                          (1 << 13)
 #define OMAP3430_EN_GPIO2_SHIFT                         13
-#define OMAP3430_EN_UART3                               (1 << 11)
+#define OMAP3430_EN_UART3_MASK                          (1 << 11)
 #define OMAP3430_EN_UART3_SHIFT                         11
-#define OMAP3430_EN_GPT9                                (1 << 10)
+#define OMAP3430_EN_GPT9_MASK                           (1 << 10)
 #define OMAP3430_EN_GPT9_SHIFT                          10
-#define OMAP3430_EN_GPT8                                (1 << 9)
+#define OMAP3430_EN_GPT8_MASK                           (1 << 9)
 #define OMAP3430_EN_GPT8_SHIFT                          9
-#define OMAP3430_EN_GPT7                                (1 << 8)
+#define OMAP3430_EN_GPT7_MASK                           (1 << 8)
 #define OMAP3430_EN_GPT7_SHIFT                          8
-#define OMAP3430_EN_GPT6                                (1 << 7)
+#define OMAP3430_EN_GPT6_MASK                           (1 << 7)
 #define OMAP3430_EN_GPT6_SHIFT                          7
-#define OMAP3430_EN_GPT5                                (1 << 6)
+#define OMAP3430_EN_GPT5_MASK                           (1 << 6)
 #define OMAP3430_EN_GPT5_SHIFT                          6
-#define OMAP3430_EN_GPT4                                (1 << 5)
+#define OMAP3430_EN_GPT4_MASK                           (1 << 5)
 #define OMAP3430_EN_GPT4_SHIFT                          5
-#define OMAP3430_EN_GPT3                                (1 << 4)
+#define OMAP3430_EN_GPT3_MASK                           (1 << 4)
 #define OMAP3430_EN_GPT3_SHIFT                          4
-#define OMAP3430_EN_GPT2                                (1 << 3)
+#define OMAP3430_EN_GPT2_MASK                           (1 << 3)
 #define OMAP3430_EN_GPT2_SHIFT                          3
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
  * be ST_* bits instead? */
-#define OMAP3430_EN_MCBSP4                              (1 << 2)
+#define OMAP3430_EN_MCBSP4_MASK                         (1 << 2)
 #define OMAP3430_EN_MCBSP4_SHIFT                        2
-#define OMAP3430_EN_MCBSP3                              (1 << 1)
+#define OMAP3430_EN_MCBSP3_MASK                         (1 << 1)
 #define OMAP3430_EN_MCBSP3_SHIFT                        1
-#define OMAP3430_EN_MCBSP2                              (1 << 0)
+#define OMAP3430_EN_MCBSP2_MASK                         (1 << 0)
 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 
 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 07a60f1204ca..c20137497c92 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -158,10 +158,10 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
                 WARN_ON(1);
 
         if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
                                                  OMAP2_RM_RSTCTRL);
         if (cpu_is_omap44xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
                                                  OMAP4_RM_RSTCTRL);
 }
 
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 4002051c20b9..0b188ffa710e 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -19,14 +19,14 @@
 /* Bits shared between registers */
 
 /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
-#define OMAP24XX_WKUP2_ST                               (1 << 1)
-#define OMAP24XX_WKUP1_ST                               (1 << 0)
+#define OMAP24XX_VOLTTRANS_ST_MASK                      (1 << 2)
+#define OMAP24XX_WKUP2_ST_MASK                          (1 << 1)
+#define OMAP24XX_WKUP1_ST_MASK                          (1 << 0)
 
 /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
-#define OMAP24XX_WKUP2_EN                               (1 << 1)
-#define OMAP24XX_WKUP1_EN                               (1 << 0)
+#define OMAP24XX_VOLTTRANS_EN_MASK                      (1 << 2)
+#define OMAP24XX_WKUP2_EN_MASK                          (1 << 1)
+#define OMAP24XX_WKUP1_EN_MASK                          (1 << 0)
 
 /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
 #define OMAP24XX_EN_MPU_SHIFT                           1
@@ -40,16 +40,16 @@
  */
 #define OMAP24XX_MEMONSTATE_SHIFT                       10
 #define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
-#define OMAP24XX_MEMRETSTATE                            (1 << 3)
+#define OMAP24XX_MEMRETSTATE_MASK                       (1 << 3)
 
 /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
-#define OMAP24XX_FORCESTATE                             (1 << 18)
+#define OMAP24XX_FORCESTATE_MASK                        (1 << 18)
 
 /*
  * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
  * PM_PWSTST_MDM shared bits
  */
-#define OMAP24XX_CLKACTIVITY                            (1 << 19)
+#define OMAP24XX_CLKACTIVITY_MASK                       (1 << 19)
 
 /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
 #define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
@@ -71,26 +71,26 @@
 #define OMAP24XX_REV_MASK                               (0xff << 0)
 
 /* PRCM_SYSCONFIG */
-#define OMAP24XX_AUTOIDLE                               (1 << 0)
+#define OMAP24XX_AUTOIDLE_MASK                          (1 << 0)
 
 /* PRCM_IRQSTATUS_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
-#define OMAP24XX_TRANSITION_ST                          (1 << 5)
-#define OMAP24XX_EVGENOFF_ST                            (1 << 4)
-#define OMAP24XX_EVGENON_ST                             (1 << 3)
+#define OMAP2430_DPLL_RECAL_ST_MASK                     (1 << 6)
+#define OMAP24XX_TRANSITION_ST_MASK                     (1 << 5)
+#define OMAP24XX_EVGENOFF_ST_MASK                       (1 << 4)
+#define OMAP24XX_EVGENON_ST_MASK                        (1 << 3)
 
 /* PRCM_IRQENABLE_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
-#define OMAP24XX_TRANSITION_EN                          (1 << 5)
-#define OMAP24XX_EVGENOFF_EN                            (1 << 4)
-#define OMAP24XX_EVGENON_EN                             (1 << 3)
+#define OMAP2430_DPLL_RECAL_EN_MASK                     (1 << 6)
+#define OMAP24XX_TRANSITION_EN_MASK                     (1 << 5)
+#define OMAP24XX_EVGENOFF_EN_MASK                       (1 << 4)
+#define OMAP24XX_EVGENON_EN_MASK                        (1 << 3)
 
 /* PRCM_VOLTCTRL */
-#define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
-#define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
+#define OMAP24XX_AUTO_EXTVOLT_MASK                      (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT_MASK                     (1 << 14)
 #define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
 #define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
-#define OMAP24XX_MEMRETCTRL                             (1 << 8)
+#define OMAP24XX_MEMRETCTRL_MASK                        (1 << 8)
 #define OMAP24XX_SETRET_LEVEL_SHIFT                     6
 #define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
 #define OMAP24XX_VOLT_LEVEL_SHIFT                       0
@@ -104,13 +104,13 @@
 
 /* PRCM_CLKOUT_CTRL */
 #define OMAP2420_CLKOUT2_EN_SHIFT                       15
-#define OMAP2420_CLKOUT2_EN                             (1 << 15)
+#define OMAP2420_CLKOUT2_EN_MASK                        (1 << 15)
 #define OMAP2420_CLKOUT2_DIV_SHIFT                      11
 #define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
 #define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
 #define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
 #define OMAP24XX_CLKOUT_EN_SHIFT                        7
-#define OMAP24XX_CLKOUT_EN                              (1 << 7)
+#define OMAP24XX_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP24XX_CLKOUT_DIV_SHIFT                       3
 #define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
 #define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
@@ -118,25 +118,25 @@
 
 /* PRCM_CLKEMUL_CTRL */
 #define OMAP24XX_EMULATION_EN_SHIFT                     0
-#define OMAP24XX_EMULATION_EN                           (1 << 0)
+#define OMAP24XX_EMULATION_EN_MASK                      (1 << 0)
 
 /* PRCM_CLKCFG_CTRL */
-#define OMAP24XX_VALID_CONFIG                           (1 << 0)
+#define OMAP24XX_VALID_CONFIG_MASK                      (1 << 0)
 
 /* PRCM_CLKCFG_STATUS */
-#define OMAP24XX_CONFIG_STATUS                          (1 << 0)
+#define OMAP24XX_CONFIG_STATUS_MASK                     (1 << 0)
 
 /* PRCM_VOLTSETUP specific bits */
 
 /* PRCM_CLKSSETUP specific bits */
 
 /* PRCM_POLCTRL */
-#define OMAP2420_CLKOUT2_POL                            (1 << 10)
-#define OMAP24XX_CLKOUT_POL                             (1 << 9)
-#define OMAP24XX_CLKREQ_POL                             (1 << 8)
-#define OMAP2430_USE_POWEROK                            (1 << 2)
-#define OMAP2430_POWEROK_POL                            (1 << 1)
-#define OMAP24XX_EXTVOL_POL                             (1 << 0)
+#define OMAP2420_CLKOUT2_POL_MASK                       (1 << 10)
+#define OMAP24XX_CLKOUT_POL_MASK                        (1 << 9)
+#define OMAP24XX_CLKREQ_POL_MASK                        (1 << 8)
+#define OMAP2430_USE_POWEROK_MASK                       (1 << 2)
+#define OMAP2430_POWEROK_POL_MASK                       (1 << 1)
+#define OMAP24XX_EXTVOL_POL_MASK                        (1 << 0)
 
 /* RM_RSTST_MPU specific bits */
 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
@@ -154,7 +154,7 @@
 /* PM_EVEGENOFFTIM_MPU specific bits */
 
 /* PM_PWSTCTRL_MPU specific bits */
-#define OMAP2430_FORCESTATE                             (1 << 18)
+#define OMAP2430_FORCESTATE_MASK                        (1 << 18)
 
 /* PM_PWSTST_MPU specific bits */
 /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
@@ -168,21 +168,21 @@
 /* PM_WKST2_CORE specific bits */
 
 /* PM_WKDEP_CORE specific bits*/
-#define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
-#define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
-#define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK              (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK              (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK              (1 << 2)
 
 /* PM_PWSTCTRL_CORE specific bits */
-#define OMAP24XX_MEMORYCHANGE                           (1 << 20)
+#define OMAP24XX_MEMORYCHANGE_MASK                      (1 << 20)
 #define OMAP24XX_MEM3ONSTATE_SHIFT                      14
 #define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
 #define OMAP24XX_MEM2ONSTATE_SHIFT                      12
 #define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
 #define OMAP24XX_MEM1ONSTATE_SHIFT                      10
 #define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
-#define OMAP24XX_MEM3RETSTATE                           (1 << 5)
-#define OMAP24XX_MEM2RETSTATE                           (1 << 4)
-#define OMAP24XX_MEM1RETSTATE                           (1 << 3)
+#define OMAP24XX_MEM3RETSTATE_MASK                      (1 << 5)
+#define OMAP24XX_MEM2RETSTATE_MASK                      (1 << 4)
+#define OMAP24XX_MEM1RETSTATE_MASK                      (1 << 3)
 
 /* PM_PWSTST_CORE specific bits */
 #define OMAP24XX_MEM3STATEST_SHIFT                      14
@@ -193,10 +193,10 @@
 #define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
 
 /* RM_RSTCTRL_GFX */
-#define OMAP24XX_GFX_RST                                (1 << 0)
+#define OMAP24XX_GFX_RST_MASK                           (1 << 0)
 
 /* RM_RSTST_GFX specific bits */
-#define OMAP24XX_GFX_SW_RST                             (1 << 4)
+#define OMAP24XX_GFX_SW_RST_MASK                        (1 << 4)
 
 /* PM_PWSTCTRL_GFX specific bits */
 
@@ -209,25 +209,25 @@
 
 /* RM_RSTST_WKUP specific bits */
 /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP24XX_EXTWMPU_RST                            (1 << 6)
-#define OMAP24XX_SECU_WD_RST                            (1 << 5)
-#define OMAP24XX_MPU_WD_RST                             (1 << 4)
-#define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
+#define OMAP24XX_EXTWMPU_RST_MASK                       (1 << 6)
+#define OMAP24XX_SECU_WD_RST_MASK                       (1 << 5)
+#define OMAP24XX_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST_MASK                     (1 << 3)
 
 /* PM_WKEN_WKUP specific bits */
 
 /* PM_WKST_WKUP specific bits */
 
 /* RM_RSTCTRL_DSP */
-#define OMAP2420_RST_IVA                                (1 << 8)
-#define OMAP24XX_RST2_DSP                               (1 << 1)
-#define OMAP24XX_RST1_DSP                               (1 << 0)
+#define OMAP2420_RST_IVA_MASK                           (1 << 8)
+#define OMAP24XX_RST2_DSP_MASK                          (1 << 1)
+#define OMAP24XX_RST1_DSP_MASK                          (1 << 0)
 
 /* RM_RSTST_DSP specific bits */
 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP2420_IVA_SW_RST                             (1 << 8)
-#define OMAP24XX_DSP_SW_RST2                            (1 << 5)
-#define OMAP24XX_DSP_SW_RST1                            (1 << 4)
+#define OMAP2420_IVA_SW_RST_MASK                        (1 << 8)
+#define OMAP24XX_DSP_SW_RST2_MASK                       (1 << 5)
+#define OMAP24XX_DSP_SW_RST1_MASK                       (1 << 4)
 
 /* PM_WKDEP_DSP specific bits */
 
@@ -235,7 +235,7 @@
 /* 2430 only: MEMONSTATE, MEMRETSTATE */
 #define OMAP2420_MEMIONSTATE_SHIFT                      12
 #define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
-#define OMAP2420_MEMIRETSTATE                           (1 << 4)
+#define OMAP2420_MEMIRETSTATE_MASK                      (1 << 4)
 
 /* PM_PWSTST_DSP specific bits */
 /* MEMSTATEST is 2430 only */
@@ -248,18 +248,18 @@
 
 /* RM_RSTCTRL_MDM */
 /* 2430 only */
-#define OMAP2430_PWRON1_MDM                             (1 << 1)
-#define OMAP2430_RST1_MDM                               (1 << 0)
+#define OMAP2430_PWRON1_MDM_MASK                        (1 << 1)
+#define OMAP2430_RST1_MDM_MASK                          (1 << 0)
 
 /* RM_RSTST_MDM specific bits */
 /* 2430 only */
-#define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
-#define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
-#define OMAP2430_MDM_SW_RST1                            (1 << 4)
+#define OMAP2430_MDM_SECU_VIOL_MASK                     (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1_MASK                     (1 << 5)
+#define OMAP2430_MDM_SW_RST1_MASK                       (1 << 4)
 
 /* PM_WKEN_MDM */
 /* 2430 only */
-#define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
+#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK                (1 << 0)
 
 /* PM_WKST_MDM specific bits */
 /* 2430 only */
@@ -269,7 +269,7 @@
 
 /* PM_PWSTCTRL_MDM specific bits */
 /* 2430 only */
-#define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
+#define OMAP2430_KILLDOMAINWKUP_MASK                    (1 << 19)
 
 /* PM_PWSTST_MDM specific bits */
 /* 2430 only */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 8f21bae6dc1c..7fd6023edf96 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -35,10 +35,10 @@
 #define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
 #define OMAP3430_INITVOLTAGE_SHIFT                      8
 #define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
-#define OMAP3430_TIMEOUTEN                              (1 << 3)
-#define OMAP3430_INITVDD                                (1 << 2)
-#define OMAP3430_FORCEUPDATE                            (1 << 1)
-#define OMAP3430_VPENABLE                               (1 << 0)
+#define OMAP3430_TIMEOUTEN_MASK                         (1 << 3)
+#define OMAP3430_INITVDD_MASK                           (1 << 2)
+#define OMAP3430_FORCEUPDATE_MASK                       (1 << 1)
+#define OMAP3430_VPENABLE_MASK                          (1 << 0)
 
 /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
@@ -65,53 +65,53 @@
 #define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
 
 /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
-#define OMAP3430_VPINIDLE                               (1 << 0)
+#define OMAP3430_VPINIDLE_MASK                          (1 << 0)
 
 /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
 #define OMAP3430_EN_PER_SHIFT                           7
 #define OMAP3430_EN_PER_MASK                            (1 << 7)
 
 /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
-#define OMAP3430_MEMORYCHANGE                           (1 << 3)
+#define OMAP3430_MEMORYCHANGE_MASK                      (1 << 3)
 
 /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
-#define OMAP3430_LOGICSTATEST                           (1 << 2)
+#define OMAP3430_LOGICSTATEST_MASK                      (1 << 2)
 
 /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
-#define OMAP3430_LASTLOGICSTATEENTERED                  (1 << 2)
+#define OMAP3430_LASTLOGICSTATEENTERED_MASK             (1 << 2)
 
 /*
  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
  */
-#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT                    0
-#define OMAP3430_LASTPOWERSTATEENTERED_MASK                     (0x3 << 0)
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT            0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK             (0x3 << 0)
 
 /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
-#define OMAP3430_WKUP_ST                                (1 << 0)
+#define OMAP3430_WKUP_ST_MASK                           (1 << 0)
 
 /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
-#define OMAP3430_WKUP_EN                                        (1 << 0)
+#define OMAP3430_WKUP_EN_MASK                           (1 << 0)
 
 /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
-#define OMAP3430_GRPSEL_MMC2                            (1 << 25)
-#define OMAP3430_GRPSEL_MMC1                            (1 << 24)
-#define OMAP3430_GRPSEL_MCSPI4                          (1 << 21)
-#define OMAP3430_GRPSEL_MCSPI3                          (1 << 20)
-#define OMAP3430_GRPSEL_MCSPI2                          (1 << 19)
-#define OMAP3430_GRPSEL_MCSPI1                          (1 << 18)
-#define OMAP3430_GRPSEL_I2C3                            (1 << 17)
-#define OMAP3430_GRPSEL_I2C2                            (1 << 16)
-#define OMAP3430_GRPSEL_I2C1                            (1 << 15)
-#define OMAP3430_GRPSEL_UART2                           (1 << 14)
-#define OMAP3430_GRPSEL_UART1                           (1 << 13)
-#define OMAP3430_GRPSEL_GPT11                           (1 << 12)
-#define OMAP3430_GRPSEL_GPT10                           (1 << 11)
-#define OMAP3430_GRPSEL_MCBSP5                          (1 << 10)
-#define OMAP3430_GRPSEL_MCBSP1                          (1 << 9)
-#define OMAP3430_GRPSEL_HSOTGUSB                        (1 << 4)
-#define OMAP3430_GRPSEL_D2D                             (1 << 3)
+#define OMAP3430_GRPSEL_MMC2_MASK                       (1 << 25)
+#define OMAP3430_GRPSEL_MMC1_MASK                       (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4_MASK                     (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3_MASK                     (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2_MASK                     (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1_MASK                     (1 << 18)
+#define OMAP3430_GRPSEL_I2C3_MASK                       (1 << 17)
+#define OMAP3430_GRPSEL_I2C2_MASK                       (1 << 16)
+#define OMAP3430_GRPSEL_I2C1_MASK                       (1 << 15)
+#define OMAP3430_GRPSEL_UART2_MASK                      (1 << 14)
+#define OMAP3430_GRPSEL_UART1_MASK                      (1 << 13)
+#define OMAP3430_GRPSEL_GPT11_MASK                      (1 << 12)
+#define OMAP3430_GRPSEL_GPT10_MASK                      (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5_MASK                     (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1_MASK                     (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB_MASK                   (1 << 4)
+#define OMAP3430_GRPSEL_D2D_MASK                        (1 << 3)
 
 /*
  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
@@ -119,49 +119,49 @@
  */
 #define OMAP3430_MEMONSTATE_SHIFT                       16
 #define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
-#define OMAP3430_MEMRETSTATE                            (1 << 8)
+#define OMAP3430_MEMRETSTATE_MASK                       (1 << 8)
 
 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
-#define OMAP3430_GRPSEL_GPIO6                           (1 << 17)
-#define OMAP3430_GRPSEL_GPIO5                           (1 << 16)
-#define OMAP3430_GRPSEL_GPIO4                           (1 << 15)
-#define OMAP3430_GRPSEL_GPIO3                           (1 << 14)
-#define OMAP3430_GRPSEL_GPIO2                           (1 << 13)
-#define OMAP3430_GRPSEL_UART3                           (1 << 11)
-#define OMAP3430_GRPSEL_GPT9                            (1 << 10)
-#define OMAP3430_GRPSEL_GPT8                            (1 << 9)
-#define OMAP3430_GRPSEL_GPT7                            (1 << 8)
-#define OMAP3430_GRPSEL_GPT6                            (1 << 7)
-#define OMAP3430_GRPSEL_GPT5                            (1 << 6)
-#define OMAP3430_GRPSEL_GPT4                            (1 << 5)
-#define OMAP3430_GRPSEL_GPT3                            (1 << 4)
-#define OMAP3430_GRPSEL_GPT2                            (1 << 3)
-#define OMAP3430_GRPSEL_MCBSP4                          (1 << 2)
-#define OMAP3430_GRPSEL_MCBSP3                          (1 << 1)
-#define OMAP3430_GRPSEL_MCBSP2                          (1 << 0)
+#define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4_MASK                      (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3_MASK                      (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2_MASK                      (1 << 13)
+#define OMAP3430_GRPSEL_UART3_MASK                      (1 << 11)
+#define OMAP3430_GRPSEL_GPT9_MASK                       (1 << 10)
+#define OMAP3430_GRPSEL_GPT8_MASK                       (1 << 9)
+#define OMAP3430_GRPSEL_GPT7_MASK                       (1 << 8)
+#define OMAP3430_GRPSEL_GPT6_MASK                       (1 << 7)
+#define OMAP3430_GRPSEL_GPT5_MASK                       (1 << 6)
+#define OMAP3430_GRPSEL_GPT4_MASK                       (1 << 5)
+#define OMAP3430_GRPSEL_GPT3_MASK                       (1 << 4)
+#define OMAP3430_GRPSEL_GPT2_MASK                       (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4_MASK                     (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3_MASK                     (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2_MASK                     (1 << 0)
 
 /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
-#define OMAP3430_GRPSEL_IO                              (1 << 8)
-#define OMAP3430_GRPSEL_SR2                             (1 << 7)
-#define OMAP3430_GRPSEL_SR1                             (1 << 6)
-#define OMAP3430_GRPSEL_GPIO1                           (1 << 3)
-#define OMAP3430_GRPSEL_GPT12                           (1 << 1)
-#define OMAP3430_GRPSEL_GPT1                            (1 << 0)
+#define OMAP3430_GRPSEL_IO_MASK                         (1 << 8)
+#define OMAP3430_GRPSEL_SR2_MASK                        (1 << 7)
+#define OMAP3430_GRPSEL_SR1_MASK                        (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1_MASK                      (1 << 3)
+#define OMAP3430_GRPSEL_GPT12_MASK                      (1 << 1)
+#define OMAP3430_GRPSEL_GPT1_MASK                       (1 << 0)
 
 /* Bits specific to each register */
 
 /* RM_RSTCTRL_IVA2 */
-#define OMAP3430_RST3_IVA2                              (1 << 2)
-#define OMAP3430_RST2_IVA2                              (1 << 1)
-#define OMAP3430_RST1_IVA2                              (1 << 0)
+#define OMAP3430_RST3_IVA2_MASK                         (1 << 2)
+#define OMAP3430_RST2_IVA2_MASK                         (1 << 1)
+#define OMAP3430_RST1_IVA2_MASK                         (1 << 0)
 
 /* RM_RSTST_IVA2 specific bits */
-#define OMAP3430_EMULATION_VSEQ_RST                     (1 << 13)
-#define OMAP3430_EMULATION_VHWA_RST                     (1 << 12)
-#define OMAP3430_EMULATION_IVA2_RST                     (1 << 11)
-#define OMAP3430_IVA2_SW_RST3                           (1 << 10)
-#define OMAP3430_IVA2_SW_RST2                           (1 << 9)
-#define OMAP3430_IVA2_SW_RST1                           (1 << 8)
+#define OMAP3430_EMULATION_VSEQ_RST_MASK                (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST_MASK                (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST_MASK                (1 << 11)
+#define OMAP3430_IVA2_SW_RST3_MASK                      (1 << 10)
+#define OMAP3430_IVA2_SW_RST2_MASK                      (1 << 9)
+#define OMAP3430_IVA2_SW_RST1_MASK                      (1 << 8)
 
 /* PM_WKDEP_IVA2 specific bits */
 
@@ -174,10 +174,10 @@
 #define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
-#define OMAP3430_L2FLATMEMRETSTATE                      (1 << 11)
-#define OMAP3430_SHAREDL2CACHEFLATRETSTATE              (1 << 10)
-#define OMAP3430_L1FLATMEMRETSTATE                      (1 << 9)
-#define OMAP3430_SHAREDL1CACHEFLATRETSTATE              (1 << 8)
+#define OMAP3430_L2FLATMEMRETSTATE_MASK                 (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK         (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE_MASK                 (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK         (1 << 8)
 
 /* PM_PWSTST_IVA2 specific bits */
 #define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
@@ -200,12 +200,12 @@
 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
 
 /* PRM_IRQSTATUS_IVA2 specific bits */
-#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST        (1 << 2)
-#define OMAP3430_FORCEWKUP_ST                           (1 << 1)
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK   (1 << 2)
+#define OMAP3430_FORCEWKUP_ST_MASK                      (1 << 1)
 
 /* PRM_IRQENABLE_IVA2 specific bits */
-#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN          (1 << 2)
-#define OMAP3430_FORCEWKUP_EN                                   (1 << 1)
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK     (1 << 2)
+#define OMAP3430_FORCEWKUP_EN_MASK                              (1 << 1)
 
 /* PRM_REVISION specific bits */
 
@@ -213,70 +213,70 @@
 
 /* PRM_IRQSTATUS_MPU specific bits */
 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
-#define OMAP3430ES2_SND_PERIPH_DPLL_ST                  (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_ST                       (1 << 24)
-#define OMAP3430_VC_RAERR_ST                            (1 << 23)
-#define OMAP3430_VC_SAERR_ST                            (1 << 22)
-#define OMAP3430_VP2_TRANXDONE_ST                       (1 << 21)
-#define OMAP3430_VP2_EQVALUE_ST                         (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_ST                       (1 << 19)
-#define OMAP3430_VP2_MAXVDD_ST                          (1 << 18)
-#define OMAP3430_VP2_MINVDD_ST                          (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_ST                   (1 << 16)
-#define OMAP3430_VP1_TRANXDONE_ST                       (1 << 15)
-#define OMAP3430_VP1_EQVALUE_ST                         (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_ST                       (1 << 13)
-#define OMAP3430_VP1_MAXVDD_ST                          (1 << 12)
-#define OMAP3430_VP1_MINVDD_ST                          (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_ST                   (1 << 10)
-#define OMAP3430_IO_ST                                  (1 << 9)
-#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST         (1 << 8)
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK             (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST_MASK                  (1 << 24)
+#define OMAP3430_VC_RAERR_ST_MASK                       (1 << 23)
+#define OMAP3430_VC_SAERR_ST_MASK                       (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST_MASK                  (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST_MASK                    (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST_MASK                  (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST_MASK                     (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST_MASK                     (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK              (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST_MASK                  (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST_MASK                    (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST_MASK                  (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST_MASK                     (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST_MASK                     (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK              (1 << 10)
+#define OMAP3430_IO_ST_MASK                             (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK    (1 << 8)
 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
-#define OMAP3430_MPU_DPLL_ST                            (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_MASK                       (1 << 7)
 #define OMAP3430_MPU_DPLL_ST_SHIFT                      7
-#define OMAP3430_PERIPH_DPLL_ST                         (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_MASK                    (1 << 6)
 #define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
-#define OMAP3430_CORE_DPLL_ST                           (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_MASK                      (1 << 5)
 #define OMAP3430_CORE_DPLL_ST_SHIFT                     5
-#define OMAP3430_TRANSITION_ST                          (1 << 4)
-#define OMAP3430_EVGENOFF_ST                            (1 << 3)
-#define OMAP3430_EVGENON_ST                             (1 << 2)
-#define OMAP3430_FS_USB_WKUP_ST                         (1 << 1)
+#define OMAP3430_TRANSITION_ST_MASK                     (1 << 4)
+#define OMAP3430_EVGENOFF_ST_MASK                       (1 << 3)
+#define OMAP3430_EVGENON_ST_MASK                        (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST_MASK                    (1 << 1)
 
 /* PRM_IRQENABLE_MPU specific bits */
 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
-#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN                    (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_EN                               (1 << 24)
-#define OMAP3430_VC_RAERR_EN                                    (1 << 23)
-#define OMAP3430_VC_SAERR_EN                                    (1 << 22)
-#define OMAP3430_VP2_TRANXDONE_EN                               (1 << 21)
-#define OMAP3430_VP2_EQVALUE_EN                                 (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_EN                               (1 << 19)
-#define OMAP3430_VP2_MAXVDD_EN                                  (1 << 18)
-#define OMAP3430_VP2_MINVDD_EN                                  (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_EN                           (1 << 16)
-#define OMAP3430_VP1_TRANXDONE_EN                               (1 << 15)
-#define OMAP3430_VP1_EQVALUE_EN                                 (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_EN                               (1 << 13)
-#define OMAP3430_VP1_MAXVDD_EN                                  (1 << 12)
-#define OMAP3430_VP1_MINVDD_EN                                  (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_EN                           (1 << 10)
-#define OMAP3430_IO_EN                                          (1 << 9)
-#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN           (1 << 8)
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK               (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN_MASK                          (1 << 24)
+#define OMAP3430_VC_RAERR_EN_MASK                               (1 << 23)
+#define OMAP3430_VC_SAERR_EN_MASK                               (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN_MASK                          (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN_MASK                            (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN_MASK                          (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN_MASK                             (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN_MASK                             (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK                      (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN_MASK                          (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN_MASK                            (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN_MASK                          (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN_MASK                             (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN_MASK                             (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK                      (1 << 10)
+#define OMAP3430_IO_EN_MASK                                     (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK      (1 << 8)
 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
-#define OMAP3430_MPU_DPLL_RECAL_EN                              (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_MASK                         (1 << 7)
 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
-#define OMAP3430_PERIPH_DPLL_RECAL_EN                           (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK                      (1 << 6)
 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
-#define OMAP3430_CORE_DPLL_RECAL_EN                             (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_MASK                        (1 << 5)
 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
-#define OMAP3430_TRANSITION_EN                                  (1 << 4)
-#define OMAP3430_EVGENOFF_EN                                    (1 << 3)
-#define OMAP3430_EVGENON_EN                                     (1 << 2)
-#define OMAP3430_FS_USB_WKUP_EN                                 (1 << 1)
+#define OMAP3430_TRANSITION_EN_MASK                             (1 << 4)
+#define OMAP3430_EVGENOFF_EN_MASK                               (1 << 3)
+#define OMAP3430_EVGENON_EN_MASK                                (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN_MASK                            (1 << 1)
 
 /* RM_RSTST_MPU specific bits */
-#define OMAP3430_EMULATION_MPU_RST                      (1 << 11)
+#define OMAP3430_EMULATION_MPU_RST_MASK                 (1 << 11)
 
 /* PM_WKDEP_MPU specific bits */
 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT              5
@@ -289,7 +289,7 @@
 #define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
 #define OMAP3430_ONLOADMODE_SHIFT                       1
 #define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
-#define OMAP3430_ENABLE                                 (1 << 0)
+#define OMAP3430_ENABLE_MASK                            (1 << 0)
 
 /* PM_EVGENONTIM_MPU */
 #define OMAP3430_ONTIMEVAL_SHIFT                        0
@@ -302,32 +302,32 @@
 /* PM_PWSTCTRL_MPU specific bits */
 #define OMAP3430_L2CACHEONSTATE_SHIFT                   16
 #define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
-#define OMAP3430_L2CACHERETSTATE                        (1 << 8)
-#define OMAP3430_LOGICL1CACHERETSTATE                   (1 << 2)
+#define OMAP3430_L2CACHERETSTATE_MASK                   (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE_MASK              (1 << 2)
 
 /* PM_PWSTST_MPU specific bits */
 #define OMAP3430_L2CACHESTATEST_SHIFT                   6
 #define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
-#define OMAP3430_LOGICL1CACHESTATEST                    (1 << 2)
+#define OMAP3430_LOGICL1CACHESTATEST_MASK               (1 << 2)
 
 /* PM_PREPWSTST_MPU specific bits */
 #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
-#define OMAP3430_LASTLOGICL1CACHESTATEENTERED           (1 << 2)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK      (1 << 2)
 
 /* RM_RSTCTRL_CORE */
-#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON              (1 << 1)
-#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST                   (1 << 0)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK         (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK              (1 << 0)
 
 /* RM_RSTST_CORE specific bits */
-#define OMAP3430_MODEM_SECURITY_VIOL_RST                (1 << 10)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON        (1 << 9)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST             (1 << 8)
+#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK           (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK   (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK        (1 << 8)
 
 /* PM_WKEN1_CORE specific bits */
 
 /* PM_MPUGRPSEL1_CORE specific bits */
-#define OMAP3430_GRPSEL_FSHOSTUSB                       (1 << 5)
+#define OMAP3430_GRPSEL_FSHOSTUSB_MASK                  (1 << 5)
 
 /* PM_IVA2GRPSEL1_CORE specific bits */
 
@@ -338,8 +338,8 @@
 #define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
 #define OMAP3430_MEM1ONSTATE_SHIFT                      16
 #define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
-#define OMAP3430_MEM2RETSTATE                           (1 << 9)
-#define OMAP3430_MEM1RETSTATE                           (1 << 8)
+#define OMAP3430_MEM2RETSTATE_MASK                      (1 << 9)
+#define OMAP3430_MEM1RETSTATE_MASK                      (1 << 8)
 
 /* PM_PWSTST_CORE specific bits */
 #define OMAP3430_MEM2STATEST_SHIFT                      6
@@ -356,7 +356,7 @@
 /* RM_RSTST_GFX specific bits */
 
 /* PM_WKDEP_GFX specific bits */
-#define OMAP3430_PM_WKDEP_GFX_EN_IVA2                   (1 << 2)
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK              (1 << 2)
 
 /* PM_PWSTCTRL_GFX specific bits */
 
@@ -365,33 +365,33 @@
 /* PM_PREPWSTST_GFX specific bits */
 
 /* PM_WKEN_WKUP specific bits */
-#define OMAP3430_EN_IO_CHAIN                            (1 << 16)
-#define OMAP3430_EN_IO                                  (1 << 8)
-#define OMAP3430_EN_GPIO1                               (1 << 3)
+#define OMAP3430_EN_IO_CHAIN_MASK                       (1 << 16)
+#define OMAP3430_EN_IO_MASK                             (1 << 8)
+#define OMAP3430_EN_GPIO1_MASK                          (1 << 3)
 
 /* PM_MPUGRPSEL_WKUP specific bits */
 
 /* PM_IVA2GRPSEL_WKUP specific bits */
 
 /* PM_WKST_WKUP specific bits */
-#define OMAP3430_ST_IO_CHAIN                            (1 << 16)
-#define OMAP3430_ST_IO                                  (1 << 8)
+#define OMAP3430_ST_IO_CHAIN_MASK                       (1 << 16)
+#define OMAP3430_ST_IO_MASK                             (1 << 8)
 
 /* PRM_CLKSEL */
 #define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
 #define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
 
 /* PRM_CLKOUT_CTRL */
-#define OMAP3430_CLKOUT_EN                              (1 << 7)
+#define OMAP3430_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP3430_CLKOUT_EN_SHIFT                        7
 
 /* RM_RSTST_DSS specific bits */
 
 /* PM_WKEN_DSS */
-#define OMAP3430_PM_WKEN_DSS_EN_DSS                     (1 << 0)
+#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK                (1 << 0)
 
 /* PM_WKDEP_DSS specific bits */
-#define OMAP3430_PM_WKDEP_DSS_EN_IVA2                   (1 << 2)
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK              (1 << 2)
 
 /* PM_PWSTCTRL_DSS specific bits */
 
@@ -402,7 +402,7 @@
 /* RM_RSTST_CAM specific bits */
 
 /* PM_WKDEP_CAM specific bits */
-#define OMAP3430_PM_WKDEP_CAM_EN_IVA2                   (1 << 2)
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK              (1 << 2)
 
 /* PM_PWSTCTRL_CAM specific bits */
 
@@ -424,7 +424,7 @@
 /* PM_WKST_PER specific bits */
 
 /* PM_WKDEP_PER specific bits */
-#define OMAP3430_PM_WKDEP_PER_EN_IVA2                   (1 << 2)
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK              (1 << 2)
 
 /* PM_PWSTCTRL_PER specific bits */
 
@@ -467,26 +467,26 @@
 /* PRM_VC_CMD_VAL_1 specific bits */
 
 /* PRM_VC_CH_CONF */
-#define OMAP3430_CMD1                                   (1 << 20)
-#define OMAP3430_RACEN1                                 (1 << 19)
-#define OMAP3430_RAC1                                   (1 << 18)
-#define OMAP3430_RAV1                                   (1 << 17)
-#define OMAP3430_PRM_VC_CH_CONF_SA1                     (1 << 16)
-#define OMAP3430_CMD0                                   (1 << 4)
-#define OMAP3430_RACEN0                                 (1 << 3)
-#define OMAP3430_RAC0                                   (1 << 2)
-#define OMAP3430_RAV0                                   (1 << 1)
-#define OMAP3430_PRM_VC_CH_CONF_SA0                     (1 << 0)
+#define OMAP3430_CMD1_MASK                              (1 << 20)
+#define OMAP3430_RACEN1_MASK                            (1 << 19)
+#define OMAP3430_RAC1_MASK                              (1 << 18)
+#define OMAP3430_RAV1_MASK                              (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK                (1 << 16)
+#define OMAP3430_CMD0_MASK                              (1 << 4)
+#define OMAP3430_RACEN0_MASK                            (1 << 3)
+#define OMAP3430_RAC0_MASK                              (1 << 2)
+#define OMAP3430_RAV0_MASK                              (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK                (1 << 0)
 
 /* PRM_VC_I2C_CFG */
-#define OMAP3430_HSMASTER                               (1 << 5)
-#define OMAP3430_SREN                                   (1 << 4)
-#define OMAP3430_HSEN                                   (1 << 3)
+#define OMAP3430_HSMASTER_MASK                          (1 << 5)
+#define OMAP3430_SREN_MASK                              (1 << 4)
+#define OMAP3430_HSEN_MASK                              (1 << 3)
 #define OMAP3430_MCODE_SHIFT                            0
 #define OMAP3430_MCODE_MASK                             (0x7 << 0)
 
 /* PRM_VC_BYPASS_VAL */
-#define OMAP3430_VALID                                  (1 << 24)
+#define OMAP3430_VALID_MASK                             (1 << 24)
 #define OMAP3430_DATA_SHIFT                             16
 #define OMAP3430_DATA_MASK                              (0xff << 16)
 #define OMAP3430_REGADDR_SHIFT                          8
@@ -495,8 +495,8 @@
 #define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
 
 /* PRM_RSTCTRL */
-#define OMAP3430_RST_DPLL3                              (1 << 2)
-#define OMAP3430_RST_GS                                 (1 << 1)
+#define OMAP3430_RST_DPLL3_MASK                         (1 << 2)
+#define OMAP3430_RST_GS_MASK                            (1 << 1)
 
 /* PRM_RSTTIME */
 #define OMAP3430_RSTTIME2_SHIFT                         8
@@ -505,23 +505,23 @@
 #define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
 
 /* PRM_RSTST */
-#define OMAP3430_ICECRUSHER_RST                         (1 << 10)
-#define OMAP3430_ICEPICK_RST                            (1 << 9)
-#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST               (1 << 8)
-#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST               (1 << 7)
-#define OMAP3430_EXTERNAL_WARM_RST                      (1 << 6)
-#define OMAP3430_SECURE_WD_RST                          (1 << 5)
-#define OMAP3430_MPU_WD_RST                             (1 << 4)
-#define OMAP3430_SECURITY_VIOL_RST                      (1 << 3)
-#define OMAP3430_GLOBAL_SW_RST                          (1 << 1)
-#define OMAP3430_GLOBAL_COLD_RST                        (1 << 0)
+#define OMAP3430_ICECRUSHER_RST_MASK                    (1 << 10)
+#define OMAP3430_ICEPICK_RST_MASK                       (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK          (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK          (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST_MASK                 (1 << 6)
+#define OMAP3430_SECURE_WD_RST_MASK                     (1 << 5)
+#define OMAP3430_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST_MASK                 (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST_MASK                     (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
 
 /* PRM_VOLTCTRL */
-#define OMAP3430_SEL_VMODE                              (1 << 4)
-#define OMAP3430_SEL_OFF                                (1 << 3)
-#define OMAP3430_AUTO_OFF                               (1 << 2)
-#define OMAP3430_AUTO_RET                               (1 << 1)
-#define OMAP3430_AUTO_SLEEP                             (1 << 0)
+#define OMAP3430_SEL_VMODE_MASK                         (1 << 4)
+#define OMAP3430_SEL_OFF_MASK                           (1 << 3)
+#define OMAP3430_AUTO_OFF_MASK                          (1 << 2)
+#define OMAP3430_AUTO_RET_MASK                          (1 << 1)
+#define OMAP3430_AUTO_SLEEP_MASK                        (1 << 0)
 
 /* PRM_SRAM_PCHARGE */
 #define OMAP3430_PCHARGE_TIME_SHIFT                     0
@@ -550,10 +550,10 @@
 #define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
 
 /* PRM_POLCTRL */
-#define OMAP3430_OFFMODE_POL                            (1 << 3)
-#define OMAP3430_CLKOUT_POL                             (1 << 2)
-#define OMAP3430_CLKREQ_POL                             (1 << 1)
-#define OMAP3430_EXTVOL_POL                             (1 << 0)
+#define OMAP3430_OFFMODE_POL_MASK                       (1 << 3)
+#define OMAP3430_CLKOUT_POL_MASK                        (1 << 2)
+#define OMAP3430_CLKREQ_POL_MASK                        (1 << 1)
+#define OMAP3430_EXTVOL_POL_MASK                        (1 << 0)
 
 /* PRM_VOLTSETUP2 */
 #define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 5fba2aa8932c..588873b9303a 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,8 +24,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)                               \
                 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
-#define OMAP44XX_CHIRONSS_REGADDR(module, reg)                          \
-                OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
+#define OMAP44XX_PRCM_MPU_REGADDR(module, reg)                          \
+                OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
 
 #include "prm44xx.h"
 
@@ -284,7 +284,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 #define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
 #define OMAP_ONLOADMODE_SHIFT                           1
 #define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
-#define OMAP_ENABLE                                     (1 << 0)
+#define OMAP_ENABLE_MASK                                (1 << 0)
 
 /* PRM_RSTTIME */
 /* Named RM_RSTTIME_WKUP on the 24xx */
@@ -296,8 +296,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 /* PRM_RSTCTRL */
 /* Named RM_RSTCTRL_WKUP on the 24xx */
 /* 2420 calls RST_DPLL3 'RST_DPLL' */
-#define OMAP_RST_DPLL3                                  (1 << 2)
-#define OMAP_RST_GS                                     (1 << 1)
+#define OMAP_RST_DPLL3_MASK                             (1 << 2)
+#define OMAP_RST_GS_MASK                                (1 << 1)
 
 
 /*
@@ -316,7 +316,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
  *       PM_PWSTST_NEON
  */
-#define OMAP_INTRANSITION                               (1 << 20)
+#define OMAP_INTRANSITION_MASK                          (1 << 20)
 
 
 /*
@@ -338,7 +338,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
  *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
  */
-#define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
+#define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
 
 /*
  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
@@ -347,7 +347,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  *
  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
  */
-#define OMAP_DOMAINWKUP_RST                             (1 << 2)
+#define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
 
 /*
  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
@@ -357,8 +357,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  *
  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
  */
-#define OMAP_GLOBALWARM_RST                             (1 << 1)
-#define OMAP_GLOBALCOLD_RST                             (1 << 0)
+#define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
+#define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
 
 /*
  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
@@ -382,7 +382,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
  *       PM_PWSTCTRL_NEON
  */
-#define OMAP_LOGICRETSTATE                              (1 << 2)
+#define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
 
 /*
  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index adb2558bb121..fe8ef26431e5 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx PRM instance offset macros
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -25,387 +25,726 @@
 
 /* PRM */
 
-
 /* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP4_REVISION_PRM_OFFSET                       0x0000
 #define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET                  0x0010
 #define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
+#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET                0x0014
 #define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
+#define OMAP4_PRM_IRQENABLE_MPU_OFFSET                  0x0018
 #define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
+#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET                0x001c
 #define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
+#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET               0x0020
 #define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
+#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET               0x0028
 #define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
+#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET                0x0030
 #define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
+#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET                0x0038
 #define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
+#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET          0x0040
 #define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
+#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET              0x0000
 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
+#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET             0x0004
 #define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
+#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET                  0x0008
 #define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
+#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET              0x000c
 #define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
+#define OMAP4_CM_SYS_CLKSEL_OFFSET                      0x0010
 #define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
 
 /* PRM.MPU_PRM register offsets */
+#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
+#define OMAP4_PM_MPU_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
+#define OMAP4_RM_MPU_RSTST_OFFSET                       0x0014
 #define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
+#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET                 0x0024
 #define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
 
 /* PRM.TESLA_PRM register offsets */
+#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET                 0x0000
 #define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
+#define OMAP4_PM_TESLA_PWRSTST_OFFSET                   0x0004
 #define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
+#define OMAP4_RM_TESLA_RSTCTRL_OFFSET                   0x0010
 #define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
+#define OMAP4_RM_TESLA_RSTST_OFFSET                     0x0014
 #define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
+#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET             0x0024
 #define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
 
 /* PRM.ABE_PRM register offsets */
+#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
+#define OMAP4_PM_ABE_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
+#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET                0x002c
 #define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
+#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET                   0x0030
 #define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
+#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET                 0x0034
 #define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
+#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET                  0x0038
 #define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
+#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET                0x003c
 #define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
+#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET                 0x0040
 #define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
+#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET               0x0044
 #define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
+#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET                0x0048
 #define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
+#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET              0x004c
 #define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
+#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET                0x0050
 #define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
+#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET              0x0054
 #define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
+#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET                0x0058
 #define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
+#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET              0x005c
 #define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
+#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET               0x0060
 #define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
+#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET             0x0064
 #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
+#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET                0x0068
 #define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
+#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET              0x006c
 #define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
+#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET                0x0070
 #define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
+#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET              0x0074
 #define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
+#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET                0x0078
 #define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
+#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET              0x007c
 #define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
+#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET                0x0080
 #define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
+#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET              0x0084
 #define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
+#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET                  0x0088
 #define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
+#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET                0x008c
 #define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
 
 /* PRM.ALWAYS_ON_PRM register offsets */
+#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET           0x0024
 #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
+#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET              0x0028
 #define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET            0x002c
 #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
+#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET              0x0030
 #define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET            0x0034
 #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
+#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET             0x0038
 #define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET           0x003c
 #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
 
 /* PRM.CORE_PRM register offsets */
+#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET                  0x0000
 #define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
+#define OMAP4_PM_CORE_PWRSTST_OFFSET                    0x0004
 #define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
+#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET               0x0024
 #define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
+#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET               0x0124
 #define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
+#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET               0x012c
 #define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
+#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET           0x0134
 #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
+#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET                  0x0210
 #define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
+#define OMAP4_RM_DUCATI_RSTST_OFFSET                    0x0214
 #define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
+#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET           0x0224
 #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
+#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET               0x0324
 #define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
+#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET               0x0424
 #define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
+#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET           0x042c
 #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
+#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET            0x0434
 #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
+#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET            0x043c
 #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
+#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET               0x0444
 #define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
+#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET           0x0454
 #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
+#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET           0x045c
 #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
+#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET             0x0464
 #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
+#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET               0x0524
 #define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
+#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET           0x052c
 #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
+#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET            0x0534
 #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
+#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET            0x0624
 #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
+#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET            0x062c
 #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
+#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET           0x0634
 #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
+#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET           0x063c
 #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
+#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET            0x0724
 #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
+#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET        0x072c
 #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
+#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET         0x0744
 #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
 
 /* PRM.IVAHD_PRM register offsets */
+#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET                 0x0000
 #define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
+#define OMAP4_PM_IVAHD_PWRSTST_OFFSET                   0x0004
 #define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
+#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET                   0x0010
 #define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
+#define OMAP4_RM_IVAHD_RSTST_OFFSET                     0x0014
 #define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
+#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET             0x0024
 #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
+#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET               0x002c
 #define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
 
 /* PRM.CAM_PRM register offsets */
+#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
+#define OMAP4_PM_CAM_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
+#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET                 0x0024
 #define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
+#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET                0x002c
 #define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
 
 /* PRM.DSS_PRM register offsets */
+#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
+#define OMAP4_PM_DSS_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
+#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET                   0x0020
 #define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
+#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET                 0x0024
 #define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
+#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET               0x002c
 #define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
 
 /* PRM.GFX_PRM register offsets */
+#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
+#define OMAP4_PM_GFX_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
+#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET                 0x0024
 #define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
 
 /* PRM.L3INIT_PRM register offsets */
+#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET                0x0000
 #define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
+#define OMAP4_PM_L3INIT_PWRSTST_OFFSET                  0x0004
 #define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
+#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET               0x0028
 #define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
+#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET             0x002c
 #define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
+#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET               0x0030
 #define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
+#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET             0x0034
 #define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
+#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET                0x0038
 #define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
+#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET              0x003c
 #define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
+#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET            0x0040
 #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
+#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET          0x0044
 #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
+#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET           0x0058
 #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
+#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET         0x005c
 #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
+#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET            0x0060
 #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
+#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET          0x0064
 #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
+#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET            0x0068
 #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
+#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET          0x006c
 #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
+#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET            0x007c
 #define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
+#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET             0x0084
 #define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
+#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET               0x0088
 #define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
+#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET             0x008c
 #define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
+#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET            0x0094
 #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
+#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET             0x0098
 #define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
+#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET           0x009c
 #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
+#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET            0x00ac
 #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
+#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET               0x00c0
 #define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
+#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET             0x00c4
 #define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
+#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET               0x00c8
 #define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
+#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET             0x00cc
 #define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
+#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET        0x00d0
 #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
+#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET      0x00d4
 #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
+#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET    0x00e4
 #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
 
 /* PRM.L4PER_PRM register offsets */
+#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET                 0x0000
 #define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
+#define OMAP4_PM_L4PER_PWRSTST_OFFSET                   0x0004
 #define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
+#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET               0x0024
 #define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
+#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET           0x0028
 #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
+#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET         0x002c
 #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
+#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET           0x0030
 #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
+#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET         0x0034
 #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
+#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET            0x0038
 #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
+#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET          0x003c
 #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
+#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET            0x0040
 #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
+#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET          0x0044
 #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
+#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET            0x0048
 #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
+#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET          0x004c
 #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
+#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET            0x0050
 #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
+#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET          0x0054
 #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
+#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET               0x005c
 #define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
+#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET               0x0060
 #define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
+#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET             0x0064
 #define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
+#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET               0x0068
 #define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
+#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET             0x006c
 #define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
+#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET               0x0070
 #define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
+#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET             0x0074
 #define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
+#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET               0x0078
 #define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
+#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET             0x007c
 #define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
+#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET               0x0080
 #define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
+#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET             0x0084
 #define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
+#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET             0x008c
 #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
+#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET               0x0090
 #define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
+#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET             0x0094
 #define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
+#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET               0x0098
 #define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
+#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET             0x009c
 #define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
+#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET                0x00a0
 #define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
+#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET              0x00a4
 #define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
+#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET                0x00a8
 #define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
+#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET              0x00ac
 #define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
+#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET                0x00b0
 #define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
+#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET              0x00b4
 #define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
+#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET                0x00b8
 #define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
+#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET              0x00bc
 #define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
+#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET            0x00c0
 #define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
+#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET              0x00d0
 #define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
+#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET            0x00d4
 #define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
+#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET              0x00d8
 #define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
+#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET            0x00dc
 #define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
+#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET              0x00e0
 #define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
+#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET            0x00e4
 #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
+#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET             0x00ec
 #define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
+#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET              0x00f0
 #define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
+#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET            0x00f4
 #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
+#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET              0x00f8
 #define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
+#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET            0x00fc
 #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
+#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET              0x0100
 #define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
+#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET            0x0104
 #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
+#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET              0x0108
 #define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
+#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET            0x010c
 #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
+#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET              0x0120
 #define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
+#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET            0x0124
 #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
+#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET              0x0128
 #define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
+#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET            0x012c
 #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
+#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET           0x0134
 #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
+#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET            0x0138
 #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
+#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET          0x013c
 #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
+#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET               0x0140
 #define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
+#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET             0x0144
 #define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
+#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET               0x0148
 #define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
+#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET             0x014c
 #define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
+#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET               0x0150
 #define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
+#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET             0x0154
 #define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
+#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET               0x0158
 #define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
+#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET             0x015c
 #define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
+#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET              0x0160
 #define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
+#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET            0x0164
 #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
+#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET                0x0168
 #define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
+#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET              0x016c
 #define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
+#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET              0x01a4
 #define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
+#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET              0x01ac
 #define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
+#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET           0x01b4
 #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
+#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET          0x01bc
 #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
+#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET               0x01c4
 #define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
+#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET          0x01cc
 #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
+#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET         0x01dc
 #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
 
 /* PRM.CEFUSE_PRM register offsets */
+#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET                0x0000
 #define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
+#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET                  0x0004
 #define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
+#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET           0x0024
 #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
 
 /* PRM.WKUP_PRM register offsets */
+#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET             0x0024
 #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
+#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET               0x002c
 #define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
+#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET                 0x0030
 #define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
+#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET               0x0034
 #define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
+#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET                0x0038
 #define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
+#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET              0x003c
 #define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
+#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET               0x0040
 #define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
+#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET             0x0044
 #define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
+#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET              0x0048
 #define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
+#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET            0x004c
 #define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
+#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET          0x0054
 #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
+#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET                 0x0058
 #define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
+#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET               0x005c
 #define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
+#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET             0x0064
 #define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
+#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET             0x0078
 #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
+#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET           0x007c
 #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
+#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET                  0x0080
 #define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
+#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET                0x0084
 #define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
 
 /* PRM.WKUP_CM register offsets */
+#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET                  0x0000
 #define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
+#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET             0x0020
 #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
+#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET               0x0028
 #define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
+#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET               0x0030
 #define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
+#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET              0x0038
 #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
+#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET             0x0040
 #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
+#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET            0x0048
 #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
+#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET          0x0050
 #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
+#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET               0x0058
 #define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
+#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET             0x0060
 #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
+#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET           0x0078
 #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
+#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET                0x0080
 #define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
+#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET            0x0088
 #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
 
 /* PRM.EMU_PRM register offsets */
+#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET                   0x0000
 #define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
+#define OMAP4_PM_EMU_PWRSTST_OFFSET                     0x0004
 #define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
+#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET             0x0024
 #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
 
 /* PRM.EMU_CM register offsets */
+#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET                   0x0000
 #define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
+#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET                  0x0008
 #define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
+#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET             0x0020
 #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
 
 /* PRM.DEVICE_PRM register offsets */
+#define OMAP4_PRM_RSTCTRL_OFFSET                        0x0000
 #define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
+#define OMAP4_PRM_RSTST_OFFSET                          0x0004
 #define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
+#define OMAP4_PRM_RSTTIME_OFFSET                        0x0008
 #define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
+#define OMAP4_PRM_CLKREQCTRL_OFFSET                     0x000c
 #define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
+#define OMAP4_PRM_VOLTCTRL_OFFSET                       0x0010
 #define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
+#define OMAP4_PRM_PWRREQCTRL_OFFSET                     0x0014
 #define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
+#define OMAP4_PRM_PSCON_COUNT_OFFSET                    0x0018
 #define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
+#define OMAP4_PRM_IO_COUNT_OFFSET                       0x001c
 #define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
+#define OMAP4_PRM_IO_PMCTRL_OFFSET                      0x0020
 #define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
+#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET            0x0024
 #define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
+#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET             0x0028
 #define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
+#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET              0x002c
 #define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
+#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET              0x0030
 #define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
+#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET       0x0034
 #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
+#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET        0x0038
 #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
+#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET        0x003c
 #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
+#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET                 0x0040
 #define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
+#define OMAP4_PRM_VP_CORE_STATUS_OFFSET                 0x0044
 #define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
+#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET               0x0048
 #define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
+#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET                0x004c
 #define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
+#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET               0x0050
 #define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
+#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET               0x0054
 #define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
+#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET                  0x0058
 #define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
+#define OMAP4_PRM_VP_MPU_STATUS_OFFSET                  0x005c
 #define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
+#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET                0x0060
 #define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
+#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET                 0x0064
 #define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
+#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET                0x0068
 #define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
+#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET                0x006c
 #define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
+#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET                  0x0070
 #define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
+#define OMAP4_PRM_VP_IVA_STATUS_OFFSET                  0x0074
 #define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
+#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET                0x0078
 #define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
+#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET                 0x007c
 #define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
+#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET                0x0080
 #define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
+#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET                0x0084
 #define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
+#define OMAP4_PRM_VC_SMPS_SA_OFFSET                     0x0088
 #define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
+#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET             0x008c
 #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
+#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET             0x0090
 #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
+#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET          0x0094
 #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
+#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET           0x0098
 #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
+#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET           0x009c
 #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
+#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET                  0x00a0
 #define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
+#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET                 0x00a4
 #define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
+#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET                0x00a8
 #define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
+#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET                 0x00ac
 #define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
+#define OMAP4_PRM_SRAM_COUNT_OFFSET                     0x00b0
 #define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
+#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET                0x00b4
 #define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
+#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET            0x00b8
 #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
+#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET             0x00bc
 #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
+#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET             0x00c0
 #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
+#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET              0x00c4
 #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
+#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET             0x00c8
 #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
+#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET              0x00cc
 #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
+#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET              0x00d0
 #define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
+#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET               0x00d4
 #define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
+#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET              0x00d8
 #define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
+#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET               0x00dc
 #define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
+#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET               0x00e0
 #define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET                0x00e4
 #define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
+#define OMAP4_PRM_PHASE1_CNDP_OFFSET                    0x00e8
 #define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
+#define OMAP4_PRM_PHASE2A_CNDP_OFFSET                   0x00ec
 #define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
+#define OMAP4_PRM_PHASE2B_CNDP_OFFSET                   0x00f0
 #define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
+#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
 #define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
 
-/* CHIRON_PRCM */
-
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
 
-/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
+#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
 
-/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
-#define OMAP4430_CHIRON_PRCM_PRM_RSTST                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+/* PRCM_MPU.DEVICE_PRM register offsets */
+#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
+#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
 
-/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
-#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU0_PWRSTST                    OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+/* PRCM_MPU.CPU0 register offsets */
+#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
+#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
+#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
+#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
+#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
+#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
+#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
 
-/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
-#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU1_PWRSTST                    OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                 OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL               OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                  OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+/* PRCM_MPU.CPU1 register offsets */
+#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
+#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
+#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
+#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
+#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
+#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
+#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
 #endif
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 5261a0923691..7190cbd92620 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -12,14 +12,12 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/mutex.h>
-#include <linux/platform_device.h>
 #include <linux/cpufreq.h>
 #include <linux/debugfs.h>
 #include <linux/io.h>
@@ -32,9 +30,9 @@ static DEFINE_SPINLOCK(clockfw_lock);
 
 static struct clk_functions *arch_clock;
 
-/*-------------------------------------------------------------------------
+/*
  * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
+ */
 
 int clk_enable(struct clk *clk)
 {
@@ -92,9 +90,9 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-/*-------------------------------------------------------------------------
+/*
  * Optional clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
+ */
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
@@ -140,9 +138,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
         unsigned long flags;
         int ret = -EINVAL;
 
-        if (cpu_is_omap44xx())
-        /* OMAP4 clk framework not supported yet */
-                return 0;
         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
                 return ret;
 
@@ -169,9 +164,9 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
-/*-------------------------------------------------------------------------
+/*
  * OMAP specific clock functions shared between omap1 and omap2
- *-------------------------------------------------------------------------*/
+ */
 
 int __initdata mpurate;
 
@@ -222,7 +217,7 @@ void clk_reparent(struct clk *child, struct clk *parent)
 }
 
 /* Propagate rate to children */
-void propagate_rate(struct clk * tclk)
+void propagate_rate(struct clk *tclk)
 {
         struct clk *clkp;
 
@@ -389,7 +384,9 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 }
 #endif
 
-/*-------------------------------------------------------------------------*/
+/*
+ *
+ */
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 /*
@@ -404,7 +401,7 @@ static int __init clk_disable_unused(void)
                 if (ck->ops == &clkops_null)
                         continue;
 
-                if (ck->usecount > 0 || ck->enable_reg == 0)
+                if (ck->usecount > 0 || !ck->enable_reg)
                         continue;
 
                 spin_lock_irqsave(&clockfw_lock, flags);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 4d99dfbc8bef..c64875f11fac 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -264,8 +264,8 @@ static struct omap_dm_timer omap4_dm_timers[] = {
         { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
 };
 static const char *omap4_dm_source_names[] __initdata = {
-        "sys_ck",
-        "omap_32k_fck",
+        "sys_clkin_ck",
+        "sys_32k_ck",
         NULL
 };
 static struct clk *omap4_dm_source_clocks[2];
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 34f7fa9ad4c0..dfc472ca0cc4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -196,15 +196,15 @@ extern struct clk dummy_ck;
 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 
 /* Clksel_rate flags */
-#define DEFAULT_RATE            (1 << 0)
-#define RATE_IN_242X            (1 << 1)
-#define RATE_IN_243X            (1 << 2)
-#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
-#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
-#define RATE_IN_36XX            (1 << 5)
-#define RATE_IN_4430            (1 << 6)
+#define RATE_IN_242X            (1 << 0)
+#define RATE_IN_243X            (1 << 1)
+#define RATE_IN_3XXX            (1 << 2)        /* rates common to all OMAP3 */
+#define RATE_IN_3430ES2         (1 << 3)        /* 3430ES2 rates only */
+#define RATE_IN_36XX            (1 << 4)
+#define RATE_IN_4430            (1 << 5)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 
+#define RATE_IN_3430ES2PLUS     (RATE_IN_3430ES2 | RATE_IN_36XX)
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index bb94a0baee8a..8b3f12ff5cbc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -30,6 +30,7 @@
 #define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
 #define OMAP4430_CM2_BASE               0x4a008000
 #define OMAP4430_PRM_BASE               0x4a306000
+#define OMAP4430_PRCM_MPU_BASE          0x48243000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
 #define OMAP443X_CTRL_BASE              0x4a100000
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 36d6ea56ab51..0eccc09ac4a9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -176,9 +176,8 @@ struct omap_hwmod_addr_space {
 #define OCP_USER_SDMA                   (1 << 1)
 
 /* omap_hwmod_ocp_if.flags bits */
-#define OCPIF_HAS_IDLEST                (1 << 0)
-#define OCPIF_SWSUP_IDLE                (1 << 1)
-#define OCPIF_CAN_BURST                 (1 << 2)
+#define OCPIF_SWSUP_IDLE                (1 << 0)
+#define OCPIF_CAN_BURST                 (1 << 1)
 
 /**
  * struct omap_hwmod_ocp_if - OCP interface data
@@ -327,14 +326,12 @@ struct omap_hwmod_omap2_prcm {
 
 /**
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
- * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
- * @device_offs: device register offset from @module_offs
+ * @clkctrl_reg: PRCM address of the clock control register
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
-        u32 module_offs;
-        u16 device_offs;
-        u8 submodule_wkdep_bit;
+        void __iomem    *clkctrl_reg;
+        u8              submodule_wkdep_bit;
 };
 
 
@@ -353,6 +350,8 @@ struct omap_hwmod_omap4_prcm {
  *     when module is enabled, rather than the default, which is to
  *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
+ * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
+ *     only for few initiator modules on OMAP2 & 3.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -360,6 +359,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
 #define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
 #define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
+#define HWMOD_NO_IDLEST                         (1 << 6)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index d82b2c00d4f1..fb6ec74fe39e 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -31,6 +31,7 @@
 #define PWRDM_MAX_PWRSTS        4
 
 /* Powerdomain allowable state bitfields */
+#define PWRSTS_ON               (1 << PWRDM_POWER_ON)
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_ON))
 
@@ -49,6 +50,12 @@
                                           * in MEM bank 1 position. This is
                                           * true for OMAP3430
                                           */
+#define PWRDM_HAS_LOWPOWERSTATECHANGE   (1 << 2) /*
+                                                  * support to transition from a
+                                                  * sleep state to a lower sleep
+                                                  * state without waking up the
+                                                  * powerdomain
+                                                  */
 
 /*
  * Number of memory banks that are power-controllable.  On OMAP4430, the
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 0f5197479513..f899603051ac 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -2,10 +2,10 @@
  * omap_device implementation
  *
  * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
+ * Paul Walmsley, Kevin Hilman
  *
  * Developed in collaboration with (alphabetical order): Benoit
- * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
+ * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
  * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
  * Woodruff
  *