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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/board.txt32
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts43
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts19
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts56
-rw-r--r--arch/powerpc/configs/85xx/mpc8572_ds_defconfig43
-rw-r--r--arch/powerpc/include/asm/qe.h37
-rw-r--r--arch/powerpc/include/asm/qe_ic.h21
-rw-r--r--arch/powerpc/platforms/83xx/mpc831x_rdb.c2
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_mds.c9
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_rdb.c5
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_mds.c81
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_rdk.c6
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_mds.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_rdb.c2
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c7
-rw-r--r--arch/powerpc/platforms/85xx/smp.c1
-rw-r--r--arch/powerpc/platforms/Kconfig11
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype2
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c7
-rw-r--r--arch/powerpc/sysdev/fsl_soc.h5
-rw-r--r--arch/powerpc/sysdev/qe_lib/Kconfig3
-rw-r--r--arch/powerpc/sysdev/qe_lib/gpio.c195
-rw-r--r--arch/powerpc/sysdev/simple_gpio.c155
-rw-r--r--arch/powerpc/sysdev/simple_gpio.h12
26 files changed, 686 insertions, 71 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index 81a917ef96e9..6c974d28eeb4 100644
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -18,7 +18,7 @@ This is the memory-mapped registers for on board FPGA.
18 18
19Required properities: 19Required properities:
20- compatible : should be "fsl,fpga-pixis". 20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the lenght of the FPPGA register 21- reg : should contain the address and the length of the FPPGA register
22 set. 22 set.
23 23
24Example (MPC8610HPCD): 24Example (MPC8610HPCD):
@@ -27,3 +27,33 @@ Example (MPC8610HPCD):
27 compatible = "fsl,fpga-pixis"; 27 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>; 28 reg = <0xe8000000 32>;
29 }; 29 };
30
31* Freescale BCSR GPIO banks
32
33Some BCSR registers act as simple GPIO controllers, each such
34register can be represented by the gpio-controller node.
35
36Required properities:
37- compatible : Should be "fsl,<board>-bcsr-gpio".
38- reg : Should contain the address and the length of the GPIO bank
39 register.
40- #gpio-cells : Should be two. The first cell is the pin number and the
41 second cell is used to specify optional paramters (currently unused).
42- gpio-controller : Marks the port as GPIO controller.
43
44Example:
45
46 bcsr@1,0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8360mds-bcsr";
50 reg = <1 0 0x8000>;
51 ranges = <0 1 0 0x8000>;
52
53 bcsr13: gpio-controller@d {
54 #gpio-cells = <2>;
55 compatible = "fsl,mpc8360mds-bcsr-gpio";
56 reg = <0xd 1>;
57 gpio-controller;
58 };
59 };
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 14534d04e4db..6e34f170fa62 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -69,8 +69,18 @@
69 }; 69 };
70 70
71 bcsr@1,0 { 71 bcsr@1,0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
72 compatible = "fsl,mpc8360mds-bcsr"; 74 compatible = "fsl,mpc8360mds-bcsr";
73 reg = <1 0 0x8000>; 75 reg = <1 0 0x8000>;
76 ranges = <0 1 0 0x8000>;
77
78 bcsr13: gpio-controller@d {
79 #gpio-cells = <2>;
80 compatible = "fsl,mpc8360mds-bcsr-gpio";
81 reg = <0xd 1>;
82 gpio-controller;
83 };
74 }; 84 };
75 }; 85 };
76 86
@@ -195,10 +205,21 @@
195 }; 205 };
196 206
197 par_io@1400 { 207 par_io@1400 {
208 #address-cells = <1>;
209 #size-cells = <1>;
198 reg = <0x1400 0x100>; 210 reg = <0x1400 0x100>;
211 ranges = <0 0x1400 0x100>;
199 device_type = "par_io"; 212 device_type = "par_io";
200 num-ports = <7>; 213 num-ports = <7>;
201 214
215 qe_pio_b: gpio-controller@18 {
216 #gpio-cells = <2>;
217 compatible = "fsl,mpc8360-qe-pario-bank",
218 "fsl,mpc8323-qe-pario-bank";
219 reg = <0x18 0x18>;
220 gpio-controller;
221 };
222
202 pio1: ucc_pin@01 { 223 pio1: ucc_pin@01 {
203 pio-map = < 224 pio-map = <
204 /* port pin dir open_drain assignment has_irq */ 225 /* port pin dir open_drain assignment has_irq */
@@ -282,6 +303,15 @@
282 }; 303 };
283 }; 304 };
284 305
306 timer@440 {
307 compatible = "fsl,mpc8360-qe-gtm",
308 "fsl,qe-gtm", "fsl,gtm";
309 reg = <0x440 0x40>;
310 clock-frequency = <132000000>;
311 interrupts = <12 13 14 15>;
312 interrupt-parent = <&qeic>;
313 };
314
285 spi@4c0 { 315 spi@4c0 {
286 cell-index = <0>; 316 cell-index = <0>;
287 compatible = "fsl,spi"; 317 compatible = "fsl,spi";
@@ -301,11 +331,20 @@
301 }; 331 };
302 332
303 usb@6c0 { 333 usb@6c0 {
304 compatible = "qe_udc"; 334 compatible = "fsl,mpc8360-qe-usb",
335 "fsl,mpc8323-qe-usb";
305 reg = <0x6c0 0x40 0x8b00 0x100>; 336 reg = <0x6c0 0x40 0x8b00 0x100>;
306 interrupts = <11>; 337 interrupts = <11>;
307 interrupt-parent = <&qeic>; 338 interrupt-parent = <&qeic>;
308 mode = "slave"; 339 fsl,fullspeed-clock = "clk21";
340 fsl,lowspeed-clock = "brg9";
341 gpios = <&qe_pio_b 2 0 /* USBOE */
342 &qe_pio_b 3 0 /* USBTP */
343 &qe_pio_b 8 0 /* USBTN */
344 &qe_pio_b 9 0 /* USBRP */
345 &qe_pio_b 11 0 /* USBRN */
346 &bcsr13 5 0 /* SPEED */
347 &bcsr13 4 1>; /* POWER */
309 }; 348 };
310 349
311 enet0: ucc@2000 { 350 enet0: ucc@2000 {
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index decadf3d9e98..37b789510d68 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -218,8 +218,23 @@
218 reg = <0x440 0x40>; 218 reg = <0x440 0x40>;
219 interrupts = <12 13 14 15>; 219 interrupts = <12 13 14 15>;
220 interrupt-parent = <&qeic>; 220 interrupt-parent = <&qeic>;
221 /* filled by u-boot */ 221 clock-frequency = <166666666>;
222 clock-frequency = <0>; 222 };
223
224 usb@6c0 {
225 compatible = "fsl,mpc8360-qe-usb",
226 "fsl,mpc8323-qe-usb";
227 reg = <0x6c0 0x40 0x8b00 0x100>;
228 interrupts = <11>;
229 interrupt-parent = <&qeic>;
230 fsl,fullspeed-clock = "clk21";
231 gpios = <&qe_pio_b 2 0 /* USBOE */
232 &qe_pio_b 3 0 /* USBTP */
233 &qe_pio_b 8 0 /* USBTN */
234 &qe_pio_b 9 0 /* USBRP */
235 &qe_pio_b 11 0 /* USBRN */
236 &qe_pio_e 20 0 /* SPEED */
237 &qe_pio_e 21 1 /* POWER */>;
223 }; 238 };
224 239
225 spi@4c0 { 240 spi@4c0 {
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 35d5e248ccd7..4481532cbe77 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -26,7 +26,13 @@
26 serial1 = &serial1; 26 serial1 = &serial1;
27 pci0 = &pci0; 27 pci0 = &pci0;
28 pci1 = &pci1; 28 pci1 = &pci1;
29 rapidio0 = &rapidio0; 29/*
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
34 */
35 /* rapidio0 = &rapidio0; */
30 }; 36 };
31 37
32 cpus { 38 cpus {
@@ -62,18 +68,17 @@
62 reg = <0x00000000 0x40000000>; // 1G at 0x0 68 reg = <0x00000000 0x40000000>; // 1G at 0x0
63 }; 69 };
64 70
65 localbus@f8005000 { 71 localbus@ffe05000 {
66 #address-cells = <2>; 72 #address-cells = <2>;
67 #size-cells = <1>; 73 #size-cells = <1>;
68 compatible = "fsl,mpc8641-localbus", "simple-bus"; 74 compatible = "fsl,mpc8641-localbus", "simple-bus";
69 reg = <0xf8005000 0x1000>; 75 reg = <0xffe05000 0x1000>;
70 interrupts = <19 2>; 76 interrupts = <19 2>;
71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>;
72 78
73 ranges = <0 0 0xff800000 0x00800000 79 ranges = <0 0 0xef800000 0x00800000
74 1 0 0xfe000000 0x01000000 80 2 0 0xffdf8000 0x00008000
75 2 0 0xf8200000 0x00100000 81 3 0 0xffdf0000 0x00008000>;
76 3 0 0xf8100000 0x00100000>;
77 82
78 flash@0,0 { 83 flash@0,0 {
79 compatible = "cfi-flash"; 84 compatible = "cfi-flash";
@@ -103,13 +108,13 @@
103 }; 108 };
104 }; 109 };
105 110
106 soc8641@f8000000 { 111 soc8641@ffe00000 {
107 #address-cells = <1>; 112 #address-cells = <1>;
108 #size-cells = <1>; 113 #size-cells = <1>;
109 device_type = "soc"; 114 device_type = "soc";
110 compatible = "simple-bus"; 115 compatible = "simple-bus";
111 ranges = <0x00000000 0xf8000000 0x00100000>; 116 ranges = <0x00000000 0xffe00000 0x00100000>;
112 reg = <0xf8000000 0x00001000>; // CCSRBAR 117 reg = <0xffe00000 0x00001000>; // CCSRBAR
113 bus-frequency = <0>; 118 bus-frequency = <0>;
114 119
115 i2c@3000 { 120 i2c@3000 {
@@ -340,17 +345,17 @@
340 }; 345 };
341 }; 346 };
342 347
343 pci0: pcie@f8008000 { 348 pci0: pcie@ffe08000 {
344 cell-index = <0>; 349 cell-index = <0>;
345 compatible = "fsl,mpc8641-pcie"; 350 compatible = "fsl,mpc8641-pcie";
346 device_type = "pci"; 351 device_type = "pci";
347 #interrupt-cells = <1>; 352 #interrupt-cells = <1>;
348 #size-cells = <2>; 353 #size-cells = <2>;
349 #address-cells = <3>; 354 #address-cells = <3>;
350 reg = <0xf8008000 0x1000>; 355 reg = <0xffe08000 0x1000>;
351 bus-range = <0x0 0xff>; 356 bus-range = <0x0 0xff>;
352 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 357 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
353 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 358 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
354 clock-frequency = <33333333>; 359 clock-frequency = <33333333>;
355 interrupt-parent = <&mpic>; 360 interrupt-parent = <&mpic>;
356 interrupts = <24 2>; 361 interrupts = <24 2>;
@@ -481,7 +486,7 @@
481 486
482 0x01000000 0x0 0x00000000 487 0x01000000 0x0 0x00000000
483 0x01000000 0x0 0x00000000 488 0x01000000 0x0 0x00000000
484 0x0 0x00100000>; 489 0x0 0x00010000>;
485 uli1575@0 { 490 uli1575@0 {
486 reg = <0 0 0 0 0>; 491 reg = <0 0 0 0 0>;
487 #size-cells = <2>; 492 #size-cells = <2>;
@@ -491,7 +496,7 @@
491 0x0 0x20000000 496 0x0 0x20000000
492 0x01000000 0x0 0x00000000 497 0x01000000 0x0 0x00000000
493 0x01000000 0x0 0x00000000 498 0x01000000 0x0 0x00000000
494 0x0 0x00100000>; 499 0x0 0x00010000>;
495 isa@1e { 500 isa@1e {
496 device_type = "isa"; 501 device_type = "isa";
497 #interrupt-cells = <2>; 502 #interrupt-cells = <2>;
@@ -549,17 +554,17 @@
549 554
550 }; 555 };
551 556
552 pci1: pcie@f8009000 { 557 pci1: pcie@ffe09000 {
553 cell-index = <1>; 558 cell-index = <1>;
554 compatible = "fsl,mpc8641-pcie"; 559 compatible = "fsl,mpc8641-pcie";
555 device_type = "pci"; 560 device_type = "pci";
556 #interrupt-cells = <1>; 561 #interrupt-cells = <1>;
557 #size-cells = <2>; 562 #size-cells = <2>;
558 #address-cells = <3>; 563 #address-cells = <3>;
559 reg = <0xf8009000 0x1000>; 564 reg = <0xffe09000 0x1000>;
560 bus-range = <0 0xff>; 565 bus-range = <0 0xff>;
561 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 566 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
562 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 567 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
563 clock-frequency = <33333333>; 568 clock-frequency = <33333333>;
564 interrupt-parent = <&mpic>; 569 interrupt-parent = <&mpic>;
565 interrupts = <25 2>; 570 interrupts = <25 2>;
@@ -582,18 +587,21 @@
582 587
583 0x01000000 0x0 0x00000000 588 0x01000000 0x0 0x00000000
584 0x01000000 0x0 0x00000000 589 0x01000000 0x0 0x00000000
585 0x0 0x00100000>; 590 0x0 0x00010000>;
586 }; 591 };
587 }; 592 };
588 rapidio0: rapidio@f80c0000 { 593/*
594 rapidio0: rapidio@ffec0000 {
589 #address-cells = <2>; 595 #address-cells = <2>;
590 #size-cells = <2>; 596 #size-cells = <2>;
591 compatible = "fsl,rapidio-delta"; 597 compatible = "fsl,rapidio-delta";
592 reg = <0xf80c0000 0x20000>; 598 reg = <0xffec0000 0x20000>;
593 ranges = <0 0 0xc0000000 0 0x20000000>; 599 ranges = <0 0 0x80000000 0 0x20000000>;
594 interrupt-parent = <&mpic>; 600 interrupt-parent = <&mpic>;
595 /* err_irq bell_outb_irq bell_inb_irq 601 // err_irq bell_outb_irq bell_inb_irq
596 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */ 602 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
597 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>; 603 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;
598 }; 604 };
605*/
606
599}; 607};
diff --git a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
index 635588319e0d..32aeb79216f7 100644
--- a/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc3 3# Linux kernel version: 2.6.28-rc8
4# Sat Nov 8 12:40:13 2008 4# Tue Dec 30 11:17:46 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -21,7 +21,10 @@ CONFIG_FSL_BOOKE=y
21CONFIG_FSL_EMB_PERFMON=y 21CONFIG_FSL_EMB_PERFMON=y
22# CONFIG_PHYS_64BIT is not set 22# CONFIG_PHYS_64BIT is not set
23CONFIG_SPE=y 23CONFIG_SPE=y
24CONFIG_PPC_MMU_NOHASH=y
24# CONFIG_PPC_MM_SLICES is not set 25# CONFIG_PPC_MM_SLICES is not set
26CONFIG_SMP=y
27CONFIG_NR_CPUS=2
25CONFIG_PPC32=y 28CONFIG_PPC32=y
26CONFIG_WORD_SIZE=32 29CONFIG_WORD_SIZE=32
27# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set 30# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
@@ -50,7 +53,7 @@ CONFIG_ARCH_MAY_HAVE_PC_FDC=y
50CONFIG_PPC_OF=y 53CONFIG_PPC_OF=y
51CONFIG_OF=y 54CONFIG_OF=y
52CONFIG_PPC_UDBG_16550=y 55CONFIG_PPC_UDBG_16550=y
53# CONFIG_GENERIC_TBSYNC is not set 56CONFIG_GENERIC_TBSYNC=y
54CONFIG_AUDIT_ARCH=y 57CONFIG_AUDIT_ARCH=y
55CONFIG_GENERIC_BUG=y 58CONFIG_GENERIC_BUG=y
56CONFIG_DEFAULT_UIMAGE=y 59CONFIG_DEFAULT_UIMAGE=y
@@ -62,7 +65,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
62# General setup 65# General setup
63# 66#
64CONFIG_EXPERIMENTAL=y 67CONFIG_EXPERIMENTAL=y
65CONFIG_BROKEN_ON_SMP=y 68CONFIG_LOCK_KERNEL=y
66CONFIG_INIT_ENV_ARG_LIMIT=32 69CONFIG_INIT_ENV_ARG_LIMIT=32
67CONFIG_LOCALVERSION="" 70CONFIG_LOCALVERSION=""
68CONFIG_LOCALVERSION_AUTO=y 71CONFIG_LOCALVERSION_AUTO=y
@@ -126,6 +129,7 @@ CONFIG_HAVE_IOREMAP_PROT=y
126CONFIG_HAVE_KPROBES=y 129CONFIG_HAVE_KPROBES=y
127CONFIG_HAVE_KRETPROBES=y 130CONFIG_HAVE_KRETPROBES=y
128CONFIG_HAVE_ARCH_TRACEHOOK=y 131CONFIG_HAVE_ARCH_TRACEHOOK=y
132CONFIG_USE_GENERIC_SMP_HELPERS=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 133# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
130CONFIG_SLABINFO=y 134CONFIG_SLABINFO=y
131CONFIG_RT_MUTEXES=y 135CONFIG_RT_MUTEXES=y
@@ -138,6 +142,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
138CONFIG_MODVERSIONS=y 142CONFIG_MODVERSIONS=y
139# CONFIG_MODULE_SRCVERSION_ALL is not set 143# CONFIG_MODULE_SRCVERSION_ALL is not set
140CONFIG_KMOD=y 144CONFIG_KMOD=y
145CONFIG_STOP_MACHINE=y
141CONFIG_BLOCK=y 146CONFIG_BLOCK=y
142CONFIG_LBD=y 147CONFIG_LBD=y
143# CONFIG_BLK_DEV_IO_TRACE is not set 148# CONFIG_BLK_DEV_IO_TRACE is not set
@@ -197,6 +202,7 @@ CONFIG_PPC_I8259=y
197# CONFIG_CPM2 is not set 202# CONFIG_CPM2 is not set
198CONFIG_FSL_ULI1575=y 203CONFIG_FSL_ULI1575=y
199# CONFIG_MPC8xxx_GPIO is not set 204# CONFIG_MPC8xxx_GPIO is not set
205# CONFIG_SIMPLE_GPIO is not set
200 206
201# 207#
202# Kernel options 208# Kernel options
@@ -224,6 +230,7 @@ CONFIG_MATH_EMULATION=y
224CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 230CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
225CONFIG_ARCH_HAS_WALK_MEMORY=y 231CONFIG_ARCH_HAS_WALK_MEMORY=y
226CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y 232CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
233# CONFIG_IRQ_ALL_CPUS is not set
227CONFIG_ARCH_FLATMEM_ENABLE=y 234CONFIG_ARCH_FLATMEM_ENABLE=y
228CONFIG_ARCH_POPULATES_NODE_MAP=y 235CONFIG_ARCH_POPULATES_NODE_MAP=y
229CONFIG_SELECT_MEMORY_MODEL=y 236CONFIG_SELECT_MEMORY_MODEL=y
@@ -241,6 +248,9 @@ CONFIG_ZONE_DMA_FLAG=1
241CONFIG_BOUNCE=y 248CONFIG_BOUNCE=y
242CONFIG_VIRT_TO_BUS=y 249CONFIG_VIRT_TO_BUS=y
243CONFIG_UNEVICTABLE_LRU=y 250CONFIG_UNEVICTABLE_LRU=y
251CONFIG_PPC_4K_PAGES=y
252# CONFIG_PPC_16K_PAGES is not set
253# CONFIG_PPC_64K_PAGES is not set
244CONFIG_FORCE_MAX_ZONEORDER=11 254CONFIG_FORCE_MAX_ZONEORDER=11
245CONFIG_PROC_DEVICETREE=y 255CONFIG_PROC_DEVICETREE=y
246# CONFIG_CMDLINE_BOOL is not set 256# CONFIG_CMDLINE_BOOL is not set
@@ -443,8 +453,10 @@ CONFIG_MISC_DEVICES=y
443# CONFIG_EEPROM_93CX6 is not set 453# CONFIG_EEPROM_93CX6 is not set
444# CONFIG_SGI_IOC4 is not set 454# CONFIG_SGI_IOC4 is not set
445# CONFIG_TIFM_CORE is not set 455# CONFIG_TIFM_CORE is not set
456# CONFIG_ICS932S401 is not set
446# CONFIG_ENCLOSURE_SERVICES is not set 457# CONFIG_ENCLOSURE_SERVICES is not set
447# CONFIG_HP_ILO is not set 458# CONFIG_HP_ILO is not set
459# CONFIG_C2PORT is not set
448CONFIG_HAVE_IDE=y 460CONFIG_HAVE_IDE=y
449# CONFIG_IDE is not set 461# CONFIG_IDE is not set
450 462
@@ -784,6 +796,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y
784CONFIG_UNIX98_PTYS=y 796CONFIG_UNIX98_PTYS=y
785CONFIG_LEGACY_PTYS=y 797CONFIG_LEGACY_PTYS=y
786CONFIG_LEGACY_PTY_COUNT=256 798CONFIG_LEGACY_PTY_COUNT=256
799# CONFIG_HVC_UDBG is not set
787# CONFIG_IPMI_HANDLER is not set 800# CONFIG_IPMI_HANDLER is not set
788CONFIG_HW_RANDOM=y 801CONFIG_HW_RANDOM=y
789CONFIG_NVRAM=y 802CONFIG_NVRAM=y
@@ -869,11 +882,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
869# CONFIG_THERMAL is not set 882# CONFIG_THERMAL is not set
870# CONFIG_THERMAL_HWMON is not set 883# CONFIG_THERMAL_HWMON is not set
871# CONFIG_WATCHDOG is not set 884# CONFIG_WATCHDOG is not set
885CONFIG_SSB_POSSIBLE=y
872 886
873# 887#
874# Sonics Silicon Backplane 888# Sonics Silicon Backplane
875# 889#
876CONFIG_SSB_POSSIBLE=y
877# CONFIG_SSB is not set 890# CONFIG_SSB is not set
878 891
879# 892#
@@ -886,14 +899,7 @@ CONFIG_SSB_POSSIBLE=y
886# CONFIG_PMIC_DA903X is not set 899# CONFIG_PMIC_DA903X is not set
887# CONFIG_MFD_WM8400 is not set 900# CONFIG_MFD_WM8400 is not set
888# CONFIG_MFD_WM8350_I2C is not set 901# CONFIG_MFD_WM8350_I2C is not set
889
890#
891# Voltage and Current regulators
892#
893# CONFIG_REGULATOR is not set 902# CONFIG_REGULATOR is not set
894# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
895# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
896# CONFIG_REGULATOR_BQ24022 is not set
897 903
898# 904#
899# Multimedia devices 905# Multimedia devices
@@ -1252,11 +1258,11 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1252# CONFIG_USB_TMC is not set 1258# CONFIG_USB_TMC is not set
1253 1259
1254# 1260#
1255# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1261# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
1256# 1262#
1257 1263
1258# 1264#
1259# may also be needed; see USB_STORAGE Help for more information 1265# see USB_STORAGE Help for more information
1260# 1266#
1261CONFIG_USB_STORAGE=y 1267CONFIG_USB_STORAGE=y
1262# CONFIG_USB_STORAGE_DEBUG is not set 1268# CONFIG_USB_STORAGE_DEBUG is not set
@@ -1348,6 +1354,7 @@ CONFIG_RTC_INTF_DEV=y
1348# CONFIG_RTC_DRV_M41T80 is not set 1354# CONFIG_RTC_DRV_M41T80 is not set
1349# CONFIG_RTC_DRV_S35390A is not set 1355# CONFIG_RTC_DRV_S35390A is not set
1350# CONFIG_RTC_DRV_FM3130 is not set 1356# CONFIG_RTC_DRV_FM3130 is not set
1357# CONFIG_RTC_DRV_RX8581 is not set
1351 1358
1352# 1359#
1353# SPI RTC drivers 1360# SPI RTC drivers
@@ -1624,6 +1631,7 @@ CONFIG_HAVE_FUNCTION_TRACER=y
1624# CONFIG_SAMPLES is not set 1631# CONFIG_SAMPLES is not set
1625CONFIG_HAVE_ARCH_KGDB=y 1632CONFIG_HAVE_ARCH_KGDB=y
1626# CONFIG_KGDB is not set 1633# CONFIG_KGDB is not set
1634CONFIG_PRINT_STACK_DEPTH=64
1627# CONFIG_DEBUG_STACKOVERFLOW is not set 1635# CONFIG_DEBUG_STACKOVERFLOW is not set
1628# CONFIG_DEBUG_STACK_USAGE is not set 1636# CONFIG_DEBUG_STACK_USAGE is not set
1629# CONFIG_DEBUG_PAGEALLOC is not set 1637# CONFIG_DEBUG_PAGEALLOC is not set
@@ -1649,11 +1657,16 @@ CONFIG_CRYPTO=y
1649# 1657#
1650# CONFIG_CRYPTO_FIPS is not set 1658# CONFIG_CRYPTO_FIPS is not set
1651CONFIG_CRYPTO_ALGAPI=y 1659CONFIG_CRYPTO_ALGAPI=y
1660CONFIG_CRYPTO_ALGAPI2=y
1652CONFIG_CRYPTO_AEAD=y 1661CONFIG_CRYPTO_AEAD=y
1662CONFIG_CRYPTO_AEAD2=y
1653CONFIG_CRYPTO_BLKCIPHER=y 1663CONFIG_CRYPTO_BLKCIPHER=y
1664CONFIG_CRYPTO_BLKCIPHER2=y
1654CONFIG_CRYPTO_HASH=y 1665CONFIG_CRYPTO_HASH=y
1655CONFIG_CRYPTO_RNG=y 1666CONFIG_CRYPTO_HASH2=y
1667CONFIG_CRYPTO_RNG2=y
1656CONFIG_CRYPTO_MANAGER=y 1668CONFIG_CRYPTO_MANAGER=y
1669CONFIG_CRYPTO_MANAGER2=y
1657# CONFIG_CRYPTO_GF128MUL is not set 1670# CONFIG_CRYPTO_GF128MUL is not set
1658# CONFIG_CRYPTO_NULL is not set 1671# CONFIG_CRYPTO_NULL is not set
1659# CONFIG_CRYPTO_CRYPTD is not set 1672# CONFIG_CRYPTO_CRYPTD is not set
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index edee15d269ea..a0a15311d0d8 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -17,6 +17,8 @@
17#ifdef __KERNEL__ 17#ifdef __KERNEL__
18 18
19#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20#include <linux/errno.h>
21#include <linux/err.h>
20#include <asm/cpm.h> 22#include <asm/cpm.h>
21#include <asm/immap_qe.h> 23#include <asm/immap_qe.h>
22 24
@@ -84,7 +86,11 @@ static inline bool qe_clock_is_brg(enum qe_clock clk)
84extern spinlock_t cmxgcr_lock; 86extern spinlock_t cmxgcr_lock;
85 87
86/* Export QE common operations */ 88/* Export QE common operations */
89#ifdef CONFIG_QUICC_ENGINE
87extern void __init qe_reset(void); 90extern void __init qe_reset(void);
91#else
92static inline void qe_reset(void) {}
93#endif
88 94
89/* QE PIO */ 95/* QE PIO */
90#define QE_PIO_PINS 32 96#define QE_PIO_PINS 32
@@ -101,16 +107,43 @@ struct qe_pio_regs {
101#endif 107#endif
102}; 108};
103 109
104extern int par_io_init(struct device_node *np);
105extern int par_io_of_config(struct device_node *np);
106#define QE_PIO_DIR_IN 2 110#define QE_PIO_DIR_IN 2
107#define QE_PIO_DIR_OUT 1 111#define QE_PIO_DIR_OUT 1
108extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, 112extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
109 int dir, int open_drain, int assignment, 113 int dir, int open_drain, int assignment,
110 int has_irq); 114 int has_irq);
115#ifdef CONFIG_QUICC_ENGINE
116extern int par_io_init(struct device_node *np);
117extern int par_io_of_config(struct device_node *np);
111extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 118extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
112 int assignment, int has_irq); 119 int assignment, int has_irq);
113extern int par_io_data_set(u8 port, u8 pin, u8 val); 120extern int par_io_data_set(u8 port, u8 pin, u8 val);
121#else
122static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
123static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
124static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
125 int assignment, int has_irq) { return -ENOSYS; }
126static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
127#endif /* CONFIG_QUICC_ENGINE */
128
129/*
130 * Pin multiplexing functions.
131 */
132struct qe_pin;
133#ifdef CONFIG_QE_GPIO
134extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
135extern void qe_pin_free(struct qe_pin *qe_pin);
136extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
137extern void qe_pin_set_dedicated(struct qe_pin *pin);
138#else
139static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
140{
141 return ERR_PTR(-ENOSYS);
142}
143static inline void qe_pin_free(struct qe_pin *qe_pin) {}
144static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
145static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
146#endif /* CONFIG_QE_GPIO */
114 147
115/* QE internal API */ 148/* QE internal API */
116int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 149int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h
index 56a7745ca343..cf519663a791 100644
--- a/arch/powerpc/include/asm/qe_ic.h
+++ b/arch/powerpc/include/asm/qe_ic.h
@@ -17,6 +17,9 @@
17 17
18#include <linux/irq.h> 18#include <linux/irq.h>
19 19
20struct device_node;
21struct qe_ic;
22
20#define NUM_OF_QE_IC_GROUPS 6 23#define NUM_OF_QE_IC_GROUPS 6
21 24
22/* Flags when we init the QE IC */ 25/* Flags when we init the QE IC */
@@ -54,17 +57,27 @@ enum qe_ic_grp_id {
54 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ 57 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
55}; 58};
56 59
60#ifdef CONFIG_QUICC_ENGINE
57void qe_ic_init(struct device_node *node, unsigned int flags, 61void qe_ic_init(struct device_node *node, unsigned int flags,
58 void (*low_handler)(unsigned int irq, struct irq_desc *desc), 62 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
59 void (*high_handler)(unsigned int irq, struct irq_desc *desc)); 63 void (*high_handler)(unsigned int irq, struct irq_desc *desc));
64unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
65unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
66#else
67static inline void qe_ic_init(struct device_node *node, unsigned int flags,
68 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
69 void (*high_handler)(unsigned int irq, struct irq_desc *desc))
70{}
71static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
72{ return 0; }
73static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
74{ return 0; }
75#endif /* CONFIG_QUICC_ENGINE */
76
60void qe_ic_set_highest_priority(unsigned int virq, int high); 77void qe_ic_set_highest_priority(unsigned int virq, int high);
61int qe_ic_set_priority(unsigned int virq, unsigned int priority); 78int qe_ic_set_priority(unsigned int virq, unsigned int priority);
62int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); 79int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
63 80
64struct qe_ic;
65unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
66unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
67
68static inline void qe_ic_cascade_low_ipic(unsigned int irq, 81static inline void qe_ic_cascade_low_ipic(unsigned int irq,
69 struct irq_desc *desc) 82 struct irq_desc *desc)
70{ 83{
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index a428f8d1ac80..5177bdd2c62a 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -42,7 +42,7 @@ static void __init mpc831x_rdb_setup_arch(void)
42 mpc831x_usb_cfg(); 42 mpc831x_usb_cfg();
43} 43}
44 44
45void __init mpc831x_rdb_init_IRQ(void) 45static void __init mpc831x_rdb_init_IRQ(void)
46{ 46{
47 struct device_node *np; 47 struct device_node *np;
48 48
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index ec43477caa63..ec0b401bc9cf 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -49,8 +49,6 @@
49#define DBG(fmt...) 49#define DBG(fmt...)
50#endif 50#endif
51 51
52static u8 *bcsr_regs = NULL;
53
54/* ************************************************************************ 52/* ************************************************************************
55 * 53 *
56 * Setup the architecture 54 * Setup the architecture
@@ -59,13 +57,14 @@ static u8 *bcsr_regs = NULL;
59static void __init mpc832x_sys_setup_arch(void) 57static void __init mpc832x_sys_setup_arch(void)
60{ 58{
61 struct device_node *np; 59 struct device_node *np;
60 u8 __iomem *bcsr_regs = NULL;
62 61
63 if (ppc_md.progress) 62 if (ppc_md.progress)
64 ppc_md.progress("mpc832x_sys_setup_arch()", 0); 63 ppc_md.progress("mpc832x_sys_setup_arch()", 0);
65 64
66 /* Map BCSR area */ 65 /* Map BCSR area */
67 np = of_find_node_by_name(NULL, "bcsr"); 66 np = of_find_node_by_name(NULL, "bcsr");
68 if (np != 0) { 67 if (np) {
69 struct resource res; 68 struct resource res;
70 69
71 of_address_to_resource(np, 0, &res); 70 of_address_to_resource(np, 0, &res);
@@ -93,9 +92,9 @@ static void __init mpc832x_sys_setup_arch(void)
93 != NULL){ 92 != NULL){
94 /* Reset the Ethernet PHYs */ 93 /* Reset the Ethernet PHYs */
95#define BCSR8_FETH_RST 0x50 94#define BCSR8_FETH_RST 0x50
96 bcsr_regs[8] &= ~BCSR8_FETH_RST; 95 clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
97 udelay(1000); 96 udelay(1000);
98 bcsr_regs[8] |= BCSR8_FETH_RST; 97 setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
99 iounmap(bcsr_regs); 98 iounmap(bcsr_regs);
100 of_node_put(np); 99 of_node_put(np);
101 } 100 }
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 0300268ce5b8..2a1295f19832 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -38,6 +38,7 @@
38#define DBG(fmt...) 38#define DBG(fmt...)
39#endif 39#endif
40 40
41#ifdef CONFIG_QUICC_ENGINE
41static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity) 42static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
42{ 43{
43 pr_debug("%s %d %d\n", __func__, cs, polarity); 44 pr_debug("%s %d %d\n", __func__, cs, polarity);
@@ -77,8 +78,8 @@ static int __init mpc832x_spi_init(void)
77 mpc83xx_spi_activate_cs, 78 mpc83xx_spi_activate_cs,
78 mpc83xx_spi_deactivate_cs); 79 mpc83xx_spi_deactivate_cs);
79} 80}
80
81machine_device_initcall(mpc832x_rdb, mpc832x_spi_init); 81machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
82#endif /* CONFIG_QUICC_ENGINE */
82 83
83/* ************************************************************************ 84/* ************************************************************************
84 * 85 *
@@ -130,7 +131,7 @@ static int __init mpc832x_declare_of_platform_devices(void)
130} 131}
131machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices); 132machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
132 133
133void __init mpc832x_rdb_init_IRQ(void) 134static void __init mpc832x_rdb_init_IRQ(void)
134{ 135{
135 136
136 struct device_node *np; 137 struct device_node *np;
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 9d46e5bdd101..09e9d6fb7411 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/stddef.h> 19#include <linux/stddef.h>
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/compiler.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/errno.h> 23#include <linux/errno.h>
23#include <linux/reboot.h> 24#include <linux/reboot.h>
@@ -43,6 +44,7 @@
43#include <asm/udbg.h> 44#include <asm/udbg.h>
44#include <sysdev/fsl_soc.h> 45#include <sysdev/fsl_soc.h>
45#include <sysdev/fsl_pci.h> 46#include <sysdev/fsl_pci.h>
47#include <sysdev/simple_gpio.h>
46#include <asm/qe.h> 48#include <asm/qe.h>
47#include <asm/qe_ic.h> 49#include <asm/qe_ic.h>
48 50
@@ -55,8 +57,6 @@
55#define DBG(fmt...) 57#define DBG(fmt...)
56#endif 58#endif
57 59
58static u8 *bcsr_regs = NULL;
59
60/* ************************************************************************ 60/* ************************************************************************
61 * 61 *
62 * Setup the architecture 62 * Setup the architecture
@@ -65,13 +65,14 @@ static u8 *bcsr_regs = NULL;
65static void __init mpc836x_mds_setup_arch(void) 65static void __init mpc836x_mds_setup_arch(void)
66{ 66{
67 struct device_node *np; 67 struct device_node *np;
68 u8 __iomem *bcsr_regs = NULL;
68 69
69 if (ppc_md.progress) 70 if (ppc_md.progress)
70 ppc_md.progress("mpc836x_mds_setup_arch()", 0); 71 ppc_md.progress("mpc836x_mds_setup_arch()", 0);
71 72
72 /* Map BCSR area */ 73 /* Map BCSR area */
73 np = of_find_node_by_name(NULL, "bcsr"); 74 np = of_find_node_by_name(NULL, "bcsr");
74 if (np != 0) { 75 if (np) {
75 struct resource res; 76 struct resource res;
76 77
77 of_address_to_resource(np, 0, &res); 78 of_address_to_resource(np, 0, &res);
@@ -93,6 +94,16 @@ static void __init mpc836x_mds_setup_arch(void)
93 94
94 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) 95 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
95 par_io_of_config(np); 96 par_io_of_config(np);
97#ifdef CONFIG_QE_USB
98 /* Must fixup Par IO before QE GPIO chips are registered. */
99 par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
100 par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
101 par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
102 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
103 par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
104 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
105 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
106#endif /* CONFIG_QE_USB */
96 } 107 }
97 108
98 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) 109 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
@@ -151,6 +162,70 @@ static int __init mpc836x_declare_of_platform_devices(void)
151} 162}
152machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices); 163machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
153 164
165#ifdef CONFIG_QE_USB
166static int __init mpc836x_usb_cfg(void)
167{
168 u8 __iomem *bcsr;
169 struct device_node *np;
170 const char *mode;
171 int ret = 0;
172
173 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
174 if (!np)
175 return -ENODEV;
176
177 bcsr = of_iomap(np, 0);
178 of_node_put(np);
179 if (!bcsr)
180 return -ENOMEM;
181
182 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
183 if (!np) {
184 ret = -ENODEV;
185 goto err;
186 }
187
188#define BCSR8_TSEC1M_MASK (0x3 << 6)
189#define BCSR8_TSEC1M_RGMII (0x0 << 6)
190#define BCSR8_TSEC2M_MASK (0x3 << 4)
191#define BCSR8_TSEC2M_RGMII (0x0 << 4)
192 /*
193 * Default is GMII (2), but we should set it to RGMII (0) if we use
194 * USB (Eth PHY is in RGMII mode anyway).
195 */
196 clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
197 BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
198
199#define BCSR13_USBMASK 0x0f
200#define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
201#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
202#define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
203#define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
204
205 clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
206
207 mode = of_get_property(np, "mode", NULL);
208 if (mode && !strcmp(mode, "peripheral")) {
209 setbits8(&bcsr[13], BCSR13_nUSBVCC);
210 qe_usb_clock_set(QE_CLK21, 48000000);
211 } else {
212 setbits8(&bcsr[13], BCSR13_USBMODE);
213 /*
214 * The BCSR GPIOs are used to control power and
215 * speed of the USB transceiver. This is needed for
216 * the USB Host only.
217 */
218 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
219 }
220
221 of_node_put(np);
222err:
223 iounmap(bcsr);
224 return ret;
225}
226machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
227#endif /* CONFIG_QE_USB */
228
154static void __init mpc836x_mds_init_IRQ(void) 229static void __init mpc836x_mds_init_IRQ(void)
155{ 230{
156 struct device_node *np; 231 struct device_node *np;
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index a5273bb28e1b..b0090aac9642 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -51,8 +51,9 @@ static void __init mpc836x_rdk_setup_arch(void)
51 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 51 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
52 mpc83xx_add_bridge(np); 52 mpc83xx_add_bridge(np);
53#endif 53#endif
54 54#ifdef CONFIG_QUICC_ENGINE
55 qe_reset(); 55 qe_reset();
56#endif
56} 57}
57 58
58static void __init mpc836x_rdk_init_IRQ(void) 59static void __init mpc836x_rdk_init_IRQ(void)
@@ -71,13 +72,14 @@ static void __init mpc836x_rdk_init_IRQ(void)
71 */ 72 */
72 ipic_set_default_priority(); 73 ipic_set_default_priority();
73 of_node_put(np); 74 of_node_put(np);
74 75#ifdef CONFIG_QUICC_ENGINE
75 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 76 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
76 if (!np) 77 if (!np)
77 return; 78 return;
78 79
79 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); 80 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
80 of_node_put(np); 81 of_node_put(np);
82#endif
81} 83}
82 84
83/* 85/*
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 8bb13c807142..530ef990ca7c 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -26,7 +26,6 @@
26#define BCSR12_USB_SER_MASK 0x8a 26#define BCSR12_USB_SER_MASK 0x8a
27#define BCSR12_USB_SER_PIN 0x80 27#define BCSR12_USB_SER_PIN 0x80
28#define BCSR12_USB_SER_DEVICE 0x02 28#define BCSR12_USB_SER_DEVICE 0x02
29extern int mpc837x_usb_cfg(void);
30 29
31static int mpc837xmds_usb_cfg(void) 30static int mpc837xmds_usb_cfg(void)
32{ 31{
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index da030afa2e2c..1d096545322b 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -21,8 +21,6 @@
21 21
22#include "mpc83xx.h" 22#include "mpc83xx.h"
23 23
24extern int mpc837x_usb_cfg(void);
25
26/* ************************************************************************ 24/* ************************************************************************
27 * 25 *
28 * Setup the architecture 26 * Setup the architecture
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 2a7cbabb410a..83cfe51526ec 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -61,6 +61,7 @@
61 61
62extern void mpc83xx_restart(char *cmd); 62extern void mpc83xx_restart(char *cmd);
63extern long mpc83xx_time_init(void); 63extern long mpc83xx_time_init(void);
64extern int mpc837x_usb_cfg(void);
64extern int mpc834x_usb_cfg(void); 65extern int mpc834x_usb_cfg(void);
65extern int mpc831x_usb_cfg(void); 66extern int mpc831x_usb_cfg(void);
66 67
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index a8301c8ad537..7326d904202c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -148,6 +148,9 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
148/* 148/*
149 * Setup the architecture 149 * Setup the architecture
150 */ 150 */
151#ifdef CONFIG_SMP
152extern void __init mpc85xx_smp_init(void);
153#endif
151static void __init mpc85xx_ds_setup_arch(void) 154static void __init mpc85xx_ds_setup_arch(void)
152{ 155{
153#ifdef CONFIG_PCI 156#ifdef CONFIG_PCI
@@ -173,6 +176,10 @@ static void __init mpc85xx_ds_setup_arch(void)
173 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 176 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
174#endif 177#endif
175 178
179#ifdef CONFIG_SMP
180 mpc85xx_smp_init();
181#endif
182
176 printk("MPC85xx DS board from Freescale Semiconductor\n"); 183 printk("MPC85xx DS board from Freescale Semiconductor\n");
177} 184}
178 185
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index d652c713f496..79a0df17078b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -58,6 +58,7 @@ smp_85xx_kick_cpu(int nr)
58 58
59 if (cpu_rel_addr == NULL) { 59 if (cpu_rel_addr == NULL) {
60 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); 60 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
61 local_irq_restore(flags);
61 return; 62 return;
62 } 63 }
63 64
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 47e956c871fe..47fe2bea9865 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -312,4 +312,15 @@ config MPC8xxx_GPIO
312 Say Y here if you're going to use hardware that connects to the 312 Say Y here if you're going to use hardware that connects to the
313 MPC831x/834x/837x/8572/8610 GPIOs. 313 MPC831x/834x/837x/8572/8610 GPIOs.
314 314
315config SIMPLE_GPIO
316 bool "Support for simple, memory-mapped GPIO controllers"
317 depends on PPC
318 select GENERIC_GPIO
319 select ARCH_REQUIRE_GPIOLIB
320 help
321 Say Y here to support simple, memory-mapped GPIO controllers.
322 These are usually BCSRs used to control board's switches, LEDs,
323 chip-selects, Ethernet/USB PHY's power and various other small
324 on-board peripherals.
325
315endmenu 326endmenu
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 3d0c776f888d..e868b5c50723 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -231,7 +231,7 @@ config VIRT_CPU_ACCOUNTING
231 If in doubt, say Y here. 231 If in doubt, say Y here.
232 232
233config SMP 233config SMP
234 depends on PPC_STD_MMU 234 depends on PPC_STD_MMU || FSL_BOOKE
235 bool "Symmetric multi-processing support" 235 bool "Symmetric multi-processing support"
236 ---help--- 236 ---help---
237 This enables support for systems with more than one CPU. If you have 237 This enables support for systems with more than one CPU. If you have
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5afce115ab1f..b33b28a6fe12 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
17obj-$(CONFIG_FSL_LBC) += fsl_lbc.o 17obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
18obj-$(CONFIG_FSL_GTM) += fsl_gtm.o 18obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
19obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o 19obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
20obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
20obj-$(CONFIG_RAPIDIO) += fsl_rio.o 21obj-$(CONFIG_RAPIDIO) += fsl_rio.o
21obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 22obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
22obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 23obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index d5f9ae0f1b75..f611d0369cc8 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -29,7 +29,8 @@
29 29
30#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) 30#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
31/* atmu setup for fsl pci/pcie controller */ 31/* atmu setup for fsl pci/pcie controller */
32void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) 32static void __init setup_pci_atmu(struct pci_controller *hose,
33 struct resource *rsrc)
33{ 34{
34 struct ccsr_pci __iomem *pci; 35 struct ccsr_pci __iomem *pci;
35 int i; 36 int i;
@@ -86,7 +87,7 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
86 out_be32(&pci->piw[2].piwar, PIWAR_2G); 87 out_be32(&pci->piw[2].piwar, PIWAR_2G);
87} 88}
88 89
89void __init setup_pci_cmd(struct pci_controller *hose) 90static void __init setup_pci_cmd(struct pci_controller *hose)
90{ 91{
91 u16 cmd; 92 u16 cmd;
92 int cap_x; 93 int cap_x;
@@ -130,7 +131,7 @@ static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
130 return ; 131 return ;
131} 132}
132 133
133int __init fsl_pcie_check_link(struct pci_controller *hose) 134static int __init fsl_pcie_check_link(struct pci_controller *hose)
134{ 135{
135 u32 val; 136 u32 val;
136 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 137 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 60f7f227327c..9c744e4285a0 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -5,8 +5,13 @@
5#include <asm/mmu.h> 5#include <asm/mmu.h>
6 6
7extern phys_addr_t get_immrbase(void); 7extern phys_addr_t get_immrbase(void);
8#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
8extern u32 get_brgfreq(void); 9extern u32 get_brgfreq(void);
9extern u32 get_baudrate(void); 10extern u32 get_baudrate(void);
11#else
12static inline u32 get_brgfreq(void) { return -1; }
13static inline u32 get_baudrate(void) { return -1; }
14#endif
10extern u32 fsl_get_sys_freq(void); 15extern u32 fsl_get_sys_freq(void);
11 16
12struct spi_board_info; 17struct spi_board_info;
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 76ffbc48d4b9..41ac3dfac98e 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,5 +22,6 @@ config UCC
22 22
23config QE_USB 23config QE_USB
24 bool 24 bool
25 default y if USB_GADGET_FSL_QE
25 help 26 help
26 QE USB Host Controller support 27 QE USB Controller support
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index 8e5a0bc36d0b..3485288dce31 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -14,6 +14,7 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/spinlock.h> 16#include <linux/spinlock.h>
17#include <linux/err.h>
17#include <linux/io.h> 18#include <linux/io.h>
18#include <linux/of.h> 19#include <linux/of.h>
19#include <linux/of_gpio.h> 20#include <linux/of_gpio.h>
@@ -24,8 +25,14 @@ struct qe_gpio_chip {
24 struct of_mm_gpio_chip mm_gc; 25 struct of_mm_gpio_chip mm_gc;
25 spinlock_t lock; 26 spinlock_t lock;
26 27
28 unsigned long pin_flags[QE_PIO_PINS];
29#define QE_PIN_REQUESTED 0
30
27 /* shadowed data register to clear/set bits safely */ 31 /* shadowed data register to clear/set bits safely */
28 u32 cpdata; 32 u32 cpdata;
33
34 /* saved_regs used to restore dedicated functions */
35 struct qe_pio_regs saved_regs;
29}; 36};
30 37
31static inline struct qe_gpio_chip * 38static inline struct qe_gpio_chip *
@@ -40,6 +47,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
40 struct qe_pio_regs __iomem *regs = mm_gc->regs; 47 struct qe_pio_regs __iomem *regs = mm_gc->regs;
41 48
42 qe_gc->cpdata = in_be32(&regs->cpdata); 49 qe_gc->cpdata = in_be32(&regs->cpdata);
50 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
51 qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
52 qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
53 qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
54 qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
55 qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
43} 56}
44 57
45static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) 58static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -103,6 +116,188 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
103 return 0; 116 return 0;
104} 117}
105 118
119struct qe_pin {
120 /*
121 * The qe_gpio_chip name is unfortunate, we should change that to
122 * something like qe_pio_controller. Someday.
123 */
124 struct qe_gpio_chip *controller;
125 int num;
126};
127
128/**
129 * qe_pin_request - Request a QE pin
130 * @np: device node to get a pin from
131 * @index: index of a pin in the device tree
132 * Context: non-atomic
133 *
134 * This function return qe_pin so that you could use it with the rest of
135 * the QE Pin Multiplexing API.
136 */
137struct qe_pin *qe_pin_request(struct device_node *np, int index)
138{
139 struct qe_pin *qe_pin;
140 struct device_node *gc;
141 struct of_gpio_chip *of_gc = NULL;
142 struct of_mm_gpio_chip *mm_gc;
143 struct qe_gpio_chip *qe_gc;
144 int err;
145 int size;
146 const void *gpio_spec;
147 const u32 *gpio_cells;
148 unsigned long flags;
149
150 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
151 if (!qe_pin) {
152 pr_debug("%s: can't allocate memory\n", __func__);
153 return ERR_PTR(-ENOMEM);
154 }
155
156 err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
157 &gc, &gpio_spec);
158 if (err) {
159 pr_debug("%s: can't parse gpios property\n", __func__);
160 goto err0;
161 }
162
163 if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
164 pr_debug("%s: tried to get a non-qe pin\n", __func__);
165 err = -EINVAL;
166 goto err1;
167 }
168
169 of_gc = gc->data;
170 if (!of_gc) {
171 pr_debug("%s: gpio controller %s isn't registered\n",
172 np->full_name, gc->full_name);
173 err = -ENODEV;
174 goto err1;
175 }
176
177 gpio_cells = of_get_property(gc, "#gpio-cells", &size);
178 if (!gpio_cells || size != sizeof(*gpio_cells) ||
179 *gpio_cells != of_gc->gpio_cells) {
180 pr_debug("%s: wrong #gpio-cells for %s\n",
181 np->full_name, gc->full_name);
182 err = -EINVAL;
183 goto err1;
184 }
185
186 err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
187 if (err < 0)
188 goto err1;
189
190 mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
191 qe_gc = to_qe_gpio_chip(mm_gc);
192
193 spin_lock_irqsave(&qe_gc->lock, flags);
194
195 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
196 qe_pin->controller = qe_gc;
197 qe_pin->num = err;
198 err = 0;
199 } else {
200 err = -EBUSY;
201 }
202
203 spin_unlock_irqrestore(&qe_gc->lock, flags);
204
205 if (!err)
206 return qe_pin;
207err1:
208 of_node_put(gc);
209err0:
210 kfree(qe_pin);
211 pr_debug("%s failed with status %d\n", __func__, err);
212 return ERR_PTR(err);
213}
214EXPORT_SYMBOL(qe_pin_request);
215
216/**
217 * qe_pin_free - Free a pin
218 * @qe_pin: pointer to the qe_pin structure
219 * Context: any
220 *
221 * This function frees the qe_pin structure and makes a pin available
222 * for further qe_pin_request() calls.
223 */
224void qe_pin_free(struct qe_pin *qe_pin)
225{
226 struct qe_gpio_chip *qe_gc = qe_pin->controller;
227 unsigned long flags;
228 const int pin = qe_pin->num;
229
230 spin_lock_irqsave(&qe_gc->lock, flags);
231 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
232 spin_unlock_irqrestore(&qe_gc->lock, flags);
233
234 kfree(qe_pin);
235}
236EXPORT_SYMBOL(qe_pin_free);
237
238/**
239 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
240 * @qe_pin: pointer to the qe_pin structure
241 * Context: any
242 *
243 * This function resets a pin to a dedicated peripheral function that
244 * has been set up by the firmware.
245 */
246void qe_pin_set_dedicated(struct qe_pin *qe_pin)
247{
248 struct qe_gpio_chip *qe_gc = qe_pin->controller;
249 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
250 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
251 int pin = qe_pin->num;
252 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
253 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
254 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
255 unsigned long flags;
256
257 spin_lock_irqsave(&qe_gc->lock, flags);
258
259 if (second_reg) {
260 clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
261 clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
262 } else {
263 clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
264 clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
265 }
266
267 if (sregs->cpdata & mask1)
268 qe_gc->cpdata |= mask1;
269 else
270 qe_gc->cpdata &= ~mask1;
271
272 out_be32(&regs->cpdata, qe_gc->cpdata);
273 clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
274
275 spin_unlock_irqrestore(&qe_gc->lock, flags);
276}
277EXPORT_SYMBOL(qe_pin_set_dedicated);
278
279/**
280 * qe_pin_set_gpio - Set a pin to the GPIO mode
281 * @qe_pin: pointer to the qe_pin structure
282 * Context: any
283 *
284 * This function sets a pin to the GPIO mode.
285 */
286void qe_pin_set_gpio(struct qe_pin *qe_pin)
287{
288 struct qe_gpio_chip *qe_gc = qe_pin->controller;
289 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
290 unsigned long flags;
291
292 spin_lock_irqsave(&qe_gc->lock, flags);
293
294 /* Let's make it input by default, GPIO API is able to change that. */
295 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
296
297 spin_unlock_irqrestore(&qe_gc->lock, flags);
298}
299EXPORT_SYMBOL(qe_pin_set_gpio);
300
106static int __init qe_add_gpiochips(void) 301static int __init qe_add_gpiochips(void)
107{ 302{
108 struct device_node *np; 303 struct device_node *np;
diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/simple_gpio.c
new file mode 100644
index 000000000000..43c4569e24b7
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.c
@@ -0,0 +1,155 @@
1/*
2 * Simple Memory-Mapped GPIOs
3 *
4 * Copyright (c) MontaVista Software, Inc. 2008.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/types.h>
19#include <linux/ioport.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_gpio.h>
23#include <linux/gpio.h>
24#include <asm/prom.h>
25#include "simple_gpio.h"
26
27struct u8_gpio_chip {
28 struct of_mm_gpio_chip mm_gc;
29 spinlock_t lock;
30
31 /* shadowed data register to clear/set bits safely */
32 u8 data;
33};
34
35static struct u8_gpio_chip *to_u8_gpio_chip(struct of_mm_gpio_chip *mm_gc)
36{
37 return container_of(mm_gc, struct u8_gpio_chip, mm_gc);
38}
39
40static u8 u8_pin2mask(unsigned int pin)
41{
42 return 1 << (8 - 1 - pin);
43}
44
45static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
46{
47 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
48
49 return in_8(mm_gc->regs) & u8_pin2mask(gpio);
50}
51
52static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
53{
54 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
55 struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
56 unsigned long flags;
57
58 spin_lock_irqsave(&u8_gc->lock, flags);
59
60 if (val)
61 u8_gc->data |= u8_pin2mask(gpio);
62 else
63 u8_gc->data &= ~u8_pin2mask(gpio);
64
65 out_8(mm_gc->regs, u8_gc->data);
66
67 spin_unlock_irqrestore(&u8_gc->lock, flags);
68}
69
70static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
71{
72 return 0;
73}
74
75static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
76{
77 u8_gpio_set(gc, gpio, val);
78 return 0;
79}
80
81static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
82{
83 struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
84
85 u8_gc->data = in_8(mm_gc->regs);
86}
87
88static int __init u8_simple_gpiochip_add(struct device_node *np)
89{
90 int ret;
91 struct u8_gpio_chip *u8_gc;
92 struct of_mm_gpio_chip *mm_gc;
93 struct of_gpio_chip *of_gc;
94 struct gpio_chip *gc;
95
96 u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
97 if (!u8_gc)
98 return -ENOMEM;
99
100 spin_lock_init(&u8_gc->lock);
101
102 mm_gc = &u8_gc->mm_gc;
103 of_gc = &mm_gc->of_gc;
104 gc = &of_gc->gc;
105
106 mm_gc->save_regs = u8_gpio_save_regs;
107 of_gc->gpio_cells = 2;
108 gc->ngpio = 8;
109 gc->direction_input = u8_gpio_dir_in;
110 gc->direction_output = u8_gpio_dir_out;
111 gc->get = u8_gpio_get;
112 gc->set = u8_gpio_set;
113
114 ret = of_mm_gpiochip_add(np, mm_gc);
115 if (ret)
116 goto err;
117 return 0;
118err:
119 kfree(u8_gc);
120 return ret;
121}
122
123void __init simple_gpiochip_init(const char *compatible)
124{
125 struct device_node *np;
126
127 for_each_compatible_node(np, NULL, compatible) {
128 int ret;
129 struct resource r;
130
131 ret = of_address_to_resource(np, 0, &r);
132 if (ret)
133 goto err;
134
135 switch (resource_size(&r)) {
136 case 1:
137 ret = u8_simple_gpiochip_add(np);
138 if (ret)
139 goto err;
140 break;
141 default:
142 /*
143 * Whenever you need support for GPIO bank width > 1,
144 * please just turn u8_ code into huge macros, and
145 * construct needed uX_ code with it.
146 */
147 ret = -ENOSYS;
148 goto err;
149 }
150 continue;
151err:
152 pr_err("%s: registration failed, status %d\n",
153 np->full_name, ret);
154 }
155}
diff --git a/arch/powerpc/sysdev/simple_gpio.h b/arch/powerpc/sysdev/simple_gpio.h
new file mode 100644
index 000000000000..3a7b0c513c76
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.h
@@ -0,0 +1,12 @@
1#ifndef __SYSDEV_SIMPLE_GPIO_H
2#define __SYSDEV_SIMPLE_GPIO_H
3
4#include <linux/errno.h>
5
6#ifdef CONFIG_SIMPLE_GPIO
7extern void simple_gpiochip_init(const char *compatible);
8#else
9static inline void simple_gpiochip_init(const char *compatible) {}
10#endif /* CONFIG_SIMPLE_GPIO */
11
12#endif /* __SYSDEV_SIMPLE_GPIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 17:23:45 -0500