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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c21
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
2 files changed, 20 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 64c07c24e300..0d051e7f6702 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -298,6 +298,7 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
299 int ret = IRQ_NONE; 299 int ret = IRQ_NONE;
300 u32 de_iir, gt_iir, de_ier, pch_iir; 300 u32 de_iir, gt_iir, de_ier, pch_iir;
301 u32 hotplug_mask;
301 struct drm_i915_master_private *master_priv; 302 struct drm_i915_master_private *master_priv;
302 struct intel_ring_buffer *render_ring = &dev_priv->render_ring; 303 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
303 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; 304 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
@@ -317,6 +318,11 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
317 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) 318 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
318 goto done; 319 goto done;
319 320
321 if (HAS_PCH_CPT(dev))
322 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
323 else
324 hotplug_mask = SDE_HOTPLUG_MASK;
325
320 ret = IRQ_HANDLED; 326 ret = IRQ_HANDLED;
321 327
322 if (dev->primary->master) { 328 if (dev->primary->master) {
@@ -358,10 +364,8 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
358 drm_handle_vblank(dev, 1); 364 drm_handle_vblank(dev, 1);
359 365
360 /* check event from PCH */ 366 /* check event from PCH */
361 if ((de_iir & DE_PCH_EVENT) && 367 if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
362 (pch_iir & SDE_HOTPLUG_MASK)) {
363 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 368 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
364 }
365 369
366 if (de_iir & DE_PCU_EVENT) { 370 if (de_iir & DE_PCU_EVENT) {
367 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 371 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
@@ -1431,8 +1435,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1431 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1435 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1432 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1436 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1433 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; 1437 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1434 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1438 u32 hotplug_mask;
1435 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1436 1439
1437 dev_priv->irq_mask_reg = ~display_mask; 1440 dev_priv->irq_mask_reg = ~display_mask;
1438 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; 1441 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
@@ -1459,6 +1462,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1459 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); 1462 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1460 (void) I915_READ(GTIER); 1463 (void) I915_READ(GTIER);
1461 1464
1465 if (HAS_PCH_CPT(dev)) {
1466 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1467 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1468 } else {
1469 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1470 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1471 }
1472
1462 dev_priv->pch_irq_mask_reg = ~hotplug_mask; 1473 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1463 dev_priv->pch_irq_enable_reg = hotplug_mask; 1474 dev_priv->pch_irq_enable_reg = hotplug_mask;
1464 1475
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88292893b255..47032186a31a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2601,6 +2601,10 @@
2601#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2601#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2602#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2602#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2603#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2603#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2604#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2605 SDE_PORTD_HOTPLUG_CPT | \
2606 SDE_PORTC_HOTPLUG_CPT | \
2607 SDE_PORTB_HOTPLUG_CPT)
2604 2608
2605#define SDEISR 0xc4000 2609#define SDEISR 0xc4000
2606#define SDEIMR 0xc4004 2610#define SDEIMR 0xc4004