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-rw-r--r--drivers/video/tridentfb.c144
-rw-r--r--include/video/trident.h26
2 files changed, 61 insertions, 109 deletions
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c
index d6796448c5ac..381e5853df6f 100644
--- a/drivers/video/tridentfb.c
+++ b/drivers/video/tridentfb.c
@@ -22,6 +22,7 @@
22#include <linux/pci.h> 22#include <linux/pci.h>
23 23
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <video/vga.h>
25#include <video/trident.h> 26#include <video/trident.h>
26 27
27#define VERSION "0.7.9-NEWAPI" 28#define VERSION "0.7.9-NEWAPI"
@@ -149,8 +150,6 @@ static int iscyber(int id)
149 } 150 }
150} 151}
151 152
152#define CRT 0x3D0 /* CRTC registers offset for color display */
153
154static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) 153static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
155{ 154{
156 fb_writeb(val, p->io_virt + reg); 155 fb_writeb(val, p->io_virt + reg);
@@ -525,60 +524,41 @@ static void tridentfb_copyarea(struct fb_info *info,
525 524
526static inline unsigned char read3X4(struct tridentfb_par *par, int reg) 525static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
527{ 526{
528 writeb(reg, par->io_virt + CRT + 4); 527 return vga_mm_rcrt(par->io_virt, reg);
529 return readb(par->io_virt + CRT + 5);
530} 528}
531 529
532static inline void write3X4(struct tridentfb_par *par, int reg, 530static inline void write3X4(struct tridentfb_par *par, int reg,
533 unsigned char val) 531 unsigned char val)
534{ 532{
535 writeb(reg, par->io_virt + CRT + 4); 533 vga_mm_wcrt(par->io_virt, reg, val);
536 writeb(val, par->io_virt + CRT + 5);
537}
538
539static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
540{
541 t_outb(par, reg, 0x3C4);
542 return t_inb(par, 0x3C5);
543}
544
545static inline void write3C4(struct tridentfb_par *par, int reg,
546 unsigned char val)
547{
548 t_outb(par, reg, 0x3C4);
549 t_outb(par, val, 0x3C5);
550} 534}
551 535
552static inline unsigned char read3CE(struct tridentfb_par *par, int reg) 536static inline unsigned char read3CE(struct tridentfb_par *par,
537 unsigned char reg)
553{ 538{
554 t_outb(par, reg, 0x3CE); 539 return vga_mm_rgfx(par->io_virt, reg);
555 return t_inb(par, 0x3CF);
556} 540}
557 541
558static inline void writeAttr(struct tridentfb_par *par, int reg, 542static inline void writeAttr(struct tridentfb_par *par, int reg,
559 unsigned char val) 543 unsigned char val)
560{ 544{
561 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */ 545 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
562 t_outb(par, reg, 0x3C0); 546 vga_mm_wattr(par->io_virt, reg, val);
563 t_outb(par, val, 0x3C0);
564} 547}
565 548
566static inline void write3CE(struct tridentfb_par *par, int reg, 549static inline void write3CE(struct tridentfb_par *par, int reg,
567 unsigned char val) 550 unsigned char val)
568{ 551{
569 t_outb(par, reg, 0x3CE); 552 vga_mm_wgfx(par->io_virt, reg, val);
570 t_outb(par, val, 0x3CF);
571} 553}
572 554
573static void enable_mmio(void) 555static void enable_mmio(void)
574{ 556{
575 /* Goto New Mode */ 557 /* Goto New Mode */
576 outb(0x0B, 0x3C4); 558 vga_io_rseq(0x0B);
577 inb(0x3C5);
578 559
579 /* Unprotect registers */ 560 /* Unprotect registers */
580 outb(NewMode1, 0x3C4); 561 vga_io_wseq(NewMode1, 0x80);
581 outb(0x80, 0x3C5);
582 562
583 /* Enable MMIO */ 563 /* Enable MMIO */
584 outb(PCIReg, 0x3D4); 564 outb(PCIReg, 0x3D4);
@@ -588,12 +568,10 @@ static void enable_mmio(void)
588static void disable_mmio(struct tridentfb_par *par) 568static void disable_mmio(struct tridentfb_par *par)
589{ 569{
590 /* Goto New Mode */ 570 /* Goto New Mode */
591 t_outb(par, 0x0B, 0x3C4); 571 vga_mm_rseq(par->io_virt, 0x0B);
592 t_inb(par, 0x3C5);
593 572
594 /* Unprotect registers */ 573 /* Unprotect registers */
595 t_outb(par, NewMode1, 0x3C4); 574 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
596 t_outb(par, 0x80, 0x3C5);
597 575
598 /* Disable MMIO */ 576 /* Disable MMIO */
599 t_outb(par, PCIReg, 0x3D4); 577 t_outb(par, PCIReg, 0x3D4);
@@ -602,7 +580,8 @@ static void disable_mmio(struct tridentfb_par *par)
602 580
603static void crtc_unlock(struct tridentfb_par *par) 581static void crtc_unlock(struct tridentfb_par *par)
604{ 582{
605 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F); 583 write3X4(par, VGA_CRTC_V_SYNC_END,
584 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
606} 585}
607 586
608/* Return flat panel's maximum x resolution */ 587/* Return flat panel's maximum x resolution */
@@ -641,7 +620,7 @@ static int __devinit get_nativex(struct tridentfb_par *par)
641/* Set pitch */ 620/* Set pitch */
642static void set_lwidth(struct tridentfb_par *par, int width) 621static void set_lwidth(struct tridentfb_par *par, int width)
643{ 622{
644 write3X4(par, Offset, width & 0xFF); 623 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
645 write3X4(par, AddColReg, 624 write3X4(par, AddColReg,
646 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); 625 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
647} 626}
@@ -668,8 +647,8 @@ static void screen_center(struct tridentfb_par *par)
668static void set_screen_start(struct tridentfb_par *par, int base) 647static void set_screen_start(struct tridentfb_par *par, int base)
669{ 648{
670 u8 tmp; 649 u8 tmp;
671 write3X4(par, StartAddrLow, base & 0xFF); 650 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
672 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8); 651 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
673 tmp = read3X4(par, CRTCModuleTest) & 0xDF; 652 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
674 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); 653 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
675 tmp = read3X4(par, CRTHiOrd) & 0xF8; 654 tmp = read3X4(par, CRTHiOrd) & 0xF8;
@@ -698,8 +677,8 @@ static void set_vclk(struct tridentfb_par *par, unsigned long freq)
698 break; 677 break;
699 } 678 }
700 if (is3Dchip(par->chip_id)) { 679 if (is3Dchip(par->chip_id)) {
701 write3C4(par, ClockHigh, hi); 680 vga_mm_wseq(par->io_virt, ClockHigh, hi);
702 write3C4(par, ClockLow, lo); 681 vga_mm_wseq(par->io_virt, ClockLow, lo);
703 } else { 682 } else {
704 outb(lo, 0x43C8); 683 outb(lo, 0x43C8);
705 outb(hi, 0x43C9); 684 outb(hi, 0x43C9);
@@ -782,7 +761,7 @@ static unsigned int __devinit get_memsize(struct tridentfb_par *par)
782 break; 761 break;
783 case 0x0E: /* XP */ 762 case 0x0E: /* XP */
784 763
785 tmp2 = read3C4(par, 0xC1); 764 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
786 switch (tmp2) { 765 switch (tmp2) {
787 case 0x00: 766 case 0x00:
788 k = 20 * Mb; 767 k = 20 * Mb;
@@ -931,7 +910,7 @@ static int tridentfb_set_par(struct fb_info *info)
931 * than requested resolution decide whether 910 * than requested resolution decide whether
932 * we stretch or center 911 * we stretch or center
933 */ 912 */
934 t_outb(par, 0xEB, 0x3C2); 913 t_outb(par, 0xEB, VGA_MIS_W);
935 914
936 shadowmode_on(par); 915 shadowmode_on(par);
937 916
@@ -941,26 +920,26 @@ static int tridentfb_set_par(struct fb_info *info)
941 screen_stretch(par); 920 screen_stretch(par);
942 921
943 } else { 922 } else {
944 t_outb(par, 0x2B, 0x3C2); 923 t_outb(par, 0x2B, VGA_MIS_W);
945 write3CE(par, CyberControl, 8); 924 write3CE(par, CyberControl, 8);
946 } 925 }
947 926
948 /* vertical timing values */ 927 /* vertical timing values */
949 write3X4(par, CRTVTotal, vtotal & 0xFF); 928 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
950 write3X4(par, CRTVDispEnd, vdispend & 0xFF); 929 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
951 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF); 930 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
952 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F)); 931 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
953 write3X4(par, CRTVBlankStart, vblankstart & 0xFF); 932 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
954 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */); 933 write3X4(par, VGA_CRTC_V_BLANK_END, 0 /* p->vblankend & 0xFF */);
955 934
956 /* horizontal timing values */ 935 /* horizontal timing values */
957 write3X4(par, CRTHTotal, htotal & 0xFF); 936 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
958 write3X4(par, CRTHDispEnd, hdispend & 0xFF); 937 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
959 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF); 938 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
960 write3X4(par, CRTHSyncEnd, 939 write3X4(par, VGA_CRTC_H_SYNC_END,
961 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); 940 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
962 write3X4(par, CRTHBlankStart, hblankstart & 0xFF); 941 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
963 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */); 942 write3X4(par, VGA_CRTC_H_BLANK_END, 0 /* (p->hblankend & 0x1F) */);
964 943
965 /* higher bits of vertical timing values */ 944 /* higher bits of vertical timing values */
966 tmp = 0x10; 945 tmp = 0x10;
@@ -972,7 +951,7 @@ static int tridentfb_set_par(struct fb_info *info)
972 if (vtotal & 0x200) tmp |= 0x20; 951 if (vtotal & 0x200) tmp |= 0x20;
973 if (vdispend & 0x200) tmp |= 0x40; 952 if (vdispend & 0x200) tmp |= 0x40;
974 if (vsyncstart & 0x200) tmp |= 0x80; 953 if (vsyncstart & 0x200) tmp |= 0x80;
975 write3X4(par, CRTOverflow, tmp); 954 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
976 955
977 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */ 956 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
978 if (vtotal & 0x400) tmp |= 0x80; 957 if (vtotal & 0x400) tmp |= 0x80;
@@ -989,11 +968,11 @@ static int tridentfb_set_par(struct fb_info *info)
989 tmp = 0x40; 968 tmp = 0x40;
990 if (vblankstart & 0x200) tmp |= 0x20; 969 if (vblankstart & 0x200) tmp |= 0x20;
991//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ 970//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
992 write3X4(par, CRTMaxScanLine, tmp); 971 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
993 972
994 write3X4(par, CRTLineCompare, 0xFF); 973 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
995 write3X4(par, CRTPRowScan, 0); 974 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
996 write3X4(par, CRTModeControl, 0xC3); 975 write3X4(par, VGA_CRTC_MODE, 0xC3);
997 976
998 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ 977 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
999 978
@@ -1041,12 +1020,12 @@ static int tridentfb_set_par(struct fb_info *info)
1041 vclk *= 2; 1020 vclk *= 2;
1042 set_vclk(par, vclk); 1021 set_vclk(par, vclk);
1043 1022
1044 write3C4(par, 0, 3); 1023 vga_mm_wseq(par->io_virt, 0, 3);
1045 write3C4(par, 1, 1); /* set char clock 8 dots wide */ 1024 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1046 /* enable 4 maps because needed in chain4 mode */ 1025 /* enable 4 maps because needed in chain4 mode */
1047 write3C4(par, 2, 0x0F); 1026 vga_mm_wseq(par->io_virt, 2, 0x0F);
1048 write3C4(par, 3, 0); 1027 vga_mm_wseq(par->io_virt, 3, 0);
1049 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */ 1028 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1050 1029
1051 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ 1030 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1052 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); 1031 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
@@ -1056,7 +1035,7 @@ static int tridentfb_set_par(struct fb_info *info)
1056 1035
1057 if (par->chip_id == CYBERBLADEXPAi1) { 1036 if (par->chip_id == CYBERBLADEXPAi1) {
1058 /* This fixes snow-effect in 32 bpp */ 1037 /* This fixes snow-effect in 32 bpp */
1059 write3X4(par, CRTHSyncStart, 0x84); 1038 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1060 } 1039 }
1061 1040
1062 /* graphics mode and support 256 color modes */ 1041 /* graphics mode and support 256 color modes */
@@ -1067,8 +1046,8 @@ static int tridentfb_set_par(struct fb_info *info)
1067 /* colors */ 1046 /* colors */
1068 for (tmp = 0; tmp < 0x10; tmp++) 1047 for (tmp = 0; tmp < 0x10; tmp++)
1069 writeAttr(par, tmp, tmp); 1048 writeAttr(par, tmp, tmp);
1070 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */ 1049 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1071 t_outb(par, 0x20, 0x3C0); /* enable attr */ 1050 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1072 1051
1073 switch (bpp) { 1052 switch (bpp) {
1074 case 8: 1053 case 8:
@@ -1086,13 +1065,13 @@ static int tridentfb_set_par(struct fb_info *info)
1086 break; 1065 break;
1087 } 1066 }
1088 1067
1089 t_inb(par, 0x3C8); 1068 t_inb(par, VGA_PEL_IW);
1090 t_inb(par, 0x3C6); 1069 t_inb(par, VGA_PEL_MSK);
1091 t_inb(par, 0x3C6); 1070 t_inb(par, VGA_PEL_MSK);
1092 t_inb(par, 0x3C6); 1071 t_inb(par, VGA_PEL_MSK);
1093 t_inb(par, 0x3C6); 1072 t_inb(par, VGA_PEL_MSK);
1094 t_outb(par, tmp, 0x3C6); 1073 t_outb(par, tmp, VGA_PEL_MSK);
1095 t_inb(par, 0x3C8); 1074 t_inb(par, VGA_PEL_IW);
1096 1075
1097 if (par->flatpanel) 1076 if (par->flatpanel)
1098 set_number_of_lines(par, info->var.yres); 1077 set_number_of_lines(par, info->var.yres);
@@ -1116,12 +1095,12 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1116 return 1; 1095 return 1;
1117 1096
1118 if (bpp == 8) { 1097 if (bpp == 8) {
1119 t_outb(par, 0xFF, 0x3C6); 1098 t_outb(par, 0xFF, VGA_PEL_MSK);
1120 t_outb(par, regno, 0x3C8); 1099 t_outb(par, regno, VGA_PEL_IW);
1121 1100
1122 t_outb(par, red >> 10, 0x3C9); 1101 t_outb(par, red >> 10, VGA_PEL_D);
1123 t_outb(par, green >> 10, 0x3C9); 1102 t_outb(par, green >> 10, VGA_PEL_D);
1124 t_outb(par, blue >> 10, 0x3C9); 1103 t_outb(par, blue >> 10, VGA_PEL_D);
1125 1104
1126 } else if (regno < 16) { 1105 } else if (regno < 16) {
1127 if (bpp == 16) { /* RGB 565 */ 1106 if (bpp == 16) { /* RGB 565 */
@@ -1232,8 +1211,7 @@ static int __devinit trident_pci_probe(struct pci_dev *dev,
1232 /* If PCI id is 0x9660 then further detect chip type */ 1211 /* If PCI id is 0x9660 then further detect chip type */
1233 1212
1234 if (chip_id == TGUI9660) { 1213 if (chip_id == TGUI9660) {
1235 outb(RevisionID, 0x3C4); 1214 revision = vga_io_rseq(RevisionID);
1236 revision = inb(0x3C5);
1237 1215
1238 switch (revision) { 1216 switch (revision) {
1239 case 0x22: 1217 case 0x22:
diff --git a/include/video/trident.h b/include/video/trident.h
index 9c3670b28906..51ec5a95d1ad 100644
--- a/include/video/trident.h
+++ b/include/video/trident.h
@@ -63,33 +63,7 @@
63#define SKey 0x37 63#define SKey 0x37
64#define SPKey 0x57 64#define SPKey 0x57
65 65
66/* 0x3x4 */
67#define CRTHTotal 0x00
68#define CRTHDispEnd 0x01
69#define CRTHBlankStart 0x02
70#define CRTHBlankEnd 0x03
71#define CRTHSyncStart 0x04
72#define CRTHSyncEnd 0x05
73
74#define CRTVTotal 0x06
75#define CRTVDispEnd 0x12
76#define CRTVBlankStart 0x15
77#define CRTVBlankEnd 0x16
78#define CRTVSyncStart 0x10
79#define CRTVSyncEnd 0x11
80
81#define CRTOverflow 0x07
82#define CRTPRowScan 0x08
83#define CRTMaxScanLine 0x09
84#define CRTModeControl 0x17
85#define CRTLineCompare 0x18
86
87/* 3x4 */ 66/* 3x4 */
88#define StartAddrHigh 0x0C
89#define StartAddrLow 0x0D
90#define Offset 0x13
91#define Underline 0x14
92#define CRTCMode 0x17
93#define CRTCModuleTest 0x1E 67#define CRTCModuleTest 0x1E
94#define FIFOControl 0x20 68#define FIFOControl 0x20
95#define LinearAddReg 0x21 69#define LinearAddReg 0x21