diff options
-rw-r--r-- | arch/arm/mach-omap2/clock.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx_data.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx_data.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock44xx.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/io.c | 15 |
9 files changed, 21 insertions, 26 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index be5a55f57030..7bc344bcbb47 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -47,7 +47,6 @@ | |||
47 | #define DPLL_LOW_POWER_BYPASS 0x5 | 47 | #define DPLL_LOW_POWER_BYPASS 0x5 |
48 | #define DPLL_LOCKED 0x7 | 48 | #define DPLL_LOCKED 0x7 |
49 | 49 | ||
50 | int omap2_clk_init(void); | ||
51 | int omap2_clk_enable(struct clk *clk); | 50 | int omap2_clk_enable(struct clk *clk); |
52 | void omap2_clk_disable(struct clk *clk); | 51 | void omap2_clk_disable(struct clk *clk); |
53 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | 52 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index bed294ac3647..32f3d0aa8fc4 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -19,6 +19,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); | |||
19 | u32 omap2xxx_get_apll_clkin(void); | 19 | u32 omap2xxx_get_apll_clkin(void); |
20 | u32 omap2xxx_get_sysclkdiv(void); | 20 | u32 omap2xxx_get_sysclkdiv(void); |
21 | void omap2xxx_clk_prepare_for_reboot(void); | 21 | void omap2xxx_clk_prepare_for_reboot(void); |
22 | int omap2xxx_clk_init(void); | ||
22 | 23 | ||
23 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ | 24 | /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ |
24 | #ifdef CONFIG_ARCH_OMAP2420 | 25 | #ifdef CONFIG_ARCH_OMAP2420 |
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2xxx_data.c index 3a435bb8f029..52c7a6c2d9e0 100644 --- a/arch/arm/mach-omap2/clock2xxx_data.c +++ b/arch/arm/mach-omap2/clock2xxx_data.c | |||
@@ -2238,7 +2238,7 @@ static struct omap_clk omap24xx_clks[] = { | |||
2238 | * init code | 2238 | * init code |
2239 | */ | 2239 | */ |
2240 | 2240 | ||
2241 | int __init omap2_clk_init(void) | 2241 | int __init omap2xxx_clk_init(void) |
2242 | { | 2242 | { |
2243 | const struct prcm_config *prcm; | 2243 | const struct prcm_config *prcm; |
2244 | struct omap_clk *c; | 2244 | struct omap_clk *c; |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 34d395046280..1f1b5a6b3eea 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -150,7 +150,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
150 | return omap3_noncore_dpll_set_rate(clk, rate); | 150 | return omap3_noncore_dpll_set_rate(clk, rate); |
151 | } | 151 | } |
152 | 152 | ||
153 | void omap3_clk_lock_dpll5(void) | 153 | void __init omap3_clk_lock_dpll5(void) |
154 | { | 154 | { |
155 | struct clk *dpll5_clk; | 155 | struct clk *dpll5_clk; |
156 | struct clk *dpll5_m2_clk; | 156 | struct clk *dpll5_m2_clk; |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9a2c07eac9ad..73f2109d6436 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -8,6 +8,7 @@ | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
10 | 10 | ||
11 | int omap3xxx_clk_init(void); | ||
11 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | 12 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
12 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | 13 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); |
13 | void omap3_clk_lock_dpll5(void); | 14 | void omap3_clk_lock_dpll5(void); |
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 9e7f68a8fca2..0d04f92f63e1 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c | |||
@@ -3212,11 +3212,9 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3212 | }; | 3212 | }; |
3213 | 3213 | ||
3214 | 3214 | ||
3215 | int __init omap2_clk_init(void) | 3215 | int __init omap3xxx_clk_init(void) |
3216 | { | 3216 | { |
3217 | /* struct prcm_config *prcm; */ | ||
3218 | struct omap_clk *c; | 3217 | struct omap_clk *c; |
3219 | /* u32 clkrate; */ | ||
3220 | u32 cpu_clkflg = CK_3XXX; | 3218 | u32 cpu_clkflg = CK_3XXX; |
3221 | 3219 | ||
3222 | if (cpu_is_omap3517()) { | 3220 | if (cpu_is_omap3517()) { |
@@ -3254,21 +3252,6 @@ int __init omap2_clk_init(void) | |||
3254 | omap2_init_clk_clkdm(c->lk.clk); | 3252 | omap2_init_clk_clkdm(c->lk.clk); |
3255 | } | 3253 | } |
3256 | 3254 | ||
3257 | /* REVISIT: Not yet ready for OMAP3 */ | ||
3258 | #if 0 | ||
3259 | /* Check the MPU rate set by bootloader */ | ||
3260 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
3261 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
3262 | if (!(prcm->flags & cpu_mask)) | ||
3263 | continue; | ||
3264 | if (prcm->xtal_speed != sys_ck.rate) | ||
3265 | continue; | ||
3266 | if (prcm->dpll_speed <= clkrate) | ||
3267 | break; | ||
3268 | } | ||
3269 | curr_prcm_set = prcm; | ||
3270 | #endif | ||
3271 | |||
3272 | recalculate_root_clocks(); | 3255 | recalculate_root_clocks(); |
3273 | 3256 | ||
3274 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | 3257 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " |
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h index 59b9ced4daa1..1f55b6b574fb 100644 --- a/arch/arm/mach-omap2/clock44xx.h +++ b/arch/arm/mach-omap2/clock44xx.h | |||
@@ -10,6 +10,8 @@ | |||
10 | #define OMAP4430_MAX_DPLL_MULT 2048 | 10 | #define OMAP4430_MAX_DPLL_MULT 2048 |
11 | #define OMAP4430_MAX_DPLL_DIV 128 | 11 | #define OMAP4430_MAX_DPLL_DIV 128 |
12 | 12 | ||
13 | int omap4xxx_clk_init(void); | ||
14 | |||
13 | extern const struct clkops clkops_noncore_dpll_ops; | 15 | extern const struct clkops clkops_noncore_dpll_ops; |
14 | 16 | ||
15 | #endif | 17 | #endif |
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index ae9649f2973d..35ffe638def8 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
@@ -2726,11 +2726,9 @@ static struct omap_clk omap44xx_clks[] = { | |||
2726 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), | 2726 | CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), |
2727 | }; | 2727 | }; |
2728 | 2728 | ||
2729 | int __init omap2_clk_init(void) | 2729 | int __init omap4xxx_clk_init(void) |
2730 | { | 2730 | { |
2731 | /* struct prcm_config *prcm; */ | ||
2732 | struct omap_clk *c; | 2731 | struct omap_clk *c; |
2733 | /* u32 clkrate; */ | ||
2734 | u32 cpu_clkflg; | 2732 | u32 cpu_clkflg; |
2735 | 2733 | ||
2736 | if (cpu_is_omap44xx()) { | 2734 | if (cpu_is_omap44xx()) { |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8c58699083f6..01ef2ae93593 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -35,7 +35,9 @@ | |||
35 | #include <plat/serial.h> | 35 | #include <plat/serial.h> |
36 | #include <plat/vram.h> | 36 | #include <plat/vram.h> |
37 | 37 | ||
38 | #include "clock.h" | 38 | #include "clock2xxx.h" |
39 | #include "clock34xx.h" | ||
40 | #include "clock44xx.h" | ||
39 | 41 | ||
40 | #include <plat/omap-pm.h> | 42 | #include <plat/omap-pm.h> |
41 | #include <plat/powerdomain.h> | 43 | #include <plat/powerdomain.h> |
@@ -320,7 +322,16 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | |||
320 | omap2_mux_init(); | 322 | omap2_mux_init(); |
321 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | 323 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); |
322 | #endif | 324 | #endif |
323 | omap2_clk_init(); | 325 | |
326 | if (cpu_is_omap24xx()) | ||
327 | omap2xxx_clk_init(); | ||
328 | else if (cpu_is_omap34xx()) | ||
329 | omap3xxx_clk_init(); | ||
330 | else if (cpu_is_omap44xx()) | ||
331 | omap4xxx_clk_init(); | ||
332 | else | ||
333 | pr_err("Could not init clock framework - unknown CPU\n"); | ||
334 | |||
324 | omap_serial_early_init(); | 335 | omap_serial_early_init(); |
325 | #ifndef CONFIG_ARCH_OMAP4 | 336 | #ifndef CONFIG_ARCH_OMAP4 |
326 | omap_hwmod_late_init(); | 337 | omap_hwmod_late_init(); |