diff options
-rw-r--r-- | arch/arm/mach-integrator/include/mach/platform.h | 42 | ||||
-rw-r--r-- | arch/arm/mach-realview/include/mach/platform.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-versatile/include/mach/platform.h | 26 |
3 files changed, 4 insertions, 84 deletions
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index 0e172e48bc85..5e6ea5cfea6e 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h | |||
@@ -23,9 +23,6 @@ | |||
23 | * | 23 | * |
24 | * Integrator address map | 24 | * Integrator address map |
25 | * | 25 | * |
26 | * NOTE: This is a multi-hosted header file for use with uHAL and | ||
27 | * supported debuggers. | ||
28 | * | ||
29 | * ***********************************************************************/ | 26 | * ***********************************************************************/ |
30 | 27 | ||
31 | #ifndef __address_h | 28 | #ifndef __address_h |
@@ -330,20 +327,6 @@ | |||
330 | */ | 327 | */ |
331 | #define PHYS_PCI_V3_BASE 0x62000000 | 328 | #define PHYS_PCI_V3_BASE 0x62000000 |
332 | 329 | ||
333 | #define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE | ||
334 | |||
335 | /* 'export' these to UHAL */ | ||
336 | #define UHAL_PCI_IO PCI_IO_BASE | ||
337 | #define UHAL_PCI_MEM PCI_MEM_BASE | ||
338 | #define UHAL_PCI_ALLOC_IO_BASE 0x00004000 | ||
339 | #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE | ||
340 | #define UHAL_PCI_MAX_SLOT 20 | ||
341 | |||
342 | /* ======================================================================== | ||
343 | * Start of uHAL definitions | ||
344 | * ======================================================================== | ||
345 | */ | ||
346 | |||
347 | /* ------------------------------------------------------------------------ | 330 | /* ------------------------------------------------------------------------ |
348 | * Integrator Interrupt Controllers | 331 | * Integrator Interrupt Controllers |
349 | * ------------------------------------------------------------------------ | 332 | * ------------------------------------------------------------------------ |
@@ -391,7 +374,7 @@ | |||
391 | */ | 374 | */ |
392 | 375 | ||
393 | /* ------------------------------------------------------------------------ | 376 | /* ------------------------------------------------------------------------ |
394 | * LED's - The header LED is not accessible via the uHAL API | 377 | * LED's |
395 | * ------------------------------------------------------------------------ | 378 | * ------------------------------------------------------------------------ |
396 | * | 379 | * |
397 | */ | 380 | */ |
@@ -404,34 +387,18 @@ | |||
404 | #define LED_BANK INTEGRATOR_DBG_LEDS | 387 | #define LED_BANK INTEGRATOR_DBG_LEDS |
405 | 388 | ||
406 | /* | 389 | /* |
407 | * Memory definitions - run uHAL out of SSRAM. | ||
408 | * | ||
409 | */ | ||
410 | #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE | ||
411 | |||
412 | /* | ||
413 | * Clean base - dummy | ||
414 | * | ||
415 | */ | ||
416 | #define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI | ||
417 | |||
418 | /* | ||
419 | * Timer definitions | 390 | * Timer definitions |
420 | * | 391 | * |
421 | * Only use timer 1 & 2 | 392 | * Only use timer 1 & 2 |
422 | * (both run at 24MHz and will need the clock divider set to 16). | 393 | * (both run at 24MHz and will need the clock divider set to 16). |
423 | * | 394 | * |
424 | * Timer 0 runs at bus frequency and therefore could vary and currently | 395 | * Timer 0 runs at bus frequency |
425 | * uHAL can't handle that. | ||
426 | * | ||
427 | */ | 396 | */ |
428 | 397 | ||
429 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE | 398 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE |
430 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) | 399 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) |
431 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) | 400 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) |
432 | 401 | ||
433 | #define MAX_TIMER 2 | ||
434 | #define MAX_PERIOD 699050 | ||
435 | #define TICKS_PER_uSEC 24 | 402 | #define TICKS_PER_uSEC 24 |
436 | 403 | ||
437 | /* | 404 | /* |
@@ -439,14 +406,9 @@ | |||
439 | * | 406 | * |
440 | */ | 407 | */ |
441 | #define mSEC_1 1000 | 408 | #define mSEC_1 1000 |
442 | #define mSEC_5 (mSEC_1 * 5) | ||
443 | #define mSEC_10 (mSEC_1 * 10) | 409 | #define mSEC_10 (mSEC_1 * 10) |
444 | #define mSEC_25 (mSEC_1 * 25) | ||
445 | #define SEC_1 (mSEC_1 * 1000) | ||
446 | 410 | ||
447 | #define INTEGRATOR_CSR_BASE 0x10000000 | 411 | #define INTEGRATOR_CSR_BASE 0x10000000 |
448 | #define INTEGRATOR_CSR_SIZE 0x10000000 | 412 | #define INTEGRATOR_CSR_SIZE 0x10000000 |
449 | 413 | ||
450 | #endif | 414 | #endif |
451 | |||
452 | /* END */ | ||
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 86c0c4435a46..1b77a27badaf 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h | |||
@@ -231,12 +231,6 @@ | |||
231 | #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ | 231 | #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ |
232 | #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ | 232 | #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ |
233 | 233 | ||
234 | /* | ||
235 | * Clean base - dummy | ||
236 | * | ||
237 | */ | ||
238 | #define CLEAN_BASE REALVIEW_BOOT_ROM_HI | ||
239 | |||
240 | /* | 234 | /* |
241 | * System controller bit assignment | 235 | * System controller bit assignment |
242 | */ | 236 | */ |
@@ -249,20 +243,6 @@ | |||
249 | #define REALVIEW_TIMER4_EnSel 21 | 243 | #define REALVIEW_TIMER4_EnSel 21 |
250 | 244 | ||
251 | 245 | ||
252 | #define MAX_TIMER 2 | ||
253 | #define MAX_PERIOD 699050 | ||
254 | #define TICKS_PER_uSEC 1 | ||
255 | |||
256 | /* | ||
257 | * These are useconds NOT ticks. | ||
258 | * | ||
259 | */ | ||
260 | #define mSEC_1 1000 | ||
261 | #define mSEC_5 (mSEC_1 * 5) | ||
262 | #define mSEC_10 (mSEC_1 * 10) | ||
263 | #define mSEC_25 (mSEC_1 * 25) | ||
264 | #define SEC_1 (mSEC_1 * 1000) | ||
265 | |||
266 | #define REALVIEW_CSR_BASE 0x10000000 | 246 | #define REALVIEW_CSR_BASE 0x10000000 |
267 | #define REALVIEW_CSR_SIZE 0x10000000 | 247 | #define REALVIEW_CSR_SIZE 0x10000000 |
268 | 248 | ||
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index 83207395191a..ec087407b163 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h | |||
@@ -205,7 +205,7 @@ | |||
205 | #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ | 205 | #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ |
206 | #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ | 206 | #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ |
207 | #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ | 207 | #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ |
208 | #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ | 208 | #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ |
209 | /* 0x10000000 - 0x100FFFFF */ | 209 | /* 0x10000000 - 0x100FFFFF */ |
210 | #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ | 210 | #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ |
211 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ | 211 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ |
@@ -213,7 +213,7 @@ | |||
213 | #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ | 213 | #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ |
214 | #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ | 214 | #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ |
215 | #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ | 215 | #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ |
216 | #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ | 216 | #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ |
217 | #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ | 217 | #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ |
218 | #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ | 218 | #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ |
219 | #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ | 219 | #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ |
@@ -379,12 +379,6 @@ | |||
379 | #define SIC_INT_PCI3 30 | 379 | #define SIC_INT_PCI3 30 |
380 | 380 | ||
381 | 381 | ||
382 | /* | ||
383 | * Clean base - dummy | ||
384 | * | ||
385 | */ | ||
386 | #define CLEAN_BASE VERSATILE_BOOT_ROM_HI | ||
387 | |||
388 | /* | 382 | /* |
389 | * System controller bit assignment | 383 | * System controller bit assignment |
390 | */ | 384 | */ |
@@ -397,20 +391,6 @@ | |||
397 | #define VERSATILE_TIMER4_EnSel 21 | 391 | #define VERSATILE_TIMER4_EnSel 21 |
398 | 392 | ||
399 | 393 | ||
400 | #define MAX_TIMER 2 | ||
401 | #define MAX_PERIOD 699050 | ||
402 | #define TICKS_PER_uSEC 1 | ||
403 | |||
404 | /* | ||
405 | * These are useconds NOT ticks. | ||
406 | * | ||
407 | */ | ||
408 | #define mSEC_1 1000 | ||
409 | #define mSEC_5 (mSEC_1 * 5) | ||
410 | #define mSEC_10 (mSEC_1 * 10) | ||
411 | #define mSEC_25 (mSEC_1 * 25) | ||
412 | #define SEC_1 (mSEC_1 * 1000) | ||
413 | |||
414 | #define VERSATILE_CSR_BASE 0x10000000 | 394 | #define VERSATILE_CSR_BASE 0x10000000 |
415 | #define VERSATILE_CSR_SIZE 0x10000000 | 395 | #define VERSATILE_CSR_SIZE 0x10000000 |
416 | 396 | ||
@@ -432,5 +412,3 @@ | |||
432 | #endif | 412 | #endif |
433 | 413 | ||
434 | #endif | 414 | #endif |
435 | |||
436 | /* END */ | ||