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-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h1
-rw-r--r--arch/mips/loongson/common/irq.c3
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c11
-rw-r--r--arch/mips/loongson/lemote-2f/irq.c11
4 files changed, 8 insertions, 18 deletions
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index fcdbe3a4ce1f..53ee881c675d 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -45,7 +45,6 @@ static inline void prom_init_uart_base(void)
45/* irq operation functions */ 45/* irq operation functions */
46extern void bonito_irqdispatch(void); 46extern void bonito_irqdispatch(void);
47extern void __init bonito_irq_init(void); 47extern void __init bonito_irq_init(void);
48extern void __init set_irq_trigger_mode(void);
49extern void __init mach_init_irq(void); 48extern void __init mach_init_irq(void);
50extern void mach_irq_dispatch(unsigned int pending); 49extern void mach_irq_dispatch(unsigned int pending);
51extern int mach_i8259_irq(void); 50extern int mach_i8259_irq(void);
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 25a11df03482..5897471dedca 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -53,9 +53,6 @@ void __init arch_init_irq(void)
53 */ 53 */
54 clear_c0_status(ST0_IM | ST0_BEV); 54 clear_c0_status(ST0_IM | ST0_BEV);
55 55
56 /* setting irq trigger mode */
57 set_irq_trigger_mode();
58
59 /* no steer */ 56 /* no steer */
60 LOONGSON_INTSTEER = 0; 57 LOONGSON_INTSTEER = 0;
61 58
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..99e08c3db3f4 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
44 .name = "cascade", 44 .name = "cascade",
45}; 45};
46 46
47void __init set_irq_trigger_mode(void)
48{
49 /* most bonito irq should be level triggered */
50 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
52}
53
54void __init mach_init_irq(void) 47void __init mach_init_irq(void)
55{ 48{
56 /* init all controller 49 /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
59 * 32-63 ------> bonito irq 52 * 32-63 ------> bonito irq
60 */ 53 */
61 54
55 /* most bonito irq should be level triggered */
56 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
57 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
58
62 /* Sets the first-level interrupt dispatcher. */ 59 /* Sets the first-level interrupt dispatcher. */
63 mips_cpu_irq_init(); 60 mips_cpu_irq_init();
64 init_i8259_irqs(); 61 init_i8259_irqs();
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 1d8b4d28a058..c6db7e7df963 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -91,13 +91,6 @@ void mach_irq_dispatch(unsigned int pending)
91 spurious_interrupt(); 91 spurious_interrupt();
92} 92}
93 93
94void __init set_irq_trigger_mode(void)
95{
96 /* setup cs5536 as high level trigger */
97 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99}
100
101static irqreturn_t ip6_action(int cpl, void *dev_id) 94static irqreturn_t ip6_action(int cpl, void *dev_id)
102{ 95{
103 return IRQ_HANDLED; 96 return IRQ_HANDLED;
@@ -122,6 +115,10 @@ void __init mach_init_irq(void)
122 * 32-63 ------> bonito irq 115 * 32-63 ------> bonito irq
123 */ 116 */
124 117
118 /* setup cs5536 as high level trigger */
119 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
120 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
121
125 /* Sets the first-level interrupt dispatcher. */ 122 /* Sets the first-level interrupt dispatcher. */
126 mips_cpu_irq_init(); 123 mips_cpu_irq_init();
127 init_i8259_irqs(); 124 init_i8259_irqs();