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-rw-r--r--arch/arm/mach-at91/clock.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 848efb2a4ebf..57c3b647ce83 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -351,7 +351,7 @@ static void init_programmable_clock(struct clk *clk)
351 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 351 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
352 parent = at91_css_to_clk(pckr & AT91_PMC_CSS); 352 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
353 clk->parent = parent; 353 clk->parent = parent;
354 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3)); 354 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
355} 355}
356 356
357#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ 357#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -587,8 +587,11 @@ int __init at91_clock_init(unsigned long main_clock)
587 mckr = at91_sys_read(AT91_PMC_MCKR); 587 mckr = at91_sys_read(AT91_PMC_MCKR);
588 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); 588 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
589 freq = mck.parent->rate_hz; 589 freq = mck.parent->rate_hz;
590 freq /= (1 << ((mckr >> 2) & 3)); /* prescale */ 590 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
591 mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */ 591 if (cpu_is_at91rm9200())
592 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
593 else
594 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
592 595
593 /* Register the PMC's standard clocks */ 596 /* Register the PMC's standard clocks */
594 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) 597 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)