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-rw-r--r--arch/mips/mips-boards/malta/malta_int.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 4b5694e19d33..b393982c0cc0 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -363,6 +363,7 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
363 363
364static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 364static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
365 365
366#if defined(CONFIG_MIPS_MT_SMP)
366/* 367/*
367 * This GIC specific tabular array defines the association between External 368 * This GIC specific tabular array defines the association between External
368 * Interrupts and CPUs/Core Interrupts. The nature of the External 369 * Interrupts and CPUs/Core Interrupts. The nature of the External
@@ -394,6 +395,7 @@ static struct gic_intr_map gic_intr_map[] = {
394 { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, 395 { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
395 { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, 396 { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
396}; 397};
398#endif
397 399
398/* 400/*
399 * GCMP needs to be detected before any SMP initialisation 401 * GCMP needs to be detected before any SMP initialisation
@@ -412,7 +414,8 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
412 return gcmp_present; 414 return gcmp_present;
413} 415}
414 416
415void __init fill_ipi_map(void) 417#if defined(CONFIG_MIPS_MT_SMP)
418static void __init fill_ipi_map(void)
416{ 419{
417 int i; 420 int i;
418 421
@@ -422,6 +425,7 @@ void __init fill_ipi_map(void)
422 (1 << (gic_intr_map[i].pin + 2)); 425 (1 << (gic_intr_map[i].pin + 2));
423 } 426 }
424} 427}
428#endif
425 429
426void __init arch_init_irq(void) 430void __init arch_init_irq(void)
427{ 431{
@@ -527,7 +531,6 @@ void __init arch_init_irq(void)
527 .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3 531 .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3
528 } 532 }
529 }; 533 };
530#define NIPI ARRAY_SIZE(ipiirq)
531 fill_ipi_map(); 534 fill_ipi_map();
532 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 535 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
533 if (!gcmp_present) { 536 if (!gcmp_present) {
@@ -549,7 +552,7 @@ void __init arch_init_irq(void)
549 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 552 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
550 write_c0_status(0x1100dc00); 553 write_c0_status(0x1100dc00);
551 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 554 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
552 for (i = 0; i < NIPI; i++) { 555 for (i = 0; i < ARRAY_SIZE(ipiirq); i++) {
553 setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched); 556 setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
554 setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call); 557 setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
555 558